TWM564825U - Chip package device - Google Patents

Abstract

A chip packaging device includes a chip carrier, a chip, and a packaging unit. The wafer carrier includes a substrate and a conductive structure disposed on the substrate. The chip is disposed on the substrate and is electrically connected to the conductive structure. The packaging unit includes a packaging board and a connection support structure, the packaging board is spaced apart from the wafer and is located on two opposite sides of the wafer from the substrate, and two ends of the connection support structure are respectively connected to the chip and the packaging board, and A cross-sectional area of the connection support structure adjacent to the wafer is smaller than a cross-sectional area of the connection support structure that is not adjacent to the wafer.

Description

Chip packaging device

The present invention relates to a chip packaging device, and more particularly to a chip packaging device.

Semiconductor package structure (Semiconductor package) is a structure for accommodating and covering one or more semiconductor components. After the wafer is cut into independent dies, the covering packaging material can prevent the wafer from being damaged or malfunctioned by external forces or moisture, and can also protect the wafer for easy assembly and transportation.

Image sensors use image chips to generate image data. They are often used in digital cameras (DC) or other electronic products with image functions, such as mobile phones and tablet computers. At present, the image chips commonly used by image sensors are mainly complementary metal oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) type wafers, which not only have low production costs, but also have the advantages of smaller size and have been widely developed. Manufacturing. For the miniaturization of image sensors, in addition to the selection of the type of image chip, the related structure for packaging the image chip is also very important. Therefore, how to provide a smaller size while also sensing Precision image sensors are still a technical issue that needs attention.

Therefore, an object of the present invention is to provide a chip packaging device capable of providing a smaller size to improve the reliability of the chip.

Therefore, in some embodiments, the novel chip packaging device includes a chip carrier, a chip, and a packaging unit. The wafer carrier includes a substrate and a conductive structure disposed on the substrate. The chip is disposed on the substrate and is electrically connected to the conductive structure. The packaging unit includes a packaging board and a connection support structure, the packaging board is spaced apart from the wafer and is located on two opposite sides of the wafer from the substrate, and two ends of the connection support structure are respectively connected to the chip and the packaging board, and A cross-sectional area of the connection support structure adjacent to the wafer is smaller than a cross-sectional area of the connection support structure that is not adjacent to the wafer.

In some embodiments, the wafer is an image wafer, and includes a photosensitive portion facing the packaging board, and a pad adjacent to the photosensitive portion and electrically connected to the conductive structure, and the connection support structure is connected to the wafer. The position is between the photosensitive part and the pad.

In some embodiments, the cross-sectional area of the connection support structure decreases gradually from one end adjacent to the package board to one end adjacent to the chip.

In some embodiments, the package board has a connection surface facing the substrate, the connection support structure has a first layer body disposed on the connection surface, and a connection A second layer body connected to the first layer body adjacent to one side of the substrate has a cross-sectional area smaller than that of the first layer body.

In some embodiments, the connection support structure further has an adhesive layer for adhering the second layer body and the wafer.

In some embodiments, the packaging unit further includes a packaging layer. The packaging board also has an exposed surface on the opposite side from the connection surface. The packaging layer covers the substrate, the conductive structure, the chip, and the package. Board and does not completely cover the exposed surface of the package board.

In some embodiments, the packaging unit further includes a packaging layer, the packaging board further has an exposed surface on the opposite side to the connection surface, and the packaging layer covers the substrate, the conductive structure, the chip and the package board.

The new model has at least the following effects: the packaging board is spaced apart from the wafer and is located on two opposite sides of the wafer from the substrate, and cooperates with the design of the connection support structure so that both ends of the connection support structure are connected to the chip and The package board, and the cross-sectional area of the connection support structure adjacent to the wafer is smaller than the cross-sectional area of the connection support structure that is not adjacent to the wafer, thereby reducing the installation and use area of the connection support structure on the wafer, thereby reducing the size of the wafer Therefore, the overall structure of the chip packaging device can be miniaturized, and at the same time, the package board can be provided with good support ability on the wafer, so as to improve the reliability of the wafer and the convenience of process assembly.

1‧‧‧ Wafer Carrier

11‧‧‧ substrate

111‧‧‧Inner bearing surface

112‧‧‧outer contact surface

12‧‧‧ conductive structure

121‧‧‧ welding wire

122‧‧‧ conductive layer

2‧‧‧Chip

21‧‧‧ Photosensitive Department

22‧‧‧ Guide Department

23‧‧‧Soldering pad

3‧‧‧Packaging Unit

31‧‧‧Packaging board

311‧‧‧ connecting surface

312‧‧‧ Appear

32‧‧‧ connected support structure

321‧‧‧first layer

322‧‧‧Second Layer

323‧‧‧Adhesive layer

33‧‧‧Encapsulation layer

Other features and functions of the present invention will be clearly presented in the embodiment with reference to the drawings, wherein: FIG. 1 is a schematic diagram illustrating a first embodiment of the new chip packaging device; FIG. 2 is a step flow block Figures illustrate a manufacturing method of the first embodiment; Figures 3 to 9 are schematic diagrams illustrating the implementation of the manufacturing processes of the first embodiment; Figure 10 is a schematic diagram similar to Figure 6 illustrating the novel Partial implementation of the manufacturing process of a second embodiment of a chip packaging device; FIG. 11 is a schematic diagram similar to FIG. 8 illustrating a partial implementation of the manufacturing process of the second embodiment of the new chip packaging device; FIG. 12 is a schematic diagram similar to FIG. 6 illustrating a part of the manufacturing process of a third embodiment of the novel chip packaging device; and FIG. 13 is a schematic diagram similar to FIG. 1 illustrating the new chip packaging device Structure of an encapsulation layer.

Before the new model is described in detail, it should be noted that in the following description, similar elements are represented by the same number.

Referring to FIG. 1, a first embodiment of the novel chip packaging device includes A wafer carrier 1, a wafer 2, and a packaging unit 3.

In detail, the wafer carrier 1 includes a substrate 11 and a conductive structure 12 disposed on the substrate 11. The substrate 11 is used to support the wafer 2 and has an inner bearing surface 111 and an outer contact surface 112 located on the opposite side of the inner bearing surface 111. In this embodiment, the substrate 11 is a rectangular thin plate, and the material of the substrate 11 is a ceramic material or a resin material. The ceramic material is mainly alumina (Al ₂ O ₃ ) or aluminum nitride (AlN). The material is not limited to aluminum oxide (Al ₂ O ₃ ) or aluminum nitride (AlN). In other embodiments, the substrate 11 may be made of metal materials such as copper and iron, and circuits such as fiberglass. Substrate. The conductive structure 12 has a bonding wire 121 provided on the inner bearing surface 111 of the substrate 11, a conductive layer 122 provided on the outer contact surface 112 of the substrate 11, and other components not provided on the substrate 11. The lead wires in the picture. The bonding wire 121 may be gold, copper, silver, copper-palladium alloy, or other metal wires. The conductive structure 12 functions to provide a signal transmission function between the chip 2 and an external circuit board (not shown).

The chip 2 is disposed on the substrate 11 and is electrically connected to the conductive structure 12. In this embodiment, the wafer 2 is described by taking an image sensing wafer as an example. Therefore, the wafer 2 includes a photosensitive portion 21, a guide portion 22 surrounding the outer periphery of the photosensitive portion 21, and a portion disposed on the wafer 2 The conductive portion 22 is adjacent to the photosensitive portion 21 and is electrically connected to the bonding pad 23 of the conductive structure 12. The chip 2 is in a wire bonding manner, and is electrically connected to the bonding wire 121 of the conductive structure 12 through the bonding pad 23. In other embodiments, In addition, the chip 2 may also be electrically connected to the conductive structure 12 of the substrate 11 by other line connection methods. The manner of setting is not limited to the content disclosed in this embodiment, and the type of the chip 2 is not limited to the image sense. Test chip.

The packaging unit 3 includes a packaging board 31, a connection support structure 32, and a packaging layer 33. The packaging board 31 is spaced from the wafer 2 and is located on two opposite sides of the wafer 2 from the substrate 11. The packaging board 31 has a connection surface 311 facing the substrate 11, the photosensitive portion 21 of the wafer 2, and The connection surface 311 is located on the exposed surface 312 on the opposite side. In this embodiment, the packaging board 31 is made of a light-transmissive material and is transparent, such as glass, thereby providing a good penetrating ability to external light to The chip 2 is used to generate a corresponding image signal after the chip 2 receives external light. However, in the embodiment where the chip 2 is a non-image sensing chip, the package board 31 does not use the above-mentioned light-transmissive implementation mode as limit.

The connection support structure 32 is provided around the outer periphery of the photosensitive portion 21 of the wafer 2. In addition, the two ends of the connection support structure 32 are connected to the wafer 2 and the package board 31 respectively, and the connection support structure 32 is connected to one end of the wafer 2 at the lead portion 22 and between the photosensitive portion 21 and the bonding pad 23. It should be particularly noted that the connection support structure 32 does not have to be provided between the photosensitive portion 21 and the bonding pad 23. In other embodiments, as long as the connection support structure 32 is provided on the lead of the wafer 2, At the position of the portion 22, the connection support structure 32 also has its function. The connection supporting structure 32 has a first layer disposed on the connection surface 311 of the packaging board 31. The body 321, a second layer body 322 connected to the first layer body 321 adjacent to one side of the substrate 11, and an adhesive layer 323 for bonding the second layer body 322 and the wafer 2. In this embodiment, the material of the raw materials used in the manufacturing of the first layer body 321 and the second layer body 322 may be liquid or film / sheet, and any material capable of achieving a photosensitive effect may be used. On the other hand, the adhesive layer 323 is a photosensitive adhesive. Since the photosensitive adhesive has the characteristics of a resin material that can be quickly cured or has a high viscosity coefficient and is not easy to flow, the size of the adhesive layer 323 is easy to be manufactured. It is controlled, but the way of setting is not limited to the content disclosed in this embodiment.

Referring to FIG. 1, the encapsulation layer 33 is used to cover the substrate 11, the conductive structure 12, the wafer 2, and the encapsulation plate 31, and the encapsulation layer 33 does not completely cover the exposed surface 312 of the encapsulation plate 31. The packaging layer 33 also does not cover the photosensitive portion 21 of the wafer 2, so that the photosensitive portion 21 of the wafer 2 can receive external light through the exposed surface 312 of the packaging plate 31. The encapsulation layer 33 preferably covers all structures except the conductive layer 122 region of the conductive structure 12 to ensure electrical safety and to prevent water vapor and oxygen from penetrating into the chip 2. In this embodiment, the encapsulation layer 33 is made of epoxy resin, polyimide, or other materials, or it is made of some silicides, oxides, etc. that will not affect the properties of the chip 2 when cured and formed into the encapsulation layer 33 Material production. In other embodiments, the encapsulation layer 33 can completely cover the substrate 11, the conductive structure 12, the chip 2, and the exposed surface 312 of the encapsulation plate 31 (as shown in FIG. 13), thereby In addition, the chip packaging device can be additionally provided with the function of an empty bridge structure.

Specifically, in this embodiment, the cross-sectional area of the connection support structure 32 adjacent to the region of the wafer 2 is configured to be smaller than the cross-sectional area of the region not adjacent to the region of the wafer 2. Therefore, the second layer body 322 is provided here. The cross-sectional area of the first layer body 321 is smaller than the cross-sectional area of the first layer body 321, and the cross-sectional area of the adhesive layer 323 is smaller than or equal to the cross-sectional area of the second layer body 322, so that the cross-sectional area of the connection support structure 32 is adjacent to the package. One end of the plate 31 is gradually reduced toward one end adjacent to the chip 2. Therefore, the overall connection support structure 32 has a shape of upper width and narrow width as viewed from the side. The dimensions of the first layer body 321 and the second layer body 322 are, for example, the first layer body 321 is a layer body with a width of 100um and a thickness of 50um, and the second layer body 322 is a layer body with a width of 50um and a thickness of 50um. . In addition, because the raw material of the adhesive layer 323 has the characteristics of rapid curing, the raw material of the adhesive layer 323 is difficult to diffuse and flow to the surroundings during the manufacturing process. Therefore, the size of the adhesive layer 323 can be adjusted, which is beneficial to Controlling the size of the connection support structure 32 also contributes to miniaturization of the chip packaging device as a whole.

It should be particularly noted that the design and manufacturer can make adjustments according to actual needs. The connection support structure 32 is not limited to the disclosure of this embodiment, and can also achieve the effect of the connection support structure 32. All are regarded as conventional changes in this embodiment. For example, the connection support structure 32 may be provided with other layers in addition to the first layer body 321 and the second layer body 322, or may be provided by a single layer only. The body is formed into a structure with a change in cross-sectional area, which is a manner in which the connection support structure 32 can be implemented. Thus, by designing the packaging unit 3, the chip package can be provided. The device has the characteristics of (1) preventing water vapor leakage, and (2) miniaturization.

Referring to FIG. 2, the manufacturing method for manufacturing the chip packaging device according to the first embodiment includes the following steps: Step S10, providing the wafer carrier 1, the wafer 2, and the packaging unit 3. In step S20, the packaging board 31 is set on the wafer 2. In step S30, the packaging layer 33 is formed. Hereinafter, a manufacturing method using the aforementioned chip packaging device will be described in detail. In this embodiment, the method for manufacturing the chip packaging device is applicable to an image sensing chip, but in other embodiments, the method for manufacturing the chip packaging device can also be applied to the chip other than the image sensing chip. 2 types.

Referring to FIG. 3, step S10: providing the wafer carrier 1 and the wafer 2.

The wafer carrier 1 and the wafer 2 are prepared as described above, and the wafer 2 is set on the substrate 11 with the photosensitive portion 21 side facing upward, and the pads 23 and the conductive structure of the wafer 2 are provided. The bonding wires 121 of 12 are electrically connected to each other.

Referring to FIG. 4 to FIG. 7, step S10: providing the packaging unit 3.

The packaging unit 3 is provided as previously described. The first layer body 321 is prepared on the side of the connection surface 311 of the packaging board 31 and presents a state as shown in FIG. 4. When the first layer body 321 is made of a liquid material such as a photosensitive resin, it is formed on the packaging board 31 in a whole surface by a coating process; when the first layer body 321 is a film / sheet such as a dry film photoresist At the time of forming the shaped material, the entire surface is formed on the package board 31 in a lamination process. Then, the first layer body 321 is formed on the connection surface 311 of the packaging board 31 (as shown in FIG. 5) according to a predetermined shape and position according to a sequence of exposure and development. Then, with something like The second layer body 322 is formed on the first layer body 321 in a manner of making the first layer body 321, and the cross-sectional area of the second layer body 322 is smaller than the cross-sectional area of the first layer body 321. The state shown in Figure 6. Finally, the adhesive layer 323 is formed on the conductive portion 22 of the wafer 2 by a dispensing method and is located between the photosensitive portion 21 and the bonding pad 23 (as shown in FIG. 7).

Referring to FIG. 8 to FIG. 9, step S20: setting the packaging board 31 on the wafer 2, because the raw material of the adhesive layer 323 has the characteristics of rapid curing, thereby preventing the adhesive layer 323 from delaminating or deforming from the wafer 2 Then there is a phenomenon of air leakage.

Before the package board 31 is assembled on the chip 2, the connection surface 311 of the package board 31 faces downward (as shown in FIG. 8). As the package board 31 is disposed above the wafer 2, the second layer 322 on the package board 31 is adhered through the adhesive layer 323 provided on the wafer 2 in advance, so that the package board 31 is cured by a curing process. It can be combined with the chip 2 at the same time, and the two ends of the connection support structure 32 are respectively connected to the chip 2 and the packaging board 31, so that the packaging board 31 and the chip 2 are spaced apart from each other, as shown in FIG. 9 Shown state.

Referring to FIG. 1, step S30: forming the encapsulation layer 33.

The encapsulation layer 33 is prepared on the substrate 11 with an epoxy resin or the like, so that the encapsulation layer 33 can completely cover the substrate 11 and the conductive structure 12 and partially cover the wafer 2 and the packaging plate 31, and This allows the packaging layer 33 to not completely cover the exposed surface 312 of the packaging board 31. In this way, the fabrication of the chip packaging device is completed.

Referring to FIG. 10 and FIG. 11, a second embodiment of the chip packaging device is shown. In this embodiment, the overall structure of the chip packaging device is the same as the aforementioned first embodiment, but in the manufacturing method, the main difference between the second embodiment and the aforementioned first embodiment lies in the adhesion in step S10. How the layer 323 is formed.

In the second embodiment, after the first layer body 321 and the second layer body 322 are sequentially formed on the packaging board 31, the adhesive layer 323 is formed in a sticking manner on the packaging board 31 in advance. The second layer body 322 is shown in FIG. 10, so this manufacturing step is different from the embodiment in which the adhesive layer 323 is first formed on the wafer 2 in the first embodiment. Then, the connection surface 311 of the packaging board 31 is directed downward, so that the packaging board 31 is disposed above the wafer 2, and is adhered to the wafer 2 through the adhesive layer 323 provided in advance on the packaging board 31 to be cured. The program enables the package board 31 to be combined with the wafer 2 and is connected to the wafer 2 and the package board 31 by the two ends of the connection support structure 32 so that the package board 31 and the wafer 2 are spaced apart from each other. The appearance shown in Figure 9 is presented. Then, the same step S30 as in the first embodiment is continued to complete the manufacturing steps of the second embodiment.

Referring to FIG. 12, a third embodiment of the chip packaging device is shown. In this embodiment, the overall structure and manufacturing method of the chip packaging device are substantially the same as those of the first embodiment. The main difference between the third embodiment and the first embodiment is the structure of the connection support structure 32. And how to make it.

In step S10, the first layer body 321 and the second layer body 322 are First, it is produced in a press-fit manner, and presents a state as shown in FIG. 12. In this embodiment, the formation structure of the connection support structure 32 is different from the divided production method of the foregoing first embodiment. The remaining structures and processes are There is no difference from the first embodiment, so it will not be described again. In this way, the first layer body 321 and the second layer body 322 can be made denser and more seamless, and can prevent leakage of moisture and oxygen to the wafer 2. Therefore, by the design of the packaging unit 3, the chip packaging device can be provided with (1) prevention of water vapor leakage, (2) controllable and consistent size of the connection support structure 32, and (3) small Dimensional characteristics.

In summary, the new chip packaging device is spaced from the wafer 2 through the packaging board 31 and is located on two opposite sides of the wafer 2 from the substrate 11 and cooperates with the design of the connection support structure 32 to make the connection support structure Both ends of 32 are connected to the chip 2 and the packaging board 31, respectively, and the cross-sectional area of the connection support structure 32 adjacent to the wafer 2 is smaller than the cross-sectional area of the connection support structure 32 which is not adjacent to the wafer 2, thereby reducing the connection support structure 32. The area of the wafer 2 is used, so that the size of the wafer 2 can be reduced, and the overall structure of the wafer packaging device can be miniaturized. At the same time, the package board 31 can be provided with good support on the wafer 2. With the manufacturing method of the chip packaging device, the size can be more miniaturized, so as to improve the reliability of the chip 2 and the convenience of process assembly, so it can indeed achieve the purpose of new cost.

However, the above are only examples of the new model. When the scope of the implementation of the new model cannot be limited in this way, any application for the patent scope and patent description of the new model is required. The simple equivalent changes and modifications made in the contents of the book are still covered by the new patent.

Claims (7)

A chip packaging device includes: a chip carrier including a substrate and a conductive structure disposed on the substrate; a chip disposed on the substrate and electrically connected to the conductive structure; and a packaging unit including a packaging board and A connection support structure, the package board is spaced from the wafer and is located on two opposite sides of the wafer from the substrate, two ends of the connection support structure are connected to the chip and the package board respectively, and the connection support structure is adjacent to the wafer The cross-sectional area at is smaller than the cross-sectional area not adjacent to the wafer. The chip packaging device according to claim 1, wherein the wafer is an image wafer and includes a photosensitive portion facing the packaging board, and a bonding pad adjacent to the photosensitive portion and electrically connected to the conductive structure, the connection The supporting structure is connected to the wafer between the photosensitive part and the bonding pad. The chip packaging device according to claim 1, wherein a cross-sectional area of the connection support structure gradually decreases from one end adjacent to the package board to one end adjacent to the chip. The chip packaging device according to claim 1, wherein the packaging board has a connection surface facing the substrate, the connection support structure has a first layer body disposed on the connection surface, and a connection layer connected to the first layer A second layer body adjacent to one side of the substrate has a cross-sectional area smaller than that of the first layer body. The wafer sealing device according to claim 4, wherein the connection support structure further has an adhesive layer for adhering the second layer body and the wafer. The chip packaging device according to claim 4, wherein the packaging unit further includes a packaging layer, the packaging board further has an exposed surface on the opposite side to the connection surface, and the packaging layer covers the substrate and the conductive structure , The chip and the package board, and the exposed surface of the package board is not completely covered. The chip packaging device according to claim 4, wherein the packaging unit further includes a packaging layer, the packaging board further has an exposed surface on the opposite side to the connection surface, and the packaging layer covers the substrate and the conductive structure , The chip and the package board.