TWM536358U - Chip testing apparatus having implantable coaxial bore connector and electrical circuit architecture - Google Patents
Chip testing apparatus having implantable coaxial bore connector and electrical circuit architecture Download PDFInfo
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Abstract
Description
本創作係關於一種測試架構及其電路架構,特別是關於一種具有植入式同軸孔連接器的晶片測試架構及其電路架構。 This creation is about a test architecture and its circuit architecture, particularly with respect to a wafer test architecture with an implanted coaxial connector and its circuit architecture.
隨著電子產品朝向精密化與多功能化發展,在電子產品內的積體電路之晶片結構趨於複雜,而且該晶片結構的操作頻率也大幅提高,以用於更高頻率波段的電子產品領域。其中用於測試該晶片的晶片測試裝置必須具有測試高頻信號的能力,特別是該晶片測試裝置的印刷電板之負載板需要製作通孔的時需要增加複雜的微影、蝕刻程序,導致生產成本提高,其中該通孔用以連接儀器設備進行各種訊號的分析以及測量,以確認該晶片的功能是否正常。因此需要提出一種新式的測試架構,以解決上述之問題。 As electronic products are becoming more sophisticated and multi-functional, the wafer structure of integrated circuits in electronic products tends to be complex, and the operating frequency of the wafer structure is also greatly increased for use in electronic products in higher frequency bands. . The wafer test apparatus for testing the wafer must have the ability to test high frequency signals, especially when the load board of the printed circuit board of the wafer test apparatus needs to make through holes, complicated lithography and etching procedures are required, resulting in production. The cost is increased, wherein the through hole is used to connect the instrument to perform analysis and measurement of various signals to confirm whether the function of the chip is normal. Therefore, a new type of test architecture needs to be proposed to solve the above problems.
本創作之一目的在於提供一種具有植入式同軸孔連接器的晶片測試架構以及電路架構,藉由同軸孔連接器將測試訊號以最短路徑由電路板的一表面傳送至另一表面,以減少測試訊號的功率耗損以及避免雜 訊干擾,並且以簡化習知技術中印刷電板之負載板製作同軸通孔的繁雜步驟,以降低晶片測試架構的生產成本。 One of the aims of the present invention is to provide a wafer test architecture and circuit architecture with an implantable coaxial connector, wherein the test signal is transmitted from one surface of the circuit board to the other surface in the shortest path by the coaxial hole connector to reduce Test signal power loss and avoid miscellaneous Interference, and to simplify the complicated steps of making coaxial vias for printed boards of printed boards in the prior art, to reduce the production cost of the wafer test architecture.
為達成上述目的,本創作之一實施例中具有植入式同軸孔連接器的晶片測試架構,包括:一晶片;一腳座,設有複數腳位,以供該晶片電性插接,該些腳位用以傳遞該晶片的測試訊號;一電路板,電性連接該腳座,用以傳送來自該些腳位的該測試訊號,該電路板之中設有至少一通孔,該通孔相對應於該腳座的至少一腳位,並且該通孔的內壁面設有一導電層;以及一同軸孔連接器,包括一纜線區段以及一接頭,該纜線區段係插入於該通孔中並且該纜線區段的外表面與該導電層形成電性接觸,使該測試訊號由該纜線區段沿著一傳遞方向傳送至該接頭,以使該測試訊號由該電路板的第一表面傳送至第二表面,該通孔的兩端分別連接該第一表面以及該第二表面。 In order to achieve the above object, a wafer test architecture having an implantable coaxial connector in one embodiment of the present invention includes: a wafer; a foot having a plurality of pins for electrically inserting the wafer, The pins are used to transmit test signals of the chip; a circuit board electrically connected to the pins for transmitting the test signals from the pins, wherein the circuit board is provided with at least one through hole, the through hole Corresponding to at least one foot of the foot, and the inner wall surface of the through hole is provided with a conductive layer; and a coaxial hole connector including a cable section and a joint, the cable section is inserted therein The through hole and the outer surface of the cable segment are in electrical contact with the conductive layer, so that the test signal is transmitted from the cable segment to the connector in a transfer direction, so that the test signal is received by the circuit board The first surface is transferred to the second surface, and the two ends of the through hole are respectively connected to the first surface and the second surface.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該導電層係以電鍍法形成於該通孔的內壁面。 In an embodiment of the wafer test structure having an implantable coaxial connector, the conductive layer is formed on the inner wall surface of the through hole by electroplating.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該纜線區段係為同軸纜線區段。 In one embodiment, a wafer test architecture having an implanted coaxial connector, wherein the cable segment is a coaxial cable segment.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該纜線區段包括:一導線,電性連接該腳座的至少一腳位,用以傳送該測試訊號;一絕緣部,用以包覆該導線,並且該絕緣部的一外表面沿著半徑方向係與該導線等距離;以及一接地屏蔽部,形成於該絕緣部的該外表面上,以與該導線互相絕緣,以控制該測試訊號在該纜線區段的阻抗值。 In one embodiment, the wafer test structure has an implantable coaxial connector, wherein the cable segment includes: a wire electrically connected to at least one pin of the foot for transmitting the test signal; and an insulation a portion for covering the wire, and an outer surface of the insulating portion is equidistant from the wire along a radial direction; and a ground shield portion is formed on the outer surface of the insulating portion to interact with the wire Insulation to control the impedance value of the test signal in the cable section.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其 中該纜線區段係將該導線、該絕緣部以及該接地屏蔽部結合之後,並且將結合的該導線、該絕緣部以及該接地屏蔽部之結構植入於該電路板的該通孔中。 a wafer test architecture with an implantable coaxial connector in an embodiment, The cable section is formed by combining the wire, the insulating portion and the grounding shield, and implanting the combined wire, the insulating portion and the structure of the grounding shield into the through hole of the circuit board .
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該纜線區段的該導線係為實心導線。 In one embodiment, a wafer test architecture having an implantable coaxial connector, wherein the wire of the cable segment is a solid wire.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該電路板的該第一表面與該第二表面係為該電路板的上、下兩個相對異側之表面。 In an embodiment of the wafer test architecture having an implantable coaxial connector, the first surface and the second surface of the circuit board are the upper and lower surfaces of the circuit board.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該通孔的內壁面之該導電層係延伸至該電路板的第一表面以及第二表面上形成一導電部,以控制該纜線區段的阻抗值。 In an embodiment of the wafer test structure having an implantable coaxial connector, wherein the conductive layer of the inner wall surface of the through hole extends to form a conductive portion on the first surface and the second surface of the circuit board to Control the impedance value of the cable segment.
在一實施例之具有植入式同軸孔連接器的晶片測試架構,其中該同軸孔連接器係以焊錫或是黏著劑固接於電路板上。 In an embodiment of the wafer test architecture with an implantable coaxial connector, the coaxial connector is secured to the circuit board with solder or an adhesive.
本創作之實施例中,一種電路架構,包括:電路板,用以傳送一測試訊號,該電路板之中設有至少一通孔,該通孔相對應於該腳座的至少一腳位,並且該通孔的內壁面設有一導電層;以及一同軸孔連接器,包括一纜線區段以及一接頭,該纜線區段係插入於該通孔中並且該纜線區段的外表面與該導電層形成電性接觸,使該測試訊號由該纜線區段沿著一傳遞方向傳送至該接頭,以使該測試訊號由該電路板的第一表面傳送至第二表面,該通孔的兩端分別連接該第一表面以及該第二表面。 In an embodiment of the present invention, a circuit structure includes: a circuit board for transmitting a test signal, wherein the circuit board is provided with at least one through hole corresponding to at least one pin of the foot, and The inner wall surface of the through hole is provided with a conductive layer; and a coaxial hole connector includes a cable section and a joint, the cable section is inserted into the through hole and the outer surface of the cable section is The conductive layer forms an electrical contact such that the test signal is transmitted from the cable segment to the connector in a direction of transmission such that the test signal is transmitted from the first surface of the circuit board to the second surface, the through hole The two ends are respectively connected to the first surface and the second surface.
本創作之實施例中具有植入式同軸孔連接器的晶片測試架構之組裝方法,包括下列步驟:將一晶片電性插接於一腳座上,其中該腳 座設有複數腳位,並且該些腳位用以傳遞該晶片的測試訊號;將插接有該晶片的腳座電性連接一電路板,使該電路板傳送來自該些腳位的該測試訊號,其中該電路板之中設有至少一通孔,該通孔相對應於該腳座的至少一腳位,並且該通孔的內壁面設有一導電層;以及將一同軸孔連接器插入於該通孔以形成具有植入式同軸孔連接器的電路板,其中該同軸孔連接器包括一纜線區段以及一接頭,該纜線區段係插入於該通孔中並且該纜線區段的外表面與該導電層形成電性接觸,使該測試訊號由該纜線區段沿著一傳遞方向傳送至該接頭,以使該測試訊號由該電路板的第一表面傳送至第二表面,該通孔的兩端分別連接該第一表面以及該第二表面。 The method for assembling a wafer test architecture having an implantable coaxial connector in the embodiment of the present invention comprises the steps of: electrically inserting a wafer onto a foot, wherein the foot The socket is provided with a plurality of pins, and the pins are used to transmit the test signal of the chip; the socket to which the wafer is inserted is electrically connected to a circuit board, so that the circuit board transmits the test from the pins a signal, wherein the circuit board is provided with at least one through hole corresponding to at least one position of the foot, and the inner wall surface of the through hole is provided with a conductive layer; and a coaxial hole connector is inserted The through hole to form a circuit board having an implantable coaxial connector, wherein the coaxial hole connector includes a cable segment and a connector, the cable segment is inserted into the through hole and the cable region The outer surface of the segment is in electrical contact with the conductive layer, such that the test signal is transmitted from the cable segment to the connector in a transfer direction to transmit the test signal from the first surface of the circuit board to the second a surface, the two ends of the through hole are respectively connected to the first surface and the second surface.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之組裝方法,其中該導電層係以電鍍法形成於該通孔的內壁面。 In an embodiment of the method of assembling a wafer test structure having an implantable coaxial connector, the conductive layer is formed on the inner wall surface of the through hole by electroplating.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之組裝方法,其中該同軸孔連接器的纜線區段之形成方法包括下列步驟:形成一導線,以電性連接該腳座的至少一腳位,用以傳送該測試訊號;形成一絕緣部,用以包覆該導線,並且該絕緣部的一外表面沿著半徑方向係與該導線等距離;以及形成一接地屏蔽部於該絕緣部的該外表面上,以與該導線互相絕緣,以控制該測試訊號在該纜線區段的阻抗值。 In an embodiment of the method of assembling a wafer test structure having an implantable coaxial connector, the method of forming a cable segment of the coaxial connector includes the steps of: forming a wire to electrically connect the socket At least one pin for transmitting the test signal; forming an insulating portion for covering the wire, and an outer surface of the insulating portion is equidistant from the wire along a radial direction; and forming a ground shield The outer surface of the insulating portion is insulated from the wire to control the impedance value of the test signal in the cable segment.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之組裝方法,其中該纜線區段係將該導線、該絕緣部以及該接地屏蔽部結合之後,並且將結合的該導線、該絕緣部以及該接地屏蔽部之結構植入於該電路板的該通孔中。 In an embodiment of the method of assembling a wafer test structure having an implantable coaxial connector, wherein the cable segment is bonded to the wire, the insulating portion, and the ground shield, and the bonded wire, The insulating portion and the structure of the ground shield are implanted in the through hole of the circuit board.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之 組裝方法,其中該纜線區段的該導線係為實心導線。 In an embodiment of a wafer test architecture with an implantable coaxial connector An assembly method wherein the wire of the cable section is a solid wire.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之組裝方法,其中該電路板的該第一表面與該第二表面係為該電路板的上、下兩個相對異側之表面。 In an embodiment of the method for assembling a wafer test structure having an implantable coaxial connector, wherein the first surface and the second surface of the circuit board are upper and lower opposite sides of the circuit board. surface.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之組裝方法,其中該通孔的內壁面之該導電層係延伸至該電路板的第一表面以及第二表面上形成一導電部,以控制該纜線區段的阻抗值。 In an embodiment of the method of assembling a wafer test structure having an implantable coaxial connector, wherein the conductive layer of the inner wall surface of the via extends to the first surface and the second surface of the circuit board to form a conductive To control the impedance value of the cable segment.
在一實施例之具有植入式同軸孔連接器的晶片測試架構之組裝方法,其中該同軸孔連接器係以焊錫或是黏著劑固接於電路板上。 In an embodiment of the method of assembling a wafer test structure having an implantable coaxial connector, the coaxial connector is secured to the circuit board by solder or an adhesive.
200‧‧‧晶片 200‧‧‧ wafer
202‧‧‧腳座 202‧‧‧ feet
204‧‧‧電路板 204‧‧‧Circuit board
204a‧‧‧第一表面 204a‧‧‧ first surface
204b‧‧‧第二表面 204b‧‧‧second surface
205‧‧‧儀器設備 205‧‧‧ instruments
206‧‧‧腳位 206‧‧‧ feet
207‧‧‧導電部 207‧‧‧Electrical Department
208‧‧‧同軸孔連接器 208‧‧‧ coaxial hole connector
210‧‧‧通孔 210‧‧‧through hole
212‧‧‧內壁面 212‧‧‧ inner wall
213‧‧‧導電層 213‧‧‧ Conductive layer
214‧‧‧纜線區段 214‧‧‧ Cable section
218‧‧‧接頭 218‧‧‧ joint
220‧‧‧導線 220‧‧‧ wire
222‧‧‧絕緣部 222‧‧‧Insulation
224‧‧‧接地屏蔽部 224‧‧‧Ground shield
226‧‧‧外表面 226‧‧‧ outer surface
R‧‧‧距離 R‧‧‧ distance
S1‧‧‧測試訊號 S1‧‧‧ test signal
S600、S602、S604‧‧‧步驟 S600, S602, S604‧‧ steps
TD1‧‧‧傳遞方向 TD1‧‧‧Transfer direction
為了更清楚地說明本創作實施例中的技術方案,下面將對實施例描述中所需要使用的附圖作簡單地介紹:圖1繪示本創作實施例中具有植入式同軸孔連接器的晶片測試架構之示意圖。 In order to more clearly illustrate the technical solutions in the present embodiment, the drawings used in the description of the embodiments will be briefly described below. FIG. 1 illustrates an embodiment of the present invention with an implantable coaxial connector. Schematic diagram of the wafer test architecture.
圖2繪示本創作實施例中該通孔與同軸纜線區段結合形成的通孔同軸孔連接器之示意圖。 2 is a schematic view showing a through-hole coaxial hole connector formed by combining the through hole and the coaxial cable section in the embodiment of the present invention.
圖3繪示本創作實施例中同軸孔連接器之剖面示意圖。 3 is a cross-sectional view showing a coaxial hole connector in the present embodiment.
圖4繪示本創作實施例中晶片測試架構的電路板之通孔的示意圖。 4 is a schematic diagram of a through hole of a circuit board of a wafer test architecture in the present embodiment.
圖5繪示本創作實施例中同軸纜線區段之示意圖。 FIG. 5 is a schematic diagram of a coaxial cable section in the present embodiment.
圖6繪示本創作實施例中具有植入式同軸孔連接器的晶片測試架構之組裝方法之流程圖。 6 is a flow chart showing a method of assembling a wafer test architecture with an implantable coaxial connector in the present embodiment.
請參照圖式,其中相同的元件符號代表相同的元件或是相似的元件,本創作的原理是以實施在適當的運算環境中來舉例說明。以下的說明是基於所例示的本創作具體實施例,其不應被視為限制本創作未在此詳述的其它具體實施例。 Referring to the drawings, wherein like reference numerals refer to the same elements or the like elements, the principles of the present invention are illustrated by the implementation in a suitable computing environment. The following description is based on the illustrated embodiments of the present invention and should not be considered as limiting the other specific embodiments of the present invention that are not described herein.
參考圖1至圖3,圖1繪示本創作實施例中具有植入式同軸孔連接器208的晶片測試架構之示意圖;圖2繪示本創作實施例中該通孔210與纜線區段214結合形成的通孔同軸孔連接器208之示意圖;以及圖3繪示本創作實施例中同軸孔連接器208通孔之徑向剖面示意圖。如圖1所示,該晶片測試架構包括晶片200、腳座202、電路板204以及同軸孔連接器208,以藉由儀器設備205進行各種訊號的分析以及測量,以確認該晶片200的功能是否正常。該晶片200例如具有定功能的積體電路,具有複數針腳(未圖示),用以產生測試訊號S1;該腳座202具有複數腳位206,該些腳位206相對應電性連接該晶片200的針腳,以供該晶片200電性插接,使該些腳位206傳遞該晶片200的測試訊號S1;在一實施例中,晶片200依據測試需求,傳送不同的測試訊號S1至該腳座202的不同腳位206。電路板204電性連接該腳座202,用以傳送來自該些腳位206的該測試訊號S1,該電路板204之中設有至少一通孔210,該孔210相對應於該腳座202的至少一腳位206,並且該通孔210的內壁面212設有一導電層213。 1 to FIG. 3, FIG. 1 is a schematic diagram of a wafer test architecture with an implantable coaxial connector 208 in the present embodiment; FIG. 2 illustrates the through hole 210 and the cable segment in the present embodiment. 214 is a schematic diagram of a through hole coaxial hole connector 208 formed in combination; and FIG. 3 is a schematic cross-sectional view showing a through hole of the coaxial hole connector 208 in the present embodiment. As shown in FIG. 1, the wafer test architecture includes a wafer 200, a foot 202, a circuit board 204, and a coaxial connector 208 for performing various signal analysis and measurement by the instrument device 205 to confirm whether the function of the wafer 200 is normal. The chip 200 has, for example, a fixed-function integrated circuit having a plurality of pins (not shown) for generating a test signal S1; the pin 202 has a plurality of pins 206, and the pins 206 are electrically connected to the wafer. The pins of the 200 are electrically inserted into the chip 200, so that the pins 206 transmit the test signal S1 of the wafer 200; in an embodiment, the chip 200 transmits different test signals S1 to the foot according to the test requirements. Different feet 206 of the seat 202. The circuit board 204 is electrically connected to the foot 202 for transmitting the test signal S1 from the pins 206. The circuit board 204 is provided with at least one through hole 210 corresponding to the foot 202. At least one foot 206 is provided, and the inner wall surface 212 of the through hole 210 is provided with a conductive layer 213.
如圖1以及圖2所示,同軸孔連接器208包括一纜線區段214以及一接頭218,該纜線區段214係插入於該通孔210中並且該纜線區段214的外表面215與該導電層213形成電性接觸,使該測試訊號S1由該纜線區段 214沿著一傳遞方向TD1傳送至該接頭218,以使該測試訊號S1由該電路板204的第一表面204a傳送至第二表面204b,該通孔210的兩端分別連接該第一表面204a以及該第二表面204b。接頭218例如螺旋接頭,但不限於此。在一實施例中,該導電層213係以電鍍法形成於該通孔210的內壁面212。在一實施例中,該同軸孔連接器208係以焊錫或是黏著劑固接於電路板204上。本創作之具有植入式同軸孔連接器的晶片測試架構藉由同軸孔連接器208將測試訊號S1以最短路徑由電路板204的一表面傳送至另一表面,以減少測試訊號的功率耗損以及避免雜訊干擾。 As shown in FIGS. 1 and 2, the coaxial hole connector 208 includes a cable section 214 and a joint 218 into which the cable section 214 is inserted and the outer surface of the cable section 214. 215 is in electrical contact with the conductive layer 213, so that the test signal S1 is from the cable segment 214 is transmitted to the connector 218 along a transmission direction TD1, so that the test signal S1 is transmitted from the first surface 204a of the circuit board 204 to the second surface 204b, and the two ends of the through hole 210 are respectively connected to the first surface 204a. And the second surface 204b. The joint 218 is, for example, a screw joint, but is not limited thereto. In one embodiment, the conductive layer 213 is formed on the inner wall surface 212 of the through hole 210 by electroplating. In one embodiment, the coaxial via connector 208 is soldered to the circuit board 204 with solder or an adhesive. The wafer test architecture with the implanted coaxial connector of the present invention transmits the test signal S1 from one surface of the circuit board 204 to the other surface by the coaxial via connector 208 to reduce the power consumption of the test signal and Avoid noise interference.
如圖1以及圖2所示,該纜線區段214包括導線220、絕緣部222以及接地屏蔽部224。導線220電性連接該腳座220的至少一腳位206,用以傳送該測試訊號S1。絕緣部222用以包覆該導線220,並且該絕緣部222的一外表面226沿著半徑方向係與該導線220形成等距離R。接地屏蔽部224形成於該絕緣部222的該外表面226上,以與該導線220互相絕緣,以控制該測試訊號S在該纜線區段214的阻抗值。在一實施例中,本創作的纜線區段214係為一預定長度的同軸電纜,例如是電路板204的厚度,但不限於此。該纜線區段214的該導線220例如是實心導線,但不限於此,亦可為空心圓柱導體。 As shown in FIGS. 1 and 2, the cable section 214 includes a wire 220, an insulating portion 222, and a ground shield portion 224. The wire 220 is electrically connected to at least one pin 206 of the foot 220 for transmitting the test signal S1. The insulating portion 222 is used to cover the wire 220, and an outer surface 226 of the insulating portion 222 is equidistant from the wire 220 along a radial direction. The grounding shield 224 is formed on the outer surface 226 of the insulating portion 222 to be insulated from the wire 220 to control the impedance value of the test signal S at the cable segment 214. In one embodiment, the cable section 214 of the present invention is a predetermined length of coaxial cable, such as the thickness of the circuit board 204, but is not limited thereto. The wire 220 of the cable section 214 is, for example, a solid wire, but is not limited thereto, and may be a hollow cylindrical conductor.
參考圖4以及圖5,圖4繪示本創作實施例中晶片測試架構的電路板204之通孔210的示意圖;圖5繪示本創作實施例中纜線區段214之示意圖。該纜線區段214係將該導線220、該絕緣部222以及該接地屏蔽部224結合之後,並且將結合的該導線220、該絕緣部222以及該接地屏蔽部224之結構植入於該電路板204的該通孔210中。由於是將纜線區段214係將該導線220、該絕緣部222以及該接地屏蔽部224結合之後,再嵌入於通孔210中, 以貫通該電路板204,以簡化印刷電板之負載板製作通孔的步驟,有效降低晶片測試架構的生產成本。 Referring to FIG. 4 and FIG. 5, FIG. 4 is a schematic diagram of the through hole 210 of the circuit board 204 of the wafer testing architecture in the present embodiment. FIG. 5 is a schematic diagram of the cable section 214 in the present embodiment. The cable section 214 is formed by combining the wire 220, the insulating portion 222, and the ground shield portion 224, and the structure of the combined wire 220, the insulating portion 222, and the ground shield portion 224 is implanted in the circuit. The through hole 210 of the plate 204. Since the cable segment 214 is combined with the wire 220, the insulating portion 222, and the ground shield portion 224, and then embedded in the through hole 210, The step of making through holes through the circuit board 204 to simplify the load board of the printed circuit board effectively reduces the production cost of the wafer test architecture.
如圖1以及圖2所示,該電路板204的該第一表面204a與該第二表面204b係為該電路板204的上、下兩個相對異側之表面。該通孔210的內壁面212之該導電層213係延伸至該電路板204的第一表面204a以及第二表面204b上形成一導電部207,以控制該纜線區段214的阻抗值。 As shown in FIG. 1 and FIG. 2, the first surface 204a and the second surface 204b of the circuit board 204 are the upper and lower surfaces of the circuit board 204. The conductive layer 213 of the inner wall surface 212 of the through hole 210 extends to the first surface 204a and the second surface 204b of the circuit board 204 to form a conductive portion 207 for controlling the impedance value of the cable section 214.
參考圖1、圖2以及圖6,圖6繪示本創作實施例中具有植入式同軸孔連接器208的晶片測試架構之組裝方法之流程圖。 Referring to FIG. 1, FIG. 2 and FIG. 6, FIG. 6 is a flow chart showing a method of assembling a wafer test architecture with an implantable coaxial connector 208 in the present embodiment.
在步驟S600中,將一晶片電性插接於一腳座上。其中該腳座設有複數腳位,並且該些腳位用以傳遞該晶片的測試訊號。 In step S600, a wafer is electrically connected to a foot. The foot is provided with a plurality of pins, and the pins are used to transmit test signals of the wafer.
在步驟S602中,將插接有該晶片的腳座電性連接一電路板,使該電路板傳送來自該些腳位的該測試訊號。其中該電路板之中設有至少一通孔,該通孔相對應於該腳座的至少一腳位,並且該通孔的內壁面設有一導電層。在一實施例中,該導電層213係以電鍍法形成於該通孔210的內壁面212。在一實施例中,如圖1以及圖2所示,該電路板204的該第一表面204a與該第二表面204b係為該電路板204的上、下兩個相對異側之表面。該通孔210的內壁面212之該導電層213係延伸至該電路板204的第一表面204a以及第二表面204b上形成一導電部207,以控制該纜線區段214的阻抗值。 In step S602, the socket to which the wafer is inserted is electrically connected to a circuit board, so that the circuit board transmits the test signal from the pins. The circuit board is provided with at least one through hole corresponding to at least one position of the foot, and an inner layer of the through hole is provided with a conductive layer. In one embodiment, the conductive layer 213 is formed on the inner wall surface 212 of the through hole 210 by electroplating. In an embodiment, as shown in FIG. 1 and FIG. 2, the first surface 204a and the second surface 204b of the circuit board 204 are the upper and lower surfaces of the circuit board 204. The conductive layer 213 of the inner wall surface 212 of the through hole 210 extends to the first surface 204a and the second surface 204b of the circuit board 204 to form a conductive portion 207 for controlling the impedance value of the cable section 214.
在步驟S604中,將一同軸孔連接器插入於該通孔以形成具有植入式同軸孔連接器的電路板。該同軸孔連接器208的纜線區段214之形成方法包括下列步驟:形成導線220以電性連接該腳座220的至少一腳位 206,用以傳送該測試訊號S1。形成絕緣部222用以包覆該導線220,並且該絕緣部222的一外表面226沿著半徑方向係與該導線220形成等距離R。形成接地屏蔽部224於該絕緣部22的該外表面226上,以與該導線220互相絕緣,以控制該測試訊號S在該纜線區段214的阻抗值。執行步驟S604時,該纜線區段214係將該導線220、該絕緣部222以及該接地屏蔽部224結合之後,並且將結合的該導線220、該絕緣部222以及該接地屏蔽部224之結構植入於該電路板204的該通孔210中。在一實施例中,該同軸孔連接器208係以焊錫或是黏著劑固接於電路板204上。 In step S604, a coaxial connector is inserted into the through hole to form a circuit board having an implantable coaxial connector. The method for forming the cable section 214 of the coaxial connector 208 includes the steps of: forming a wire 220 to electrically connect at least one leg of the foot 220 206, for transmitting the test signal S1. An insulating portion 222 is formed to cover the wire 220, and an outer surface 226 of the insulating portion 222 is equidistant from the wire 220 along a radial direction. A grounding shield 224 is formed on the outer surface 226 of the insulating portion 22 to be insulated from the wire 220 to control the impedance value of the test signal S at the cable segment 214. When the step S604 is performed, the cable segment 214 is combined with the wire 220, the insulating portion 222, and the ground shield portion 224, and the combined wire 220, the insulating portion 222, and the ground shield portion 224 are combined. It is implanted in the through hole 210 of the circuit board 204. In one embodiment, the coaxial via connector 208 is soldered to the circuit board 204 with solder or an adhesive.
綜上所述,本創作之具有植入式同軸孔連接器的晶片測試架構,藉由同軸孔連接器將測試訊號以最短路徑由電路板的一表面傳送至另一表面,以減少測試訊號的功率耗損以及避免雜訊干擾,並且以簡化印刷電板之負載板製作通孔的步驟,以降低晶片測試架構的生產成本。 In summary, the wafer test architecture of the present invention has an implantable coaxial connector, wherein the test signal is transmitted from one surface of the circuit board to the other surface in the shortest path by the coaxial connector to reduce the test signal. Power consumption and avoidance of noise interference, and the steps of making vias to simplify the load board of the printed board to reduce the production cost of the wafer test architecture.
雖然本創作已用較佳實施例揭露如上,然其並非用以限定本創作,本創作所屬技術領域中具有通常知識者,在不脫離本創作之精神和範圍內,當可作各種之更動與潤飾,因此本創作之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make various changes without departing from the spirit and scope of the present invention. Retouching, therefore, the scope of protection of this creation is subject to the definition of the scope of the patent application attached.
204‧‧‧電路板 204‧‧‧Circuit board
204a‧‧‧第一表面 204a‧‧‧ first surface
204b‧‧‧第二表面 204b‧‧‧second surface
207‧‧‧導電部 207‧‧‧Electrical Department
208‧‧‧同軸孔連接器 208‧‧‧ coaxial hole connector
210‧‧‧通孔 210‧‧‧through hole
212‧‧‧內壁面 212‧‧‧ inner wall
213‧‧‧導電層 213‧‧‧ Conductive layer
214‧‧‧纜線區段 214‧‧‧ Cable section
218‧‧‧接頭 218‧‧‧ joint
220‧‧‧導線 220‧‧‧ wire
222‧‧‧絕緣部 222‧‧‧Insulation
224‧‧‧接地屏蔽部 224‧‧‧Ground shield
226‧‧‧外表面 226‧‧‧ outer surface
S1‧‧‧測試訊號 S1‧‧‧ test signal
TD1‧‧‧傳遞方向 TD1‧‧‧Transfer direction
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