TWM514034U - Switch driving circuit capable of saving fan processor timer - Google Patents

Description

Switch drive circuit capable of saving timer of fan processor

The present invention relates to a fan motor control circuit, and more particularly to a switch drive circuit having a cost-saving fan processor-saving timer.

With the advancement of technology and the development of the computer industry, lightweight electronic products, such as notebook computers, have become the mainstream of the market. In this thin and short electronic product, the heat dissipation capability often affects the stability of the system, the performance of the product, and even the service life of the product. In the case of a computer system, in order to enable the thermal energy generated by the computer system to be quickly dissipated, the computer system is usually equipped with a fan as a heat sink to enable the computer system to operate normally under an appropriate temperature environment.

Generally, a fan used in a computer system for heat dissipation is driven by a brushless DC motor. Referring to FIG. 1 , the conventional DC fan motor driving circuit includes a processor 5 (micro control unit; MCU), two upper PMOS transistors 61 and 62, and two lower NMOS transistors 63 and 64. The processor 5 has a plurality of pins and a plurality of timers 50. The first and second pins 51 and 52 of the processor 5 are electrically connected to the two PMOS transistors 61 and 62 of the upper arm, respectively. And the two pins 51 and 52 respectively transmit a first pulse width modulation (PWM) signal and a second pulse width modulation (PWM) signal, and the first and second pulse width modulation signals are the same. A third and fourth pins 53 and 54 of the processor 5 are electrically connected to the two NMOS transistors 63 and 64 of the lower arm, respectively, and the third and fourth pins 63 and 64 of the processor are corresponding to the timer. 50. The third and fourth pins 63 and 64 are respectively configured to output a first high frequency pulse modulation (PWM) signal modulated by the timers 50 and a second high frequency pulse wave modulation. (PWM) signal. Therefore, the first pulse width modulation signal and the second high frequency pulse modulation signal and the second pulse width modulation signal and the first high frequency pulse modulation signal are used to drive four full bridge switches (ie, the upper arm two The PMOS transistors 61, 62 and the lower arm two NMOS transistors 63, 64) control the speed and operation of the DC fan motor. The two PMOS transistors 61 and 62 of the upper arm are respectively connected to the one end 71 and the other end 72 of the corresponding motor coil between the two NMOS transistors 63 and 64 corresponding to the lower arm.

The speed of the fan adjustment speed is determined by the internal cutting pulse duty cycle (Duty cycle) of the first and second high frequency pulse modulation signals, and the frequency of the internal cutting pulse wave is generally greater than 20KHZ (hertz). Therefore, the output precision of the first and second high-frequency pulse modulation signals is high, so that the output precision of the first high-frequency pulse modulation signal needs to be modulated by the timer 50 of the processor 5 corresponding to the third pin 53. The output precision of the second high-frequency pulse modulation signal also needs to be modulated by the processor 5 corresponding to another timer 50 of the fourth pin 54; in other words, the lower arm of the motor drive circuit of the conventional single fan is two The NMOS transistors 63 and 64 must be used to support the two pins 53 and 54 of the timer 50 in order to modulate the first and second high-frequency pulse signals with high output accuracy.

However, the conventional processor 5 has a limited number of pins corresponding to the timer 50. The number of timers 50 in the processor 5 of FIG. 1 is only enough to support two pins (ie, the third and fourth pins 53, 54), the two pins 53, 54 have been used to connect the two NMOS transistors 63, 64 corresponding to the lower arm, so that the processor 5 does not have a redundant timer 51 to support the corresponding pin, so it is known that the timer 50 is required. When the number is more, the processor 50 with a larger number of timers 50 must be selected, but the relative cost will increase greatly, and the size of the body package will also increase, which is also not conducive to fan design optimization, for example, if the customer proposes for the fan For special functions (such as virtual speed, etc.), the fan design will encounter a shortage of the usual processor 5 timer 50.

Therefore, how to solve the above problems and problems in the past, that is, the creators of the case and the relevant manufacturers engaged in this industry are eager to study the direction of improvement.

Therefore, in order to effectively solve the above problems, the main purpose of the present invention is to provide a switch drive circuit having a fan-saving timer that saves cost.

Another object of the present invention is to provide a switch drive circuit having a processor-saving timer that saves the use of an in-processor timer and facilitates fan design.

To achieve the above objective, the present invention provides a switch driving circuit for saving a fan processor timer, which is applied to a processor, the switch driving circuit includes a plurality of upper arm switch components, a plurality of lower arm switch components, and a first a driving control unit and a second driving control unit, wherein the upper arm switching components are driven by a first pulse width modulation signal and a second pulse width modulation signal, and the lower arm switching components are corresponding to the upper arm switching components Electrically connected, the first driving control unit is electrically connected to a lower arm switch assembly of the lower arm switch assembly, and the first drive control unit receives a third pulse width modulation signal and a high frequency pulse The second modulation control unit is electrically connected to the other lower arm switch assembly of the lower arm switch assembly, and the second drive control unit receives the third pulse width modulation signal and the high a frequency pulse modulation signal, wherein the first pulse width modulation signal is at a high level and triggers an upper arm switch component to be turned on, the second drive control list Receiving the third pulse width modulation signal to a low level, receiving the high frequency pulse modulation signal output trigger is turned on relative to the other lower arm switch component, and the second pulse width modulation signal is a high level And triggering the other upper arm switch component to be turned on, and the first drive control unit receives the third pulse width modulation signal to a high level, and then receives the high frequency pulse wave modulation signal output trigger relative to the lower arm The switch component is turned on; through the design of the switch drive circuit, the use of the timer in the processor can be effectively saved, thereby achieving a cost-saving effect and benefiting the fan design.

1, 1'‧‧‧ switch drive circuit

111‧‧‧First upper arm switch assembly

112‧‧‧Second upper arm switch assembly

113‧‧‧Third upper arm switch assembly

114‧‧‧Four upper arm switch assembly

1111, 1121, 1131, 1141‧‧‧ first end

1112, 1122, 1132, 1142‧‧‧ second end

1113, 1123, 1133, 1143‧‧‧ third end

131‧‧‧First lower arm switch assembly

132‧‧‧Second lower arm switch assembly

133‧‧‧ Third Lower Arm Switch Assembly

134‧‧‧4th lower arm switch assembly

First end, 1311, 1321, 1331, 1341‧‧

1312, 1322, 1332, 1342‧‧‧ second end

1313, 1323, 1333, 1343, ‧ third end

14‧‧‧First Drive Control Unit

15‧‧‧Second drive control unit

16‧‧‧ Third drive control unit

17‧‧‧Fourth drive control unit

2‧‧‧ Processor

20‧‧‧Timer

21‧‧‧First pin

22‧‧‧second pin

23‧‧‧ third pin

24‧‧‧fourth pin

25‧‧‧ fifth pin

26‧‧‧ sixth pin

27‧‧‧ seventh pin

28‧‧‧8th pin

29‧‧‧ ninth pin

210‧‧‧10th pin

211‧‧‧ eleventh pin

212‧‧‧Twelfth pin

213‧‧‧13th pin

31, 32‧‧‧ fans

311, 321‧‧ ‧ one end of the motor coil

312, 322‧‧ ‧ the other end of the motor coil

314, 324‧‧‧ Hall element

33‧‧‧Circuit board

41‧‧‧First current limiting amplifier

42‧‧‧Second current limiting amplifier

Q1‧‧‧First transistor

Q2‧‧‧Second transistor

Q3‧‧‧ Third transistor

Q4‧‧‧4th transistor

Q5‧‧‧ fifth transistor

R1'‧‧‧First Drive Resistor

R2'‧‧‧second drive resistor

R3'‧‧‧ third drive resistor

R4'‧‧‧fourth drive resistor

R5'‧‧‧ fifth drive resistor

M1‧‧‧First MOS transistor

M2‧‧‧Second MOS transistor

M3‧‧‧ Third MOS transistor

M4‧‧‧4th MOS transistor

R1‧‧‧first resistance

R2‧‧‧second resistance

R3‧‧‧ third resistor

R4‧‧‧fourth resistor

R5‧‧‧ fifth resistor

R6‧‧‧ sixth resistor

R7‧‧‧ seventh resistor

R8‧‧‧ eighth resistor

R9‧‧‧ ninth resistor

R10‧‧‧10th resistor

R11‧‧‧ eleventh resistor

C1‧‧‧first capacitor

C2‧‧‧second capacitor

C3‧‧‧ third capacitor

C4‧‧‧fourth capacitor

Vin‧‧‧Input voltage

Vc‧‧‧ operating voltage

Vcc‧‧‧ working voltage

GND‧‧‧ ground terminal

Figure 1 is a schematic diagram of a conventional block.

Figure 2 is a block diagram of a first preferred embodiment of the preferred embodiment of the present invention.

Figure 3 is a block diagram showing another preferred embodiment of the preferred embodiment of the present invention.

Figure 4 is a circuit diagram of a first preferred embodiment of the preferred embodiment of the present invention.

Figure 5 is a block diagram showing another preferred embodiment of the preferred embodiment of the present invention.

Figure 6 is a block diagram of a second preferred embodiment of the preferred embodiment of the present invention.

Figure 7 is another block diagram of a second preferred embodiment of the preferred embodiment of the present invention.

Figure 8A is an exploded perspective view of a second preferred embodiment of the preferred embodiment of the present invention.

Figure 8B is a perspective view showing the combination of the second preferred embodiment of the preferred embodiment of the present invention.

Figure 9 is another block diagram of a second preferred embodiment of the preferred embodiment of the present invention.

The above object of the present invention, as well as its structural and functional features, will be described in accordance with the preferred embodiments of the drawings.

The present invention provides a switch driving circuit for saving a timer of a fan processor. Referring to FIGS. 2 and 3, a block diagram of a first preferred embodiment of the present invention is shown; the switch driving circuit 1 is applied to In a processor 2 of a fan 31, the processor 2 is described in the preferred embodiment by a microprocessor 2 (MCU), but is not limited thereto. The switch drive circuit 1 includes a plurality of upper arm switch assemblies, a plurality of lower arm switch assemblies, a first drive control unit 14 and a second drive control unit 15, and the upper arm switch assemblies are modulated by a first pulse width (Pulse) The Width Modulation; PWM) signal is driven by a second Pulse Width Modulation (PWM) signal.

The plurality of upper arm switch assemblies 111 have a first upper arm switch assembly 111 and a second upper arm switch assembly 112. The first and second upper arm switch assemblies 111 and 112 each have a first end 1111, 1121 and a second end 1112. The first end 1111 of the first upper arm switch assembly 112 is electrically connected to the first end 1121 of the second upper arm switch assembly 112 and an input voltage Vin. The first upper arm switch assembly 111 is connected to the first end 1111 and the first end 1111, 1123. The second end 1112 receives the first pulse width modulation signal, the second end 1122 of the second upper arm switch component 112 receives the second pulse width modulation signal, and the first and second upper arm switch components 111, 112 The third ends 1113 and 1123 are electrically connected to opposite ends 311 and 312 of the motor coil of the fan 31, respectively.

The lower arm switch assemblies are electrically connected to the corresponding upper arm switch assemblies, and the lower arm switch assemblies have a first lower arm switch assembly 131 and a second lower arm switch assembly 132, the first and second The lower arm switch assemblies 131 and 132 each have a first end 1311, 1321, a second end 1312, 1322 and a third end 1313, 1323. The first end 1311 of the first and second lower arm switch assemblies 131, 132 The first end of the first lower arm switch assembly 131 is electrically connected (or coupled) to the third end 1113 of the first upper arm switch assembly 111 and the third end 1123 of the second upper arm switch assembly 112. 1312 is electrically connected to the first driving control unit 14 . The third end 1313 of the first lower arm switch assembly 131 is electrically connected to the third end 1323 of the second lower arm switch assembly 132 . The second lower arm The second end 1322 of the switch assembly 132 is electrically connected to the second drive control unit 15.

The first driving control unit 14 is electrically connected to the lower arm switch assembly (ie, the first lower arm switch assembly 131) of the lower arm switch assembly, and the first drive control unit 14 receives a third pulse. a Pulse Width Modulation (PWM) signal and a Pulse Width Modulation (PWM) signal, the high frequency pulse modulation signal being a plurality of timers 20 included in the processor 2 The output of the timer 20 is modulated, in other words, the output precision of the high-frequency pulse-modulated signal is modulated by a timer 20 in the processor 2, so that the frequency of the high-frequency pulse-modulated signal is (Frequency) The duty cycle is accurate, and the size of the fan 31 to adjust the speed depends on the internal cutting pulse duty ratio of the high frequency pulse modulation signal output. And the first and second pulse width modulation signals are the same as the third pulse width modulation signal, that is, the frequencies of the first, second and third pulse width modulation signals are the same, and the first, second and third pulse width adjustments The frequency of the variable signal is the same as the frequency at which a Hall element 314 connected to the processor 2 outputs a Hall signal, and the high frequency pulse modulated signal is different from the first, second and third pulse width modulated signals, that is, the frequency is high. The frequency of the frequency pulse modulation signal is different from the frequency of the first, second and third pulse width modulation signals.

Referring to FIG. 3, the second driving control unit 15 is electrically connected to another lower arm switch assembly (ie, the second lower arm switch assembly 132) opposite to the lower arm switch assemblies, and the second drive control is The unit 15 receives the third pulse width modulation signal and the high frequency pulse modulation signal. Therefore, when the first pulse width modulation signal is at a high level and one of the upper arm switch assemblies (ie, the first upper arm switch assembly 111) is turned on, the second drive control unit 15 receives the third pulse width modulation signal as When the low level is low, the second driving control unit 15 receives the high frequency pulse modulation signal output trigger to be turned on relative to the other lower arm switch assembly (ie, the second lower arm switch assembly 132). The second upper arm switch assembly 112 and the first lower arm switch assembly 131 are in an off state (ie, not turned on); if the first pulse width modulation signal is from a high level to a low level, the first upper arm switch unit 111 is turned off. At this time, the second pulse width modulation signal is at a high level to trigger the other upper arm switch assembly (ie, the second upper arm switch assembly 112) to be turned on, and the first drive control unit 14 receives the third pulse width modulation. When the variable signal is at a high level, the first driving control unit 14 receives the high frequency pulse modulation signal output trigger relative to the lower arm switch assembly (ie, the first lower arm switch assembly 131). The second Switch arm assembly 132 is in the OFF state (i.e., not conducting), whereby the above-described embodiment conduction operation of the fan motor 31 and fan 31 to control motor speed.

The foregoing processor 2 is illustrated by a 16 pin (pin) in the preferred embodiment, but is not limited thereto, and other such as 10 pin, 12 pin, and 24 pin may also be applied to the present invention. The processor 2 has a plurality of pins and the plurality of timers 20, wherein a first pin 21 is coupled to the second end 1112 of the first upper arm switch assembly 111, and the first pin 21 is configured to output the first The second pin 22 is coupled to the second end 1122 of the second upper arm switch assembly 112. The second pin 22 is configured to output the second pulse width modulation signal, and a third pin. The first and second driving control units 14 and 15 are coupled to the first and second driving control units 14 and 15 for outputting the third pulse width modulation signal, and a fourth pin 24 is coupled to the first and second driving control units 14 . The fifth pin 24 is configured to output a high frequency pulse modulation signal modulated by a corresponding one of the timers 20. A fifth pin 25 is coupled to the Hall element 314, and the fifth pin 25 is used. The receiving Hall element 314 senses the Hall signal generated by the rotor position of the fan 31, a sixth pin 26 corresponds to the other timer 20, and the sixth pin 26 is not connected to the upper and lower arm switches. The components 11 and 13 and the first and second driving control units 14 and 15 are coupled (or electrically connected), and the six pins can be outputted through corresponding ones. Another timer 20 modulated high-frequency pulse modulation (Pulse Width Modulation; PWM) signal. A thirteenth pin 213 of the processor 2 is configured to receive a stable operating voltage Vcc (eg, 5 volts) provided by the input voltage Vin.

The number of the timers 20 of the processor 2 of the fan 31 of the preferred embodiment is to support two pins (ie, the fourth and sixth pins 24, 26), and the remaining pins (ie, the first pins) The timers 20 are not supported by the three pins 21 to 23 and the fifth pin 25 and the seventh pin to the sixteenth pin 27 to 216. However, the present invention is not limited thereto. Therefore, the fan 31 of the present invention only needs to output the high frequency pulse modulation signal to drive the first lower arm switch component 131 or the second lower arm switch component by using the fourth pin 24 corresponding to a timer 20 in the processor 2. 132, and the sixth pin 26 of the processor 2 can be provided to another fan having the plurality of lower arm switch assemblies of the switch drive circuit 1 of the present invention, or the sixth pin 26 can also be used for the fan 31. There are special features (such special functions need to rely on the timer 20 to complete) the use of demand, such as virtual speed. Therefore, the design of the switch driving circuit 1 is such that the speed adjustment function of the fan 31 only needs to spend the resources of a timer 20 in the processor 2, and the normal rotation speed can be adjusted, and the processor 2 timer 20 can be effectively saved. Use, as well as cost savings and optimized design of the fan 31 design.

Please refer to the 4th figure, and refer to the 3rd figure, which will explain in detail about each structure:

The first driving control unit 14 is provided with a first transistor Q1, a first driving resistor R1' and a second driving resistor R2'. The first transistor Q1 is BJT (Bipolar Junction Transistor) in the preferred embodiment. The transistor is described, but is not limited thereto; the first transistor Q1 has a base terminal, an emitter terminal and an collector terminal, and one end of the first driving resistor R1' is coupled to the first transistor Q1. The collector terminal is connected to the fourth pin 24 of the processor 2, and the collector terminal of the first transistor Q1 is configured to receive the high frequency pulse modulation signal, and the other end of the first driving resistor R1' is coupled to the first terminal. a grounding terminal GND, one end of the second driving resistor R2' is coupled to the base terminal, and the other end of the second driving resistor R2' is coupled to the third pin 23 of the processor 2, the second driving resistor R2 The other end of the ' is for receiving the third pulse width modulation signal, and the emitter end of the first transistor Q1 is coupled to the second end of the first lower arm switch block.

The second driving control unit 15 is provided with a second transistor Q2, a third transistor Q3, a third driving resistor R3', a fourth driving resistor R4' and a fifth driving resistor R5'. The three-electrode is described in the preferred embodiment by a BJT (Bipolar Junction Transistor) transistor, but is not limited thereto; the second and third transistors each have a base extreme, an emitter extreme, and an extreme set. The base of the second transistor Q2 is coupled to the terminal of the third transistor Q3 and one end of the third driving resistor R3'. The collector of the second transistor Q2 is coupled to the fourth driving resistor R4'. One end of the second pin 24 of the processor 2, and the collector terminal of the second transistor Q2 is configured to receive the high frequency pulse modulation signal, the other end of the fourth driving resistor R4' and the third The emitter of the transistor Q3 is coupled to the ground GND, the emitter of the second transistor Q2 is coupled to the second end of the second lower arm switch, and the other end of the third resistor R3 is coupled. Connected to an operating voltage Vc (eg, 5 volts), the base of the third transistor Q3 is coupled to the fifth driving resistor R5' The other end of the fifth driving resistor R5' is coupled to the third pin 23 of the processor 2, and the other end of the fifth driving resistor R5' is configured to receive the third pulse width modulation signal.

The first upper arm switch module 111 is provided with a first MOS transistor M1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth transistor Q4 and a first capacitor C1. The first MOS transistor M1 is described in the preferred embodiment as a P-type metal oxide half field effect (PMOS) transistor, but is not limited thereto; the first MOS transistor M1 has a gate terminal and a source. In an extreme and an extreme, the gate of the first MOS transistor M1 is coupled to one end of the first capacitor C1 and one end of the first resistor R1 and one end of the second resistor R2. The first MOS transistor M1 The first terminal 1111 of the first upper arm switch module 111 is coupled to the other end of the first capacitor C1 and the other end of the first resistor R1 and the input voltage Vin, the first MOS transistor M1 The source terminal (ie, the third end 1113 of the first upper arm switch assembly 111) is coupled to one end 311 of the motor coil of the fan 31. The fourth transistor Q4 is described in the preferred embodiment by a BJT (Bipolar Junction Transistor) transistor, but is not limited thereto; the fourth transistor Q4 has a base terminal, an emitter terminal, and an episode terminal. The fourth transistor Q4 is coupled to the other end of the second resistor R2. The emitter of the fourth transistor Q4 is coupled to the ground GND. The base of the fourth transistor Q4 is coupled to the terminal. One end of the third resistor R3, the other end of the third resistor R3 (ie, the second end of the first upper arm switch assembly 111) is coupled to the first pin 21 of the processor 2, and the other end of the third resistor R3 The system is configured to receive the first pulse width modulation signal.

In the fourth embodiment, the second upper arm switch assembly 112 is provided with a second MOS transistor M2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fifth transistor Q5, and a second capacitor. C2, the second MOS transistor M2 is described in the preferred embodiment as a P-type metal oxide half field effect (PMOS) transistor, but is not limited thereto; the second MOS transistor M2 has a gate The terminal of the second MOS transistor M2 is coupled to one end of the second capacitor C2 and one end of the fourth resistor R4 and one end of the fifth resistor R5. The second MOS is connected to the terminal. The second terminal of the second capacitor C2 is coupled to the other end of the second capacitor C2 and the other end of the fourth resistor R4 and the input voltage Vin, the second MOS. The source terminal of the transistor M2 (ie, the third end 1123 of the second upper arm switch assembly 112) is coupled to the other end 312 of the motor coil of the fan 31, and the fifth transistor Q5 is BJT (in the preferred embodiment). Bipolar Junction Transistor) is described, but not limited thereto; the fifth transistor Q5 has a base terminal and an emitter And an extreme set of the fifth transistor Q5 is coupled to the other end of the fifth resistor R5. The emitter of the fifth transistor Q5 is coupled to the ground GND, and the base of the fifth transistor Q5 is extremely coupled. Connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 (ie, the second end 1122 of the second upper arm switch assembly 112) is coupled to the second pin 22 of the processor 2, the sixth resistor The other end of R6 is for receiving the aforementioned second pulse width modulation signal.

The first lower arm switch assembly 131 is provided with a third MOS transistor M3, a seventh resistor R7, an eighth resistor R8 and a third capacitor C3. The third MOS transistor M3 is in the preferred embodiment. An N-type metal oxide half field effect (NMOS) transistor is described, but is not limited thereto; the third MOS transistor M3 has a gate terminal, a source terminal and a terminal electrode, and the third MOS transistor M3 The extreme end (ie, the first end 1311 of the first lower arm switch assembly 131131) is coupled to the one end 311 of the motor coil and the source terminal of the first MOS transistor M1, and the gate terminal of the third MOS transistor M3 An end of the third capacitor C3 is coupled to one end of the seventh and eighth resistors, and the other end of the eighth resistor R8 is coupled to the other end of the third capacitor C3 and the ground GND, and the seventh resistor R7 The other end (the second end of the first lower arm switch assembly 131) is coupled to the emitter end of the first transistor Q1 of the first drive control unit 14, and the source terminal of the third MOS transistor M3 ( The third end of the first lower arm switch assembly 131 is coupled to one end of a ninth resistor R9, and the other of the ninth resistor R9 Coupled to the ground terminal GND.

The second lower arm switch assembly 132 is provided with a fourth MOS transistor M4, a tenth resistor R10, an eleventh resistor R11 and a fourth capacitor C4. The fourth MOS transistor M4 is in the preferred embodiment. The description is made by an N-type metal oxide half field effect (NMOS) transistor, but is not limited thereto; the fourth MOS transistor M4 has a gate terminal, a source terminal and a terminal electrode, and the fourth MOS transistor The extreme end of M4 (ie, the first end 1321 of the second lower arm switch assembly 132) is coupled to the other end 312 of the motor coil and the source terminal of the second MOS transistor M2, and the fourth MOS transistor M4 The gate is coupled to one end of the fourth capacitor C4 and one end of the tenth and eleventh resistors, and the other end of the tenth resistor R10 is coupled to the other end of the fourth capacitor C4 and the ground GND, and the tenth The other end of the resistor R11 (the second end of the second lower arm switch assembly 132) is coupled to the emitter end of the second transistor Q2 of the second drive control unit 15, and the source of the fourth MOS transistor M4 The terminal (the third end of the second lower arm switch assembly 132) is coupled to the end of the ninth resistor R9 and the third MOS transistor M3. Extreme.

In addition, in a specific implementation, the third ends 1313, 1323 of the first and second lower arm switch assemblies 131, 132 and the processor 2 may have a first current limiting amplifier 41 (as shown in FIG. 5). One end of the first current limiting amplifier 41 is electrically connected to the third ends 1313 and 1323 of the first and second lower arm switch assemblies 131 and 132. The other end of the first current limiting amplifier 41 is electrically connected to the processor 2 A seventh pin 27.

Therefore, through the design of the switch driving circuit 1 of the present invention, the use of the timer 20 in the processor 2 can be effectively saved, thereby achieving the cost-saving effect and benefiting the design of the fan 31.

Please refer to FIG. 6 and FIG. 7 for a block diagram showing a second preferred embodiment of the present invention, and supplemented with reference to FIGS. 8A and 8B; the preferred embodiment is mainly the first preferred embodiment. The switch drive circuit 1 is applied to two fans 31, 32 (such as a series fan), and the two fans 31, 32 share the same processor 2, and the switch drive circuits 1, 1' of the two fans 31, 32. Cooperating with the processor 2 on a circuit board 33, and the circuit board 33 is disposed between the bottoms of the two fans 31, 32, that is, the two fans 31, 32 each have the first preferred implementation described above. The switch drive circuit 1 of the example, and the structure and connection relationship of the switch drive circuits 1 and 1' of the two fans 31 and 32 and the functions thereof are the same as those of the switch drive circuit 1 of the first preferred embodiment, and will not be described again herein. . The structure and connection relationship between the switch driver circuit 1 of one of the fans 31 and the processor 2 are the same as those of the processor 2 connected to the switch driver circuit 1 of the first preferred embodiment, and therefore will not be described again. The switch drive circuit 1' of the other fan 32 has a third upper arm switch assembly 113, a fourth upper arm switch assembly 114, a third lower arm switch assembly 133, a fourth lower arm switch assembly 134, and a third drive. The control unit 16 and a fourth driving control unit 17 respectively have a first end 1131, 1141, a second end 1132, 1142 and a third end 1133, 1143. The first end 1131 of the third upper arm switch assembly 113 is electrically coupled to the first end 1141 of the fourth upper arm switch assembly 114 and the input voltage Vin. The second end 1132 of the third upper arm switch assembly 113 is coupled to the processor 2 A ninth pin 29 is provided for outputting the fourth pulse width modulation (PWM) signal to the second end 1132 of the third upper arm switch assembly 113.

The second end of the fourth upper arm switch assembly 114 is coupled to a tenth pin 210 of the processor 2, and the tenth pin 210 is configured to output the fifth pulse width modulation (Pulse Width Modulation; PWM) The signal is transmitted to the second end of the fourth upper arm switch assembly 114, and the third ends 1133, 1143 of the third and fourth upper arm switch assemblies are electrically connected to one end 321 of the motor coil of the other fan 32, respectively. One end 322. The third and fourth lower arm switch assemblies each have a first end 1331, 1341, a second end 1332, 1342, and a third end 1333, 1343. The first end 1331 of the third and fourth lower arm switch assemblies 1341 is electrically connected (or coupled) to the third end 1131 of the third upper arm switch assembly 113 and the third end 1143 of the fourth upper arm switch assembly 114, and the second end 1332 of the third lower arm switch assembly 133 The third driving end of the third lower arm switch assembly 133 is electrically connected to the third end 1343 of the fourth lower arm switch assembly 134, and the fourth lower arm is electrically connected. The second end 1342 of the switch assembly 134 is electrically connected to the fourth drive control unit 17. The structure and connection relationship of the third and fourth upper arm switch assemblies 113 and 114 of the preferred embodiment are the same as those of the first and second upper arm switch assemblies 111 and 112, and the third and fourth lower arm switches are the same. The structures and connection relationships of the components 133 and 134 and their functions are the same as those of the first and second lower arm switch assemblies 131 and 132, and therefore will not be described again.

The processor 2 and its internal complex timer 20 in the preferred embodiment only support two pins (ie, the fourth and sixth pins 24, 26) and are the same as the processor 2 of the first preferred embodiment. Repeat again. The sixth pin 26 of the processor 2 is electrically connected to the third and fourth driving control units 16, 17 of the switch driving circuit 1' of the other fan 32, and the sixth pin 26 is used for outputting corresponding Another high frequency Pulse Width Modulation (PWM) signal modulated by the timer 20 is transmitted to the third and fourth drive control units, respectively. An eighth pin 28 of the processor 2 is coupled to the third and fourth driving control units, and the eighth pin 28 is configured to output the sixth pulse width modulation (PWM) signal, respectively Transfer to the third and fourth drive control units. The structures, the connection relationships, the executions, and the functions of the third and fourth drive control units 16, 17 of the preferred embodiment are the same as those of the first and second drive control units 14, 15 and will not be described again.

The eleventh pin 211 of the processor 2 is coupled to another Hall element 324 for receiving the other Hall element 324 to sense the rotor position of the other fan 32. A Hall signal. In addition, in a specific implementation, in the ninth diagram, the third end 1313, 1323 of the first and second lower arm switch assemblies 131, 132 and the processor 2 may have the first current limiting amplifier 41, the first A third current limiting amplifier 42 may be disposed between the third ends 1333 and 1343 of the third and fourth lower arm switch assemblies 133 and 134, and the second current limiting amplifier 42 is electrically connected to the third end. The third ends 1333 and 1343 of the four lower arm switch assemblies 133 and 134 are electrically connected to a twelfth pin 212 of the processor 2 at the other end of the second current limiting amplifier 42. The fourth and fifth pulse width modulation signals are the same as the sixth pulse width modulation signal, that is, the frequencies of the fourth, fifth and sixth pulse width modulation signals are the same, and the fourth, fifth and sixth pulse widths are further The frequency of the modulation signal is also the same as the frequency of the Hall signal of the other Hall element 324, and the other high frequency pulse modulation signal is different from the fourth, fifth, and sixth pulse width modulation signals, that is, another The frequency of a high frequency pulse modulation signal is different from the frequency of the fourth, fifth and sixth pulse width modulation signals.

Therefore, when the first pulse width modulation signal is at a high level and the first upper arm switch assembly 111 is turned on, and the second drive control unit 15 receives the third pulse width modulation signal at a low level, the first The second driving control unit 15 receives the high frequency pulse modulation signal output triggering to be turned on with respect to the second lower arm switching component 132. At this time, the second upper arm switching component 112 and the first lower arm switching component 131 are in an off state ( That is, when the fourth pulse width modulation signal is at a high level, the third upper arm switching component 113 is turned on, and the fourth driving control unit 17 receives the sixth pulse width modulation signal at a low level. The fourth driving control unit 17 receives the other high frequency pulse modulation signal output trigger to be turned on relative to the fourth lower arm switch assembly 134, and the fourth upper arm switch assembly 114 and the third lower arm switch at this time. Component 133 is in an off state (ie, not conducting).

If the first pulse width modulation signal is switched from the high level to the low level, the first upper arm switch component 111 is in an off state, and the second pulse width modulation signal is at a high level to trigger the second upper arm switch component 112. When the first driving control unit 14 receives the third pulse width modulation signal to a high level, the first driving control unit 14 receives the high frequency pulse wave modulation signal output triggering relative to the first The lower arm switch assembly 131 is turned on. At this time, the second lower arm switch assembly 132 is in an off state (ie, not turned on), and the fourth pulse width modulation signal is switched from a high level to a low level, so that the third upper arm switch The component 113 is in an off state. At this time, the fifth pulse width modulation signal is at a high level to trigger the fourth upper arm switch component 114 to be turned on, and the third driving control unit 16 receives the sixth pulse width modulation signal is high. When the position is correct, the third driving control unit 16 receives the other high frequency pulse modulation signal output trigger to be turned on with respect to the third lower arm switch assembly 133, and the fourth lower arm switch assembly 134 is turned off. status( In this way, the motors of the two fans 31 and 32 can be simultaneously turned on and the motor speeds of the two fans 31 and 32 can be controlled simultaneously (or synchronously), in other words, the two fans 31 and 32 are respectively provided with The switch drive circuit 1, 1' of the present invention is designed such that the motor operation of the two fans 31, 32 can be simultaneously controlled by a single processor 2, and by the fourth and sixth pins 24, 26 of the processor 2 simultaneously The effect of controlling the motor speed of the two fans 31, 32 is controlled.

Therefore, by designing the switch driving circuit 1, 1' applied to the two fans 31, 32, it is possible to effectively save the circuit portion material (such as saving the processor of the other fan 32 and another circuit board). And saving the use of the timer 20 in the processor 2, thereby achieving the effect of cost saving, and can also benefit the fan design.

However, the above descriptions are only preferred embodiments of the present invention, and variations of the methods, shapes, structures, and devices described above are intended to be included in the scope of the present invention.

1‧‧‧Switch drive circuit

111‧‧‧First upper arm switch assembly

112‧‧‧Second upper arm switch assembly

113‧‧‧Third upper arm switch assembly

114‧‧‧Four upper arm switch assembly

1111, 1121, 1131, 1141‧‧‧ first end

1112, 1122, 1132, 1142‧‧‧ second end

1113, 1123, 1133, 1143‧‧‧ third end

131‧‧‧First lower arm switch assembly

132‧‧‧Second lower arm switch assembly

133‧‧‧ Third Lower Arm Switch Assembly

134‧‧‧4th lower arm switch assembly

First end, 1311, 1321, 1331, 1341‧‧

1312, 1322, 1332, 1342‧‧‧ second end

1313, 1323, 1333, 1343, ‧ third end

14‧‧‧First Drive Control Unit

15‧‧‧Second drive control unit

2‧‧‧ Processor

20‧‧‧Timer

21‧‧‧First pin

22‧‧‧second pin

23‧‧‧ third pin

24‧‧‧fourth pin

25‧‧‧ fifth pin

26‧‧‧ sixth pin

213‧‧‧13th pin

314‧‧‧ Hall element

Claims (11)

A switch drive circuit for saving a timer of a fan processor is applied to a processor, the switch drive circuit comprising:
a plurality of upper arm switch assemblies are driven by a first pulse width modulation signal and a second pulse width modulation signal;
a plurality of lower arm switch assemblies are electrically connected to the upper arm switch assemblies;
a first driving control unit is electrically connected to a lower arm switch assembly of the lower arm switch assembly, and the first drive control unit receives a third pulse width modulation signal and a high frequency pulse wave modulation signal;
a second drive control unit is electrically connected to the other lower arm switch assembly of the lower arm switch assembly, and the second drive control unit receives the third pulse width modulation signal and the high frequency pulse wave modulation a signal; wherein the first pulse width modulation signal is at a high level and one of the upper arm switch components is turned on, and the second drive control unit receives the third pulse width modulation signal at a low level, and then receives The high frequency pulse modulation signal output trigger is turned on relative to the other lower arm switch assembly, and the second pulse width modulation signal is at a high level to trigger the other upper arm switch assembly to be turned on, and the first drive control unit receives When the third pulse width modulation signal is at a high level, the high frequency pulse wave modulation signal output trigger is received, and the lower arm switch component is turned on. The switch drive circuit for saving a fan processor timer according to the first aspect of the invention, wherein the upper arm switch assembly has a first upper arm switch assembly and a second upper arm switch assembly, the first and second upper arms The switch assembly has a first end, a second end, and a third end. The first end of the first upper arm switch assembly is electrically connected to the first end of the second upper arm switch assembly and an input voltage, the first The second ends of the two upper arm switch assemblies respectively receive the first pulse width modulation signal and the second pulse width modulation signal, and the third ends of the first and second upper arm switch assemblies are electrically connected to the motor of a fan respectively. Both ends of the coil. The switch drive circuit for saving a fan processor timer according to the second aspect of the invention, wherein the lower arm switch assembly has a first lower arm switch assembly and a second lower arm switch assembly, the first The two lower arm switch assemblies each have a first end, a second end, and a third end, and the first ends of the first and second lower arm switch assemblies are electrically connected to the third of the first upper arm switch assemblies The second end of the first lower arm switch assembly is electrically connected to the first drive control unit, and the third end of the first lower arm switch assembly is opposite to the first end The third end of the second lower arm switch assembly is electrically connected, and the second end of the second lower arm switch assembly is electrically connected to the second drive control unit. The switch drive circuit of the fan processor can be saved as described in claim 3, wherein the first drive control unit is provided with a first transistor, a first drive resistor and a second drive resistor. a transistor has a base terminal, an emitter terminal and an collector terminal. One end of the first driving resistor is coupled to the collector terminal, and the collector terminal is configured to receive the high frequency pulse wave modulation signal. The first driving resistor The other end of the second driving resistor is coupled to the base terminal, and the other end of the second driving resistor is configured to receive the third pulse width modulation signal, and the first transistor is The emitter end is coupled to the second end of the first lower arm switch block. The switch drive circuit for saving a fan processor timer according to the fourth aspect of the invention, wherein the second drive control unit is provided with a second transistor, a third transistor, a third drive resistor, and a second drive control unit. a fourth driving resistor and a fifth driving resistor, wherein the second and third transistors each have a base terminal, an emitter terminal and an collector terminal, and a base of the second transistor is coupled to the collector terminal of the third transistor. And an end of the second driving resistor is coupled to one end of the fourth driving resistor to receive the high frequency pulse modulation signal, and the other end of the fourth driving resistor is opposite to the first driving resistor The emitter of the third transistor is coupled to the ground, the emitter of the second transistor is coupled to the second end of the second lower arm switch, and the other end of the third resistor is coupled to an operating voltage. The base of the third transistor is coupled to one end of the fifth driving resistor, and the other end of the fifth driving resistor is configured to receive the third pulse width modulation signal. The switch drive circuit for saving a fan processor timer according to the fifth aspect of the invention, wherein the first upper arm switch assembly is provided with a first MOS transistor, a first resistor, a second resistor, and a first a third resistor, a fourth transistor and a first capacitor, the first MOS transistor having a gate terminal, a source terminal and a terminal, the gate terminal of the first MOS transistor being coupled to one end of the first capacitor And an end of the first resistor and an end of the second resistor, the first MOS transistor is coupled to the other end of the first capacitor and the other end of the first resistor and the input voltage, the first MOS The source of the transistor is coupled to one end of the motor coil, and the fourth transistor has a base terminal, an emitter terminal and an collector terminal, and the collector of the fourth transistor is coupled to the other end of the second resistor. The emitter of the fourth transistor is coupled to the ground. The base of the fourth transistor is coupled to one end of the third resistor, and the other end of the third resistor is configured to receive the first pulse width modulation signal. The switch drive circuit for saving a fan processor timer according to the sixth aspect of the invention, wherein the second upper arm switch assembly is provided with a second MOS transistor, a fourth resistor, a fifth resistor, and a second a sixth resistor, a fifth transistor and a second capacitor, the second MOS transistor having a gate terminal, a source terminal and a terminal, the gate terminal of the second MOS transistor being coupled to one end of the second capacitor And an end of the fourth resistor and an end of the fifth resistor, the second terminal of the second MOS transistor is coupled to the other end of the second capacitor and the other end of the fourth resistor and the input voltage, the second MOS The source of the transistor is coupled to the other end of the motor coil, and the fifth transistor has a base terminal, an emitter terminal and an collector terminal. The collector of the fifth transistor is coupled to the other end of the fifth resistor. The emitter of the fifth transistor is coupled to the ground, the base of the fifth transistor is coupled to one end of the sixth resistor, and the other end of the sixth resistor is configured to receive the second pulse width modulation signal. . The switch drive circuit for saving a fan processor timer according to the seventh aspect of the invention, wherein the first lower arm switch assembly is provided with a third MOS transistor, a seventh resistor, an eighth resistor, and a a third capacitor, the third MOS transistor has a gate terminal, a source terminal and a terminal electrode, wherein the third MOS transistor is coupled to the end of the motor coil and the source terminal of the first MOS transistor The gate of the third MOS transistor is coupled to one end of the third capacitor and one end of the seventh and eighth resistors, and the other end of the eighth resistor is coupled to the other end of the third capacitor and the ground. The other end of the seventh resistor is coupled to the emitter of the first transistor, and the source terminal of the third MOS transistor is coupled to one end of the ninth resistor, and the other end of the ninth resistor is coupled to the ground. end. The switch drive circuit for saving a fan processor timer according to the eighth aspect of the invention, wherein the second lower arm switch assembly is provided with a fourth MOS transistor, a tenth resistor, an eleventh resistor, and a fourth capacitor, the fourth MOS transistor has a gate terminal, a source terminal and a terminal, and the fourth MOS transistor is coupled to the other end of the motor coil and the second MOS transistor The terminal of the fourth MOS transistor is coupled to one end of the fourth capacitor and one end of the tenth and eleventh resistors, and the other end of the tenth resistor is coupled to the other end of the fourth capacitor and the ground And the other end of the eleventh resistor is coupled to the emitter end of the second transistor, and the source terminal of the fourth MOS transistor is coupled to one end of the ninth resistor. The switch drive circuit for saving a fan processor timer according to claim 3 or 9, wherein the processor has a plurality of pins and a plurality of timers, and a first pin is coupled to the first upper arm switch a second end of the component, the first pin is configured to output the first pulse width modulation signal, and a second pin is coupled to the second end of the second upper arm switch component, the second pin is configured to output the first a second pulse width modulation signal, a third pin is coupled to the first and second driving control units, the third pin is configured to output the third pulse width modulation signal, and a fourth pin is coupled to the first And a second driving control unit, wherein the fourth pin is configured to output a high frequency pulse wave modulation signal modulated by a corresponding one of the timers. The switch drive circuit for saving a fan processor timer according to claim 3 or 9, wherein the high frequency pulse modulation signal is modulated by one of a plurality of timers in the processor And generating, the first and second pulse width modulation signals are the same as the third pulse width modulation signal, and the high frequency pulse modulation signal is different from the first, second, and third pulse width modulation signals.