TWM501677U - Adapter card - Google Patents

Abstract

An adapter card is provided, and the adapter card includes a first bus interface, M second bus interfaces and a control chip. The first bus interface includes N first interface channels, and each of the second bus interfaces includes N second interface channels. The control chip is electronically connected to the first bus interface and the second bus interfaces includes. The control chip transfers N first channel signals transmitting via the first interface channels into N*M second channel signals transmitting via the second interface channels.

Description

Riser card

The present invention relates to an interface expansion device, and more particularly to a riser card.

For the control chipset of today's computer motherboards, it is necessary to transmit data to and from peripheral devices through the busbars. With the rapid development of serial communication technology, the Peripheral Component Interconnect Express (PCIe) interface has become a new generation bus interface commonly found in computer systems due to its high transmission rate. In addition, since the PCIe interface can flexibly utilize a combination of multiple transmission channels to establish a connection, the PCIe interface also has the advantages of speed adjustable and application flexibility.

FIG. 1A is an example of a conventional motherboard. FIG. 1B is a schematic structural diagram of a conventional motherboard. Referring to FIG. 1A and FIG. 1B , the motherboard 100 includes a central processing unit (CPU) 110 , a switching device 120 , a PCIe slot 130 , and a PCIe slot 140 . The CPU 110 supports the PCIe 16x channel signal specification (with 16 transmission channels), the PCIe slot 130 also supports the PCIe 16x channel signal specification, and the PCIe slot 140 supports the PCIe 8x channel signal specification (with 8 Transmission channel). The PCIe slot 130 and the PCIe slot 140 are connected through the switching device 120 to switch the 16 channel signals output by the central processing unit 110 to the PCIe slot 140.

PCIe slot 130 and PCIe slot 140 support dual display card technology, like It is a Scalable Link Interface (SLI) or a CrossFire. It uses two identical graphics cards to process graphics together to improve the performance of the graphics card. However, when the user inserts two PCIe 16x-compatible display cards into the PCIe slot 130 and the PCIe slot 140, the two display cards can only transmit data to the central processing unit 110 by using eight transmission channels. To achieve the purpose of two display cards operating at the same time. That is to say, the transmission channel of the display card in this application state cannot be fully used, and the available bus bar bandwidth of the dual display card will be limited by the channel signal specification of the central processing unit 110. Therefore, in order to fully utilize the maximum bus width of the dual display card, the user must purchase a higher specification and more expensive motherboard. Obviously, this is a waste of money and very inconvenient for the user.

In view of this, the novel creation provides a riser card, which allows the user to increase the busbar width of the PCIe interface on the motherboard by inserting the adapter card into the motherboard, thereby improving the design and use of the PCIe interface. Flexibility.

The present invention proposes a riser card that includes a first busbar interface, M second busbar interfaces, and a control wafer. The first bus interface has N first The transmission channels, and the second bus interfaces each have N second transmission channels. The control chip is electrically connected to the first bus interface and the second bus interface, and converts the N first channel signals transmitted through the first transmission channel into N* transmitted through the second transmission channels. M second channel signals. Wherein N and M are integers greater than zero.

In an embodiment of the present invention, the second bus interface is an accelerated component interconnect Express (PCIe) interface.

In an embodiment of the present invention, the second bus interface is an accelerated version of the peripheral component interconnection interface supporting P equal to 2, and P is an integer greater than or equal to 0.

In an embodiment of the present invention, each of the second busbar interfaces includes an accelerated version of the peripheral component interconnect slot that supports the intervening peripheral component interconnect interface.

In an embodiment of the present invention, the first bus interface is an accelerated peripheral component interconnect interface or a Next-generation form factor (NGFF) interface.

In an embodiment of the present invention, the first bus interface is used to connect the chipsets of the motherboard, and the second bus is used to connect the graphics units of the display cards.

In an embodiment of the novel creation, the chip set includes a central processing unit (CPU) and/or a platform control hub (Platform Controller Hub, PCH), and the drawing unit includes a Graphics Processing Unit (GPU).

Based on the above, in an embodiment of the present invention, the riser card can be connected to the chipset of the motherboard through the first bus interface having N transmission channels, and includes a plurality of seconds having the same N transmission channels. Bus interface. The control chip of the riser card can convert N channel signals transmitted through the first bus interface to N times of second channel signals, and transmit to the second bus interface on average. In this way, the available busbar bandwidth of the peripheral expansion device connected to the motherboard through the riser card will not be limited by the number of transmission channels of the chipset of the motherboard, thereby upgrading the busbar transmission bandwidth of the motherboard.

The above described features and advantages of the present invention will become more apparent and understood from the following description.

100, 300, 600‧‧‧ motherboard

110‧‧‧Central Processing Unit

120‧‧‧Switching device

130, 140‧‧‧ PCIe slots

200, 400, 700‧‧‧ transit cards

210, 410, 710‧‧‧ first bus interface

440, 740‧‧‧ physical transfer surface

220-1, 220-2, 220-3, 220-M, 420-1, 420-2, 720-1, 720-2, 720-3‧‧‧ second bus interface

230, 430, 730‧‧‧ control wafer

310, 610‧‧‧ chipset

320, 620‧‧‧ connectors

421-1, 421-2, 630, 640, 650‧‧‧ slots

500-1, 500-2, 800-1, 800-2, 800-3‧‧‧ display cards

510-1, 510-2, 810-1, 810-2, 810-3‧‧‧ drawing unit

520-1, 520-2, 820-1, 820-2, 820-3‧‧‧ connection surface

The following drawings are part of the specification of the present invention, and illustrate exemplary embodiments of the present invention, which together with the description of the specification illustrate the principles of the novel creation.

FIG. 1A is an example of a conventional motherboard.

FIG. 1B is a schematic structural diagram of a conventional motherboard.

2 is a schematic diagram of a riser card according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a dual display card architecture according to an embodiment of the present invention.

FIG. 4 is a schematic diagram showing an example of a riser card according to the embodiment shown in FIG.

FIG. 5 is a schematic structural diagram of a dual display card architecture according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of an example of a riser card according to the embodiment shown in FIG. 5.

The present exemplary embodiments will now be described in detail, and examples of the exemplary embodiments are illustrated in the drawings. In addition, wherever possible, the same reference numerals in the drawings

It should be noted that the PCIe interface protocol connection is based on a bidirectional sequence of point-to-point lines, and each single point-to-point line is called a transmission channel. Therefore, a bus that supports the PCIe interface protocol can increase transmission efficiency by increasing the number of transmission channels. Specifically, the PCIe interface protocol includes a variety of different channel signal specifications, such as PCIe x1 specification, PCIe x2 specification, PCIe x4 specification, PCIe x8 specification, PCIe x16 specification, etc., where the number represents the number of transmission channels. For example, the PCIe x16 specification is composed of 16 transmission channels.

2 is a schematic diagram of a riser card according to an embodiment of the present invention. Referring to FIG. 2, the riser card 200 of the embodiment includes a first bus interface interface 210, M second bus interfaces 220-1, 220-2, 220-3, ..., 220-M and a control chip 230. . The first bus interface 210 has N first transmission channels. Wherein N and M are integers greater than zero. The first bus interface 210 of this embodiment is, for example, a bus interface interface supporting a PCIe interface protocol, such as a PCIe interface or a Next-generation form factor (NGFF) interface.

Similarly, the second bus interface 220-1, 220-2, 220-3, ..., 220-M Each has N second transmission channels. That is, the first bus interface interface 210 has the same number of transmission channels as the second bus interface interfaces 220-1, 220-2, 220-3, ..., 220-M. In this embodiment, the second bus interfaces 220-1, 220-2, 220-3, ..., 220-M are PCIe interfaces, and the second bus interface interfaces 220-1, 220-2, 220-3, ..., 220-M may be an accelerated version of the peripheral component interconnection interface supporting the P-th power of N equal to 2. Where P is an integer greater than or equal to zero. For example, if P is equal to 4, the second bus interface 220-1, 220-2, 220-3, ..., 220-M may be an accelerated peripheral component interconnection interface supporting N equal to 16. Therefore, the second bus interfaces 220-1, 220-2, 220-3, ..., 220-M can be supported by the PCIe x1 standard, the PCIe x2 standard, the PCIe x4 standard, the PCIe x8 standard, or the PCIe x16 standard. The PCIe interface of the number of different transmission channels is not limited in this creation. In this embodiment, if the second bus interfaces 220-1, 220-2, 220-3, ..., 220-M are PCIe x8-compliant PCIe interfaces, the first bus interface 210 also supports PCIe. X8-size bus interface.

The control chip 230 is electrically connected to the first busbar interface 210 and the second bus The interface interfaces 220-1, 220-2, 220-3, ..., 220-M convert the N first channel signals transmitted through the N first transmission channels to each of the M second transmission channels. N*M second channel signals transmitted. Briefly, the control chip 230 can The N input signals transmitted via the first channel are converted into N*M output signals transmitted via the second channel. Conversely, the control chip 230 can also convert N*M input signals transmitted via the second channel into N output signals transmitted via the first channel.

As shown in FIG. 2, between the first bus interface interface 210 and the control wafer 230 The first channel signals of N are respectively transmitted through the N first transmission channels, and the second channel signals of N are respectively transmitted through the N second transmission channels between each of the second bus interfaces and the control chip 230. In detail, the second bus signal is transmitted between the second bus interface 220-1 and the control chip 230 through the N second transmission channels, and so on, the second bus interface 220-M and the control chip. The second channel signals of N are also transmitted through the N second transmission channels, respectively.

That is, since the control chip 230 can turn N first channel signals Switching to N*M second channel signals respectively transmitted through the M second transmission channels, and thus through the second bus interfaces 220-1, 220-2, 220-3, ..., 220-M and switching The transmission bandwidth of the peripheral devices to which the cards 200 are connected will not be limited by the number of transmission channels on the first bus interface interface 210. Therefore, the peripheral expansion device connected to the motherboard through the riser card 200 can fully utilize its own transmission channel to improve the transmission performance.

In order to explain this creation more clearly and in detail, Figure 3 is created in accordance with the present invention. An architectural diagram of a dual display card architecture depicted in an embodiment. FIG. 4 is a schematic diagram showing an example of a riser card according to the embodiment shown in FIG. The dual display card architecture shown in Figure 3 can be applied to a computer system such as a desktop computer, but the present invention is not limited thereto. In addition, in this embodiment, the first bus interface is And the second bus interface has 16 transmission channels as an example for description, and the adapter card includes two second bus interfaces as an example, but the creation is not limited thereto. Referring to FIG. 3 and FIG. 4, the dual display card architecture of this embodiment includes a motherboard 300, a riser card 400, a display card 500-1, and a display card 500-2. The display card 500-1 and the display card 500-2 can support, for example, Cross Fire technology or SLI technology to improve the processing performance of the display card.

The motherboard 300 includes a via set 310 and a connector 320. The chipset 310 is, for example, a central processing unit, a platform controller hub (PCH), or a combination thereof, which is not limited in this creation. It should be noted that in the present embodiment, the PCIe x16 standard is supported by the wafer set 310, the display card 500-1, and the display card 500-2. However, the present invention is not limited thereto. In the present embodiment, the wafer set 310 is coupled to a connector 320 that also supports the PCIe x16 specification. Referring to FIG. 4, the chip set 310 and the connector 320 are disposed on the motherboard 300, and the connector 320 is, for example, a slot supporting the PCIe x16 specification.

In this embodiment, the riser card 400 includes a first bus bar interface 410, a second bus bar interface 420-1, a second bus bar interface 420-2, and a control chip 430. The first bus interface 410 is used to connect the chip set 310 of the motherboard 300. That is, the first bus interface 410 can be coupled to the connector 320 of the motherboard 300 and also supports the PCIe x16 specification with 16 transmission channels. Referring to FIG. 4 , when the connector 320 is a slot supporting the PCIe x16 specification, the physical transmission surface 440 of the first busbar interface may have a plug end of the common name as a gold finger and be engaged with the connector 320. The first bus interface 410 and the control chip 430 pass through the 16 first transmission channels Data transmission with 16 first channel signals. The control chip 430 converts the 16 first channel signals into 32 second channel signals, and transmits the 32 second channel signals to the second bus interface interface 420-1 and the second bus interface interface 420-2.

Further, the second bus interface interface 420-1 and the second embodiment of the embodiment The bus interface 420-2 is a PCIe interface supporting the PCIe x16 specification, and the second bus interface 420-1 and the second bus interface 420-2 each receive 16 second channel signals through the 16 second transmission channels. Moreover, the second bus interface interface 420-1 is used to connect the drawing unit 510-1 of the display card 500-1, and the second bus interface interface 420-2 is used to connect the drawing unit 510-2 of the display card 500-2.

More specifically, the second bus interface 420-1 includes support for PCIe x16 The slot 421-1 of the specification, and the second bus interface 420-2 includes a slot 421-2 supporting the PCIe x16 specification to provide a physical interface for connecting the display card 500-1 and the display card 500-2. Referring to FIG. 4, the PCIe x16 slot 421-1 and the PCIe x16 slot 421-2 are disposed on the riser card 400. However, the slot arrangement shown in FIG. 4 is merely exemplary and is not intended to limit the present creation. Those skilled in the art can design PCIe x16 slot 421-1 and PCIe x16 slot 421-2 according to the actual application.

The display card 500-1 includes a drawing unit 510-1 and a connection surface 520-1, The display card 500-2 includes a drawing unit 510-2 and a connection surface 520-2. The drawing unit 510-1 and the drawing unit 510-2 are, for example, a graphics processing unit (GPU) or other arithmetic unit having a drawing function. Referring to FIG. 4, the connecting surface 520-1 and the connecting surface 520-2 may be commonly referred to as gold finger insertion. The connection surface 520-1 is electrically connected to the control wafer 430 via the socket 421-1, and the connection surface 520-2 is electrically connected to the control wafer 430 via the socket 421-2. As such, the display card 500-1 and the display card 500-2 can each exchange data with the chip set 310 of the motherboard 300 using 16 transfer channels, and cannot be fully used without being limited by the number of transfer channels of the chip set. The available bandwidth of the PCIe x16 specification increases the overall processing performance of the dual graphics card architecture.

In order to clarify and explain the different implementations of the present invention, FIG. 5 is a schematic structural diagram of a dual display card architecture according to an embodiment of the present invention. FIG. 6 is a schematic diagram of an example of a riser card according to the embodiment shown in FIG. 5. The dual display card architecture shown in Figure 5 can be applied to a computer system such as a desktop computer, but the creation is not limited thereto. It should be noted that, in this embodiment, the first bus interface is the same as the physical transmission interface of the second bus interface. That is, the plurality of second busbar interfaces shown in FIG. 2 and the first busbar interface may be the same transmission interface, and the plurality of second transmission channels may be regarded as the first transmission channel. The following is an example in which the first bus interface has 16 transmission channels, and the control chip can convert 16 first channel signals into 16*3 second channel signals as an example, but the creation is not limited. herein. Referring to FIG. 5 and FIG. 6, the dual display card architecture of this embodiment includes a motherboard 600, a riser card 700, a display card 800-1, a display card 800-2, and a function expansion card 800-3. The display card 800-1 and the display card 800-2 can support, for example, Cross Fire technology or SLI technology to improve the processing performance of the display card.

The motherboard 600 includes a via set 610 and a connector 620. The chipset 610 is, for example, a central processing unit, a platform control hub (Platform Controller) Hub, PCH) or a combination thereof, this creation is not limited. Specifically, in the present embodiment, the chipset 610, the display card 800-1, the display card 800-2, and the function expansion card 800-3 each support the PCIe x16 specification as an example, but this creation does not This is limited to this. In the present embodiment, the chip set 610 is coupled to a connector 620 that supports the PCIe x16 protocol. Referring to FIG. 6, the chip set 610 and the connector 620 are disposed on the motherboard 600, and the connector 620 is, for example, a Next-generation form factor (NGFF) interface slot.

In this embodiment, the riser card 700 includes a first bus interface 710, The two bus interfaces 720-1, the second bus interface 720-2, the second bus interface 720-3, and the control chip 730. The first bus interface 710 can be coupled to the connector 620 of the motherboard 600 and also supports the PCIe x16 specification with at least 16 transmission channels. For example, referring to FIG. 6 , when the connector 620 is an M.2 slot supporting the PCIe x16 protocol, the first bus interface 710 may have a docking end commonly known as a gold finger to be engaged with the connector 620 . The first bus interface 710 and the control chip 730 transmit data through 16 first transmission channels and 16 first channel signals. The control chip 730 converts the 16 first channel signals into 3*16=48 second channel signals, and transmits the 48 second channel signals to the second bus interface interface 720-1 and the second bus interface 720- 2 and the second bus interface 720-3.

It should be noted that, in this embodiment, the first bus interface 710 The physical transmission interface is the same as the physical transmission interface of the second bus interfaces 720-1~720-3, that is, the first channel signal received by the control chip 730 and the second channel signal outputted by the control chip 730 are transmitted through the same physical interface. Referring to FIG. 6, the adapter card 700 passes through the first bus interface. The physical transmission interface 740 of the 710 and the second bus interface 720-1~720-3 is used for data transmission and signal transmission. The second bus interface interface 720-1 is configured to transmit the second channel signal to the drawing unit 810-1 of the display card 800-1, and the second bus interface interface 720-2 is configured to transmit the second channel signal to the display card 800. The drawing unit 810-2 of -2, and the second bus interface 720-3 is used to transmit the second channel signal to the chip unit 810-3 of the function expansion card 800-3.

More specifically, referring to FIG. 6, the motherboard 600 includes a slot 630 supporting the PCIe x16 specification, a slot 640, and a slot 650 for providing a connection between the display card 800-1, the display card 800-2, and the function expansion. The physical interface of card 800-3. The chipset 610 of the motherboard 600 transmits 16 first channel signals to the control card 730 of the riser card through the connector 620 and the physical connection interface 740. In addition, the control chip 730 converts the 16 first channel signals into 48 second channel signals, and transmits the 48 second channel signals to the PCIe x16 slot 630 and the PCIe x16 plug through the connector 620 and the physical connection interface 740. The slot 640 and the PCIe x16 slot 650 enable the display card 800-1, the display card 800-2, and the function expansion card 800-3 to each pass through the PCIe x16 connection surface 820-1, the PCIe x16 connection surface 820-2, and the PCIe x16 connection. The surface 820-3 receives the second channel signal output by the control wafer 730 on average. However, the slot arrangement shown in FIG. 6 is merely exemplary and is not intended to limit the present creation.

The component coupling relationship and function of the display card 800-1 and the display card 800-2 are similar or identical to those of the display card 500-1 shown in FIG. 3, and details are not described herein again. This creation is not limited to the function expansion card 810-3, as long as it is connected through PCIe x16 The function cards connected to the motherboard are all within the scope of this creation. The function expansion card 810-3 includes a connection surface 820-3 and a wafer unit 810-3. The chip unit 810-3 also supports the specification of the PCIe x16, and the connection surface 820-3 may be a plug-in end point commonly known as a gold finger. In detail, the connection surface 820-1 is used for transmitting 16 second channel signals through the slot 630 and the control chip 730, and the connection surface 820-2 is used to perform 16 second channels through the slot 640 and the control chip 730. The signal is transmitted, and the connection surface 820-3 is used to transmit 16 second channel signals through the slot 650 and the control chip 730. As such, the display card 800-1, the display card 800-2, and the function expansion card 800-3 can each exchange data with the chip set 610 of the motherboard 600 using 16 transfer channels, and are not limited by the chip set 610. The number of transmission channels cannot fully utilize the available bandwidth of the PCIe x16 specification, thereby increasing the transmission bandwidth of all physical interfaces supporting the PCIe x16 specification.

In summary, in an embodiment of the novel creation, the adapter card can pass through The first bus interface supporting the PCIe x16 specification is connected to the chipset of the motherboard, and can be connected to multiple peripheral expansion devices supporting the PCIe x16 standard through a plurality of second bus interfaces supporting the PCIe x16 standard. Moreover, the control chip of the riser card can convert 16 channel signals transmitted through the first bus interface to 16 times of second channel signals, and transmit to the second bus interface on average. In this way, the peripheral expansion device connected to each of the second bus interface can fully utilize the 16 transmission channels specified by the PCIe x16 specification, and is not limited by the number of transmission channels of the chipset on the motherboard, thereby fully utilizing PCIe. The interface bus has a wide bandwidth and more efficient data transmission. In this way, the user can install one of the created adapter cards by himself. The PCIe bandwidth available for a motherboard can be upgraded to a higher level, providing a more economical and convenient approach.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.

200‧‧‧Transfer card

210‧‧‧First bus interface

220-1, 220-2, 220-3, 220-M‧‧‧ second bus interface

230‧‧‧Control chip

Claims (8)

A riser card comprising: a first busbar interface having at least N first transmission channels; and a control chip electrically connected to the first busbar interface to transmit N through the first transmission channels The first channel signals are converted into N*M second channel signals, where N and M are integers greater than zero. The adapter card of claim 1, further comprising: M second bus interfaces, coupled to the control chip and each having M second transmission channels, wherein the second channel signals respectively pass through the These second transmission channels are transmitted. The adapter card of claim 2, wherein the second bus interface is a Peripheral Component Interconnect Express (PCIe) interface supporting P equal to 2, P is An integer greater than or equal to 0. The riser card of claim 2, wherein each of the second bus interface comprises an accelerated version of the peripheral component interconnect slot that supports an intervening peripheral component interconnect interface. The adapter card of claim 2, wherein the second bus interface is the same transmission interface as the first bus interface, and the second transmission channels are the first transmission channels. The adapter card of claim 1, wherein the first bus interface is an accelerated peripheral component interconnection interface or M.2 (Next-generation form) Factor, NGFF) interface. The adapter card of claim 2, wherein the first bus interface is used to connect a chipset of a motherboard, and the second bus interface is used to connect each of the plurality of display cards. Drawing unit. The adapter card of claim 7, wherein the chipset comprises a central processing unit (CPU) and/or a platform controller hub (PCH), the drawing unit comprising a graphics processing unit (Graphics Processing) Unit, GPU).