CN204360266U - Adapter - Google Patents
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- CN204360266U CN204360266U CN201420696696.1U CN201420696696U CN204360266U CN 204360266 U CN204360266 U CN 204360266U CN 201420696696 U CN201420696696 U CN 201420696696U CN 204360266 U CN204360266 U CN 204360266U
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- 230000005540 biological transmission Effects 0.000 claims abstract description 75
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 14
- 230000001133 acceleration Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 8
- 238000012935 Averaging Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- VEMKTZHHVJILDY-UHFFFAOYSA-N resmethrin Chemical compound CC1(C)C(C=C(C)C)C1C(=O)OCC1=COC(CC=2C=CC=CC=2)=C1 VEMKTZHHVJILDY-UHFFFAOYSA-N 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012559 user support system Methods 0.000 description 1
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Abstract
The utility model provides a kind of adapter, and it comprises the first bus interface, M the second bus interface and control chip.First bus interface has N number of first transmission channel, and this little second bus interface has N number of second transmission channel separately.Control chip is electrically connected this first bus interface a little second bus interface therewith, and the N number of first passage signal transmitted by the first transmission channel is converted to N*M the second channel signal transmitted by this little second transmission channel.
Description
Technical field
The utility model relates to a kind of interface expanding device, and relates to a kind of adapter especially.
Background technology
For the control chip group of computer motherboard now, it all needs to transmit data with peripheral equipment by bus.Along with the fast development of the sequence communication technology, (PeripheralComponent Interconnect Express is called for short: PCIe) interface has become a new generation and the bus interface be common in computer system due to its high transfer rate to accelerate version peripheral assembly interconnect.In addition, because PCIe interface can flexibly utilize the collocation of multiple transmission channel to connect, therefore PCIe interface also has speed adjustable and applies flexible advantage.
Figure 1A is the example of existing a kind of motherboard.Figure 1B is the configuration diagram of existing a kind of motherboard.Please refer to Figure 1A and Figure 1B, motherboard 100 comprises central processing unit (CPU) 110, switching device shifter 120, PCIe slot 130 and PCIe slot 140.The channel signal specification of PCIe 16x (possessing 16 transmission channels) supported by central processing unit 110, PCIe slot 130 supports the channel signal specification of PCIe 16x equally, and PCIe slot 140 then supports the channel signal specification of PCIe 8x (possessing 8 transmission channels).Connected by switching device shifter 120 between PCIe slot 130 and PCIe slot 140, switch to PCIe slot 140 with exported by central processing unit 110 16 channel signals.
PCIe slot 130 and PCIe slot 140 can support TVGA technology, similarly be extendible link interface (Scalable Link Interface, be called for short: SLI) or video card fight (CrossFire), namely carry out processing graphics together with two the same display cards, and then improve the usefulness of display card.But, when by two, user supports that the display card of PCIe 16x inserts PCIe slot 130 and PCIe slot 140 respectively, the object that two display cards operate simultaneously is reached in the transmission that these two display cards only can distinctly utilize 8 transmission channels and central processing unit 110 to carry out data.That is, the transmission channel of the display card under this application state also cannot fully be used, and the available bus bandwidth of TVGA will be limited to the channel signal specification of central processing unit 110.Therefore, the maximum bus bandwidth possessed to fully use TVGA, user must buy in addition more high standard and a motherboard costly.Obviously, this is a kind of sinking money and the very not convenient practice concerning user.
Summary of the invention
In view of this, the utility model provides a kind of adapter, allows user by adapter being inserted into bus bandwidth motherboard promoting PCIe interface on motherboard, improves the upper elasticity with using of PCIe interface design by this.
The utility model proposes a kind of adapter, it comprises the first bus interface, M the second bus interface and control chip.First bus interface has N number of first transmission channel, and this little second bus interface has N number of second transmission channel separately.Control chip is electrically connected this first bus interface a little second bus interface therewith, and the N number of first passage signal transmitted by the first transmission channel is converted to N*M the second channel signal transmitted by this little second transmission channel.Wherein, N and M be greater than 0 integer.
In an embodiment of the present utility model, the second above-mentioned bus interface is for accelerating version peripheral assembly interconnect interface.
In an embodiment of the present utility model, the second above-mentioned bus interface is support that N equals the acceleration version peripheral assembly interconnect interface of the P power of 2, P be more than or equal to 0 integer.
In an embodiment of the present utility model, each above-mentioned second bus interface comprises supports that accelerating one of version peripheral assembly interconnect interface accelerates version peripheral assembly interconnect slot.
In an embodiment of the present utility model, the first above-mentioned bus interface is for accelerating version peripheral assembly interconnect interface or M.2 form factor NGFF interface of future generation.
In an embodiment of the present utility model, the first above-mentioned bus interface is in order to connect the chipset of motherboard, and the second above-mentioned bus is in order to connect the image-drawing unit of display card separately.
In an embodiment of the present utility model, above-mentioned chipset comprises central processor CPU and/or platform courses hub PCH, and image-drawing unit comprises Graphics Processing Unit GPU.
Based on above-mentioned, in an embodiment of the present utility model, adapter is connected with the chipset of motherboard by first bus interface with N number of transmission channel, and comprises multiple second bus interface equally with N number of transmission channel.The N number of channel signal transmitted by the first bus interface can be converted to a N doubly second channel signal by the control chip of adapter, and is on average sent to each the second bus interface.So, the available bus bandwidth of the periphery expanding device be connected with motherboard by adapter can not be limited to the quantity of the transmission channel of the chipset of motherboard, thus the bus transfer bandwidth of upgrading motherboard.
For above-mentioned feature and advantage of the present utility model can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Accompanying drawing is below a part for instructions of the present utility model, shows example embodiment of the present utility model, and accompanying drawing illustrates principle of the present utility model together with the description of instructions.
Figure 1A is the example of existing a kind of motherboard;
Figure 1B is the configuration diagram of existing a kind of motherboard;
Fig. 2 is the schematic diagram of the adapter shown by an embodiment of the present utility model;
Fig. 3 is the configuration diagram of the TVGA framework shown by an embodiment of the present utility model;
Fig. 4 is the example schematic of shown adapter embodiment illustrated in fig. 3;
Fig. 5 is the configuration diagram of the TVGA framework shown by an embodiment of the present utility model;
Fig. 6 is the example schematic of shown adapter embodiment illustrated in fig. 5.
100,300,600: motherboard;
110: central processing unit;
120: switching device shifter;
130,140:PCIe slot;
200,400,700: adapter;
210,410,710: the first bus interface;
440,740: entity transmission interface;
220-1,220-2,220-3,220-M, 420-1,420-2,720-1,720-2,720-3: the second bus interface;
230,430,730: control chip;
310,610: chipset;
320,620: connector;
421-1,421-2,630,640,650: slot;
500-1,500-2,800-1,800-2: display card;
800-3: function expansion board;
510-1,510-2,810-1,810-2: image-drawing unit;
810-3: chip unit;
520-1,520-2,820-1,820-2,820-3: connecting surface.
Embodiment
With detailed reference to this one exemplary embodiment, the example of described one exemplary embodiment is described in the accompanying drawings.In addition, all possibility parts, use the element/component of identical label to represent identical or similar portions in drawings and the embodiments.
Need first illustrate, the line of PCIe interface agreement be based upon a two-way sequence point to point line basis on, each single point to point line is referred to as transmission channel.Therefore, support that the bus of PCIe interface agreement increases transfer efficiency by the number increasing transmission channel.Specifically, PCIe interface agreement comprises multiple different channel signal specification, such as PCIe x1 specification, PCIe x2 specification, PCIe x4 specification, PCIe x8 specification, PCIe x16 specification etc., the number of digitized representation transmission channel wherein.For example, the connection of PCIe x16 specification is made up of 16 transmission channels.
Fig. 2 is the schematic diagram of the adapter shown by an embodiment of the present utility model.Please refer to Fig. 2, the adapter 200 of the present embodiment comprises one first bus interface 210, M the second bus interface 220-1,220-2,220-3 ..., 220-M and control chip 230.First bus interface 210 has N number of first transmission channel, wherein N and M be greater than 0 integer.First bus interface 210 of the present embodiment be such as PCIe interface or M.2 form factor of future generation (Next-generation form factor is called for short: NGFF) interface etc. support the bus interface of PCIe interface agreement.
Similar, the second bus interface 220-1,220-2,220-3 ..., 220-M have N number of second transmission channel separately.That is, the first bus interface 210 and the second bus interface 220-1,220-2,220-3 ..., 220-M have the transmission channel of equal number.In the present embodiment, second bus interface 220-1,220-2,220-3 ..., 220-M are PCIe interface, and the second bus interface 220-1,220-2,220-3 ..., 220-M can for supporting that N equals the acceleration version peripheral assembly interconnect interface of the P power of 2.Wherein, P be more than or equal to 0 integer.For example, if when P equals 4, the acceleration version peripheral assembly interconnect interface that the second bus interface 220-1,220-2,220-3 ..., 220-M can equal 16 for support N.It can thus be appreciated that, second bus interface 220-1,220-2,220-3 ..., 220-M can be support PCIe x1 specification, PCIe x2 specification, PCIe x4 specification, PCIe x8 specification or PCIe x16 specification etc. possess different transmission channel quantity PCIe interface, this is novel does not limit this.In the present embodiment, if when the second bus interface 220-1,220-2,220-3 ..., 220-M are the PCIe interface supporting PCIe x8 specification, then the first bus interface 210 is also for supporting the bus interface of PCIe x8 specification.
Control chip 230 is electrically connected the first bus interface 210 and the second bus interface 220-1,220-2,220-3 ..., 220-M, and the N number of first passage signal transmitted by N number of first transmission channel is converted to N*M the second channel signal distinctly transmitted by M the second transmission channel.In simple terms, N number of input signal transmitted by first passage can be converted to N*M the output signal transmitted by second channel by control chip 230.Otherwise the input signal that N*M is transmitted by second channel also can be converted to N number of output signal transmitted by first passage by control chip 230.
As shown in Figure 2, transmitted the first passage signal of N between first bus interface 210 and control chip 230 by N number of first transmission channel respectively, and between each the second bus interface and control chip 230, transmitted the second channel signal of N by N number of second transmission channel respectively.Specifically, transmitted the second channel signal of N respectively by N number of second transmission channel between second bus interface 220-1 and control chip 230, the rest may be inferred, transmitted the second channel signal of N between the second bus interface 220-M and control chip 230 too by N number of second transmission channel respectively.
That is, because N number of first passage signal can be converted to N*M the second channel signal distinctly transmitted by M the second transmission channel by control chip 230, therefore pass through the second bus interface 220-1,220-2,220-3 ..., 220-M and the interconnective peripheral equipment of adapter 200 transmission bandwidth can not be limited to the number of transmission channel in the first bus interface 210.Base this, the transmission channel of self can be made full use of by adapter 200 and the interconnective periphery expanding device of motherboard and improve transmission usefulness.
In order to clearer originally novel with detailed description, Fig. 3 is the configuration diagram of the TVGA framework shown by an embodiment of the present utility model.Fig. 4 is the example schematic of shown adapter embodiment illustrated in fig. 3.TVGA framework shown in Fig. 3 can be applied to similarly be desktop computer a computer system in, but this is novel not as limit.It should be noted that in the present embodiment, for the first bus interface and the second bus interface, there are 16 transmission channels separately and be described in addition, and comprise two the second bus interface for adapter and be described, but this is novelly not restricted to this.Please refer to Fig. 3 and Fig. 4, the TVGA framework of the present embodiment comprises motherboard 300, adapter 400, display card 500-1 and display card 500-2.Display card 500-1 and display card 500-2 such as can support Cross Fire technology or SLI technology and promote the treatment efficiency of display card.
Motherboard 300 comprises through chipset 310 and connector 320.PCH) or its combination chipset 310 is such as central processing unit, (Platform Controller Hub, be called for short:, this is novel does not limit this platform courses hub.Specifically, in the present embodiment, support that PCIe x16 specification is described for chipset 310, display card 500-1 and display card 500-2, but this is novel not as limit.In the present embodiment, with same, chipset 310 supports that the connector 320 of PCIe x16 specification connects.Please refer to Fig. 4, chipset 310 and connector 320 are arranged on motherboard 300, and connector 320 is such as supporting the slot of PCIe x16 specification.
In the present embodiment, adapter 400 comprises the first bus interface 410, second bus interface 420-1, the second bus interface 420-2 and control chip 430.First bus interface 410 is in order to connect the chipset 310 of motherboard 300.That is, the first bus interface 410 can be connected with the connector 320 of motherboard 300, and supports PCIe x16 specification equally and have 16 transmission channels.Please refer to Fig. 4, when connector 320 is the slot supporting PCIe x16 specification, the entity transmission surface 440 of the first bus interface 410 can have the grafting end points that is commonly called as golden finger and chimeric with connector 320.First bus interface 410 carries out data transmission with control chip 430 by 16 the first transmission channels and 16 first passage signals.16 first passage signals are converted to 32 second channel signals by control chip 430, and 32 second channel signal averagings are sent to the second bus interface 420-1 and the second bus interface 420-2.
Furthermore, the second bus interface 420-1 of the present embodiment and the second bus interface 420-2 is the PCIe interface supporting PCIe x16 specification, and the second bus interface 420-1 and the second bus interface 420-2 receives 16 second channel signals each via 16 the second transmission channels.Further, the second bus interface 420-1 is in order to connect the image-drawing unit 510-1 of display card 500-1, and the second bus interface 420-2 is in order to connect the image-drawing unit 510-2 of display card 500-2.
More particularly, second bus interface 420-1 comprises the slot 421-1 supporting PCIe x16 specification, and the second bus interface 420-2 comprises the slot 421-2 supporting PCIe x16 specification, to provide the entity interface connecting display card 500-1 and display card 500-2.Please refer to Fig. 4, PCIe x16 slot 421-1 and PCIe x16 slot 421-2 is arranged on adapter 400.But the slot set-up mode shown in Fig. 4 is only exemplary illustrated, and this is novel to be not used to restriction.Those skilled in the art can design the set-up mode of PCIe x16 slot 421-1 and PCIe x16 slot 421-2 according to practical application situation.
Display card 500-1 comprises image-drawing unit 510-1 and connecting surface 520-1, and display card 500-2 comprises image-drawing unit 510-2 and connecting surface 520-2.Image-drawing unit 510-1 and image-drawing unit 510-2 be such as Graphics Processing Unit (Graphics Processing Unit, be called for short: GPU) or other possess the arithmetic element of drawing function.Please refer to Fig. 4, connecting surface 520-1 and connecting surface 520-2 can be commonly called as the grafting end points of golden finger, connecting surface 520-1 is in order to be electrically connected through slot 421-1 and control chip 430, and connecting surface 520-2 is in order to be electrically connected through slot 421-2 and control chip 430.So, display card 500-1 and display card 500-2 can use the chipset 310 of 16 transmission channels and motherboard 300 to carry out the exchange of data separately, and the number of the transmission channel of chipset can not be limited to and fully cannot use the available bandwidth of PCIe x16 specification, thus promote the bulk treatment usefulness of TVGA framework.
In order to the clearer different embodiments novel from describing this in detail, Fig. 5 is the configuration diagram of the TVGA framework shown by an embodiment of the present utility model.Fig. 6 is the example schematic of shown adapter embodiment illustrated in fig. 5.TVGA framework shown in Fig. 5 can be applied to similarly be desktop computer a computer system in, but this is novel not as limit.It should be noted that in addition, in the present embodiment, the first bus interface is identical with the entity transmission interface of the second bus interface.That is, multiple second bus interface shown in Fig. 2 can be identical transmission interface with the first bus interface, and multiple second transmission channel can be considered the first transmission channel.For the first bus interface, there are 16 transmission channels to be below described, and 16 first passage signals can be converted to 16*3 second channel signal for control chip and be described, but this is novelly not restricted to this.Please refer to Fig. 5 and Fig. 6, the TVGA framework of the present embodiment comprises motherboard 600, adapter 700, display card 800-1, display card 800-2 and function expansion board 800-3.Display card 800-1 and display card 800-2 such as can support Cross Fire technology or SLI technology and promote the treatment efficiency of display card.
Motherboard 600 comprises through chipset 610 and connector 620.PCH) or its combination chipset 610 is such as central processing unit, (Platform Controller Hub, be called for short:, this is novel does not limit this platform courses hub.Specifically, in the present embodiment, be described for chipset 610, display card 800-1, display card 800-2 and function expansion board 800-3 each self-supporting PCIe x16 specification, but this is novel not as limit.In the present embodiment, chipset 610 with can support that the connector 620 that PCIex16 reaches an agreement on is connected.Please refer to Fig. 6, chipset 610 and connector 620 are arranged on motherboard 600, and connector 620 is such as M.2NGFF interface slot.
In the present embodiment, adapter 700 comprises the first bus interface 710, second bus interface 720-1, the second bus interface 720-2, the second bus interface 720-3 and control chip 730.First bus interface 710 can be connected with the connector 620 of motherboard 600, and supports PCIe x16 specification equally and at least have 16 transmission channels.For example, please refer to Fig. 6, when connector 620 is the M.2 slot supporting PCIe x16 agreement, the first bus interface 710 can have the grafting end points that is commonly called as golden finger and chimeric with connector 620.First bus interface 710 carries out data transmission with control chip 730 by 16 the first transmission channels and 16 first passage signals.16 first passage signals are converted to 3*16=48 second channel signal by control chip 730, and 48 second channel signal averagings are sent to the second bus interface 720-1, the second bus interface 720-2 and the second bus interface 720-3.
Specifically be, in the present embodiment, first bus interface 710 is identical with the entity transmission interface of the second bus interface 720-1 ~ 720-3, and the first passage signal that namely control chip 730 receives is transmitted by identical entity interface with the second channel signal of its output.Please refer to Fig. 6, adapter 700 carries out the transmission of data and the transmission of signal by the entity transmission interface 740 of the first bus interface 710 and the second bus interface 720-1 ~ 720-3.Wherein, second bus interface 720-1 is in order to transmit the image-drawing unit 810-1 of second channel signal to display card 800-1, and the second bus interface 720-2 is in order to transmit the image-drawing unit 810-2 of second channel signal to display card 800-2, and the second bus interface 720-3 is in order to transmit the chip unit 810-3 of second channel signal to function expansion board 800-3.
More particularly, please refer to Fig. 6, motherboard 600 comprises slot 630, slot 640 and the slot 650 of supporting PCIe x16 specification, to provide the entity interface connecting display card 800-1, display card 800-2 and function expansion board 800-3.16 first passage signals are sent to the control chip 730 of adapter by connector 620 and entity transmission interface 740 by the chipset 610 of motherboard 600.In addition, 16 first passage signals are converted to 48 second channel signals by control chip 730, and by connector 620 and entity transmission interface 740,48 second channel signal averagings are sent to PCIe x16 slot 630, PCIe x16 slot 640 and PCIe x16 slot 650, cause display card 800-1, display card 800-2 and function expansion board 800-3 can average received exports to control chip 730 each via PCIe x16 connecting surface 820-1, PCIe x16 connecting surface 820-2 and PCIe x16 connecting surface 820-3 second channel signal.But the slot set-up mode shown in Fig. 6 is only exemplary illustrated, and this is novel to be not used to restriction.
It is similar or identical that the element of display card 800-1 and display card 800-2 couples the display card 500-1 shown in relation and function and Fig. 3, do not repeat them here.Basis is novel not to be limited for function expansion board 800-3, as long as the function card be connected with motherboard by PCIe x16 connecting interface is all in the protection domain that this is novel.Function expansion board 800-3 comprises connecting surface 820-3 and chip unit 810-3.Chip unit 810-3 supports the specification of PCIe x16 equally, and connecting surface 820-3 can for being commonly called as the grafting end points of golden finger.Specifically, connecting surface 820-1 is in order to carry out the transmission of 16 second channel signals through slot 630 and control chip 730, connecting surface 820-2 is in order to carry out the transmission of 16 second channel signals through slot 640 and control chip 730, and connecting surface 820-3 is in order to carry out the transmission of 16 second channel signals through slot 650 and control chip 730.So, display card 800-1, display card 800-2 and function expansion board 800-3 can use the chipset 610 of 16 transmission channels and motherboard 600 to carry out the exchange of data separately, and the number of the transmission channel of chipset 610 can not be limited to and fully cannot use the available bandwidth of PCIe x16 specification, thus promote the transmission bandwidth of the entity interface of all support PCIe x16 specifications.
In sum, in an embodiment of the present utility model, adapter is connected with the chipset of motherboard by the first bus interface of support PCIe x16 specification, and by supporting that multiple second bus interface of PCIe x16 specification and the multiple periphery expanding device of support PCIe x16 specification are connected.Moreover transmitted by the first bus interface 16 channel signals can be converted to 16 times of several second channel signals by the control chip of adapter, and are on average sent to each the second bus interface.So, the periphery expanding device be connected with each second bus interface fully can use 16 transmission channels of PCIe x16 specification institute specification, and the quantity of the transmission channel of chipset on motherboard can not be limited to, thus make full use of the bus bandwidth of PCIe interface and the more efficient transmission carrying out data.By this, user by install voluntarily this novel adapter and by general motherboard can PCIe bandwidth upgrading to higher level, provide one more economical and the practice easily.
Last it is noted that above each embodiment is only in order to illustrate the technical solution of the utility model, be not intended to limit; Although be described in detail the utility model with reference to foregoing embodiments, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the utility model.
Claims (6)
1. an adapter, is characterized in that, comprising:
First bus interface, at least has N number of first transmission channel;
Control chip, is electrically connected described first bus interface, and the N number of first passage signal transmitted by described first transmission channel is converted to N*M second channel signal, wherein N and M be greater than 0 integer; And
M the second bus interface, couple described control chip and there is N number of second transmission channel separately, wherein said second channel signal is respectively by described second transmission channel transmission, described second bus interface is support that N equals the acceleration version peripheral assembly interconnect interface of the P power of 2, P be more than or equal to 0 integer.
2. adapter according to claim 1, is characterized in that, each described second bus interface comprises the acceleration version peripheral assembly interconnect slot of supporting to accelerate version peripheral assembly interconnect interface.
3. adapter according to claim 1, is characterized in that, described second bus interface is identical transmission interface with described first bus interface, and described second transmission channel is described first transmission channel.
4. adapter according to claim 1, is characterized in that, described first bus interface is for accelerating version peripheral assembly interconnect interface or form factor NGFF interface of future generation.
5. adapter according to claim 1, is characterized in that, described first bus interface is in order to connect the chipset of a motherboard, and described second bus interface is in order to connect multiple display card image-drawing unit separately.
6. adapter according to claim 5, is characterized in that, described chipset comprises central processing unit and/or platform courses hub, and described image-drawing unit comprises Graphics Processing Unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420696696.1U CN204360266U (en) | 2014-11-18 | 2014-11-18 | Adapter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420696696.1U CN204360266U (en) | 2014-11-18 | 2014-11-18 | Adapter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204360266U true CN204360266U (en) | 2015-05-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420696696.1U Expired - Fee Related CN204360266U (en) | 2014-11-18 | 2014-11-18 | Adapter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108255759A (en) * | 2016-12-29 | 2018-07-06 | 联想（上海）信息技术有限公司 | PCI-E adapters and data processing system |
| CN110221999A (en) * | 2019-05-23 | 2019-09-10 | 深圳市同泰怡信息技术有限公司 | It is realized based on standard PCIE and supports GPU and M2 SSD extension adapter and implementation method |
| CN113282149A (en) * | 2021-05-24 | 2021-08-20 | 英业达科技有限公司 | Server and electronic assembly |
-
2014
- 2014-11-18 CN CN201420696696.1U patent/CN204360266U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108255759A (en) * | 2016-12-29 | 2018-07-06 | 联想（上海）信息技术有限公司 | PCI-E adapters and data processing system |
| CN110221999A (en) * | 2019-05-23 | 2019-09-10 | 深圳市同泰怡信息技术有限公司 | It is realized based on standard PCIE and supports GPU and M2 SSD extension adapter and implementation method |
| CN113282149A (en) * | 2021-05-24 | 2021-08-20 | 英业达科技有限公司 | Server and electronic assembly |
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Granted publication date: 20150527 |