TWM498384U - Semiconductor package structure - Google Patents
Semiconductor package structure Download PDFInfo
- Publication number
- TWM498384U TWM498384U TW103217686U TW103217686U TWM498384U TW M498384 U TWM498384 U TW M498384U TW 103217686 U TW103217686 U TW 103217686U TW 103217686 U TW103217686 U TW 103217686U TW M498384 U TWM498384 U TW M498384U
- Authority
- TW
- Taiwan
- Prior art keywords
- type transistor
- connecting piece
- low
- semiconductor package
- package structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本創作是有關於一種半導體封裝結構。This creation is about a semiconductor package structure.
近年來，隨著積體電路技術的進步，相關的電子產品也越來越多樣化。其中的功率電晶體由於具有高集成密度、相當低的靜態漏電流以及不斷提升的功率容量，因此目前被廣泛應用在開關電源和變頻器等領域。In recent years, with the advancement of integrated circuit technology, related electronic products have become more diverse. Among them, power transistors are widely used in switching power supplies and inverters due to their high integration density, relatively low static leakage current, and ever-increasing power capacity.
舉例而言，功率電晶體可應用在轉換器上。轉換器可包含多個功率電晶體，藉由控制各個功率電晶體的開啟或關閉，可將輸入電壓轉換為不同的輸出電壓，例如可將輸入電壓轉換為較低的輸出電壓，達到降壓的目的。然而在結構上，功率電晶體彼此之間，或者是功率電晶體本身與其他元件之間會有電性連接的需求。但目前現有的電性連接方式存在有可靠度較差的問題。因此，如何能夠提昇電性連接的可靠度成為本技術領域有待解決的課題之一。For example, a power transistor can be applied to the converter. The converter can include a plurality of power transistors, and by controlling the turning on or off of the respective power transistors, the input voltage can be converted to different output voltages, for example, the input voltage can be converted to a lower output voltage to achieve a step-down voltage. purpose. However, structurally, there is a need for electrical connections between the power transistors, or between the power transistors themselves and other components. However, the current existing electrical connection methods have problems of poor reliability. Therefore, how to improve the reliability of the electrical connection has become one of the problems to be solved in the technical field.
本創作之目的在於提供一種新穎的半導體封裝結構，其包含引線框架、高側N型電晶體、低側N型電晶體、第一連接片(clip)以及第二連接片(clip)，其中第一連接片及 第二連接片可以是雙點連接，可靠度佳，而可解決本領域目前所面臨的問題。The purpose of the present invention is to provide a novel semiconductor package structure including a lead frame, a high-side N-type transistor, a low-side N-type transistor, a first clip, and a second clip, wherein a connecting piece and The second connecting piece can be a double-point connection with good reliability, and can solve the problems currently faced in the art.
本創作提供的半導體封裝結構包含引線框架、高側N型電晶體、低側N型電晶體、第一連接片及第二連接片。引線框架包含一電源輸入板、一接地板及一相位板。高側N型電晶體設置於電源輸入板上。低側N型電晶體設置於接地板上。第一連接片設置於高側N型電晶體及低側N型電晶體上，其中高側N型電晶體透過第一連接片電性連接低側N型電晶體。第二連接片位於低側N型電晶體及相位板上，其中低側N型電晶體透過第二連接片電性連接相位板。The semiconductor package structure provided by the present invention comprises a lead frame, a high-side N-type transistor, a low-side N-type transistor, a first connecting piece and a second connecting piece. The lead frame includes a power input board, a ground board, and a phase board. The high-side N-type transistor is disposed on the power input board. The low side N-type transistor is disposed on the ground plate. The first connecting piece is disposed on the high-side N-type transistor and the low-side N-type transistor, wherein the high-side N-type transistor is electrically connected to the low-side N-type transistor through the first connecting piece. The second connecting piece is located on the low-side N-type transistor and the phase plate, wherein the low-side N-type transistor is electrically connected to the phase plate through the second connecting piece.
根據本創作之一實施例，低側N型電晶體之源極面向並電性連接接地板。According to an embodiment of the present invention, the source of the low-side N-type transistor faces and is electrically connected to the ground plate.
根據本創作之一實施例，高側N型電晶體之汲極面向並電性連接電源輸入板。According to an embodiment of the present invention, the drain of the high-side N-type transistor faces and is electrically connected to the power input board.
根據本創作之一實施例，高側N型電晶體之源極電性連接第一連接片。According to an embodiment of the present invention, the source of the high-side N-type transistor is electrically connected to the first connecting piece.
根據本創作之一實施例，低側N型電晶體之汲極電性連接第一連接片及第二連接片。According to an embodiment of the present invention, the drain of the low-side N-type transistor is electrically connected to the first connecting piece and the second connecting piece.
根據本創作之一實施例，第一連接片與第二連接片彼此分離。According to an embodiment of the present invention, the first connecting piece and the second connecting piece are separated from each other.
根據本創作之一實施例，第一連接片與第二連接片至少部分相互重疊。According to an embodiment of the present invention, the first connecting piece and the second connecting piece at least partially overlap each other.
根據本創作之一實施例，第一連接片之上視形狀與第二連接片之上視形狀互補。According to an embodiment of the present invention, the top tab shape of the first tab is complementary to the top view shape of the second tab.
根據本創作之一實施例，半導體封裝結構更包含一封裝材料層包覆高側N型電晶體及低側N型電晶體，並露 出第一連接片之一部分、第二連接片之一部分或其組合。According to an embodiment of the present invention, the semiconductor package structure further comprises a package material layer covering the high side N-type transistor and the low side N-type transistor, and exposing A portion of the first tab, a portion of the second tab, or a combination thereof.
根據本創作之一實施例，第一連接片及第二連接片皆為銅片。According to an embodiment of the present invention, the first connecting piece and the second connecting piece are both copper pieces.
根據本創作之一實施例，第二連接片之一側視形狀為Z形。According to an embodiment of the present invention, one of the second connecting pieces has a side view shape of a Z shape.
110‧‧‧引線框架110‧‧‧ lead frame
112‧‧‧電源輸入板112‧‧‧Power input board
114‧‧‧接地板114‧‧‧ Grounding plate
116‧‧‧相位板116‧‧‧phase plate
120‧‧‧第一連接片120‧‧‧First connecting piece
130‧‧‧第二連接片130‧‧‧Second connection piece
140‧‧‧導電黏著層140‧‧‧Electrically conductive adhesive layer
150‧‧‧封裝材料層150‧‧‧Package material layer
HS‧‧‧高側N型電晶體HS‧‧‧High-side N-type transistor
LS‧‧‧低側N型電晶體LS‧‧‧Low-side N-type transistor
第1圖係依照本創作之一實施例之轉換器的電路示意圖。Figure 1 is a circuit diagram of a converter in accordance with one embodiment of the present invention.
第2圖係依照本創作之一實施例之半導體封裝結構的剖面示意圖。2 is a cross-sectional view of a semiconductor package structure in accordance with an embodiment of the present invention.
第3圖係依照本創作之一實施例之半導體封裝結構的上視示意圖。Figure 3 is a top plan view of a semiconductor package structure in accordance with one embodiment of the present invention.
第4圖係依照本創作之另一實施例之半導體封裝結構的上視示意圖。4 is a top plan view of a semiconductor package structure in accordance with another embodiment of the present invention.
第5圖係依照本創作之又一實施例之半導體封裝結構的上視示意圖。Figure 5 is a top plan view of a semiconductor package structure in accordance with yet another embodiment of the present invention.
第6圖係依照本創作之另一實施例之半導體封裝結構的剖面示意圖。Figure 6 is a cross-sectional view showing a semiconductor package structure in accordance with another embodiment of the present invention.
第7圖係依照本創作之又一實施例之半導體封裝結構的剖面示意圖。Figure 7 is a cross-sectional view showing a semiconductor package structure in accordance with still another embodiment of the present invention.
以下將以圖式揭露本創作之複數個實施例，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然 而，應瞭解到，這些實務上的細節不應用以限制本創作。也就是說，在本創作部分實施例中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。In the following, a plurality of embodiments of the present invention are disclosed in the drawings, and for the sake of clarity, a number of practical details will be described in the following description. Of course However, it should be understood that these practical details are not applied to limit this creation. That is to say, in the part of this creation part, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.
本創作提供一種半導體封裝結構，其可應用在轉換器上。第1圖係依照本創作之一實施例之轉換器的電路圖。在一實施例中，此轉換器為直流-直流轉換器(DC-DC converter)。在一實施例中，此轉換器藉由高側N型電晶體HS及低側N型電晶體LS將輸入電壓轉為較低的輸出電壓。在一實施例中，一驅動晶片(未繪示)可透過驅動電路分別控制高側N型電晶體HS的閘極及低側N型電晶體LS的閘極的開啟或關閉，以將輸入電壓轉換為較低的輸出電壓。在一實施例中，驅動晶片可以與脈衝寬度調變(pulse-width modulation,PWM)控制晶片整合為一個控制器。The present application provides a semiconductor package structure that can be applied to a converter. Figure 1 is a circuit diagram of a converter in accordance with an embodiment of the present invention. In an embodiment, the converter is a DC-DC converter. In one embodiment, the converter converts the input voltage to a lower output voltage by the high side N-type transistor HS and the low side N-type transistor LS. In one embodiment, a driving chip (not shown) can respectively control the opening of the gate of the high-side N-type transistor HS and the gate of the low-side N-type transistor LS through the driving circuit to input the input voltage. Convert to a lower output voltage. In one embodiment, the driver die can be integrated into a controller with a pulse-width modulation (PWM) control chip.
在一實施例中，如第1圖所示，高側N型電晶體HS的汲極電性連接引線框架的電源輸入板112，以取得工作電壓。低側N型電晶體LS的源極電性連接引線框架的接地板114。高側N型電晶體HS的源極與低側N型電晶體LS的汲極電性連接引線框架的相位板116，以輸出電壓。在一實施例中，高側N型電晶體HS及低側N型電晶體LS與驅動電路整合在一起，而構成整合驅動型金氧半場效電晶體(driver MOS,DrMOS)。當然，在其他實施例中，高側N型電晶體HS及低側N型電晶體LS亦可不與驅動電路整合在一起。In one embodiment, as shown in FIG. 1, the drain of the high-side N-type transistor HS is electrically connected to the power input board 112 of the lead frame to obtain an operating voltage. The source of the low side N-type transistor LS is electrically connected to the ground plate 114 of the lead frame. The source of the high-side N-type transistor HS and the drain of the low-side N-type transistor LS are electrically connected to the phase plate 116 of the lead frame to output a voltage. In one embodiment, the high-side N-type transistor HS and the low-side N-type transistor LS are integrated with the driving circuit to form an integrated driving type MOS transistor (DrMOS). Of course, in other embodiments, the high-side N-type transistor HS and the low-side N-type transistor LS may not be integrated with the driving circuit.
第2圖係依照本創作之一實施例之半導體封裝結構的剖面示意圖。第3圖係依照本創作之一實施例之半導體封 裝結構的上視示意圖。以下請參照第2-3圖，半導體封裝結構包含引線框架110、高側N型電晶體HS、低側N型電晶體LS、第一連接片(clip)120及第二連接片(clip)130。引線框架110包含電源輸入板112、接地板114及相位板116。2 is a cross-sectional view of a semiconductor package structure in accordance with an embodiment of the present invention. Figure 3 is a semiconductor package in accordance with an embodiment of the present invention A top view of the structure. Referring to FIG. 2-3 below, the semiconductor package structure includes a lead frame 110, a high-side N-type transistor HS, a low-side N-type transistor LS, a first connecting clip (clip) 120, and a second connecting chip (clip) 130. . The lead frame 110 includes a power input board 112, a ground board 114, and a phase board 116.
高側N型電晶體HS設置於電源輸入板112上，因此高側N型電晶體HS在運作過程中產生的大量熱能可透過電源輸入板112散出。在一實施例中，高側N型電晶體HS透過導電黏著層140黏接電源輸入板112。在其他實施例中，高側N型電晶體透過熱壓而與電源輸入板接著。在一實施例中，高側N型電晶體HS的汲極面向並電性連接電源輸入板112，以取得工作電壓。在一實施例中，高側N型電晶體HS為溝渠式電晶體。The high-side N-type transistor HS is disposed on the power input board 112, so that a large amount of thermal energy generated by the high-side N-type transistor HS during operation can be dissipated through the power input board 112. In one embodiment, the high side N-type transistor HS is bonded to the power input board 112 through the conductive adhesive layer 140. In other embodiments, the high side N-type transistor is passed through the power input pad by hot pressing. In one embodiment, the drain of the high side N-type transistor HS faces and is electrically connected to the power input board 112 to obtain an operating voltage. In one embodiment, the high side N-type transistor HS is a trench type transistor.
低側N型電晶體LS設置於接地板114上，因此低側N型電晶體LS在運作過程中產生的大量熱能可透過接地板114散出。在一實施例中，低側N型電晶體LS透過導電黏著層140黏接接地板114。在其他實施例中，低側N型電晶體透過熱壓而與接地板接著。在一實施例中，低側N型電晶體LS的源極面向並電性連接接地板114。在一實施例中，低側N型電晶體LS為橫向雙擴散金氧半場效電晶體(lateral double-diffused MOS,LDMOS)。在一實施例中，低側N型電晶體LS為溝渠式電晶體。The low-side N-type transistor LS is disposed on the ground plate 114, so that a large amount of thermal energy generated during operation of the low-side N-type transistor LS can be dissipated through the ground plate 114. In one embodiment, the low side N-type transistor LS is bonded to the ground plane 114 through the conductive adhesive layer 140. In other embodiments, the low side N-type transistor is passed through the ground plate by hot pressing. In an embodiment, the source of the low side N-type transistor LS faces and is electrically connected to the ground plate 114. In one embodiment, the low side N-type transistor LS is a lateral double-diffused MOS (LDMOS). In one embodiment, the low side N-type transistor LS is a trench type transistor.
第一連接片120設置於高側N型電晶體HS及低側N型電晶體LS上。高側N型電晶體HS透過第一連接片120電性連接低側N型電晶體LS。在一實施例中，高側N型電晶體HS的源極電性連接第一連接片120。在一實施例中，高側N型電晶體HS的源極透過第一連接片120電性連接低 側N型電晶體LS的汲極。在一實施例中，高側N型電晶體HS透過導電黏著層140黏接第一連接片120，而低側N型電晶體LS透過另一導電黏著層140黏接第一連接片120。在其他實施例中，第一連接片藉由熱壓而與高側N型電晶體及低側N型電晶體接著。在一實施例中，第一連接片120為銅片(或稱銅薄板)，例如可為銅箔。The first connecting piece 120 is disposed on the high side N-type transistor HS and the low side N-type transistor LS. The high-side N-type transistor HS is electrically connected to the low-side N-type transistor LS through the first connection piece 120. In an embodiment, the source of the high-side N-type transistor HS is electrically connected to the first connecting piece 120. In an embodiment, the source of the high-side N-type transistor HS is electrically connected through the first connecting piece 120. The drain of the side N-type transistor LS. In one embodiment, the high-side N-type transistor HS is bonded to the first connecting piece 120 through the conductive adhesive layer 140, and the low-side N-type transistor LS is bonded to the first connecting piece 120 through the other conductive adhesive layer 140. In other embodiments, the first tab is followed by a high side N-type transistor and a low side N-type transistor by hot pressing. In an embodiment, the first connecting piece 120 is a copper piece (or a copper thin plate), and may be, for example, a copper foil.
第二連接片130位於低側N型電晶體LS及相位板116上。低側N型電晶體LS透過第二連接片130電性連接相位板116。在一實施例中，低側N型電晶體LS的汲極透過第二連接片130電性連接相位板116。在一實施例中，低側N型電晶體LS的汲極電性連接第一連接片120及第二連接片130。在一實施例中，低側N型電晶體LS透過導電黏著層140黏接第一連接片120及第二連接片130。在其他實施例中，第二連接片藉由熱壓而與低側N型電晶體及相位板接著。在本實施例中，第一連接片120與第二連接片130彼此分離。在一實施例中，第二連接片130為銅片，例如可為銅箔。在一實施例中，第二連接片130的側視形狀為Z形，以便於黏接或連接相位板116。也就是說，第二連接片130具有足夠的面積與相位板116黏著，而可避免脫落。The second connecting piece 130 is located on the low side N-type transistor LS and the phase plate 116. The low-side N-type transistor LS is electrically connected to the phase plate 116 through the second connecting piece 130. In one embodiment, the drain of the low side N-type transistor LS is electrically connected to the phase plate 116 through the second connecting piece 130. In one embodiment, the drain of the low-side N-type transistor LS is electrically connected to the first connecting piece 120 and the second connecting piece 130. In one embodiment, the low side N-type transistor LS is bonded to the first connecting piece 120 and the second connecting piece 130 through the conductive adhesive layer 140. In other embodiments, the second tab is followed by a low side N-type transistor and phase plate by hot pressing. In the embodiment, the first connecting piece 120 and the second connecting piece 130 are separated from each other. In an embodiment, the second connecting piece 130 is a copper piece, and may be, for example, a copper foil. In an embodiment, the second connecting piece 130 has a zigzag shape in a side view to facilitate bonding or connecting the phase plate 116. That is to say, the second connecting piece 130 has a sufficient area to adhere to the phase plate 116 to avoid falling off.
值得注意的是，第一連接片120以及第二連接片130可以是雙點連接。因此相較於單一個連接元件連接三點(例如連接高側N型電晶體、低側N型電晶體與相位板)而言，第一連接片120及第二連接片130的可靠度更佳。這是因為連接元件在連接這三點時或連接這三點之後，容易發生翹曲、連接不良或甚至脫落等現象，導致可靠度降低，或甚至無法使用。但本創作的第一連接片120及第二連接片130因 為是雙點連接，因此不會有前述問題產生。此外，相較於一般的打線，第一連接片120以及第二連接片130所需的空間較小，而可縮短高側N型電晶體HS及低側N型電晶體LS的距離。It should be noted that the first connecting piece 120 and the second connecting piece 130 may be a double point connection. Therefore, the reliability of the first connecting piece 120 and the second connecting piece 130 is better than that of a single connecting element connecting three points (for example, connecting a high-side N-type transistor, a low-side N-type transistor and a phase plate) . This is because the connecting element is prone to warping, poor connection, or even falling off when the three points are connected or after the three points are connected, resulting in a decrease in reliability or even inability to use. However, the first connecting piece 120 and the second connecting piece 130 of the present creation are In order to be a two-point connection, there is no such problem. In addition, the space required for the first connecting piece 120 and the second connecting piece 130 is smaller than that of the general wire bonding, and the distance between the high-side N-type transistor HS and the low-side N-type transistor LS can be shortened.
在一實施例中，第一連接片120與第二連接片130皆為銅片(或稱銅薄板)；相較於鋁帶，銅片的導電能力較佳。在一實施例中，第一連接片120與第二連接片130的厚度為約25微米至75微米，但不限於此。In one embodiment, the first connecting piece 120 and the second connecting piece 130 are both copper sheets (or copper sheets); compared to the aluminum strips, the copper sheets have better electrical conductivity. In an embodiment, the first tab 120 and the second tab 130 have a thickness of about 25 micrometers to 75 micrometers, but are not limited thereto.
在一實施例中，半導體封裝結構更包含封裝材料層150包覆高側N型電晶體HS及低側N型電晶體LS，以阻隔水氣腐蝕高側N型電晶體HS及低側N型電晶體LS。此外，封裝材料層150可露出第一連接片120的一部分、第二連接片130的一部分或其組合，以幫助散熱。如第2圖所示，封裝材料層150露出第一連接片120的一部分與第二連接片130的一部分，以幫助散熱，但本創作不限於此。In one embodiment, the semiconductor package structure further includes a package material layer 150 covering the high-side N-type transistor HS and the low-side N-type transistor LS to block the water vapor corrosion high-side N-type transistor HS and the low-side N-type Transistor LS. Additionally, the encapsulating material layer 150 may expose a portion of the first tab 120, a portion of the second tab 130, or a combination thereof to aid in heat dissipation. As shown in FIG. 2, the encapsulating material layer 150 exposes a portion of the first connecting piece 120 and a portion of the second connecting piece 130 to help dissipate heat, but the present creation is not limited thereto.
第4圖係依照本創作之另一實施例之半導體封裝結構的上視示意圖。特別的是，第一連接片120的上視形狀與第二連接片130的上視形狀互補。因為第一連接片120與第二連接片130具有相互對應的上視形狀，所以在製程對位時十分方便，使第一連接片120及第二連接片130可分別被準確地設置在高側N型電晶體HS與低側N型電晶體LS上，以及低側N型電晶體LS與相位板116上。4 is a top plan view of a semiconductor package structure in accordance with another embodiment of the present invention. In particular, the top view shape of the first web 120 is complementary to the top view shape of the second web 130. Because the first connecting piece 120 and the second connecting piece 130 have mutually corresponding top view shapes, it is convenient when the process is aligned, so that the first connecting piece 120 and the second connecting piece 130 can be accurately set on the high side, respectively. The N-type transistor HS and the low-side N-type transistor LS, and the low-side N-type transistor LS and the phase plate 116.
第5圖係依照本創作之又一實施例之半導體封裝結構的上視示意圖。在本實施例中，第一連接片120的上視形狀亦與第二連接片130的上視形狀互補，所以在製程對位時可使第一連接片120及第二連接片130分別被準確地設置在 高側N型電晶體HS與低側N型電晶體LS上，以及低側N型電晶體LS與相位板116上。Figure 5 is a top plan view of a semiconductor package structure in accordance with yet another embodiment of the present invention. In this embodiment, the top view shape of the first connecting piece 120 is also complementary to the top view shape of the second connecting piece 130. Therefore, the first connecting piece 120 and the second connecting piece 130 can be accurately determined when the process is aligned. Set in The high-side N-type transistor HS and the low-side N-type transistor LS, and the low-side N-type transistor LS and the phase plate 116.
第6圖係依照本創作之另一實施例之半導體封裝結構的剖面示意圖。第6圖與第2圖的差異在於，第6圖的第一連接片120與第二連接片130至少部分相互重疊，且第一連接片120位於第二連接片130的上方。因此在一實施例中，高側N型電晶體HS的源極是透過堆疊的第一連接片120與第二連接片130電性連接低側N型電晶體LS的汲極。Figure 6 is a cross-sectional view showing a semiconductor package structure in accordance with another embodiment of the present invention. The difference between FIG. 6 and FIG. 2 is that the first connecting piece 120 and the second connecting piece 130 of FIG. 6 at least partially overlap each other, and the first connecting piece 120 is located above the second connecting piece 130. Therefore, in one embodiment, the source of the high-side N-type transistor HS is electrically connected to the drain of the low-side N-type transistor LS through the stacked first connecting piece 120 and the second connecting piece 130.
第7圖係依照本創作之又一實施例之半導體封裝結構的剖面示意圖。第7圖與第2圖的差異在於，第7圖的第一連接片120與第二連接片130至少部分相互重疊，且第一連接片120位於第二連接片130的下方。因此在一實施例中，低側N型電晶體LS的汲極是透過堆疊的第一連接片120與第二連接片130電性連接相位板116。Figure 7 is a cross-sectional view showing a semiconductor package structure in accordance with still another embodiment of the present invention. The difference between FIG. 7 and FIG. 2 is that the first connecting piece 120 and the second connecting piece 130 of FIG. 7 at least partially overlap each other, and the first connecting piece 120 is located below the second connecting piece 130. Therefore, in one embodiment, the drain of the low-side N-type transistor LS is electrically connected to the phase plate 116 through the stacked first connecting piece 120 and the second connecting piece 130.
綜合上述，本創作提供一種半導體封裝結構，可藉由第一連接片及第二連接片進行雙點連接。相較於單一個連接元件連接三點，第一連接片及第二連接片的雙點連接的可靠度較佳。此外，第一連接片及第二連接片可為銅片，故其導電表現較為優異。In summary, the present invention provides a semiconductor package structure in which a two-point connection can be made by a first connection piece and a second connection piece. Compared with a single connection element connecting three points, the reliability of the two-point connection of the first connection piece and the second connection piece is better. In addition, the first connecting piece and the second connecting piece may be copper pieces, so that the conductive performance is excellent.
雖然本創作已以實施例揭露如上，然其並非用以限定本創作，任何熟習此技藝者，在不脫離本創作之精神和範圍內，當可作各種之更動與潤飾，因此本創作之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
110‧‧‧引線框架110‧‧‧ lead frame
112‧‧‧電源輸入板112‧‧‧Power input board
114‧‧‧接地板114‧‧‧ Grounding plate
116‧‧‧相位板116‧‧‧phase plate
120‧‧‧第一連接片120‧‧‧First connecting piece
130‧‧‧第二連接片130‧‧‧Second connection piece
140‧‧‧導電黏著層140‧‧‧Electrically conductive adhesive layer
150‧‧‧封裝材料層150‧‧‧Package material layer
HS‧‧‧高側N型電晶體HS‧‧‧High-side N-type transistor
LS‧‧‧低側N型電晶體LS‧‧‧Low-side N-type transistor
Claims (11)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103217686U TWM498384U (en) | 2014-10-03 | 2014-10-03 | Semiconductor package structure |
| CN201420606022.8U CN204102895U (en) | 2014-10-03 | 2014-10-20 | Semiconductor packaging structure |
| CN201510197454.7A CN106158734B (en) | 2014-10-03 | 2015-04-24 | Semiconductor packaging device |
| US14/732,130 US20160099198A1 (en) | 2014-10-03 | 2015-06-05 | Semiconductor package apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103217686U TWM498384U (en) | 2014-10-03 | 2014-10-03 | Semiconductor package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWM498384U true TWM498384U (en) | 2015-04-01 |
Family
ID=52271301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103217686U TWM498384U (en) | 2014-10-03 | 2014-10-03 | Semiconductor package structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN204102895U (en) |
| TW (1) | TWM498384U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI619226B (en) * | 2015-01-15 | 2018-03-21 | 力祥半導體股份有限公司 | Semiconductor package apparatus |
| CN106505058A (en) * | 2016-12-05 | 2017-03-15 | 嘉盛半导体(苏州)有限公司 | Semiconductor multi-chip modular system |
-
2014
- 2014-10-03 TW TW103217686U patent/TWM498384U/en unknown
- 2014-10-20 CN CN201420606022.8U patent/CN204102895U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN204102895U (en) | 2015-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3107120B1 (en) | Power semiconductor module | |
| JP4973059B2 (en) | Semiconductor device and power conversion device | |
| CN107534032B (en) | Semiconductor device with a plurality of semiconductor chips | |
| US9240371B2 (en) | Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module | |
| JP5273101B2 (en) | Semiconductor module and manufacturing method thereof | |
| JP7267930B2 (en) | semiconductor equipment | |
| JP6077773B2 (en) | Power module semiconductor device | |
| TWI493680B (en) | Power semiconductor package and manufacturing method thereof | |
| JP2017005165A (en) | Semiconductor device | |
| US20150221582A1 (en) | Connector frame and semiconductor device | |
| JP6610568B2 (en) | Semiconductor device | |
| CN105702639A (en) | integrated power assembly with stacked individually packaged power devices | |
| JP2012182250A (en) | Semiconductor device | |
| JP6354674B2 (en) | Semiconductor device | |
| TWM498384U (en) | Semiconductor package structure | |
| JP6922450B2 (en) | Semiconductor module | |
| JPWO2017130370A1 (en) | Semiconductor device | |
| JP7176397B2 (en) | Semiconductor device and its manufacturing method | |
| TWM456043U (en) | Power switch device | |
| CN107507814B (en) | Power semiconductor module comprising a switching device | |
| JP2015208200A (en) | Power supply device | |
| JP2017069351A (en) | Semiconductor device | |
| TWI619226B (en) | Semiconductor package apparatus | |
| TW201349398A (en) | Packaged circuit with a lead frame and laminate substrate | |
| US20230378145A1 (en) | Flip-Chip Packaged Power Transistor Module Having Built-in Gate Driver |