TWM482114U - High accuracy of the narrow border embedded flat display touch structure - Google Patents

Description

High-accuracy narrow bezel embedded flat display touch structure

The present invention relates to a structure having a touch panel, and more particularly to a high-accuracy narrow bezel embedded flat display touch structure.

Modern consumer electronic devices are often equipped with a touchpad as one of their input devices. The touchpad can be divided into resistive, capacitive, sonic, and optical types according to different sensing principles.

The technical principle of the touch panel is to detect the voltage, current, sound wave or infrared light according to different sensing methods when the finger or other medium touches the screen, thereby measuring the coordinate position of the touch pressure point. For example, the resistance type is to use the potential difference between the upper and lower electrodes to calculate the position of the pressure point to detect the touch point. A capacitive touch panel detects a change in capacitance from a generated current or voltage by utilizing a change in capacitance generated by electrostatic coupling between a transparent electrode arranged and a human body.

With the popularity of smart phones, the demand for multi-touch technology is increasing. At present, multi-touch is mainly realized by Projected Capacitive touch technology.

Projected capacitive technology is mainly through double-layer indium tin oxide Indium Tin Oxide (ITO) forms a matrix of interlaced sensing units to detect accurate touch positions. The basic principle of the projected capacitive touch technology is based on capacitive sensing. By designing a plurality of etched indium tin oxide electrodes, the array has different planes and transparent lines perpendicular to each other to form an X- and Y-axis drive. line. These wires are controlled by the controller, which sequentially feeds the detected capacitance value changes to the controller.

FIG. 1 is a schematic diagram of a conventional mutual capacitance sensing. The sensing conductor lines 110, 120 on the touch panel structure 100 sensed by the conventional mutual induction capacitance (Cm) are arranged along the first direction (X) and the second direction (Y). There is a mutual induction capacitance (Cm) 160 between the sensing conductor line 110 arranged in the first direction (X) and the sensing conductor line 120 arranged in the second direction (Y), and the mutual induction capacitance (Cm) 160 is not a physical capacitance, and the edge thereof is The mutual induction capacitance (Cm) between the sensing conductor line 110 arranged in the first direction (X) and the sensing conductor line 120 arranged in the second direction (Y).

When the touch sensing is to be performed, an internal driver (not shown) of the control circuit 131 on the flexible circuit board 130 drives the sensing conductor line 110 arranged in the first direction (X) for the first time period T1, and uses the same. The voltage Vy_1 charges the mutual induction capacitor (Cm) 160. During the first time period T1, all the sensors (not shown) inside the control circuit 131 sense all the second direction (Y) arranged on the sensing conductor line 120. The voltage (Vo_1, Vo_2, ..., Vo_n) is used to obtain n data, that is, after m driving cycles, m×n data can be obtained.

The mutual sensing capacitor (Cm) is mainly used to form a matrix of interlaced sensing units with double-layer Indium Tin Oxide (ITO) on the display panel to detect an accurate touch position. . therefore Will increase manufacturing procedures and costs. At the same time, when the sensing conductor 120 transmits the sensed signal to the control circuit 131 on the flexible circuit board 130 when performing the touch sensing, the side line 150 of the panel 140 needs to be routed to connect to the flexible circuit board. 130. This design will increase the width of the touch panel border and is not suitable for the narrow bezel design trend.

In view of the above problems, the In-Cell Touch technology integrates the touch components into the display panel, so that the display panel itself has a touch function, so that no additional process of assembling or assembling with the touch panel is required. The In-Cell Touch technology is provided with an ITO transparent sensing electrode layer or an optical sensing element on the upper glass substrate or the lower glass substrate of the display panel. However, this not only increases the cost, but also increases the process procedure, which leads to a decrease in process yield and a rise in process cost, and a need for a stronger backlight with a lower aperture ratio, which also increases power consumption. Therefore, there is still room for improvement in the conventional flat display touch structure.

The main purpose of this creation is to provide a high-accuracy narrow-frame in-line flat-panel display touch structure, which only needs to be connected on one side, which can increase the amount of capacitance change between conductor blocks, and use less The voltage can drive the conductor block line and improve the accuracy of contact point detection.

According to one of the features of the present invention, the present invention provides a high-accuracy narrow bezel embedded flat display touch structure, including a first substrate, a second substrate, a thin film transistor layer, a sensing electrode and a trace layer. ,and A sensing electrode layer. The first substrate and the second substrate are arranged in a parallel pair to sandwich a display layer between the two substrates. The thin film transistor layer is located on a surface of the second substrate facing the display layer, the thin film transistor layer has K gate driving lines and L source driving lines, the K gate driving lines and the L strips The source driving line is disposed in a first direction and a second direction to form a plurality of pixel blocks, each pixel block having a corresponding pixel transistor and a pixel capacitor, according to a display pixel signal And displaying a driving signal to drive the corresponding pixel transistor and the pixel capacitor to perform a display operation, wherein K and L are positive integers. The sensing electrode and the wiring layer are located on one side of the thin film transistor layer facing the display layer, and have M first conductor block lines and N connecting lines arranged along a first direction, according to a touch Controlling the driving signal to sense whether there is an external object approaching, wherein M and N are positive integers, and each of the first conductor block lines of the M first conductor block lines is composed of a plurality of first conductor blocks. The sensing electrode layer is located on a side of the thin film transistor layer facing the display layer, and is disposed between the sensing electrode and the wiring layer and the thin film transistor layer, and has N arranged along a second direction The second conductor block line receives the touch driving signal when performing touch sensing, and each second conductor block line extends to the high-accuracy narrow border with a corresponding ith connecting line The planar display shows one side of the touch structure, i is a positive integer and 1≦i≦N, and each of the second conductor block lines of the N second conductor block lines is composed of a plurality of second conductor blocks The plurality of first conductor blocks, the N connecting lines, and the plurality of second conductor blocks are located according to the K gate driving lines and the L sources of the thin film transistor layer The position of the pole drive line is set correspondingly.

According to another feature of the present invention, the present invention provides a high-accuracy narrow-frame in-cell planar display touch structure, including a first substrate, a second substrate, a thin film transistor layer, a sensing electrode layer, and A sensing electrode and a wiring layer. The first substrate and the second substrate are arranged in a parallel pair to sandwich a display layer between the two substrates. The thin film transistor layer is located on a surface of the second substrate facing the display layer, the thin film transistor layer has K gate driving lines and L source driving lines, the K gate driving lines and the L strips The source driving line is disposed in a first direction and a second direction to form a plurality of pixel blocks, each pixel block having a corresponding pixel transistor and a pixel capacitor, according to a display pixel signal And displaying a driving signal to drive the corresponding pixel transistor and the pixel capacitor to perform a display operation, wherein K and L are positive integers. The sensing electrode layer is located on one side of the thin film transistor layer facing the display layer, and has N second conductor block lines arranged along a second direction. When performing touch sensing, receiving a touch driving Signal. The sensing electrode and the wiring layer are located on one side of the sensing electrode layer facing the display layer, and have M first conductor block lines and N connecting lines arranged along a first direction, according to a touch Driving the signal to sense whether there is an external object approaching, wherein M and N are positive integers, and each of the first conductor block lines of the M first conductor block lines is composed of a plurality of first conductor blocks. The positions of the plurality of first conductor blocks, the N connecting lines, and the plurality of second conductor blocks are driven according to the K gate driving lines and the L source driving lines of the thin film transistor layer. The positions of the lines are correspondingly arranged, and when the first conductor block and the second conductor block are stacked, they are stacked in a differential manner.

100‧‧‧Touch panel structure for mutual induction capacitance sensing

110,120‧‧‧Inductive conductor lines

160‧‧‧ mutual induction capacitor

130‧‧‧Soft circuit board

131‧‧‧Control circuit

140‧‧‧ panel

150‧‧‧ side

200‧‧‧High-accuracy narrow bezel in-line flat display touch structure

210‧‧‧First substrate

220‧‧‧second substrate

230‧‧‧Display layer

240‧‧‧film transistor layer

250‧‧‧Induction electrode and trace layer

260‧‧‧Induction electrode layer

270‧‧‧ shading layer

280‧‧‧Color filter layer

300‧‧‧First polarizing layer

310‧‧‧Second polarizing layer

320‧‧‧First insulation

330‧‧‧Second insulation

340‧‧‧ third insulation layer

291‧‧‧Thin film transistor

293‧‧‧Transparent electrode

271‧‧‧ shading lines

273‧‧‧ shading block

40-1, 40-2,...,40-M‧‧‧first conductor block line

41-1, 41-2,...,41-N‧‧‧Connected cable

400‧‧‧First conductor block

50-1, 50-2,...,50-N‧‧‧Second conductor block line

201‧‧‧ side

500‧‧‧Second conductor block

600‧‧‧Soft circuit board

610‧‧‧Control circuit

241‧‧‧ gate drive line

243‧‧‧Source drive line

245,245-1,245-2,245-3,245-4,245-5‧‧‧ pixels block

Vertex of Q‧‧‧

P‧‧‧ vertex

O1, O2, O3, O4, O5‧‧‧ Vertices

X1, X2‧‧ Center

V1~V5‧‧‧ ellipse

H1~H6‧‧‧ ellipse

52‧‧‧through holes

S1, S2‧‧ points

L1‧‧‧ line segment

L2‧‧‧ line segment

1200‧‧‧High-accuracy narrow bezel in-line flat display touch structure

1210‧‧‧ cathode layer

1220‧‧‧Display layer

1230‧‧‧ anode layer

1231‧‧‧Anode element electrode

1221‧‧‧ hole transmission sublayer

1223‧‧‧Lighting layer

1225‧‧‧Electronic transmission sublayer

247‧‧‧ pixel drive circuit

2471‧‧‧ gate

2473‧‧‧Bungee/source

2475‧‧‧Bungee/source

1290‧‧‧Organic LED layer

1300‧‧‧High-accuracy narrow bezel in-line flat display touch structure

FIG. 1 is a schematic diagram of a conventional mutual induction capacitance sensing.

FIG. 2 is a schematic diagram of a stack of a high-accuracy narrow bezel embedded flat display touch structure of the present invention.

Figure 3 is a schematic illustration of a light shielding layer.

FIG. 4 is a schematic diagram of the sensing electrode and the wiring layer and the sensing electrode layer.

FIG. 5 is a schematic diagram of the first conductor block line and the second conductor block line of the present invention.

FIG. 6 is another schematic diagram of the first conductor block line and the second conductor block line of the present invention.

7A and FIG. 7B are schematic diagrams showing the mutual induction capacitance of the first conductor block and the second conductor block of the present invention.

Figure 8 is a cross-sectional view taken along line A-A' of Figure 4 of the present invention.

FIG. 9 is still another schematic diagram of the first conductor block line and the second conductor block line of the present invention.

FIG. 10 is another schematic diagram of a high-accuracy narrow bezel embedded flat display touch structure of the present invention.

Figure 11 is a schematic illustration of the first conductor block line of the present invention.

FIG. 12 is another stacked diagram of a high-accuracy narrow-frame in-cell planar display touch structure of the present invention.

FIG. 13 is another stacked schematic diagram of a high-accuracy narrow-frame in-cell planar display touch structure of the present invention.

This creation is about a high-accuracy narrow bezel embedded flat display touch structure. FIG. 2 is a schematic diagram of a high-accuracy narrow-frame in-cell planar display touch structure 200. As shown in FIG. 2, the high-accuracy narrow bezel in-line display touch structure 200 includes There is a first substrate 210, a second substrate 220, a display layer 230, a thin film transistor layer 240, a sensing electrode and wiring layer 250, a sensing electrode layer 260, a black matrix 270, a color a color filter 280, a first polarizer layer 300, a second polarizer layer 310, a first insulating layer 320, a second insulating layer 330, and a third insulating layer Layer 340. The display layer 230 is preferably a liquid crystal layer in this embodiment.

The first substrate 210 and the second substrate 220 are preferably glass substrates. The first substrate 210 and the second substrate 220 are disposed in parallel with each other to sandwich the display layer 230 between the two substrates 210 and 220. The second substrate 220 is generally referred to as a thin film transistor substrate (TFT substrate), and the thin film transistor used as a switch is generally disposed on a thin film transistor substrate (TFT substrate).

The black matrix 270 is located on a surface of the first substrate 210 facing the display layer 230. The light shielding layer 270 is formed by a plurality of light shielding lines, and the plurality of light shielding lines 271 are disposed in a first direction. (X) and a second direction (Y) to form a plurality of light shielding blocks 273 comprising a light shielding grid and a light transmitting region.

3 is a schematic view of a light shielding layer 270 which is the same as a light shielding layer of a conventional liquid crystal display. As shown in FIG. 3, the light shielding layer 270 is impervious The black insulating material of the light constitutes a plurality of light-shielding lines 271, and the plurality of light-shielding lines 271 of the black insulating material are vertically distributed to the conventional light-shielding layer 270, so the light-shielding layer 270 is also called a black matrix. ). The present invention has such a light shielding layer 270, and a color filter 280 is distributed over the light blocking block 273 between the lines of the black insulating material.

In the present invention, the sensing electrode, the wiring layer 250 and the sensing electrode layer 260 are disposed on the side of the thin film transistor layer 240 facing the display layer 230, and an inductive touch pattern structure is implanted thereon.

The thin film transistor layer 240 is located on a surface of the second substrate 220 facing the display layer 230. The thin film transistor layer 240 has K gate driving lines and L source driving lines, and the K gate driving The line and the L source driving lines are disposed in the first direction (X) and the second direction (Y) to form a plurality of pixel blocks. Each pixel block has a corresponding pixel transistor and a pixel capacitor, and drives the corresponding pixel transistor and the pixel capacitor according to a display pixel signal and a display driving signal to perform a display operation. Where K and L are positive integers. The thin film transistor layer 240 has a thin film transistor 291 and a transparent electrode 293. The transparent electrode 293 and a common electrode layer (Vcom, not shown) form the aforementioned pixel capacitance.

FIG. 4 is a schematic diagram of the sensing electrode and the wiring layer and the sensing electrode layer. The sensing electrode and the wiring layer 250 are located on one side of the thin film transistor layer 240 facing the display layer 230, and have M first conductor block lines 40-1 arranged along a first direction (X). 40-2,..., 40-M and N connecting wires 41-1, 41-2, ..., 41-N, which sense whether there is an external object approaching according to a touch driving signal, wherein, M , N is a positive integer. The M first conductor block lines 40-1, Each of the first conductor block lines of 40-2, ..., 40-M is comprised of a plurality of first conductor blocks 400. Wherein, the M first conductor block lines 40-1, 40-2, ..., 40-M and the N connection lines 41-1, 41-2, ..., 41-N are made of metal Made of a conductive material, in the present embodiment, the lengths of the N connecting wires 41-1, 41-2, ..., 41-N are the same.

The sensing electrode layer 260 is located on a surface of the thin film transistor layer 240 facing the display layer 230, and is interposed between the sensing electrode and the wiring layer 250 and the thin film transistor layer 240, and has a along N second conductor block lines 50-1, 50-2, ..., 50-N arranged in a second direction (Y), which receive the touch drive signal when performing touch sensing, each The two conductor block lines 50-1, 50-2, ..., 50-N extend to the high accuracy with a corresponding ith connection line 41-1, 41-2, ..., 41-N The narrow frame in-line display shows one side 201 of the touch structure, i is a positive integer and 1≦i≦N. Each of the N second conductor block lines 50-1, 50-2, ..., 50-N is composed of a plurality of second conductor blocks 500. Wherein the first direction is perpendicular to the second direction. The plurality of first conductor blocks 400, the N connecting lines 41-1, 41-2, ..., 41-N, and the positions of the plurality of second conductor blocks 500 are based on the thin film transistor The K gate drive lines of the layer 240 and the positions of the L source drive lines are disposed correspondingly.

As shown in FIG. 4, the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, .. Each of the conductor block lines of 50-N is composed of the plurality of first conductor blocks 400 and the plurality of second conductor blocks 500, respectively.

Each of the M first conductor block lines 40-1, 40-2, ..., 40-M A plurality of first conductor blocks 400 of a first conductor block line form a quadrilateral region electrically connected together, and the M first conductor block lines 40-1, 40-2, ..., There is no electrical connection between each of the first conductor block lines of the 40-M. Similarly, the plurality of second conductor blocks 500 of each of the N second conductor block lines 50-1, 50-2, ..., 50-N form a quadrilateral type The regions are electrically connected together, and each of the N second conductor block lines 50-1, 50-2, ..., 50-N is not connected between each of the second conductor block lines. Wherein, each of the N connecting lines is arranged between the two first conductor block lines 40-1, 40-2, ..., 40-M.

The M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50-N and Not electrically connected. A first insulating layer 320 is disposed between the sensing electrode and the wiring layer 250 and the sensing electrode layer 260. Alternatively, only the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., An insulating block is provided at the 50-N intersection.

The plurality of first conductor blocks 400 and the plurality of second conductor blocks 500 form a quadrilateral region and are made of a metal conductive material, wherein the quadrilateral region is one of the following shapes: a rectangle, square. The metal conductive material is one of the following: molybdenum, niobium, aluminum, silver, copper, titanium, nickel, lanthanum, cobalt, tungsten, magnesium (Mg), calcium (Ca), potassium (K), lithium (Li) Indium (In), alloy, lithium fluoride (LiF), magnesium fluoride (MgF2), lithium oxide (LiO).

Each of the N connecting wires 41-1, 41-2, ..., 41-N is disposed on the two first conductor block lines 40-1, 40-2, ..., 40- Between M.

Figure 5 is the first conductor block line and the second conductor block of the present invention. Schematic diagram of the line, gate drive line and source drive line. The plurality of first conductor blocks 400, the N connecting lines 41-1, 41-2, ..., 41-N, and the positions of the plurality of second conductor blocks 500 are based on the thin film transistor The positions of the K gate driving lines 241 and the L source driving lines 243 of the layer 240 are correspondingly arranged.

In FIG. 5, the gate drive lines 241 are arranged along the second direction (Y), and the source drive lines 243 are arranged along the first direction (X). In other embodiments, the gate drive lines 241 can be aligned along a first direction (X) and the source drive lines 243 can be aligned along a second direction (Y). As shown in FIG. 4, the K gate driving lines 241 of the thin film transistor layer 240 and the L source driving lines 243 of the thin film transistor layer 240 form a plurality of pixel blocks 245. The length and width of each pixel block 245 are a first distance d1 and a second distance d2, respectively.

As shown in FIG. 5, when the first conductor block line and the second conductor block line are stacked, they are stacked in a dislocation manner. The center position of the first conductor block 400 and the center position of the second conductor block 500 are different in the second direction (Y) by a first multiple h of the first distance d1, in the first direction (X) And a second multiple of the second distance d2, wherein h and w are positive integers.

The length and width of each pixel block of the plurality of pixel blocks 245 are the first distance d1 and the second distance d2, respectively. The length and width of each of the first conductor blocks 400 of the plurality of first conductor blocks are respectively a third distance and a fourth distance, and each second conductor block 500 of the plurality of second conductor blocks The length and the width are respectively the fifth distance and the sixth distance, wherein the third distance is twice the third multiple of the first distance d1 (=2h1×d1), and the fourth distance is the second distance Double the fourth multiple of d2, w1 (2w1×d2), the fifth distance is twice (=2h2×d1) of a fifth multiple h2 of the first distance d1, and the sixth distance is twice the sixth multiple of the second distance d2 2w2×d2), where h1, w1, h2, and w2 are positive integers.

As shown in FIG. 5, the length and width of each pixel block of the plurality of pixel blocks 245 are the first distance d1 and the second distance d2, respectively, and the third multiple h1 is 1, the fourth multiple. When w1 is 1, the fifth multiple h2 is 1, and the sixth multiple is w1, the length and width of each first conductor block of the plurality of first conductor blocks 400 are respectively a third distance and a fourth The length and the width of each of the second conductor blocks of the plurality of second conductor blocks 500 are the fifth distance and the sixth distance, respectively. That is, since the third multiple h1 is 1, the fourth multiple w1 is 1, the fifth multiple h2 is 1, and the sixth multiple w2 is 1, the third distance is twice the first distance d1 (= 2h1 × D1=2×d1), the fourth distance is twice the second distance d2 (2w1×d2=2×d2), and the fifth distance is twice the first distance d1 (=2h2×d1=2×d1 The sixth distance is twice the second distance d2 (2w2 × d2 = 2 × d2). That is, the size of each of the first conductor block 400 and each of the second conductor blocks 500 is the size of the four pixel blocks 245.

As shown in FIG. 5, when the first conductor block 400 and the second conductor block 500 are dislocated, the center position X1 of the first conductor block 400 and the second conductor block are overlapped. The center position X2 of 500 is different by one time in the second direction (Y) by a first distance d1 (=hxd1=d1), and the first direction (X) is different by one w times by the second distance d2 (=w× D2=d2). That is, when the vertex P of the first conductor block 400 is aligned with the vertex O1 of the pixel block 245-1, the vertex Q of the second conductor block 500 and the vertex of the first conductor block 400 P differs by a first distance d1 in the second direction (Y) and a second distance d2 in the first direction (X). When the vertex P of the first conductor block 400 is aligned with the vertex O1 of the pixel block 245-1, the vertex Q of the second conductor block 500 is aligned with the vertex O2 of the pixel block 245-2. Or, the center point X1 of the first conductor block 400 is aligned with the vertex O2 of the pixel block 245-2, and the center point X2 of the second conductor block 500 and the vertex O3 of the pixel block 245-3 Align.

The distance between the first conductor block 400 and the second conductor block 500, the distance between the line width and the gate drive line 241, the line width and the distance between the source drive line 243, the line width, and the thin film The crystal layer 240 must be provided with a gate driving line 241 and a source driving line 243 to form a pixel block 245. Therefore, the first conductor block 400 and the second conductor block 500 of the present case do not affect the light transmittance.

FIG. 6 is another schematic diagram of the first conductor block line and the second conductor block line of the present invention. The center position of the first conductor block 400 and the center position of the second conductor block 500 are different in the second direction (Y) by a first multiple h of the first distance d1, in the first direction ( X) is a difference between a second distance d2 and a second multiple, where h and w are positive integers. The length and width of each pixel block of the plurality of pixel blocks 245 are the first distance d1 and the second distance d2, respectively. The length and width of each of the first conductor blocks 400 of the plurality of first conductor blocks are respectively a third distance and a fourth distance, and each second conductor block 500 of the plurality of second conductor blocks The length and the width are respectively the fifth distance and the sixth distance, wherein the third distance is twice the third multiple of the first distance d1 (=2h1×d1), and the fourth distance is the second distance Twice the fourth multiple w1 of d2 (2w1×d2), the fifth distance being twice the fifth multiple of the first distance h2 (=2h2×d1), the sixth distance being the second distance Double the multiple of six times w2 (2w2 × d2).

As shown in FIG. 6, the length and width of each pixel block 245 of the plurality of pixel blocks are the first distance d1 and the second distance d2, respectively, and the third multiple h1 is 2 and the fourth multiple. When w1 is 2, the fifth multiple h2 is 2, and the sixth multiple w2 is 2, the third distance is four times the first distance d1 (=2h1×d1=4×d1), and the fourth distance is the second distance. Four times d2 (2w1 × d2 = 4 × d2), the fifth distance is four times the first distance d1 (= 2h2 × d1 = 4 × d1), and the sixth distance is four times the second distance d2 ( 2w2 × d2 = 4 × d2). That is, the size of each of the first conductor block 400 and each of the second conductor blocks 500 is the size of the 16 pixel blocks 245.

When the first conductor block 400 and the second conductor block 500 are dislocated, the center position of the first conductor block 400 and the center position X2 of the second conductor block 500 are In the second direction (Y), the first multiple is h times the first distance, the first multiple h is 2 (h×d1=2d1), and the first direction (X) is different by a second multiple w times second For the distance, the second multiple h is 2 (wxd2 = 2d2). That is, the vertex Q of the second conductor block 500 and the vertex P of the first conductor block 400 are different by a second distance (h×d1=2d1) in the second direction (Y). The first direction (X) differs by a factor of two from the second distance (wxd2 = 2d2). When the vertex P of the first conductor block 400 is aligned with the vertex O1 of the pixel block 245-1, the vertex Q of the second conductor block 500 is aligned with the vertex O3 of the pixel block 245-3. Or, the center point X1 of the first conductor block 400 is aligned with the vertex O3 of the pixel block 245-3, and the second conductor block The center point X2 of 500 is aligned with the vertex O5 of the pixel block 245-5.

5, FIG. 6 and related description, when the third multiple h1 is 2 and the fourth multiple w1 is 3, the fifth multiple h2 is 2, the sixth multiple is w2, or other values, the skilled person is familiar with The case where the first conductor block line 400 and the second conductor block line 500 are overlapped in a dislocation manner can be known according to the description of the present invention, and details are not described herein again.

7A and 7B are schematic diagrams showing the mutual capacitance of the first conductor block and the second conductor block of the present invention. As shown in FIG. 7A, the first conductor block line 40-1 is parallel to the second conductor block line 50-N at the ellipse V1 and the ellipse V3 at the ellipse V2, and the second conductor block line 50- N is parallel to the first conductor block line 40-1 at the ellipse V2 and the ellipse V4 at the ellipse V3, thereby increasing the distance between the first conductor block line 40-1 and the second conductor block line 50-N. Induction capacitor. Similarly, as shown in FIG. 7B, the second conductor block line 50-N is parallel to the first conductor block line 40-1 at the ellipse H1 and the ellipse H3 at the ellipse H2, thereby increasing the first conductor block. The induced capacitance between the line 40-1 and the second conductor block line 50-N. Similarly, the first conductor block line 40-1 is parallel to the second conductor block line 50-N at the ellipse H2 and the ellipse H4 at the ellipse H3. The present invention can increase the first conductor block line 40-1, 40-2, by disposing the first conductor block line and the second conductor block line in a dislocation manner. The induced capacitance between 40-M and the second conductor block lines 50-1, 50-2, ..., 50-N. Therefore, the internal driver (not shown) of the control circuit can use a smaller voltage to drive the first conductor block line, and obtain the same amount of induced capacitance change as the prior art, which can save power consumption compared with the prior art. This creation is especially suitable for handheld devices. At the same time, because of Change in induced capacitance between the first conductor block lines 40-1, 40-2, ..., 40-M and the second conductor block lines 50-1, 50-2, ..., 50-N As the amount becomes larger, the sensor of the control circuit (not shown) can more accurately detect the voltage on the second conductor block lines 50-1, 50-2, ..., 50-N, and can raise the touch. The accuracy of the touch.

As shown in FIG. 4, each of the second conductor block lines 50-1, 50-2, ..., 50-N is at the dotted ellipse and the corresponding connecting line 41-1, 41-2, ... 41-N is electrically connected, and each of the N connecting wires 41-1, 41-2, ..., 41-N also extends to the high-precision narrow frame with corresponding metal wires respectively The in-line plane displays the same side 201 of the touch structure 200 for further connection to a flexible circuit board 600. Each of the first conductor block lines 40-1, 40-2, ..., 40-M extends to the same side 201 of the panel with corresponding metal traces for further connection to a flexible circuit board 600 .

The surface of the high-accuracy narrow-frame in-line display touch structure 200 is configured to receive at least one touch point. The control circuit 610 further includes a control circuit 610 electrically connected to the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second via the flexible circuit board 600. Conductor block lines 50-1, 50-2, ..., 50-N.

The M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50-N Correspondingly generating an inductive signal according to the position of the at least one touch point of the high-accuracy narrow-frame embedded in-plane display touch structure 200 according to a finger or an external object. A control circuit 610 is electrically connected to the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50 via the flexible circuit board 600. -1, 50-2, ..., 50-N, and calculating the coordinates of the at least one touch point according to the sensing signal.

Figure 8 is a cross-sectional view taken along line A-A' of Figure 4 of the present invention. As shown in FIG. 8, the second conductor block line 50-N is electrically connected to the connection line 41-1 at the B ellipse in FIG. As shown in FIG. 2 and FIG. 8 , the first insulating layer 320 is disposed between the sensing electrode and the wiring layer 250 and the sensing electrode layer 260 , and the second conductor block line 50-N passes through the through hole (via The second insulating layer 320 is electrically connected to the connecting line 41-1, that is, the second conductor block line 50-N can sense the signal through the connecting line 41-1. Transfer to the control circuit 610.

In the embodiment of FIG. 5 and FIG. 6, the third distance is twice (=2h1×d1) of the third multiple h1 of the first distance d1, and the fourth distance is the second distance d2. Two times the quadruple number w1 (2w1×d2), the fifth distance being twice (=2h2×d1) of the fifth multiple h2 of the first distance d1, the sixth distance being the second distance d2 Double the sixth multiple w2 (2w2 × d2). In other embodiments, the third distance is greater than or equal to twice the first distance d1, and the fourth distance is greater than or equal to twice the second distance d2, and the fifth distance is greater than or equal to the second distance. The first distance d1 is twice as long as the sixth distance is greater than or equal to twice the second distance d2.

FIG. 9 is still another schematic diagram of the first conductor block line and the second conductor block line of the present invention. As shown in FIG. 9, the third distance is twice the first distance d1, and the fourth distance is three times the second distance d2, and the fifth distance is twice the first distance d1. The six distances are three times the second distance d2. At this time, the center position of the first conductor block 400 and the center position X2 of the second conductor block 500 in X1 are different by a first distance (d1) in the second direction (Y), in the first direction ( X) differs by a second distance (d2). That is, when the first guide When the vertex P of the body block 400 is aligned with the vertex O1 of the pixel block 245-1, the vertex Q of the second conductor block 500 and the vertex P of the first conductor block 400 are in the second direction (Y) The upper phase is separated by a first distance (d1) which is different by a second distance (d2) in the first direction (X). When the vertex P of the first conductor block 400 is aligned with the vertex O1 of the pixel block 245-1, the vertex Q of the second conductor block 500 is aligned with the vertex O2 of the pixel block 245-2. Or, the center point X1 of the first conductor block 400 is aligned with a point S1 of the pixel block 245-2, and the center point X2 of the second conductor block 500 and the point S2 of the pixel block 245-3 Align.

As can be seen from FIG. 5, FIG. 6 and FIG. 9, in the present creation, the first multiple h is less than or equal to the smaller of the third multiple h1 or the fifth multiple h2, and the second multiple w is less than or equal to the first The smaller of the quadruple number w1 or the sixth multiple w2. It can be expressed by a mathematical formula: h≦min(h1, h2), w≦min(w1, w2), where h is the first multiple, w is the second multiple, h1 is the third multiple, w1 is the The fourth multiple, h2 is the fifth multiple, and w2 is the sixth multiple.

FIG. 10 is another schematic diagram of a high-accuracy narrow bezel embedded flat display touch structure 200 of the present invention. The main difference from FIG. 4 is that the lengths of the N connecting lines 41-1, 41-2, ..., 41-N are not uniform, but are gradually reduced.

Figure 11 is a schematic view showing the first conductor block lines 40-1, 40-2, ..., 40-M of the present invention, as shown in Figure 11, the first conductor block lines 40-1, 40-2, ..., 40-M is the first conductor block 400 of 24 rows in the second direction, and the first conductor block 400 of 2 rows in the first direction The rectangle formed. In other embodiments, the number of the first conductor blocks 400 can be Need to change.

The width of the line segment L1 and the line segment L2 is preferably the same as or slightly smaller than the width of the gate driving line 241 or the width of the source driving line 243. The M first conductor block lines 40-1, 40-2, ..., 40-M, the N connection lines 41-1, 41-2, ..., 41-N, and the N pieces The positions of the second conductor block lines 50-1, 50-2, ..., 50-N are based on the positions of the plurality of gate drive lines 241 and the source drive lines 243 of the thin film transistor layer 240. Set accordingly. The plurality of light-shielding lines 271 are mainly intended to cover the gate driving line 241 and the source driving line 243. That is, the M first strip conductor lines 40-1, 40-2, ..., 40-M, and the N connecting lines 41 are viewed from the first substrate 210 toward the second substrate 220. -1, 41-2, ..., 41-N, and the N second conductor block lines 50-1, 50-2, ..., 50-N are disposed on the plurality of shading lines 271 The lower part of the position is thus covered by the plurality of light-shielding lines 271, and the user can not see the M first conductor block lines 40-1, 40-2, ..., 40-M, the N pieces Connecting wires 41-1, 41-2, ..., 41-N, and the N second conductor block wires 50-1, 50-2, ..., 50-N, thus not affecting light transmission rate.

A first insulating layer 320 is disposed between the sensing electrode and the wiring layer 250 and the sensing electrode layer 260. A second insulating layer 330 may be disposed between the sensing electrode layer 260 and the thin film transistor layer 240. The color filter layer 280 is located on a surface of the light shielding layer 270 facing the display layer 230 side. A third insulating layer 340 is disposed between the color filter layer 280 and the display layer 230. The first polarizing layer 300 is located on a surface of the first substrate 210 facing away from the display layer 230. The second polarizing layer 310 is located on a surface of the lower substrate 220 facing away from the display layer 230.

Figure 12 is a high-accuracy narrow border inlay of the creation. As shown in FIG. 12 , the high-precision narrow-frame in-cell planar display touch structure 1200 includes a first substrate 210 , a second substrate 220 , and a a thin film transistor layer 240, a sensing electrode and wiring layer 250, a sensing electrode layer 260, a black matrix 270, a color filter 280, a first insulating layer 320, and a first A second insulating layer 330, a cathode layer 1210, a display layer 1220, and an anode layer 1230. The display layer 1220 is preferably an organic light emitting diode layer 1290 in this embodiment. The main difference from FIG. 2 is that the organic light emitting diode layer 1290 is used instead of the liquid crystal layer, so the cathode layer 1210 and the anode layer 1230 are also added.

In this embodiment, the sensing electrode, the wiring layer 250 and the sensing electrode layer 260 are disposed on the side of the thin film transistor layer 240 facing the display layer 1220, and an inductive touch pattern structure is implanted thereon. M first conductor block lines 40-1, 40-2, ..., 40-M and N connection lines 41-1, 41-2, ... disposed in the sensing electrode and wiring layer 250, 41-N, and the details of the N second conductor block lines 50-1, 50-2, ..., 50-N disposed in the sensing electrode layer 260 are as in the first embodiment, and in FIGS. 3 to 11. It is disclosed that those skilled in the art can complete the disclosure based on the first embodiment of the present invention, and therefore will not be described again.

The organic light emitting diode layer 1290 includes a hole transporting layer (HTL) 1221, an emitting layer 1223, and an electron transporting layer (HTL) 1225.

The thin film transistor layer 240 is located on a surface of the second substrate 220 facing the organic light emitting diode layer 1290, and the thin film transistor layer The 240 has a plurality of gate driving lines (not shown), a plurality of source driving lines (not shown), and a plurality of pixel driving circuits 247. Each of the pixel driving circuits 247 corresponds to a pixel, according to A display pixel signal and a display driving signal are used to drive the corresponding pixel driving circuit 247 to perform a display operation.

Depending on the design of the pixel driving circuit 247, for example, the 2T1C is designed as a pixel driving circuit 247 by a thin film transistor and a storage capacitor, and the 6T2C is designed as a pixel driving circuit 247 by a 6 thin film transistor and a 2 storage capacitor. . The gate electrode 2471 of at least one thin film transistor of the pixel driving circuit 247 is connected to a gate driving line (not shown). According to the design of the driving circuit, at least one thin film transistor has a drain/source 2473 in the control circuit. Connected to a source driving line (not shown), a drain/source 2475 of at least one thin film transistor in the pixel driving circuit 247 is connected to a corresponding anode pixel 1231 of the anode layer 1230.

The anode layer 1230 is located on a side of the thin film transistor layer 240 facing the organic light emitting diode layer 1290. The anode layer 1230 has a plurality of anode pixel electrodes 1231. Each anode pixel electrode of the plurality of anode pixel electrodes 1231 corresponds to a pixel driving transistor of the pixel driving circuit 247 of the thin film transistor layer 240, that is, each of the plurality of anode pixel electrodes An anode pixel electrode is connected to the source/drain of the pixel driving transistor of the corresponding pixel driving circuit 247 to form a pixel electrode of a specific color, such as a red pixel electrode or a green pixel electrode. , or blue pixel electrodes.

The cathode layer 1210 is located on a surface of the first substrate 210 facing the side of the organic light emitting diode layer 1290. At the same time, the cathode layer 1210 is located The first substrate 210 is between the organic light emitting diode layer 1290. The cathode layer 1210 is formed of a metal conductive material. Preferably, the cathode layer 1210 is formed of a metal material having a thickness of less than 50 nanometers (nm) selected from one of the group consisting of aluminum (Al), silver (Ag), and magnesium (Mg). ), calcium (Ca), potassium (K), lithium (Li), indium (In), an alloy of the above materials or a combination of lithium fluoride (LiF), magnesium fluoride (MgF2), lithium oxide (LiO) and Al Made. Since the thickness of the cathode layer 1210 is less than 50 nm, the light generated by the organic light emitting diode layer 1290 can still penetrate the cathode layer 1210 to display an image on the first substrate 210. The cathode layer 1210 is electrically connected to the entire sheet and thus can be used as a shield. At the same time, the cathode layer 1210 also receives current from the anode pixel electrode 1231.

FIG. 13 is still another schematic diagram of a high-accuracy narrow-frame in-cell planar display touch structure 1300. As shown in FIG. 13, the main difference from FIG. 2 is that the sensing electrode and the wiring layer 250 are The positions of the sensing electrode layers 260 are interchanged. That is, a sensing electrode and wiring layer 250 (the sensing electrode and wiring layer 250 of FIG. 2) is located on a surface of the thin film transistor layer 240 facing the display layer 230 and has a first direction (X) M first conductor block lines 40-1, 40-2, ..., 40-M and N connection lines 41-1, 41-2, ..., 41-N, which According to a touch driving signal, it is sensed whether there is an external object approaching, wherein M and N are positive integers. Each of the first conductor block lines 40-1, 40-2, ..., 40-M of the M first conductor block lines is composed of a plurality of first conductor blocks 400. Wherein, the M first conductor block lines 40-1, 40-2, ..., 40-M and the N connection lines 41-1, 41-2, ..., 41-N are made of metal Made of conductive material. A sensing electrode layer 260 (the sensing electrode layer 260 of FIG. 2) is located at the sensing The electrode and the wiring layer 250 (the sensing electrode and the wiring layer 250 of FIG. 2 ) face the display layer 230 , that is, the sensing electrode layer 260 is interposed between the sensing electrode and the wiring layer 250 and the display layer 230 . The sensing electrode and the wiring layer 250 are interposed between the sensing electrode layer 260 and the thin film transistor layer 240. The sensing electrode layer 260 has N second conductor block lines 50-1, 50-2, ..., 50-N arranged along a second direction (Y), which is accepted when performing touch sensing The touch driving signal, each of the second conductor block lines 50-1, 50-2, ..., 50-N is connected to the corresponding i-th connecting line 41-1, 41-2, ..., 41 -N extends to the side 201 of one of the high-precision narrow-frame in-cell planar display touch structures, i being a positive integer and 1≦i≦N. Each of the N second conductor block lines 50-1, 50-2, ..., 50-N is composed of a plurality of second conductor blocks 500. The plurality of first conductor blocks 400, the N connecting lines 41-1, 41-2, ..., 41-N, and the positions of the plurality of second conductor blocks 500 are based on the thin film transistor The positions of the K gate driving lines of the layer 240 and the L source driving lines are correspondingly arranged, and when the first conductor block 400 and the second conductor block 500 are stacked, they are arranged in a differential manner ( Dislocation).

It is known that the electrode dots made of indium tin oxide (ITO) have an average light transmittance of only about 90%, and the M first conductor block lines 40-1, 40-2, ... 40-M, the N connecting lines 41-1, 41-2, ..., 41-N, and the N second conductor block lines 50-1, 50-2, ..., 50-N It is disposed above the position of the K gate drive lines and the L source drive lines, and thus does not affect the light transmittance. Therefore, the average light transmittance of the present creation is much better than the conventional technology. When the touch panel structure of the narrow frame of the present invention is combined with the liquid crystal display panel, the brightness of the liquid crystal display panel can be made brighter than the prior art. Or reduce the LCD display at the same brightness The backlight energy consumption of the display panel.

It can be seen from the foregoing description that the design of the prior art of FIG. 1 will increase the width of the touch panel frame and is not suitable for the trend of narrow frame design. At the same time, when using indium tin oxide as a bridge structure to connect two indium tin oxide electrode points, since indium tin oxide material does not have good ductility like metal, it is easy to generate breakpoints at the bridge or Bad electrical signals and other phenomena. If metal is used as a bridge structure to connect two indium tin oxide electrode points, since the metal and indium tin oxide are heterogeneous materials, it is easy to generate electrical signal defects at the bridge, which affects the detection of touch points. Correctness.

The creation is M, the first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50 -N or the traces are made of metal, which has better conductivity than the conventional technology, and it is easy to transmit the sensing signal of the conductor line to the control circuit, so that the coordinates calculated by the control circuit are more accurate. Compared with the prior art, the light transmittance is better, and the expensive indium tin oxide material can be avoided, thereby reducing the cost. Compared with the conventional technology, it is more suitable for designing a touch panel with a narrow bezel, and the use of metal as a touch sensing electrode has high ductility, and is suitable for a flexible display.

Meanwhile, the present creation is performed by the first conductor block lines 40-1, 40-2, ..., 40-M and the second conductor block lines 50-1, 50-2, ..., 50 -N is superposed in a dislocation manner to increase the first conductor block lines 40-1, 40-2, ..., 40-M and the second conductor block lines 50-1, 50- 2,..., 50-N between the sensing capacitors. Therefore, the internal driver (not shown) of the control circuit can use a smaller voltage to drive the first conductor block line, and obtain the same amount of induced capacitance variation as the prior art, which can save power consumption compared with the prior art. Therefore, this creation is especially It is suitable for handheld devices. At the same time, due to the first conductor block line 40-1, 40-2, ..., 40-M and the second conductor block line 50-1, 50-2, ..., 50-N The amount of change in the sense capacitance becomes larger, and the sensor of the control circuit (not shown) can more accurately detect the voltage on the second conductor block lines 50-1, 50-2, ..., 50-N, Compared with the prior art, the accuracy of the touch can be improved.

The above-described embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

200‧‧‧High-accuracy narrow bezel in-line flat display touch structure

210‧‧‧First substrate

220‧‧‧second substrate

230‧‧‧Display layer

240‧‧‧film transistor layer

250‧‧‧Induction electrode and trace layer

260‧‧‧Induction electrode layer

270‧‧‧ shading layer

280‧‧‧Color filter layer

300‧‧‧First polarizing layer

310‧‧‧Second polarizing layer

320‧‧‧First insulation

330‧‧‧Second insulation

340‧‧‧ third insulation layer

291‧‧‧Thin film transistor

293‧‧‧Transparent electrode

Claims (18)

A high-accuracy narrow-frame in-cell planar display touch structure includes: a first substrate; a second substrate, the first substrate and the second substrate are sandwiched by a display layer in a parallel pair configuration Between the two substrates; a thin film transistor layer on a surface of the second substrate facing the display layer, the thin film transistor layer having K gate driving lines and L source driving lines, the K gates The pole driving line and the L source driving lines are disposed in a first direction and a second direction to form a plurality of pixel blocks, each pixel block having a corresponding pixel transistor and a pixel capacitor And performing a display operation according to a display pixel signal and a display driving signal to drive the corresponding pixel transistor and the pixel capacitor, wherein K and L are positive integers; a sensing electrode and a wiring layer are located The thin film transistor layer faces one side of the display layer, and has M first conductor block lines and N connection lines arranged along a first direction, which sense whether there is an external part according to a touch driving signal The object is close, where M and N are positive integers Each of the first conductor block lines of the M first conductor block lines is composed of a plurality of first conductor blocks; and a sensing electrode layer is disposed on the thin film transistor layer facing the display layer The sensing electrode layer is interposed between the sensing electrode and the wiring layer and the thin film transistor layer, and has N second conductor block lines arranged along a second direction, when performing touch sensing Receiving the touch driving signal, each second conductor block line extends to a side of one of the high-precision narrow frame in-cell planar display touch structures with a corresponding ith connection line, i is positive Integer and 1≦i≦N, each second conductor block line of the N second conductor block lines is composed of a plurality of second conductor blocks; The positions of the plurality of first conductor blocks, the N connecting lines, and the plurality of second conductor blocks are driven according to the K gate driving lines and the L source driving lines of the thin film transistor layer. The position of the line is set correspondingly. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 1, wherein the first conductor block and the second conductor block are stacked in a differential manner Set. The high-accuracy narrow-frame in-line planar display touch structure as described in claim 2, wherein each pixel block of the plurality of pixel blocks has a length and a width respectively Distance and a second distance. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 3, wherein the first conductor block and the second conductor block are stacked in a differential manner, the first a central portion of the one conductor block and a center position of the second conductor block differing in the second direction by a first multiple of the first distance, in the first direction being different from the second multiple of the second distance Wherein the first multiple and the second multiple are positive integers. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 4, wherein each of the plurality of first conductor blocks has a length and a width of one a third distance and a fourth distance, the length and the width of each of the second conductor blocks of the plurality of second conductor blocks are respectively a fifth distance and a sixth distance, wherein the third distance is the first distance a double of a third multiple of the distance, the fourth distance being twice a fourth multiple of the second distance, the fifth distance being twice a fifth multiple of the first distance, the sixth The distance is twice a sixth multiple of the second distance, wherein the third multiple, the fourth multiple, the fifth multiple, and the sixth multiple are positive integers. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 5, wherein the first multiple is less than or equal to the third one of the third multiple or the fifth multiple, the first The multiple is less than or equal to the fourth multiple Or the smaller of the sixth multiples, h≦min(h1, h2), w≦min(w1, w2), where h is the first multiple, w is the second multiple, and h1 is the third multiple , w1 is the fourth multiple, h2 is the fifth multiple, and w2 is the sixth multiple. The high-accuracy narrow-frame in-line planar display touch structure as described in claim 1 , wherein each of the first conductor block lines extends to the first substrate by a corresponding metal trace The same side to further connect to a flexible circuit board. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 7, wherein the N connection lines, the plurality of first conductor blocks, and the plurality of second conductor block systems Made of metal conductive material. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 8 wherein the first plurality of first conductor block lines of the M first conductor block lines are first The conductor block forms a quadrilateral region and is electrically connected together, and each of the first conductor block lines of the M first conductor block lines is not connected, and the N second conductor block lines are a plurality of second conductor blocks of each of the second conductor block lines form a quadrilateral region and are electrically connected together, and each of the N second conductor block lines is between each of the second conductor block lines not connected. The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 1, wherein the first direction is perpendicular to the second direction. The high-accuracy narrow bezel embedded flat display touch structure as described in claim 1, wherein each of the N connecting lines is arranged between the two first conductor block lines . The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 9, wherein the quadrilateral region formed by the first conductor block and the second conductor block is as follows One of the shapes: rectangle, square. The high-accuracy narrow bezel embedded flat display touch structure as described in claim 8 wherein the metal conductive material is one of the following: molybdenum, niobium, aluminum, silver, copper, titanium, Nickel, bismuth, cobalt, tungsten, magnesium (Mg), calcium (Ca), potassium (K), lithium (Li), indium (In), alloy, lithium fluoride (LiF), magnesium fluoride (MgF2), oxidation Lithium (LiO). The high-accuracy narrow-frame in-cell planar display touch structure as described in claim 1, further comprising: a light shielding layer on a surface of the first substrate facing one side of the display layer, The light shielding layer is composed of a plurality of light shielding lines, wherein the plurality of light shielding lines are disposed in the first direction and the second direction to form a plurality of light shielding blocks; and a color filter layer is disposed on the light shielding layer facing the display a surface on one side of the layer; a first polarizing layer on a surface of the first substrate facing away from the side of the display layer; and a second polarizing layer on the back side of the second substrate Side surface. The high-accuracy narrow bezel embedded flat display touch structure as described in claim 1, wherein the display layer is a liquid crystal layer. The high-accuracy narrow bezel embedded flat display touch structure as described in claim 1, wherein the display layer is an organic light emitting diode layer. A high-accuracy narrow-frame in-cell planar display touch structure includes: a first substrate; a second substrate, the first substrate and the second substrate are sandwiched by a display layer in a parallel pair configuration Between the two substrates; a thin film transistor layer on a surface of the second substrate facing the display layer, the thin film transistor layer has K gate drive lines and L source drive lines, The K gate driving lines and the L source driving lines are disposed in a first direction and a second direction to form a plurality of pixel blocks, each pixel block having a corresponding pixel transistor and a pixel capacitor, according to a display pixel signal and a display driving signal, to drive the corresponding pixel transistor and the pixel capacitor, thereby performing a display operation, wherein K and L are positive integers; a sensing electrode layer, Located on one side of the thin film transistor layer facing the display layer, and having N second conductor block lines arranged along a second direction, when receiving touch sensing, receiving a touch driving signal; The sensing electrode and the wiring layer are located on one side of the sensing electrode layer facing the display layer, and have M first conductor block lines and N connecting lines arranged along a first direction, according to a touch Driving the signal to sense whether there is an external object approaching, wherein M and N are positive integers, and each of the first conductor block lines of the M first conductor block lines is composed of a plurality of first conductor blocks, The plurality of first conductor blocks, the N strips The wiring and the position of the plurality of second conductor blocks are disposed according to positions of the K gate driving lines and the L source driving lines of the thin film transistor layer, and the first conductor block When stacked with the second conductor block, they are stacked in a differential manner. The high-accuracy narrow bezel embedded flat display touch structure as described in claim 17 wherein the first direction is perpendicular to the second direction.