TWM470372U - Wafer placement and wafer testing machine - Google Patents

Description

Wafer placement and wafer test machine

This creation is a wafer placement and wafer test machine, especially a wafer placement and wafer test machine that can hold multiple wafers of different sizes.

In the semiconductor process, a step of detecting a wafer is usually required, the main purpose of which is to use a conductive probe to each die on the wafer before cutting the semiconductor wafer ( Contact) to conduct a continuity check and detect defective products. This process is also called Wafer Level Test (WLT).

In order to pursue higher throughput, the size of the wafer must be larger and larger, from the early 6-inch wafer to 8吋, 12吋, 16吋 or even 20吋, and the technology of the wafer process continues to evolve. Now, these large-size wafers are slowly being put into mass production. In order to respond to changes in wafer size, the machine for testing wafers needs to be continuously updated.

In fact, the technology for testing wafers has not grown as rapidly as wafer size development, that is, the machines required to test small-size wafers and the machines required to test large-size wafers can be loaded with wafers. Except for the size, there is not much difference. It is quite inefficient to replace the test machine of small-sized wafers in order to test large-size wafers, and it will also cause unnecessary waste of cost; While large-size wafers are being mass-produced, small-size wafers are usually not eliminated by the market in the first place, but still maintain a certain capacity. Of course, the fab needs to have the ability to test wafers of different sizes at the same time. Obviously, It is not the best practice to have multiple machines that test wafers of different sizes at the same time.

Therefore, this creation believes that a solution is needed to enable the fab to more efficiently use the existing resources to complete the test when the wafer process is evolving and it is necessary to simultaneously face multiple wafers of different sizes.

In order to solve the above mentioned problems, one of the main purposes of this creation is to provide a wafer placement base and a wafer test machine, in particular, a wafer placement seat that can be replaced by a simple disassembly and assembly. The test machine can be quickly modified when testing different size wafers, and the large number of wafer test machines can be configured without extra resources and space.

According to the above object, the present invention provides a wafer placement base comprising: a first wafer carrier having an upper surface and an upper surface and having a plurality of vacuum suction holes; the wafer placement base is characterized in that the wafer placement seat further has a second wafer carrier, the second wafer carrier includes an upper surface and a lower surface opposite the upper surface, and the second wafer carrier is stacked on the first wafer carrier, wherein the lower surface of the second wafer carrier is The upper surface of the first wafer carrier is opposite, the upper surface of the second wafer carrier further has a plurality of second wafer carrier perforations extending from the upper surface of the second wafer carrier to the lower surface, and the second wafer carrier is perforated The vacuum suction holes are opposite.

In accordance with the above objects, the present application proposes a wafer testing machine for testing a plurality of dies on a wafer, including: a probe holder having an upper surface and a lower surface relative to the upper surface, the probe a plurality of probes extend from the upper surface to the lower surface, and each probe forms a probe upper end and a probe lower end on the upper surface and the lower surface, respectively; a substrate having an upper surface and opposite to the probe a lower surface of the upper surface, the lower surface of the substrate is in contact with the upper surface of the probe base, and a plurality of wires are embedded in the substrate from the upper surface of the substrate to the lower surface of the substrate, and each of the wires forms a surface on the upper surface of the substrate The first end forms a second end on the lower surface of the substrate, and the second end of the wiring is electrically connected to the upper end of the probe of the probe; a test head has a connecting seat, and the connecting seat is connected to the upper surface of the substrate And electrically connected to the first end of each of the wires; a wafer test carrier having an upper surface and a lower surface opposite to the upper surface, the wafer test carrier further having a plurality of carrier perforations from the wafer test load Upper surface of the board To the lower surface of the wafer test carrier, and each carrier plate has a metal material in the perforation, the upper surface of the wafer test carrier is connected to the lower surface of the probe holder, and the metal material is located on the wafer test carrier One end of the upper surface is electrically connected to the lower end of the probe, and the other end of the metal material forms a plurality of detecting joints; and the wafer testing machine is characterized by: a wafer placing base under the wafer test carrier, The method includes a first wafer carrier having an upper surface and an upper surface and having a plurality of vacuum suction holes; the wafer placement base is characterized in that the wafer placement base further has a second wafer carrier, and the second wafer carrier comprises An upper surface and a lower surface opposite to the upper surface, the second wafer carrier is stacked on the first wafer carrier, wherein the lower surface of the second wafer carrier is opposite to the upper surface of the first wafer carrier, the second crystal The upper surface of the circular carrier further has a plurality of second wafer carrier perforations extending from the upper surface of the second wafer carrier to the lower surface, and the second wafer carrier is opposite to the vacuum suction hole; wherein the wafer is placed in the second Wafer carrier Party, and to detect the joint testing of dies on the wafer.

According to the above object, the present invention further provides a wafer placement base comprising: a first wafer carrier having an upper surface and an upper surface and having a plurality of vacuum suction holes; the wafer placement base is characterized by a wafer placement base further Having a second wafer carrier, the second wafer carrier includes an upper surface and a lower surface opposite the upper surface, the second wafer carrier is stacked on the first wafer carrier, wherein the lower surface of the second wafer carrier Opposite the upper surface of the first wafer carrier, the upper surface of the second wafer carrier further has a plurality of second wafer carrier perforations extending from the upper surface of the second wafer carrier to the lower surface, and the second wafer carrier is perforated Opposite the vacuum suction hole; and a third wafer carrier stacked on the second wafer carrier, the third wafer carrier including an upper surface and a lower surface opposite the upper surface, wherein the lower surface of the third wafer carrier Opposite the upper surface of the second wafer carrier, the third wafer carrier has a plurality of third wafer carrier perforations extending from the upper surface of the third wafer carrier to the lower surface of the third wafer carrier, and each Three wafer load Perforations are of a metal material.

According to the above object, the present invention further proposes a wafer testing machine for testing a plurality of dies on a wafer, comprising: a probe holder having an upper surface and a lower surface relative to the upper surface, The probe has a plurality of probes extending from the upper surface to the lower surface, and each probe forms a probe upper end and a probe lower end on the upper surface and the lower surface respectively; a substrate having an upper surface and opposite to a lower surface of the upper surface, the lower surface of the substrate is in contact with the upper surface of the probe base, and a plurality of wires are embedded in the substrate from the upper surface of the substrate to the lower surface of the substrate, and each of the wires is formed on the upper surface of the substrate a first end and a second end is formed on the lower surface of the substrate, and the second end of the wiring is electrically connected to the upper end of the probe of the probe; a test head has a connecting seat, and the connecting seat is opposite to the upper surface of the substrate And electrically connected to the first end of each of the wires; a wafer test carrier having an upper surface and a lower surface opposite to the upper surface, the wafer test carrier further having a plurality of carrier perforations from the wafer test The top of the carrier Through the lower surface of the wafer test carrier, and each carrier plate has a metal material in the perforation, the upper surface of the wafer test carrier is connected to the lower surface of the probe holder, and the metal material is located on the wafer test load. One end of the upper surface of the board is electrically connected to the lower end of the probe, and the other end of the metal material forms a plurality of detecting joints; and the wafer testing machine is characterized by: a wafer placing base under the wafer test carrier The method includes: a first wafer carrier having an upper surface and an upper surface and having a plurality of vacuum suction holes; the wafer placement base is characterized in that the wafer placement base further has a second wafer carrier, and the second wafer carrier An upper surface and a lower surface opposite to the upper surface, the second wafer carrier being stacked on the first wafer carrier, wherein the lower surface of the second wafer carrier is opposite to the upper surface of the first wafer carrier, and the second The upper surface of the wafer carrier further has a plurality of second wafer carrier perforations extending from the upper surface of the second wafer carrier to the lower surface, and the second wafer carrier is opposite to the vacuum suction hole; and a third wafer carrier ,versus The two wafer carriers are stacked, the third wafer carrier includes an upper surface and a lower surface opposite to the upper surface, wherein a lower surface of the third wafer carrier is opposite the upper surface of the second wafer carrier, and the third wafer carrier And a plurality of third wafer carrier perforations are penetrated from the upper surface of the third wafer carrier to the lower surface of the third wafer carrier, and each of the third wafer carriers has a metal material in the perforation; wherein, the wafers are respectively Placed on the upper surface of the second wafer carrier and the upper surface of the third wafer carrier, and the die position of the wafer is opposite to the metal material in the third wafer carrier through-hole and is electrically connected, and the probe pair is The die is tested.

Through the wafer placement and wafer testing machine proposed by this creation, no matter the size of the wafer to be tested, no complicated disassembly or replacement or replacement of a new machine is required. Tests are completed with simple modifications to save test costs and increase productivity.

1A‧‧‧ wafer placement
1B‧‧‧ wafer placement
1C‧‧‧ wafer placement
1D‧‧‧ wafer placement
12‧‧‧First wafer carrier
121‧‧‧ upper surface
122‧‧‧Vacuum suction holes
14, 14A, 14B‧‧‧Second wafer carrier
141‧‧‧ upper surface
142‧‧‧Second wafer carrier perforation
143‧‧‧ lower surface
144‧‧‧Border wall
16‧‧‧ Third wafer carrier
161‧‧‧ upper surface
162‧‧‧ Third wafer carrier perforation
163‧‧‧ lower surface
164‧‧‧Border wall
165‧‧‧Metal materials
2A‧‧‧Watt Testing Machine
20, 20A, 20B‧‧‧ wafer
202, 202A, 202B‧‧‧ grain
30‧‧‧ Wafer Test Carrier
32‧‧‧ upper surface
33‧‧‧ Carrier perforation
330‧‧‧ wiring
331‧‧‧ upper end of wiring
34‧‧‧ lower surface
345‧‧‧Detector connector
40‧‧‧ probe holder
401‧‧‧ upper surface
403‧‧‧ lower surface
42‧‧‧Probe
421‧‧‧ probe upper end
423‧‧‧ probe lower end
50‧‧‧Substrate
501‧‧‧ upper surface
503‧‧‧ lower surface
52‧‧‧Wiring
521‧‧‧ first end
523‧‧‧ second end
60‧‧‧ test seat
62‧‧‧Connecting seat

1 is a schematic view showing a first embodiment of a wafer placement seat of the present invention;
Figure 2 is a cross-sectional view showing the first embodiment of the wafer placement seat of the present invention;
Figure 3 is a schematic view showing a second embodiment of the wafer placement seat of the present invention;
Figure 4 is a schematic view showing a third embodiment of the wafer placement seat of the present invention;
Figure 5 is a schematic view showing a fourth embodiment of the wafer placement seat of the present invention;
Figure 6 is a cross-sectional view showing the first embodiment of the wafer placement seat and the wafer testing machine of the present invention;
Figure 7 is a schematic cross-sectional view showing a second embodiment of the wafer placement and wafer testing machine of the present invention.

In order to clarify the purpose, technical features and advantages of the present invention, the author can understand and implement the present invention, and the technical features and implementation manners of the present invention are explained in the following description in conjunction with the drawings. The description of the preferred embodiments is further illustrated, but the following description of the embodiments is not intended to limit the present invention, and the drawings in the following description are intended to be illustrative of the features of the present invention.

First, please refer to FIG. 1 and FIG. 2 together, which are schematic views of the first embodiment of the wafer placement seat of the present invention and a cross-sectional view of the first embodiment of the wafer placement seat of the present invention. As shown in FIGS. 1 and 2, the first wafer carrier 12 has an upper surface 121, and the second wafer carrier 14 has an upper surface 141 and a lower surface 143 opposite to the upper surface 141, wherein, in a preferred implementation In the state, the upper surface 141 of the second wafer carrier 14 has a side wall portion 144, and the side wall portion 144 is higher than the upper surface 141; the first wafer carrier 12 and the second wafer carrier 14 are stacked to form a wafer placement seat. 1A, wherein the lower surface 143 of the second wafer carrier 14 is opposite to the upper surface 121 of the first wafer carrier 12; the second wafer carrier 14 further has a plurality of second wafer carrier through holes 142 extending from the upper surface 141 to the lower surface. The upper surface 121 of the first wafer carrier 12 has a plurality of vacuum suction holes 122. In a preferred embodiment, the vacuum suction holes 122 are opposite to the second wafer carrier through holes 142. In addition, in this embodiment, The second wafer carrier 14 is fan shaped.

Next, please refer to FIG. 3 , which is a schematic diagram of a second embodiment of the wafer placement seat of the present invention. As shown in FIG. 3, the wafer placement base 1B is further stacked with a third wafer carrier 16 on the wafer placement base 1A as shown in FIG. 1, and the third wafer carrier 16 has an upper surface 161 and a lower surface 163 opposite the upper surface 161, wherein the lower surface 163 is opposite to and joined to the upper surface 141 of the second wafer carrier 14; in a preferred embodiment, the edge of the upper surface 161 has a side wall portion 164, side The wall portion 164 is higher than the upper surface 161; the third wafer carrier 16 further has a plurality of third wafer carrier through holes 162 extending from the upper surface 161 to the lower surface 163, and each of the third wafer carrier through holes 162 is provided with a metal material. 165. Further, in the present embodiment, the second wafer carrier 14 and the third wafer carrier 16 are fan-shaped.

Next, please refer to FIG. 4 and FIG. 5 together for a schematic view of a third embodiment of the wafer placement seat of the present invention and a fourth embodiment of the wafer placement seat of the present invention. As shown in FIGS. 4 and 5, the second wafer carriers 14A, 14B may be rectangular or circular. As described above, the second wafer carrier 14 may be a geometric shape composed of a sector, a rectangle or a circle. Similarly, the third wafer carrier 16 may also be a geometric group composed of a sector, a rectangle or a circle; however, the above illustration is only used to explain the implementation state of the creation, and the creation is The shape of the second wafer carrier 14 and the third wafer carrier 16 are not limited.

Next, please refer to FIG. 6 , which is a cross-sectional view of the first embodiment of the wafer placement base and the wafer testing machine of the present invention. As shown in FIG. 6, the wafer testing machine 2A includes a probe holder 40 having an upper surface 401 and a lower surface 403 opposite to the upper surface 401. The probe holder 40 has a plurality of probes 42 therein. Each of the probes 42 extends from the upper surface 401 to the lower surface 403 and forms a probe upper end 421 and a probe lower end 423. A substrate 50 has an upper surface 501 and a lower surface 503 opposite to the upper surface 501. The lower surface 503 is connected to the upper surface 401 of the probe base 40. The substrate 50 has a plurality of wires 52. Each of the wires 52 forms a first end 521 on the upper surface 501 of the substrate 50, and is formed on the lower surface 503 of the substrate 50. a second end 523, the second end 523 of each of the wires 52 is electrically connected to the probe upper end 421 of each probe 42; a test head 60 has a connecting base 62, and the connecting base 62 is connected to the substrate 50. The upper surface 501 is electrically connected to the first end 521 of the wiring 52; the wafer test carrier 30 has an upper surface 32 and a lower surface 34 opposite to the upper surface 32, wherein the upper surface 32 of the wafer test carrier 30 Opposite and joined to the lower surface 403 of the probe holder 40; the wafer test carrier 30 further has a plurality of loads The through holes 33 extend from the upper surface 32 to the lower surface 34. Each of the carrier through holes 33 has a wiring 330. The wiring 330 forms a wiring upper end 331 on the upper surface 32, and each wiring upper end 331 is electrically connected to each probe lower end 423. The wiring 330 and the plurality of probes 345 are formed on the lower surface 34.

Below the wafer test carrier 30, for the wafer stand 1A of the present creation, a wafer 20 is placed on the upper surface 141 of the second wafer carrier 14 of the wafer placement stand 1A, and the wafer 20 may be cut to The geometry of the second wafer carrier 14 is matched, and the second wafer carrier 14 has a plurality of uncut die 202, wherein the probe connector 345 can be associated with each test point on each die 202 (not shown) Corresponding to the figure; when the wafer test machine 2A is in operation, the wafer test carrier 30 is pressed down by the test head 60, so that the probe joint 345 and each test point on each die 202 are pressed. (not shown) is electrically connected to measure each die 202 on the entire wafer 20; in a preferred implementation, the vacuum port 122 on the first wafer carrier 12 can pass through the second The second wafer carrier through hole 142 on the wafer carrier 14 sucks the wafer 20 and is fixed through the sidewall portion 144, so that the wafer 20 can be more firmly placed on the upper surface 141 of the second wafer carrier 14; In the above implementation state, the wafer 20 can be cut according to the geometry of the second wafer carrier 14, and the wafer test carrier 30 And the probe connector 345 can also be diced to different sizes of the wafer 20 in different sizes and configurations, so that the probe connector 345 can correspond to the die 202 of the wafer 20; in other such as the wafer placement seat 1C In the implementation state of the wafer testing machine 2A, the wafer 20 may be a complete disk or a cut fan shape, and the second wafer carrier 14A can accommodate the wafer 20, and the wafer test carrier 30 and the detection The joints 345 can also be sized and configured to allow the probe joint 345 to correspond to the die 202 of the wafer 20; in other implementation states, such as the wafer mount 1D mating wafer tester 2A, The wafer 20 can also be a complete disk without being cut. In this case, the second wafer carrier 14B is circular, and the wafer test carrier 30 and the probe connector 345 can also be correspondingly sized and configured. The probe joint 345 can be made to correspond to the die 202 of the wafer 20.

Next, please refer to FIG. 7 , which is a schematic cross-sectional view of a second embodiment of the wafer placement base and the wafer testing machine of the present invention. As shown in FIG. 7, the bottom of the wafer test carrier 30 of the wafer test machine 2A is the created wafer placement stand 1B, and the second wafer carrier 14 of the wafer placement stand 1B is placed on the upper surface 141. One wafer 20A, while the third wafer carrier 16 has a wafer 20B placed on the upper surface 161; the wafers 20A, 20B may be cut to match the geometry of the second wafer carrier 14 and the third wafer carrier 16 The wafer 20A and the wafer 20B respectively have a plurality of uncut die 202A and a die 202B, wherein the die 202A, the die 202B and the third wafer carrier via 162 are opposite in position, and the die 202A and the crystal are respectively The particles 202B are electrically connected through the metal material 165; the plurality of probe joints 345 on the wafer test carrier 30 of the wafer testing machine 2A are opposite to the positions of the die 202A and the die 202B, and are on the wafer testing machine. When the 2A is in operation, the wafer test carrier 30 is pressed down by the test head 60, and the probe connector 345 is electrically connected to each test point (not shown) on each die 202B for measurement. Each of the dies 202A, 202B on the wafers 20A, 20B; in a preferred implementation, on the first wafer carrier 12 The empty suction holes 122 can be sucked into the wafer 20A through the second wafer carrier through holes 142 on the second wafer carrier 14 and fixed through the side wall portion 144 and the side wall portion 164 to make the wafers 20A and 20B more Firmly placed on the upper surface 141 of the second wafer carrier 14 and the upper surface 161 of the third wafer carrier 16; in the above implementation state, the wafer test carrier 30 and the probe connector 345 can also be matched. The different sized wafers 20A, 20B are of different sizes and configurations to enable the probe joint 345 to correspond to the dies 202A, 202B of the wafers 20A, 20B.

Through the wafer placement bases 1A, 1B, 1C, 1D and the wafer testing machine 2A proposed by the present invention, only the test machine 2A of a single size of the wafer to be tested can be tested, and the wafer placement seat 1A is 1B, 1C, 1D and wafer test carrier 30 are converted and the wafer to be tested is cut as necessary, and the wafers 20, 20A, 20B to be tested can be formed into a plurality of wafer groups of different sizes. Moreover, the above conversion does not involve the test head 60, the substrate 50 and the probe base 40 of the wafer testing machine 2A, so the modification is relatively simple, and the test cost and the work efficiency can be saved. purpose.

Although the present invention has been described above with reference to the preferred embodiments thereof, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of patent protection of this creation is subject to the definition of the scope of the patent application attached to this specification.

1B‧‧‧ wafer placement

12‧‧‧First wafer carrier

121‧‧‧ upper surface

122‧‧‧Vacuum suction holes

14‧‧‧Second wafer carrier

141‧‧‧ upper surface

142‧‧‧Second wafer carrier perforation

143‧‧‧ lower surface

144‧‧‧Border wall

16‧‧‧ Third wafer carrier

161‧‧‧ upper surface

162‧‧‧ Third wafer carrier perforation

163‧‧‧ lower surface

164‧‧‧Border wall

165‧‧‧Metal materials

Claims (12)

A wafer placement base comprising: a first wafer carrier having an upper surface and having a plurality of vacuum suction holes;
The wafer placement base is characterized in that the wafer placement seat further has:
a second wafer carrier, the second wafer carrier includes an upper surface and a lower surface opposite the upper surface, the second wafer carrier is stacked on the first wafer carrier, and the second wafer carrier is The lower surface is opposite to the upper surface of the first wafer carrier, and the upper surface of the second wafer carrier further has a plurality of second wafer carrier perforations extending from the upper surface of the second wafer carrier to the upper surface The lower surface of the second wafer carrier, and the second wafer carrier perforations are opposite to the vacuum suction holes. The wafer placement base according to claim 1, wherein the second wafer carrier is a geometric shape, and the geometric shape is a group consisting of a circle, a sector, and a rectangle. A wafer testing machine for testing a plurality of dies on a wafer, including:
a probe holder having an upper surface and a lower surface opposite to the upper surface, wherein the probe holder has a plurality of probes extending from the upper surface to the lower surface, and each of the probes is respectively Forming an upper end of the probe and a lower end of the probe on the upper surface and the lower surface;
a substrate having an upper surface and a lower surface opposite to the upper surface, the lower surface of the substrate being in contact with the upper surface of the probe holder, the substrate having a plurality of wires from the upper surface of the substrate Through the lower surface of the substrate, each of the wires forms a first end on the upper surface of the substrate, and each of the wires forms a second end on the lower surface of the substrate, the wires The second end is electrically connected to the upper ends of the probes of the probes;
a test head having a connector that is connected to the upper surface of the substrate and electrically connected to the first ends of the wires; and a wafer test carrier having an upper surface and a relative On the lower surface of the upper surface, the wafer test carrier further has a plurality of carrier plate perforations extending from the upper surface of the wafer test carrier to the lower surface of the wafer test carrier, and the carrier plates Each of the through holes has a metal material, the wafer is tested on the upper surface of the carrier and is in contact with the lower surface of the probe holder, and the metal material is located at one end of the upper surface of the wafer test carrier The lower ends of the probes are electrically connected, and the other ends of the metal materials form a plurality of detecting joints;
The wafer test machine is characterized by:
A wafer placement station located below the wafer test carrier, including:
a first wafer carrier having an upper surface having a plurality of vacuum suction holes; and a second wafer carrier, the second wafer carrier including an upper surface and a lower surface opposite the upper surface The second wafer carrier is stacked on the first wafer carrier, the lower surface of the second wafer carrier is opposite the upper surface of the first wafer carrier, and the upper surface of the second wafer carrier Further having a plurality of second wafer carrier perforations extending from the upper surface of the second wafer carrier to the lower surface, and the second wafer carrier perforations are opposite to the vacuum suction holes;
The wafer is placed on the upper surface of the second wafer carrier, and the die on the wafer is tested by the probe. The wafer testing machine of claim 3, wherein the second wafer carrier is in a geometric shape, the geometric shape being a group consisting of a circle, a sector, and a rectangle. The wafer testing machine of claim 4, wherein the wafer is diced to match the geometry of the second wafer carrier. A wafer placement base comprising: a first wafer carrier having an upper surface and having a plurality of vacuum suction holes;
The wafer placement base is characterized in that the wafer placement seat further has:
a second wafer carrier, the second wafer carrier includes an upper surface and a lower surface opposite the upper surface, the second wafer carrier is stacked on the first wafer carrier, wherein the second wafer carrier The lower surface of the first wafer carrier is opposite to the upper surface of the first wafer carrier, and the upper surface of the second wafer carrier further has a plurality of second wafer carrier perforations running through the upper surface of the second wafer carrier To the lower surface of the second wafer carrier, and the second wafer carrier is opposite to the vacuum suction holes; and a third wafer carrier stacked on the second wafer carrier, the third The wafer carrier includes an upper surface and a lower surface opposite the upper surface, wherein the lower surface of the third wafer carrier is opposite the upper surface of the second wafer carrier, and the third wafer carrier has A plurality of third wafer carrier perforations are penetrated from the upper surface of the third wafer carrier to the lower surface of the third wafer carrier, and the third wafer carrier vias respectively have a metal material. The wafer placement base according to claim 6, wherein the second wafer carrier is a geometric shape, and the geometric shape is a group consisting of a circle, a sector, and a rectangle. The wafer placement base according to claim 6, wherein the third wafer carrier is a geometric shape, and the geometric shape is a group consisting of a circle, a sector, and a rectangle. A wafer testing machine for testing a plurality of dies on a plurality of wafers, including:
a probe holder having an upper surface and a lower surface opposite to the upper surface, wherein the probe holder has a plurality of probes extending from the upper surface to the lower surface, and each of the probes is respectively Forming an upper end of the probe and a lower end of the probe on the upper surface and the lower surface;
a substrate having an upper surface and a lower surface opposite to the upper surface, the lower surface of the substrate being in contact with the upper surface of the probe holder, the substrate having a plurality of wires from the upper surface of the substrate Through the lower surface of the substrate, each of the wires forms a first end on the upper surface of the substrate, and each of the wires forms a second end on the lower surface of the substrate, the wires The second end is electrically connected to the upper ends of the probes of the probes;
a test head having a connector that is connected to the upper surface of the substrate and electrically connected to the first ends of the wires; and a wafer test carrier having an upper surface and a relative On the lower surface of the upper surface, the wafer test carrier further has a plurality of carrier plate perforations extending from the upper surface of the wafer test carrier to the lower surface of the wafer test carrier, and the carrier plates Each of the through holes has a metal material, the wafer is tested on the upper surface of the carrier and is in contact with the lower surface of the probe holder, and the metal material is located at one end of the upper surface of the wafer test carrier The lower ends of the probes are electrically connected, and the other ends of the metal materials form a plurality of detecting joints;
The wafer test machine is characterized by:
A wafer placement station located below the wafer test carrier, including:
a first wafer carrier having an upper surface having a plurality of vacuum suction holes;
a second wafer carrier, the second wafer carrier includes an upper surface and a lower surface opposite the upper surface, the second wafer carrier is stacked on the first wafer carrier, wherein the second wafer carrier The lower surface of the first wafer carrier is opposite to the upper surface of the first wafer carrier, and the upper surface of the second wafer carrier further has a plurality of second wafer carrier perforations running through the upper surface of the second wafer carrier To the lower surface of the second wafer carrier, and the second wafer carrier is opposite to the vacuum suction holes; and a third wafer carrier stacked on the second wafer carrier, the third The wafer carrier includes an upper surface and a lower surface opposite the upper surface, wherein the lower surface of the third wafer carrier is opposite the upper surface of the second wafer carrier, and the third wafer carrier has a plurality of third wafer carrier perforations extending from the upper surface of the third wafer carrier to the lower surface of the third wafer carrier, and the third wafer carrier perforations respectively have a metal material;
The wafers are respectively disposed on the upper surface of the second wafer carrier and the upper surface of the third wafer carrier, and the dies on the wafers are tested by the probe. The wafer testing machine of claim 9, wherein the second wafer carrier is in a geometric shape, the geometric shape being a group consisting of a circle, a sector, and a rectangle. The wafer testing machine of claim 9, wherein the third wafer carrier is in a geometric shape, the geometric shape being a group consisting of a circle, a sector, and a rectangle. The wafer testing machine of claim 10 or 11, wherein the wafers are diced to match the geometry of the second wafer carrier and the geometry of the third wafer carrier shape.