TWM462439U - Semiconductor apparatus - Google Patents

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a method for forming a stepped oxide layer by oxidation and deposition by using a single photomask etching process to simultaneously form grooves of different widths.

Semiconductor power components usually have low on-resistance and high reverse voltage. However, in order to achieve low on-resistance, it is necessary to increase the doping concentration of the source and the drain, so that the electrons are easily driven in the drift region under voltage driving, thereby reducing the on-resistance. The current is increased, but the reverse voltage is lowered, making it difficult for conventional semiconductor power components to overcome the problem of achieving low on-resistance and high reverse voltage at the same time.

The super junction structure usually has a structure in which a P-type epitaxial layer and an N-type epitaxial layer are staggered, which can achieve low on-resistance and high reverse voltage while increasing the doping concentration in the source and the drain. The advantage, but in the high voltage operating state, due to the distribution problem of the electric field, the termination region is not evenly distributed due to the electric charge, so that the termination region collapses due to the high voltage, thereby causing the semiconductor power component to be damaged.

As described above, since the conventional semiconductor device operates under high voltage, the termination region is liable to collapse due to uneven charge distribution, causing damage to the semiconductor device.

Therefore, the present invention provides a semiconductor device including a semiconductor substrate having an active region and a termination region adjacent to the active region, and the semiconductor substrate includes a first doped substrate layer and a plurality of first doping layers. a balance layer, a plurality of second doped balance layers, a second doped implant layer, a first oxide layer, and a second oxide layer.

The first doped balance layer is disposed on the first doped base layer at intervals; the second doped balance layer is disposed on the first doped base layer in a staggered manner with the first doped balance layer The second doped implant layer is disposed on the second doped balance layer at the boundary between the active region and the termination region; the first oxide layer is disposed in the first doped balance layer in the termination region, The second doped balance layer and the second doped implant layer, and the first oxide layer has a first groove structure and a plurality of second groove structures, and the first groove structure is adjacent to the active region. The second groove structure is away from the active area, and the second groove structure is disposed at a spacing interval; the second oxide layer is disposed in the first groove structure and the second groove structure, and is in the first groove The structure has a third groove structure.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the width of the first groove structure is greater than the width of the second groove structure.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the distance between the second groove structures is less than or equal to eight times the thickness of the first oxide layer.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the width of the second groove structure is less than or equal to the thickness of the second oxide layer. double.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the semiconductor device further comprises a second doped source implant layer disposed on one of the second doped balance layers and adjacent to The second doped implant layer is located in the active region.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the semiconductor device further comprises a channel termination implant layer disposed on one of the first doped balance layers and located at the edge of the termination region.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the semiconductor device further comprises a gate oxide layer and a gate layer, the gate oxide layer is deposited on the second doped implant layer and the second doping The first doped balance layer between the source implant layers is partially disposed on the second doped implant layer and the second doped source implant layer, and the gate layer is disposed on the gate On the pole oxide layer.

An auxiliary technical means derived from the above-mentioned essential technical means is that the semiconductor device comprises a polysilicon layer deposited on the first oxide layer and the second oxide layer of the semiconductor device. Preferably, the semiconductor device includes a third oxide layer overlying the second doped implant layer, the second doped source implant layer, the first oxide layer, the second oxide layer, and the gate Further on the layer and the polysilicon layer; further, the semiconductor device comprises a metal field plate formed on the third oxide layer and located at the edge of the termination region.

An auxiliary technical means derived from the above-mentioned necessary technical means is that the semiconductor device comprises a source layer which is disposed on the second doped source implant layer.

An auxiliary technical means derived from the above-mentioned essential technical means is that the semiconductor device comprises a drain layer which is disposed on the bottom surface of the first doped base layer.

As described above, the semiconductor device provided by the present invention mainly uses a single photomask etching process to form first grooves and second grooves of different widths, and then forms a first oxide layer formed by high temperature oxidation and deposited. The second oxide layer, the stepped oxide layer formed by laminating the first oxide layer and the second oxide layer can make the electric field distribution in the termination region uniform, and only a single mask is used in the process of forming the first oxide layer and the second oxide layer. The etching process also saves time, energy costs, and raw material costs for the process.

The specific embodiments used in the present application will be further illustrated by the following examples and drawings.

100‧‧‧Semiconductor device

100a‧‧‧Semiconductor device

1‧‧‧Semiconductor substrate

1a‧‧‧Semiconductor substrate

1b‧‧‧Semiconductor substrate

1c‧‧‧Semiconductor substrate

1d‧‧‧Semiconductor for semiconductor devices

11‧‧‧First doped base layer

121‧‧‧First doped equilibrium layer

121a‧‧‧First doped equilibrium layer

121b‧‧‧First doped equilibrium layer

122‧‧‧Second doped equilibrium layer

131‧‧‧Second-doped implant layer

131a‧‧‧Second-doped implant layer

131b‧‧‧Second-doped implant layer

132‧‧‧Second doped source implant layer

132a‧‧‧Second doped source implant layer

132b‧‧‧Second doped source implant layer

1321, 1323‧‧‧First doped implanted epitaxial layer

1322‧‧‧Second-doped implanted epitaxial layer

141‧‧‧first groove

142‧‧‧second groove

143‧‧‧ platform

151‧‧‧First oxide layer

151a‧‧‧First oxide layer

1511a‧‧‧First groove structure

1512a‧‧‧second groove structure

152‧‧‧Second oxide layer

152a‧‧‧Second oxide layer

1521a‧‧‧ third groove structure

2‧‧‧End of the channel

31‧‧‧ gate oxide layer

32‧‧‧ gate layer

4‧‧‧Polysilicon layer

5‧‧‧ third oxide layer

6‧‧‧Metal field plate

7‧‧‧ source layer

8‧‧‧汲层层

A‧‧‧active area

T‧‧‧ termination zone

Width of d1‧‧‧

D2‧‧‧Width

D3‧‧‧Width

1 to 4 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to a preferred embodiment of the present invention; and a fifth embodiment showing a schematic cross-sectional view of a semiconductor device provided by the preferred embodiment of the present invention; A schematic cross-sectional view of a semiconductor device provided by another preferred embodiment of the present invention is shown.

Since the semiconductor device provided by the present invention has a related combination of implementations, it will not be repeated here. Familiar It is well known to those skilled in the art that this is not intended to limit the novelty itself. The contents of the preferred embodiment of the present creation are detailed below.

Please refer to the first to fifth figures. The first to fourth figures are schematic cross-sectional views showing the manufacturing process of the semiconductor device provided by the preferred embodiment of the present invention. The fifth figure shows the preferred embodiment of the present invention. A schematic cross-sectional view of a semiconductor device.

As shown in the figure, a manufacturing method of a semiconductor device 100 is first to fabricate a semiconductor substrate 1a having an active region A and a termination region T adjacent to the active region A, and the semiconductor substrate 1a includes a first doping. a hetero-substrate layer 11, a plurality of first doped balance layers 121, a plurality of second doped balance layers 122, a second doped implant layer 131, and a second doped source implant layer 132.

The first doped balance layer 121 is disposed on the first doped base layer 11 , and the second doped balance layer 122 is staggered with the first doped balance layer 121 and vertically disposed on the first doped layer On the hetero-substrate layer 11, wherein the first doped balance layer 121 is doped with an N-type conductivity type impurity; the first doped base layer 11 is doped with a high concentration of N-type conductivity type impurities; The second doping type balancing layer 122 is doped with a P-type conductivity type impurity. The second doped implant layer 131 is disposed on the second doped balance layer 122 at a boundary between the active region A and the termination region T; and the second doped source implant layer 132 is disposed at the second The doped balance layer 122a is located in the active region A adjacent to the second doped implant layer 131. The second doped implant layer 131 and the second doped source implant layer 132 are doped with low Concentration of P-type conductivity type impurities.

A first trench 141, eight second recesses 142 and eight platforms 143 are simultaneously etched by a single mask etch process on the semiconductor substrate 1a provided by the above process steps. The first recess 141 is adjacent to the active The region A is located in the termination region T and a portion of the first recess 141 is disposed in a portion of the second doped implant layer 131a, and the width d1 of the first recess 141 is greater than or equal to the width of the second recess 142. D2. In other preferred embodiments, a second number of grooves of appropriate number and width can be etched on the semiconductor substrate by a single mask etch process depending on the applied voltage conditions.

The surface of the semiconductor substrate 1b provided by the above process steps is oxidized at a high temperature to oxidize the yttrium component of the surface to form cerium oxide, and the platform 143 between the eight second grooves 142 is completely oxidized from the surface to the inside to form a first The oxide layer 151 is further formed into a semiconductor substrate 1c, wherein 60% of the thickness of the first oxide layer 151 formed by high temperature oxidation is an oxide layer formed outward from the surface, and 40% of the thickness of the first oxide layer 151 is The oxide layer formed by oxidizing from the surface to the inside, therefore, the distance d3 between the second grooves 142 is equal to eight times the thickness of the first oxide layer 151, that is, the width of the land 143 is equal to the thickness of the first oxide layer 151. At eight times, in other preferred embodiments, the distance d3 between the second grooves 142 is less than or equal to eight times the thickness of the first oxide layer 151.

Depositing a second oxide layer 152 on the first oxide layer 151 to fill the eight second recesses 142, thereby forming a semiconductor device semi-finished product 1d, wherein the second oxide layer 152 is cerium oxide, and the second oxygen The thickness of the layer 152 is equal to one-half of the width d2 of the second recess 142. In other preferred embodiments, the thickness of the second oxide layer 152 is greater than or equal to the width d2 of the second recess 142. one. Further, the first oxide layer 151 and the second oxide layer 152 are superposed on each other to form a stepped oxide layer.

The semiconductor device semi-finished product 1d provided by the above process steps is polished to expose the second doped implant layer 131b and the second doped source implant layer 132a to form the semiconductor device 100, and the semiconductor device 100 includes a semiconductor substrate 1 having an active region A and a termination region T thereof, and the semiconductor substrate 1 includes a first doped base layer 11, a first doped balance layer 121a, a second doped balance layer 122, and a second doping The pattern implant layer 131b, the first oxide layer 151a, the second oxide layer 152a, and the second dopant type source implant layer 132a.

The first doping type balance layer 121a is disposed on the first doped base layer 11 at intervals. The second doping type balancing layer 122 is disposed on the first doping type underlayer 11 in a staggered manner with the first doping type balancing layer 121a. The second doped implant layer 131b is disposed on the plurality of second doped balance layers 122 on the boundary between the active region A and the termination region T. The first oxide layer 151a is disposed on the first doping type balance layer 121a, the second doping type balance layer 122, and the second doped type implant layer 131b in the termination region T, and the first oxide layer 151a has a a first groove structure 1511a and eight second groove structures 1512a, the first groove structure 1511a is adjacent to the active area A, the second groove structure 1512a is away from the active area A, and the second groove structure 1512a is The spacing d3 is set at intervals. Wherein the first groove structure 1511a The width d1 is greater than or equal to the width d2 of the second groove structure 1512a, and the distance d3 between the second groove structures 1512a is less than or equal to eight times the thickness of the first oxide layer 151a, and the second groove structure The width d2 of 1512a is less than or equal to twice the thickness of the second oxide layer 152a. In other preferred embodiments, a second number of grooves of appropriate number and width can be etched on the semiconductor substrate by a single mask etch process depending on the applied voltage conditions.

The second oxide layer 152a is disposed in the first groove structure 1511a and the second groove structure 1512a, and has a third groove structure 1521a in the first groove structure 1511a.

The second doped source implant layer 132a is disposed on the second doped balance layer 122 in the active region A and adjacent to the second doped implant layer 131b.

Please refer to the sixth drawing, which is a cross-sectional view showing a semiconductor device provided by another preferred embodiment of the present invention.

As shown in the figure, the second doped source implant layer 132a of the semiconductor device 100 provided after the above grinding is formed into two first doped implanted epitaxial layers (1321, 1323) via an implantation or diffusion process. And a second doped type implant epitaxial layer 1322, wherein the two first doped implanted epitaxial layers (1321, 1323) are doped with a high concentration of N-type conductivity type impurities, and the second doping The impurity-type epitaxial layer 1322 is doped with a high concentration of P-type conductivity type impurities.

The first doped balance layer 121b at the edge of the termination region T terminates the implant layer 2 via a implantation or diffusion process to form a channel doped with a high concentration of N-type conductivity type impurities to prevent leakage. Health.

Depositing a gate oxide layer 31 to deposit a gate oxide layer 31 on the first doped balance layer 121a between the second doped implant layer 131b and the second doped source implant layer 132b, and Partially disposed on the second doped implant layer 131b and the second doped source implant layer 132b, and then the gate layer 32 is disposed on the gate oxide layer 31, wherein the gate oxide layer 31 is As the cerium oxide, the gate layer 32 is polycrystalline germanium.

Depositing a polysilicon layer 4 on the first oxide layer 151a and the second oxide layer 152a, and forming a second doped implant layer 131b, a second doped source implant layer 132b, a first oxide layer 151a, A third oxide layer 5 is deposited on the second oxide layer 152a, the gate layer 32, and the polysilicon layer 4, wherein the third oxide layer 5 is cerium oxide.

A metal field plate 6 is disposed on the third oxide layer 5 at the termination region T, and a source layer 7 is deposited on the second doped source implant layer 132a, and the drain layer 8 is disposed on the first layer. The bottom surface of the doped base layer 11.

Compared with the conventional process steps, a secondary mask etching process must be performed in the conventional process to form trenches having different depths, thereby depositing the first oxide layer 151a and the second oxide as in the present invention. The stepped oxide layer is formed by laminating the layer 152a. However, the present invention only needs a single mask etching process to simultaneously form the first recess 141 and the second recess 142, and then formed by the high temperature oxidation and deposition process. A stepped oxide layer in which the oxide layer 151a and the second oxide layer 152a are stacked. The manufacturing method of the present invention can reduce the steps required for the process, thereby saving the process time and energy cost required for the mask etching. And the cost of raw materials, and the semiconductor device provided by the present invention is formed by the above-described manufacturing method.

In practical terms, when the gate layer 32 and the source layer 7 are coupled to the ground (not shown) and a high reverse voltage is applied to the drain layer 8, the semiconductor device 100a is subjected to high Operating at a voltage, a plurality of first doping type balancing layers 121a and a plurality of second doping type balancing layers 122 alternately arranged with each other form a charge balancing layer, so that the electric field is uniformly distributed in the charge balancing layer, and the termination region T is a stepped oxide layer formed by laminating the first oxide layer 151a and the second oxide layer 152a, which is thicker at an oxide layer away from the active region A, such a stepped oxide layer and a portion of the first recess 141 The structure of a portion of the second doped implant layer 131b enables the semiconductor device 100a to maintain a uniform distribution of the electric field in the termination region T even under high voltage operation without causing a charge distribution. A phenomenon in which the termination region T of the semiconductor device 100a collapses occurs.

In summary, the semiconductor device provided by the present invention is mainly provided by the first recess structure and the second recess structure of the first oxide layer, and the second oxide layer is compared with the conventional semiconductor device. The stepped oxide layer is formed to make the electric field distribution in the termination region uniform, and only a single mask etching process is used in the process of forming the first oxide layer and the second oxide layer, thereby saving time and energy cost required for the process. And raw material costs.

With the above detailed description of the preferred embodiments, it is desirable to more clearly describe the features and spirit of the present invention, rather than the above disclosed The specific embodiment is intended to limit the scope of the creation. On the contrary, it is intended to cover all kinds of changes and equivalences within the scope of the patent application to which the present invention is intended.

1d‧‧‧Semiconductor for semiconductor devices

11‧‧‧First doped base layer

121a‧‧‧First doped equilibrium layer

122‧‧‧Second doped equilibrium layer

141‧‧‧first groove

142‧‧‧second groove

151‧‧‧First oxide layer

152‧‧‧Second oxide layer

Claims (12)

A semiconductor device comprising: a semiconductor substrate having an active region and a termination region adjacent to the active region, and the semiconductor substrate comprises: a first doped base layer; and a plurality of first doped balance layers Disposed on the first doped base layer at intervals; a plurality of second doped balance layers are disposed on the first doped base in a staggered manner with the first doped balance layers a second doped implant layer disposed on the second doped balance layer at a boundary between the active region and the termination region; a first oxide layer in the termination region And disposed on the first doped balance layer, the second doped balance layer, and the second doped implant layer, and the first oxide layer has a first groove structure and a plurality of a second groove structure, the first groove structure is adjacent to the active area, the second groove structures are away from the active area, and the second groove structures are disposed at a spacing interval; a dioxide layer disposed on the first recess structure and the second recesses Configuration, and the third groove having a groove structure in the first configuration. The semiconductor device of claim 1, wherein the width of the first groove structure is greater than or equal to the width of the second groove structures. The semiconductor device of claim 1, wherein the distance between the second groove structures is less than or equal to the thickness of the first oxide layer. Times. The semiconductor device of claim 1, wherein the width of the second recess structure is less than or equal to twice the thickness of the second oxide layer. The semiconductor device of claim 1, further comprising a second doped source implant layer disposed on one of the second doped balance layers adjacent to the The second doped implant layer is located in the active region. The semiconductor device of claim 1, further comprising a channel termination implant layer disposed on one of the first doped balance layers and located at an edge of the termination region. The semiconductor device of claim 5, further comprising a gate oxide layer and a gate layer, the gate oxide layer being deposited on the second doped implant layer and the second doped type The first doped balance layer between the source implant layers is partially overlaid on the second doped implant layer and the second doped source implant layer, and the gate layer is disposed On the gate oxide layer. The semiconductor device of claim 1, further comprising a polysilicon layer deposited on the first oxide layer and the second oxide layer of the semiconductor device. The semiconductor device of claim 7, wherein the semiconductor device comprises a third oxide layer overlying the second doped implant a layer, the second doped source implant layer, the first oxide layer, the second oxide layer, the gate layer, and the polysilicon layer. The semiconductor device of claim 9, comprising a metal field plate formed on the third oxide layer and located at an edge of the termination region. The semiconductor device of claim 5, wherein the semiconductor device comprises a source layer disposed on the second doped source implant layer. The semiconductor device of claim 1, wherein the semiconductor device comprises a drain layer disposed on a bottom surface of the first doped base layer.