TWM451666U - Solar cell - Google Patents

Abstract

A solar cell having a plurality of polygonal light receiving units neighboring to each other is provided. The solar cell includes a first type semiconductor substrate, a second type semiconductor layer, a first electrode layer, an anti-reflection layer, a second electrode layer, a plurality of conductive plugs and a third electrode layer. The first type semiconductor substrate has a plurality of first through holes penetrating the first type semiconductor substrate. The second type semiconductor layer has a plurality of second through holes penetrating the second type semiconductor layer. Each of the second through holes is connected to one of the first through holes. A plurality of apexes of the light receiving units are defined by the second through holes. The first electrode layer includes a plurality of hollow patterns. Each of the hollow patterns are located corresponding to one of the light receiving units, a center of the hollow pattern is overlapped with a center of the light receiving unit, and apexes of the hollow pattern are connected to apexes of the light receiving unit.

Description

Solar battery

This creation is about a solar cell.

A solar cell is an energy-converting photovoltaic device. The basic structure of a typical solar cell includes four main parts: a substrate, an emitter layer, an anti-reflection layer, and two metal electrodes. In short, the working principle of a solar cell is to illuminate the emitter layer via sunlight, and the emitter layer converts the energy of the light into electrical energy, and then transmits the electric energy through the two metal electrodes. Generally, two metal electrodes in a solar cell are respectively disposed on a light receiving surface and an unaffected surface for external connection, wherein the uncovered surface is generally regarded as the back surface, and the light receiving surface is regarded as the front surface.

The light-receiving electrode is designed to be one of the important techniques for improving the efficiency of solar cells. In short, in addition to effectively collecting the carriers, the electrodes on the light-receiving surface should minimize the proportion of the electrodes that shield the incident light. Therefore, the electrodes of the light-receiving surface are generally designed to have a special pattern structure, for example, a plurality of very fine finger electrodes extending from a bus bar. However, the area that can be reduced by the electrode of the light receiving surface is limited, and excessively reducing the area occupied by the electrode of the light receiving surface causes an increase in resistance, which increases the resistance of the electrode of the light receiving surface, resulting in loss of energy. Therefore, the structural design of the back-contact solar cell has become one of the key technologies of solar cells in recent years.

Back-contact solar cell is utilized The back surface of the bus electrode is used to reduce the ratio of the incident light to the electrode on the light receiving surface, thereby improving the efficiency of the solar cell. The back electrode solar cells are mainly divided into three categories, namely, interdigitated, Emitter Wrap Through (EWT) and Metal Wrap Through (MWT) back electrode solar cells. For example, a metal-transmissive back electrode solar cell is provided through a hole in the substrate, and the holes are filled with metal to guide the electrons collected by the light-receiving surface to the back surface of the solar cell. Thus, the light-receiving surface of the light-receiving electrode can be changed into a dot-like structure by a conventional linear structure, thereby providing more freedom in the distribution of the finger electrodes and the design of the electrode patterns. However, although the current technology has a design for the distribution of the spot-shaped bus electrodes, the distribution and structural design of the finger electrodes are mainly aesthetically pleasing, so that the energy loss of the carriers during conduction cannot be effectively reduced.

The present invention provides a solar cell that reduces energy loss of a carrier when it is conducted.

The present invention proposes a solar cell having a plurality of light receiving units of polygonal shapes adjacent to each other. The solar cell includes a first type semiconductor substrate, a second type semiconductor layer, a first electrode layer, an anti-reflection layer, a second electrode layer, a plurality of conductive plugs, and a third electrode layer. The first type semiconductor substrate has a plurality of first through holes penetrating through the first type semiconductor substrate. The second type semiconductor layer is on the first type semiconductor substrate. The second type semiconductor layer has a plurality of second through holes penetrating the second type semiconductor layer. Each of the second through holes is connected to one of the first through holes. The second through hole defines the apex of the light receiving unit. Second type semiconductor layer Between the first electrode layer and the first type semiconductor substrate. The first electrode layer includes a plurality of hollow patterns. Each of the cutout patterns is disposed corresponding to one of the light receiving units, and a center of the hollow pattern overlaps with a center of the light receiving unit, and a vertex of the hollow pattern is connected to a vertex of the light receiving unit. The first electrode layer and the anti-reflection layer are on the same side of the second type semiconductor layer, and the anti-reflection layer is located in a region other than the first electrode layer. The second electrode layer is disposed corresponding to the first electrode layer, and the first type semiconductor substrate is located between the second electrode layer and the second type semiconductor layer. The conductive plugs are located in the first through holes and the second through holes connected to each other to electrically connect the second electrode layer and the first electrode layer. The third electrode layer and the second electrode layer are on the same side of the first type semiconductor substrate, and the third electrode layer is electrically insulated from the second electrode layer.

In an embodiment of the present invention, the area enclosed by each of the hollow patterns accounts for between 5% and 50% of the area of the corresponding light receiving unit.

In one embodiment of the present invention, each of the aforementioned hollow patterns is a closed pattern.

In an embodiment of the present invention, the first electrode layer further includes a plurality of extension patterns. The extension patterns respectively extend from the apex of the hollow pattern and are connected to the vertices of the light receiving unit.

In an embodiment of the present invention, each of the hollow patterns described above has substantially the same shape as each of the light receiving units.

In an embodiment of the present invention, each of the hollow patterns is formed by a plurality of arcs, and each arc connects the vertices of two adjacent light receiving units, and the area enclosed by the arc occupies 5% to 50% of the area of the light receiving unit. .

In an embodiment of the present invention, the shape of each of the aforementioned hollow patterns is Fan-shaped or dart-shaped.

In one embodiment of the present invention, each of the aforementioned hollow patterns has a plurality of sides on different sides of the light receiving unit.

In one embodiment of the present invention, one of the first type semiconductor substrate and the second type semiconductor layer is P-type, and the other of the first type semiconductor substrate and the second type semiconductor layer is N-type.

In an embodiment of the present invention, the solar cell further includes an insulating layer on the first type semiconductor substrate and at least between the first type semiconductor substrate and the conductive plug and the first type semiconductor substrate and the second electrode Between the layers.

Based on the above, the present invention reduces the carrier collection efficiency by moving the center of the hollow pattern (the pattern of the finger electrodes) away from the conductive plug (the point-like bus electrode) to reduce the carrier collection efficiency away from the conductive plug, thereby reducing the carrier. The energy loss during conduction improves the photoelectric conversion efficiency of the solar cell.

In order to make the above features and advantages of the present invention more comprehensible, the following embodiments are described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view of a solar cell according to an embodiment of the present invention. Referring to FIG. 1 , the solar cell 100 of the present embodiment includes a first type semiconductor substrate 110 , a second type semiconductor layer 120 , a first electrode layer 130 , an anti-reflection layer 140 , a second electrode layer 150 , and a plurality of conductive plugs 160 . And a third electrode layer 170.

The second type semiconductor layer 120 is located on the first type semiconductor substrate 110 Glossy S1. The light receiving surface S1 is a surface on which the solar cell 100 absorbs photons. Further, one of the first type semiconductor substrate and the second type semiconductor layer is P-type, and the other of the first type semiconductor substrate and the second type semiconductor layer is N-type. In the present embodiment, the first type semiconductor substrate is, for example, a P type, and the second type semiconductor layer is, for example, an N type.

Further, the first type semiconductor substrate 110 is, for example, a P-type germanium substrate, and the second type semiconductor layer 120 is, for example, an N-type semiconductor layer, and the material of the semiconductor layer is, for example, germanium and its alloy, cadmium sulfide (CdS), CuInGaSe ₂ (CIGS), CuInSe ₂ (CIS), CdTe, organic materials or a multilayer structure of the above materials. The ruthenium includes single crystal silicon, poly-crystal silicon, and amorphous silicon. The above ruthenium alloy refers to a hydrogen atom (H), a fluorine atom (F), a chlorine atom (Cl), a ruthenium atom (Ge), an oxygen atom (O), a carbon atom (C) or a nitrogen atom (N). Equal atoms. In some embodiments, the surface of the first type semiconductor substrate 110 can be enhanced by the formation of a serrated textured surface to enhance the absorption of sunlight, as is known to those of ordinary skill in the art. No longer.

Further, the first type semiconductor substrate 110 has a plurality of first through holes V1 penetrating the first type semiconductor substrate 110, and the second type semiconductor layer 120 has a plurality of second through holes V2 penetrating the second type semiconductor layer 120. Each of the second through holes V2 is connected to one of the first through holes V1. In the present embodiment, the diameter of the first through hole V1 and the diameter of the second through hole V2 are substantially the same.

The first electrode layer 130 is located on the second type semiconductor layer 120, and the second The semiconductor layer 120 is located between the first electrode layer 130 and the first type semiconductor substrate 110. In other words, the first electrode layer 130 is electrically connected to the first type semiconductor substrate 110 through the second type semiconductor layer 120 . The material of the first electrode layer 130 is, for example, aluminum conductive paste, aluminum paste or silver-aluminum glue.

The anti-reflective layer 140 is located on the second type semiconductor layer 120, and the anti-reflective layer 140 is located on the same side of the second electrode layer 120 as the first electrode layer 130, and is located in a region other than the first electrode layer 130. The material of the anti-reflection layer 140 is, for example, bismuth oxynitride, tantalum nitride or other suitable material.

The second electrode layer 150 is disposed corresponding to the first electrode layer 130, and the second electrode layer 150 and the first electrode layer 130 are respectively located on the light receiving surface S1 and the unglazed surface S2 of the first type semiconductor substrate 110, wherein the light receiving surface S1 is not The light receiving surface S2 is the opposite surfaces of the first type semiconductor substrate 110. Further, the first type semiconductor substrate 110 is located between the second electrode layer 150 and the second type semiconductor layer 120. Further, the second electrode layer 150 may be made of a material similar to the first electrode layer 130. In short, the material of the second electrode layer 150 is, for example, aluminum conductive glue, aluminum glue or silver-aluminum glue.

The conductive plugs 160 are located in the first through holes V1 and the second through holes V2 connected to each other to electrically connect the second electrode layer 150 and the first electrode layer 130.

The third electrode layer 170 is located on the first type semiconductor substrate 110 and is located on the same side of the first type semiconductor substrate 110 as the second electrode layer 150. Further, the third electrode layer 170 is electrically insulated from the second electrode layer 150.

In addition, the solar cell 100 of the embodiment may further include an insulating layer 180 on the first type semiconductor substrate 110, and at least in the first type. The semiconductor substrate 110 and the conductive plug 160 are interposed between the first type semiconductor substrate 110 and the second electrode layer 150. Further, by the arrangement of the insulating layer 180, the short circuit problem caused by the conductive plug 160 and the second electrode layer 150 being in direct contact with the first type semiconductor substrate 110 can be avoided.

It should be noted that the above embodiments are for illustrative purposes only, and the present creation is not limited thereto. Specifically, the present creation does not limit the relative arrangement position of the second electrode layer 150 and the third electrode layer 170, the electrode pattern of the second electrode layer 150 or the third electrode layer 170, the shape or diameter of the conductive plug 160, and the first Whether the surface of the type semiconductor substrate 110 is a textured surface or the like. For example, in other embodiments, the third electrode layer 170 may be a full-surface electrode and comprehensively cover the unglazed surface S2 of the first type semiconductor substrate 110, and the third electrode layer 170 may have a third surface. The through hole, wherein the conductive plug 160 is electrically connected to the second electrode layer 150 and the first electrode layer 130 through the third through hole.

The electrode pattern design of the first electrode layer 130 of FIG. 1 and its distribution will be described in more detail below. 2A is a partial top plan view showing a first electrode layer of a solar cell according to an embodiment of the invention. Referring to FIG. 2A, the solar cell of the present embodiment has a plurality of light receiving units U1 adjacent to each other, wherein the second through holes V2 (ie, the positions where the conductive plugs 160 are located) define the vertices of the light receiving units U1.

In detail, the first electrode layer 130A includes a plurality of hollow patterns P1A, wherein each of the hollow patterns P1A is, for example, a closed pattern, that is, each of the hollow patterns P1A is a continuous and unbroken pattern, but the present creation is not limited thereto. The general knowledge in the field can change the hollow pattern P1A according to actual needs. good.

In addition, each of the hollow patterns P1A is disposed corresponding to one of the light receiving units U1, wherein an area surrounded by each of the hollow patterns P1A occupies between 5% and 50% of the area of the corresponding light receiving unit U1. Specifically, the center C _{P of the} hollow pattern P1A overlaps with the center C _{U of the} light receiving unit U1. The center as used herein refers to a position in the pattern that is equidistant from each vertex.

Further, the apex of the hollow pattern P1A is connected to the apex of the light receiving unit U1. In the present embodiment, the first electrode layer 130A further includes a plurality of extension patterns P2, and the apex of the hollow pattern P1A is connected to the apex of the light receiving unit U1 through the respective extension patterns P2, for example. Specifically, the extension pattern P2 extends from the apex of the hollow pattern P1A and is connected to the vertex of the light receiving unit U1.

Further, the shape of the light receiving unit U1 of the present embodiment is, for example, a triangle, wherein one conductive plug 160 is connected to the adjacent six hollow patterns P1A. Further, the shape of each of the cutout patterns P1A is substantially the same as the shape of each of the light receiving units U1. In other words, the shape of each of the hollow patterns P1A of the present embodiment is also a triangle. In addition, the three sides of the hollow pattern P1A are respectively parallel to the three sides of the light receiving unit U1, and the pairs of parallel sides are disposed adjacent to each other.

In this embodiment, the center of the polygonal hollow pattern P1A is disposed at a position away from the conductive plug 160. Thus, after the photocell is received by the solar cell, the distance required for the carrier generated by the first type semiconductor substrate 110 (shown in FIG. 1) at the conductive plug 160 to move toward the first electrode layer 130A can be effectively reduced. And the overall carrier collection area can also be improved. Therefore, this The embodiment can effectively improve the collection efficiency of the carrier away from the conductive plug 160, and reduce the energy loss of the carrier during conduction, so that the photoelectric conversion efficiency of the solar cell can be improved.

It should be noted that the embodiment of FIG. 2A has a triangular light receiving unit U1 and a triangular hollow pattern P1A as an example, but the present creation is not limited thereto. In other embodiments, the shape of the light receiving unit may be different from the shape of the hollow pattern, or the shape of the light receiving unit and the hollow pattern may be the same, but not a triangle.

2B is a partial top plan view of a first electrode layer of a solar cell according to another embodiment of the present invention. Referring to FIG. 2B, the first electrode layer 130B of the present embodiment has a similar structure to the first electrode layer 130A of FIG. 2A. The main difference between the two is the electrode pattern design of the first electrode layer 130B and its distribution. Specifically, the light receiving unit U2 and the hollow pattern P1B of the present embodiment have a quadrangular shape, and one conductive plug 160 is connected to the adjacent four hollow patterns P1B.

The embodiment of FIG. 2B can also be disposed at a position away from the conductive plug 160 by the center of the hollow pattern P1B, so that the solar cell receives the photon and is away from the first type semiconductor substrate 110 at the conductive plug 160 (shown in The distance required for the generated carrier to move toward the first electrode layer 130B is effectively reduced, and the overall carrier collection area is also increased. As such, the present embodiment can effectively improve the collection efficiency of the carrier away from the conductive plug 160, and reduce the energy consumption of the carrier during conduction, thereby improving the photoelectric conversion efficiency of the solar cell.

Vertices of the hollow patterns P1A, P1B in the embodiment of Figures 2A and 2B It is connected to the vertices of the light receiving units U1 and U2 through the respective extension patterns P2. However, this creation is not limited to this. Other embodiments of the first electrode layer will be described below with reference to FIGS. 3A, 3B, 4A, 4B, 5A, and 5B. 3A, 3B, 4A, 4B, 5A, and 5B are schematic top views of the first electrode layer of the solar cell of another embodiment.

Referring to FIGS. 3A and 3B, the first electrode layers 130C, 130D have a similar structure to the first electrode layers 130A, 130B. The main difference is that each of the hollow patterns P1C and P1D of the first electrode layers 130C and 130D is composed of a plurality of arcs, and each arc directly connects the vertices of the adjacent two light receiving units U1 and U2, and the area surrounded by the arc occupies the light receiving unit. The area is between 5% and 50%. Further, the arcs located in the respective light receiving units U1, U2 are recessed into the light receiving units U1, U2.

Referring to FIGS. 4A and 4B, the first electrode layers 130E, 130F have a similar structure to the first electrode layers 130A, 130B. The main difference is that the shapes of the respective hollow patterns P1E, P1F of the first electrode layers 130E, 130F are fan-shaped. Further, the shape of each of the hollow patterns P1E, P1F may be divided into a body region 10 and a plurality of extended regions 20A, wherein each of the hollow patterns P1E, P1F is distributed around the outer contours of the body region 10 and the extended region 20A. In the embodiment of FIG. 4A and FIG. 4B, the number of the extended regions 20A is the same as the number of the sides of the light receiving units U1, U2, but the present invention is not limited thereto.

Further, the extended region 20A extends from the body region 10 to the boundary of the light receiving units U1, U2 such that each of the hollow patterns P1E, P1F has a plurality of sides on different sides of the light receiving units U1, U2. In Figures 4A and 4B In the embodiment, the shape of the body region 10 is substantially the same as the shape of the light receiving units U1, U2, for example, and the plurality of sides of the body region 10 are parallel to the plurality of sides of the light receiving units U1, U2, respectively, and the pairs of parallel sides Set close to each other. On the other hand, the shape of each of the extending regions 20A of the embodiment of FIGS. 4A and 4B is, for example, a parallelogram in which a pair of parallel short sides of each of the extending regions 20A are located on a side of the body region 10 while the other side is located. The portions of the light receiving units U1, U2 are connected to the conductive plug 160.

Of course, this creation is limited to the above. Referring to FIGS. 5A and 5B, the first electrode layers 130G, 130H have a similar structure to the first electrode layers 130E, 130F. The main difference is that the shapes of the respective hollow patterns P1G, P1H of the first electrode layers 130G, 130H are in the shape of a dart. Specifically, the shape of each of the extended regions 20B is, for example, an arrow shape. Further, each of the extended regions 20B has a convex vertical corner and a concave vertical corner, wherein the vertical corners of the recess are located on the adjacent sides of the body region 10, and the convex vertical corners are located in the light receiving unit. U1 and U2 are adjacent to each other and connected to the conductive plug 160.

It should be noted that the foregoing FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B, FIG. 5A and FIG. 5B are only used to illustrate the implementation of the first electrode layers 130C, 130D, 130E, 130F, 130G, and 130H of the present invention. It is not intended to limit the invention. Although the foregoing embodiment is exemplified only by the triangular and quadrilateral light receiving units U1 and U2, in other embodiments, the light receiving unit may be other polygonal shapes, and details are not described herein again.

The embodiments of FIGS. 3A, 3B, 4A, 4B, 5A, and 5B can also pass through the hollow patterns P1C, P1D, P1E, P1F of the polygon, The centers of P1G and P1H are disposed at positions away from the conductive plugs 160. Thus, after the photocell receives the photon, the carrier generated by the first type semiconductor substrate 110 (shown in FIG. 1) at the conductive plug 160 is transferred to the first electrode layer 130C, 130D, 130E, 130F, 130G, 130H. The distance required to be moved can be effectively reduced, and the overall carrier collection area can also be increased. Therefore, the above embodiments can effectively improve the collection efficiency of the carrier away from the conductive plug 160, and reduce the energy loss of the carrier during conduction, thereby improving the photoelectric conversion efficiency of the solar cell.

In summary, the creation can reduce the distance required to move away from the carrier at the conductive plug and increase the collection area of the carrier by setting the center of the hollow pattern of the polygon to a position away from the conductive plug. In this way, the collection efficiency of the carrier away from the conductive plug can be effectively improved, and the energy loss of the carrier during conduction can be reduced, and the photoelectric conversion efficiency of the solar cell can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person having ordinary knowledge in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of this creation is subject to the definition of the scope of the patent application attached.

100‧‧‧ solar cells

110‧‧‧First type semiconductor substrate

120‧‧‧Second type semiconductor layer

130, 130A, 130B, 130C, 130D, 130E, 130F, 130G, 130H‧‧‧ first electrode layer

140‧‧‧Anti-reflective layer

150‧‧‧Second electrode layer

160‧‧‧conductive plug

170‧‧‧ third electrode layer

180‧‧‧Insulation

10‧‧‧ body area

20A, 20B‧‧‧ Extended area

S1‧‧‧Stained surface

S2‧‧‧ is not smooth

V1‧‧‧ first through hole

V2‧‧‧ second through hole

U1, U2‧‧‧ light receiving unit

P1A, P1B, P1C, P1D, P1E, P1F, P1G, P1H‧‧‧ hollow patterns

P2‧‧‧Extension pattern

C _P , C _U ‧‧‧ Center

1 is a schematic cross-sectional view of a solar cell according to an embodiment of the present invention.

2A is a partial top plan view showing a first electrode layer of a solar cell according to an embodiment of the invention.

2B is a first electrode of a solar cell according to another embodiment of the present invention A partial top view of the layer.

3A, 3B, 4A, 4B, 5A, and 5B are schematic top views of the first electrode layer of the solar cell of another embodiment.

130A‧‧‧First electrode layer

160‧‧‧conductive plug

V2‧‧‧ second through hole

U1‧‧‧ light receiving unit

P1A‧‧‧ hollow pattern

P2‧‧‧Extension pattern

C _P , C _U ‧‧‧ Center

Claims (10)

A solar cell having a plurality of light receiving units adjacent to each other, the solar cell comprising: a first type semiconductor substrate having a plurality of first through holes penetrating the first type semiconductor substrate; a second type semiconductor layer, Located on the first type semiconductor substrate, the second type semiconductor layer has a plurality of second through holes penetrating the second type semiconductor layer, and each of the second through holes is connected to one of the first through holes, and the second type The through hole defines an apex of the light receiving unit; a first electrode layer, wherein the second type semiconductor layer is located between the first electrode layer and the first type semiconductor substrate, and the first electrode layer comprises a plurality of hollow patterns, Each of the hollow patterns is disposed corresponding to one of the light receiving units, and a center of the hollow pattern overlaps a center of the light receiving unit, and an apex of the hollow pattern is connected to an apex of the light receiving unit; an anti-reflection layer, and the first electrode layer Located on the same side of the second type semiconductor layer, and the anti-reflection layer is located outside the first electrode layer; a second electrode layer corresponding to the first electrode layer is disposed, The first type semiconductor substrate is located between the second electrode layer and the second type semiconductor layer; a plurality of conductive plugs are located in the first through holes and the second through holes connected to each other to make the first The second electrode layer is electrically connected to the first electrode layer; and a third electrode layer is disposed on the same side of the first electrode substrate as the second electrode layer, and the third electrode layer and the second electrode layer Electrical edge. The solar cell of claim 1, wherein an area enclosed by each of the hollow patterns accounts for between 5% and 50% of an area of the corresponding light receiving unit. The solar cell of claim 1, wherein each of the hollow patterns is a closed pattern. The solar cell of claim 1, wherein the first electrode layer further comprises a plurality of extending patterns, the extending patterns respectively extending from the vertices of the hollow patterns and the vertices of the light receiving units connection. The solar cell according to claim 3, wherein the shape of each of the hollow patterns is substantially the same as the shape of each of the light receiving units. The solar cell of claim 1, wherein each of the hollow patterns is formed by a plurality of arcs, each of the arcs connecting an apex of two adjacent light receiving units, and an area surrounded by the arcs occupies the light receiving unit The area is between 5% and 50%. The solar cell according to claim 1, wherein each of the hollow patterns has a shape of a fan blade or a dart. The solar cell of claim 7, wherein each of the hollow patterns has a plurality of sides on different sides of the light receiving unit. The solar cell of claim 1, wherein one of the first type semiconductor substrate and the second type semiconductor layer is P type, and the first type semiconductor substrate and the second type semiconductor layer are another It is N type. Such as the solar cell described in claim 1 of the patent scope, An insulating layer is disposed on the first type semiconductor substrate and at least between the first type semiconductor substrate and the conductive plug and between the first type semiconductor substrate and the second electrode layer.