TWM445805U - Power factor controller - Google Patents

Abstract

A power factor controller is provided and which includes an AC input terminal, an error input terminal, a detected input terminal, an output terminal, a low level clamp circuit, a multiplier and a control circuit. The low level clamp circuit is coupled to the AC input terminal, used for an AC input signal is clamped at low level in a nonzero crossover offset level. The multiplier is coupled to the AC input terminal and the error input terminal, used for calculating by multiplying a DC error signal and clamped AC input signal, and to output a product signal. The control circuit is coupled to the detected input terminal and the output terminal, and to receive the product signal, and to generate a driving signal to the output terminal according to the product signal and a detection signal.

Description

Power factor controller

The present invention relates to a power conversion technique, and more particularly to a power factor controller for use in a power conversion device.

A conventional power factor control integrated circuit includes a multiplier and a comparator. The multiplier is configured to receive an AC input signal related to the input voltage, a DC error signal related to the output voltage, and calculate a product of the AC input signal and the DC error signal to generate a product signal, and then output the product signal to the comparator (or control) Circuit) for subsequent related operations. However, the AC input signal has a zero crossing condition, so that the product signal will also have a zero crossing condition, which will cause the comparator to be unable to compare and cause signal distortion. In general, conventional techniques result in poor total harmonic distortion (THD) of the input voltage and input current.

The prior art approach is very complicated for the distortion caused by zero crossing. Usually, in order to solve the zero-crossover, complex computing circuits are used, which often makes the power factor control integrated circuit bulky, and the circuit cost increases with complicated computing circuits, so it is still ill and difficult to solve.

The present creation is to provide a power factor controller that addresses the problems of the prior art and prior art.

This creation provides a power factor controller that includes an AC input Sub, error input terminal, detection input terminal, output terminal, low level clamp circuit, multiplier and control circuit. The AC input terminal is used to receive an AC input signal. The error input terminal is used to receive the DC error signal. The detection input terminal is used to receive the detection signal. The low-level clamp circuit is coupled to the AC input terminal for clamping the AC input signal to a non-zero crossover offset level at a low level. The multiplier is coupled to the AC input terminal and the error input terminal for multiplying the DC error signal and the clamped AC input signal to output a product signal. The control circuit is coupled to the detection input terminal and the output terminal, and receives the product signal, and generates a driving signal to the output terminal according to the product signal and the detection signal.

In an exemplary embodiment in accordance with the present teachings, the low level clamp circuit includes an amplifier, a switch, and a current limiting resistor. The non-inverting input of the amplifier receives the reference voltage, and the inverting input receives the AC input signal. The switch has a first end, a second end and a control end, and the control end is coupled to the output end of the amplifier, and the first end receives the working voltage. The current limiting resistor is coupled between the second end and the inverting input of the amplifier.

In an exemplary embodiment in accordance with the present invention, the reference voltage has a level that is the same as the non-zero crossover offset level, and the reference voltage is much smaller than the operating voltage.

In an exemplary embodiment in accordance with the present creation, the reference voltage is 50 mV and the operating voltage is 5V.

In an exemplary embodiment in accordance with the present teachings, the power factor controller is configured on an integrated circuit.

Based on the above, this creation clamps the AC input signal at a low level, so as to avoid the range of zero crossover distortion, which can effectively solve the traditional cause. The cost problem caused by the use of complex circuits and the huge size of the circuit. In addition, the power factor controller of the present invention is easy to implement low-level potential clamping, and it is easier to select components for the periphery.

In order to make the above features and advantages of the present invention more comprehensible, the following detailed description of the embodiments and the accompanying drawings will be described below.

Exemplary embodiments of the present invention will now be referred to in the detailed description, in which the examples of the exemplary embodiments are illustrated. Wherever possible, the same reference numerals are used in the drawings to refer to the same or.

1 is a circuit block diagram of a power conversion device in accordance with an embodiment of the disclosure. Please refer to Figure 1. The power conversion device 100 includes a rectifier 110, a resistor 112, a resistor 114, a capacitor 116, an inductor 118, a switch 120, a resistor 122, a diode 124, a capacitor 126, a resistor 128, a resistor 130, an amplifier 132, a capacitor 134, a resistor 136, and Power factor controller 200. The power conversion device 100 maintains the power quality by the power factor controller 200 and converts an AC input voltage Vin into a DC output voltage Vout.

In the present embodiment, the power factor controller 200 includes an AC input terminal 10, an error input terminal 20, a detection input terminal 30, an output terminal 40, a low level clamp circuit 50, a multiplier 60, and a control circuit 70. The AC input terminal 10 is used to receive the rectified AC input signal VI. The error input terminal 20 is for receiving a DC error signal SE, and the DC error signal SE is related to the DC output voltage Vout. Detection input terminal 30 is used to receive the detection The test signal CS, the detection signal CS is from the coupling of the switch 110 and the resistor 120. The low level clamp circuit 50 is coupled to the AC input terminal 10. The multiplier 60 is coupled to the AC input terminal 10 and the error input terminal 20. The control circuit 70 is coupled to the detection input terminal 30 and the output terminal 40.

The low level clamp circuit 50 is used to clamp the AC input signal VI to a non-zero crossover offset level at a low level to avoid the zero crossover level. Thus, the multiplier 60 calculates the product of the DC error signal SE and the clamped AC input signal VI1. Since the AC input signal VI is a non-zero value signal, the output of the multiplier 60 will be proportional to the clamped AC input signal VI1. That is to say, the product signal SM is proportional to the clamped AC input signal VI1. Next, the multiplier 60 outputs the product signal SM to the control circuit 70. After receiving the product signal SM, the control circuit 70 generates a driving signal SG to the output terminal 40 according to the product signal SM and the detection signal CS to perform related power quality control.

2 is a block diagram of a power factor controller 200 in accordance with an embodiment of the disclosure. 3 is a block diagram of a low level clamp circuit 50 in accordance with an embodiment of the disclosure. 4 is a waveform diagram in accordance with an embodiment of the disclosure. Please refer to Figure 2, Figure 3 and Figure 4.

The low level clamp circuit 50 can include an amplifier 52, a switch 54 and a current limiting resistor 56. The non-inverting input of amplifier 52 receives the reference voltage REF and the inverting input receives the AC input signal VI. The control terminal of the switch 54 is coupled to the output of the amplifier 52, and the first terminal of the switch 54 receives the operating voltage VCC. The current limiting resistor 56 is coupled between the second end of the switch 54 and the inverting input of the amplifier 52.

When the AC input signal VI is greater than the reference voltage REF, the switch 54 is not turned on, and the level of the AC input signal VI is not clamped; and when the AC input signal VI is less than the reference voltage REF, the current limiting resistor 56 limits the flow through the switch. The amount of current of 54 is such that the degree of conduction of the switch 54 is only slightly turned on, and the level of the inverting input of the amplifier 52 is not higher than the reference voltage REF, thereby clamping the level of the AC input signal VI to the reference voltage REF. The reference voltage REF is at the same level as the non-zero crossover offset level. In addition, when designing the low level clamp circuit 50, the reference voltage can be much smaller than the operating voltage. In yet another example, the reference voltage is 50 mV and the operating voltage is 5 V, however, the creation is not limited thereto.

On the other hand, the components of the power factor controller 220 illustrated in FIG. 2 can be packaged and configured on an integrated circuit (IC).

It should be noted that, as can be clearly seen from the waveform diagram of FIG. 4, the low-level clamp circuit 50 of the present invention processes the AC input signal VI so that the signals input to the multiplier 60 are higher than the zero level. The lowest level is clamped to the reference voltage REF, which is equivalent to providing a level of offset zero value, which avoids the range of zero crossover distortion. Moreover, since the multiplier 60 multiplies the DC error signal SE and the clamped AC input signal VI1, the product signal SM output by the multiplier 60 is proportional to the AC input signal VI1.

Moreover, the power factor controller 200 of the present invention easily realizes the potential clamping of the AC input signal at a low level, and it is also easier to select components for the periphery. Therefore, this creation can effectively solve the traditional use of complex circuits. The cost problem caused by the huge size of the circuit.

As with the preferred embodiment described above and the evaluation of the circuit analysis, the novel circuit of the present invention provides an alternative to high efficiency and mass production as compared to conventional techniques.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person having ordinary knowledge in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of this creation is subject to the definition of the scope of the patent application attached.

10‧‧‧AC input terminal

20‧‧‧Error input terminal

30‧‧‧Detection input terminal

40‧‧‧Output terminal

50‧‧‧Low-level clamp circuit

52‧‧‧Amplifier

54‧‧‧ switch

56‧‧‧ Current limiting resistor

60‧‧‧multiplier

70‧‧‧Control circuit

100‧‧‧Power conversion device

110‧‧‧Rectifier

112, 114, 122, 128, 130, 136‧ ‧ resistance

116, 126, 134‧‧‧ capacitor

118‧‧‧Inductance

120‧‧‧ switch

124‧‧‧ diode

132‧‧‧Amplifier

200‧‧‧Power Factor Controller

CS‧‧‧Detection signal

REF‧‧‧reference voltage

SE‧‧‧DC error signal

SG‧‧‧ drive signal

SM‧‧‧ product signal

VCC‧‧‧ working voltage

VI‧‧‧AC input signal

VI1‧‧‧Clamped AC input signal

Vin‧‧‧AC input voltage

Vout‧‧‧DC output voltage

1 is a block diagram of a power conversion device in accordance with an embodiment of the disclosure.

2 is a block diagram of a power factor controller in accordance with an embodiment of the disclosure.

3 is a circuit block diagram of a low level clamp circuit in accordance with an embodiment of the disclosure.

4 is a waveform diagram in accordance with an embodiment of the disclosure.

10‧‧‧AC input terminal

20‧‧‧Error input terminal

30‧‧‧Detection input terminal

40‧‧‧Output terminal

50‧‧‧Low-level clamp circuit

60‧‧‧multiplier

70‧‧‧Control circuit

200‧‧‧Power Factor Controller

CS‧‧‧Detection signal

SE‧‧‧DC error signal

SG‧‧‧ drive signal

SM‧‧‧ product signal

VI‧‧‧AC input signal

VI1‧‧‧Clamped AC input signal

Claims (5)

A power factor controller includes: an AC input terminal for receiving an AC input signal; an error input terminal for receiving a DC error signal; a detection input terminal for receiving a detection signal; an output terminal; and a low level a clamping circuit coupled to the AC input terminal for clamping the AC input signal to a non-zero crossover offset level when the AC input signal is at a low level; a multiplier coupled to the AC input terminal and the error input terminal And outputting a product signal by multiplying the DC error signal and the clamped AC input signal; and a control circuit coupled to the detection input terminal and the output terminal, and receiving the product signal, according to the product The signal and the detection signal generate a driving signal to the output terminal. The power factor controller of claim 1, wherein the low level clamp circuit comprises: an amplifier, the positive phase input terminal receives a reference voltage, the inverting input terminal receives the AC input signal; and a switch has a first end, a second end and a control end, the control end is coupled to the output end of the amplifier, the first end receives an operating voltage; and a current limiting resistor coupled to the second end and the amplifier Between the inverting inputs. A power factor controller as described in claim 2, The reference voltage is at the same level as the non-zero crossover offset level, and the reference voltage is much smaller than the operating voltage. The power factor controller of claim 3, wherein the reference voltage is 50 mV, and the operating voltage is 5V. The power factor controller of claim 1, wherein the power factor controller is configured on an integrated circuit.