M439178 五、新型說明： 【新型所屬之技術領域】 . 本創作為提供一種I C測試暨分類裝置， 尤指一種快速且節省成本的RFIC交錯式分 ¥ 類測試之結構。 【先前技術】 按，目前市面上習用I C測試與分類裝置 係可區分兩大類，一者為獨立作業之R F I C • 測試裝置以及I C自動分類機，另一者係為高 價位之整合裝置，然而由於R F I C測試裝置 其測試時間和效能已經接近於高價位之整合裝 置之單一測試站之單元之表現。 然而，當習用整合裝置同時進行分類時， 其自身之測試功能係為閒置而無法發揮最高效 益，且R F I C測試裝置的測試時間愈來愈短 且愈接近I C自動分類機的分配時間，因此測 w 試生產的單位時間的產出和成本的瓶頸漸漸由 測試端變成I C分類的時間和成本。 是以，要如何解決上述習用之問題與缺 失，即為本創作之創作人與從事此行業之相關 廠商所亟欲研究改善之方向所在者。 【新型内容】 故，本創作之創作人有鑑於上述缺失，乃 搜集相關資料，經由多方評估及考量，並以從 事於此行業累積之多年經驗，經由不斷試作及 3 M439178 修改’始設計出此種快# 々，丨、M439178 V. New description: [New technical field] This is to provide an I C test and classification device, especially a fast and cost-effective RFIC interleaved type of test structure. [Prior Art] According to the current market, the IC test and classification device on the market can be divided into two categories, one is the independent operation RFIC • the test device and the IC automatic sorter, and the other is the high-priced integrated device, however The test time and performance of the RFIC test set is already close to the performance of the unit of a single test station of the high-priced integrated device. However, when the conventional integrated device is classified at the same time, its own test function is idle and cannot achieve the highest efficiency, and the test time of the RFIC test device becomes shorter and shorter and closer to the distribution time of the IC automatic sorter, so the test is performed. The bottleneck of output and cost per unit time of trial production gradually changes from the test end to the time and cost of IC classification. Therefore, how to solve the problems and shortcomings of the above-mentioned practices, that is, the creators of the creation and the relevant manufacturers engaged in the industry are eager to study the direction of improvement. [New content] Therefore, the creators of this creation, in view of the above-mentioned deficiencies, are collecting relevant information, and through multi-party evaluation and consideration, and through years of experience accumulated in this industry, through continuous trials and 3 M439178 modification 'designed this Kind of fast # 々, 丨,
• r ^ -V- ,χ ^ 悝陕連且即省成本的RFI C父錯式/刀類測試士 、，·°構新型專利者。• r ^ -V- , χ ^ 悝 连 且 且 且 且 且 且 且 且 且 RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF
本創作之主I 測試與分_壯在於：為針對習用1 C 且镯立裴置'"置所存在之整合裝置硬體成本高 且節省由丄耗時的問題點加以突破，達到快速 本之實用進步性。 $|| 交錯式八上述之目的，本創作一種Rp I ς 类員至少〜員測試之結構，其為一用來檢測並分 分类員測钟 F 1 C晶片模組之分類測試襞置， 數分類模f置係包括：至少一測試模組以及複 剛試模Γ起，測試模組係測試各晶片模組’且 單元，=係於測試各晶片模組後產生分類指令 分類棋f中分類模組係接收分類指令單元，且 分類異魬係依據分類指令單元對晶片模組進行 分類模^分類模組係包括第一分類模組及第二 訊連接挺，第—分類模組及第二分類模組係資 模組係!!軾模組，且第一分類模組及第二分類 級針對'刀別分類各晶片模組’藉此’當測試模 時，第一分類模組内之晶片模組進行測試 之旁〜分類模組係同步對已被測試模組測試 組進!!模級進行分類動作，故，其中一分類模 行測I7晶片模組分類之空檐時’測試模組係進 者式另—分類模組内之晶片模組，進而利用 3卩民資、、塔 省 碌而能提高測試分類量，達到快速且節 战本之優點。 4 M439178 【實施方式】 ' 為達成上述目的及功效，本創作所採用之 . 技術手段及構造，茲繪圖就本創作較佳實施例 詳加說明其特徵與功能如下，俾利完全了解。 請參閱第一圖所示，係為本創作較佳實施 例之立體組合圖，由圖中可清楚看出本創作一 種R F I C交錯式分類測試之結構，其為一用 來檢測並分類至少一 R F I C之晶片模組3之 • 分類測試裝置4，該分類測試裝置係包括：一測 試模組1以及複數分類模組2，該測試模組1係 測試各該晶片模組3，且該測試模組1係於測試 各該晶片模組3後產生一分類指令單元1 1，其 中該些分類模組2係接收該分類指令單元11， 且該些分類模組2係依據該分類指令單元1 1對 該晶片模組3進行分類，並該些分類模組3係 包括一第一分類模組2 1及一第二分類模組2 2， * 該第一分類模組2 1及該第二分類模組2 2係資 訊連接該測試模組1，且該第一分類模組2 1及 該第二分類模組2 2係分別分類各該晶片模組 3，藉此，當該測試模組1針對該第一分類模組 21内之晶片模組3進行測試時，該第二分類模 組2 2係同步對已被該測試模組1測試之晶片模 組3進行分類動作。 藉由上述之結構、組成設計，茲就本創作 之使用作動情形說明如下，請同時配合參閱第 5 M439178The main test I of this creation I and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Practical and progressive. $|| Interlaced Eight The purpose of the above, this creation is a Rp I class member at least ~ member test structure, which is used to detect and classify the classifier clock F 1 C chip module classification test device, number The classification module f includes: at least one test module and a complex test module are picked up, and the test module tests each wafer module 'and the unit, = is generated after the test of each wafer module to generate a classification instruction classification chess f classification The module receives the classification instruction unit, and the classification is based on the classification instruction unit, and the classification module is divided into the first classification module and the second communication connection, the first classification module and the second The classification module is a module module!!轼 module, and the first classification module and the second classification level are for the 'knife to classify each chip module' by which, when the test mode is used, the first classification module The chip module is tested next to the classification module is synchronized to the tested module test group!! The mode level is classified, so one of the classification models tests the I7 chip module classification when the space is 'test mode The group is in the other type, the chip module in the classification module, The use of 3 卩 资 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 4 M439178 [Embodiment] 'To achieve the above purpose and effect, the technical means and structure used in this creation, the drawing is based on the preferred embodiment of the creation. The characteristics and functions are as follows. Please refer to the first figure, which is a three-dimensional combination diagram of the preferred embodiment of the present invention. It can be clearly seen from the figure that the structure of an RFIC interleaved classification test is used to detect and classify at least one RFIC. The test module 4 includes: a test module 1 and a plurality of classification modules 2, the test module 1 tests each of the wafer modules 3, and the test module 1 is to generate a classification command unit 1 1 after testing each of the wafer modules 3, wherein the classification modules 2 receive the classification instruction unit 11, and the classification modules 2 are based on the classification instruction unit 1 1 The chip module 3 is classified, and the classifying module 3 includes a first sorting module 2 1 and a second sorting module 2 2, * the first sorting module 2 1 and the second sorting module The group 2 2 is connected to the test module 1 , and the first classification module 2 1 and the second classification module 2 2 respectively classify each of the wafer modules 3 , whereby the test module 1 is targeted When the chip module 3 in the first classification module 21 is tested, the second classification mode The group 2 2 is synchronized to classify the wafer module 3 that has been tested by the test module 1. With the above structure and composition design, the following is the use of this creation. Please refer to the 5 M439178
. 二A圖、第二B圖及第二C圖所示，係為本創 ‘作較佳實施例之第一動作示意圖、第二動作示 . 意圖及第三動作示意圖，由圖中可清楚看出藉 由裝設測試速度相同於習用整合裝置R F I C * 之測試模組1，雖然其一次進行測試之數量不如 習用整合裝置，然而其成本遠低習用整合分類 裝置，當該測試模組1針對該第一分類模組2 1 内之晶片模組3進行測試時，該第二分類模組2 • 2係同步對已被該測試模組1測試之晶片模組3 進行分類動作，藉此使測試模組1係不間斷的 在第一分類模組2 1及第二分類模組2 2之間進 行切換交錯測試，且隨後第一分類模組2 1及第 二分類模組22係依據分類指令單元1 1進行分 類動作，並節省原本需等待之時間，進而提高 其測試晶片模組3之數量。 請同時配合參閱第三A圖、第三B圖、第 ® 三C圖及第三D圖所示，係為本創作再一較佳 實施例之第一動作示意圖、第二動作示意圖、 第三動作示意圖及第四動作示意圖，由圖中可 清楚看出，複數測試模組1 a係共同交替測試各 該晶片模組3a，除可有效節省測試之時間成本 外，更可在不需擴充軟體、和分類單元及複製 一低成本的R F I C之測試模組1 a之情形下， 達到更高效率之測試效果，以提升測試之晶片 模組3a數量，以降低整體成本。 6 M439178 • 惟，以上所述僅為本創作之較佳营γ & ^ 本創作之專利範圍，故舉凡 運用本創作說明書及圖式内容 及篝纷4士接傲β马之間易修飾 均應同理包含於本創作之專 矛J靶圍内，合予陳明。 f "ί括6:ΐ ?全部附圖所示，本創作使用時， 兴备用技術相較，签香六士 权者實存在下列優點： :、硬體成本遠低習用整合測試暨分類裝置。 一、=模組1係不間斷的在第-分類模組21 刀類模組22之間進行測試，並節省 f本需等待之時間，進而提高其測試晶片 模組3之數量。 三、測試模組1a係共同交替測試各該晶片 模、.且3a，除可有效節省測試之時間成本 外’更可在不需擴充軟體、和分類單元及 複製一低成本的1^ F I C之測試模組情形 ▲下，達至|!更高效率之測試效$，以提升測 试之晶片模組數量，以降低整體成本。 综上所述’本創作之R F ! c交錯式分類 目=之結構於使用時’為確實能達到其功效及 、，故本創作誠為—實用性優異 :合：型專利之申請要件，麦依法提出申請為 二審委早曰賜准本創作，以保障創作人之辛 :J: ’倘若鈞局審委有任何稽疑，請不吝 來函指示，創作人定當竭力配合，實感德便吝 7 M439178 立 之 例 施 實 佳 較 JW1 作 1 創 明本 說為。 單係圖 簡 式圖 圖一 [第· 合 第二A圖 係為本創作較佳實施例之第一動作 不意圖。 第二B圖 係為本創作較佳實施例之第二動作 示意圖。 第二C圖 係為本創作較佳實施例之第三動作 示意圖。 第三A圖 係為本創作再一較佳實施例之第一 動作示意圖。 第三B圖 係為本創作再一較佳實施例之第二 動作示意圖。 第三C圖 係為本創作再一較佳實施例之第三 動作示意圖。 第三D圖 係為本創作再一較佳實施例之第四 動作示意圖。 8 M439178 【主要元件符號說明】 測試模組 …1. la 分類指令單元 … 11 分類模組 … 2 第一分類模組 … 21 第二分類模組 … 22 晶片核組 …3.3a 分類測試裝置 … 4The second action diagram, the second B diagram, and the second C diagram are shown in the first embodiment of the preferred embodiment, the second action diagram, the intention and the third motion diagram, which are clear from the figure. It can be seen that by installing the test module 1 with the same test speed as the conventional integrated device RFIC*, although the number of tests performed at one time is not as good as that of the conventional integrated device, the cost is much lower than that of the conventional integrated classification device, when the test module 1 is targeted When the chip module 3 in the first classification module 2 1 is tested, the second classification module 2 • 2 synchronizes the wafer module 3 that has been tested by the test module 1 to perform a sorting operation. The test module 1 performs the switching interleaving test between the first classification module 2 1 and the second classification module 2 2 without interruption, and then the first classification module 2 1 and the second classification module 22 are classified according to the classification. The command unit 1 1 performs a sorting operation and saves the time required to wait, thereby increasing the number of test wafer modules 3 thereof. Please refer to the third A figure, the third B picture, the third C picture, and the third D picture, which are the first action schematic diagram, the second action diagram, and the third embodiment of the present preferred embodiment. The schematic diagram of the action and the fourth action diagram can be clearly seen from the figure. The plurality of test modules 1a alternately test each of the chip modules 3a, which can save the time cost of the test, and can be used without expanding the software. In the case of a classification unit and a test module 1a for replicating a low-cost RFIC, a more efficient test effect is achieved to increase the number of test wafer modules 3a to reduce the overall cost. 6 M439178 • However, the above is only the patent scope of the creation of this creation γ & ^, so the use of this creation manual and the content of the drawings and the 4 4 4 接 接 β β β It should be included in the special target of this creation, and it should be included in Chen Ming. f " 括6: ΐ ? All the drawings show that when this creation is used, compared with the spare technology, the holder of the six-rights has the following advantages: :, the hardware cost is much lower than the custom integration test and classification device . 1. The module 1 is continuously tested between the first classifying module 21 and the tooling module 22, and saves the time required for f, thereby increasing the number of test chip modules 3. Third, the test module 1a is a common test of each of the wafer modules, and 3a, in addition to effectively saving the time cost of the test, more than without the need to expand the software, and the classification unit and copy a low-cost 1^ FIC In the case of the test module ▲, the test efficiency of the higher efficiency is achieved to increase the number of wafer modules tested to reduce the overall cost. In summary, the 'RF of this creation! c-interlaced classification target = the structure in use' can really achieve its efficacy and, therefore, the creation is sincerely - practical and excellent: the combination of: the application requirements of the patent, Mai Applying in accordance with the law for the second-instance committee to grant this creation to protect the creator: J: 'If there is any doubt in the arbitral tribunal, please do not hesitate to give instructions, the creator will try his best to cooperate, and the real sense is 7 M439178 The example of Shi Shijia is better than JW1. Single Diagram Diagram Figure 1 [Part 2 and Figure A is the first action of the preferred embodiment of the creation. The second B diagram is a schematic diagram of the second action of the preferred embodiment of the present invention. The second C diagram is a schematic diagram of the third action of the preferred embodiment of the present invention. The third A diagram is a schematic diagram of the first action of a further preferred embodiment of the present invention. The third B diagram is a schematic diagram of the second action of a further preferred embodiment of the present invention. The third C diagram is a schematic diagram of the third operation of a further preferred embodiment of the creation. The third D diagram is a fourth schematic diagram of a further preferred embodiment of the present invention. 8 M439178 [Key component symbol description] Test module ...1. la classification command unit ... 11 classification module ... 2 first classification module ... 21 second classification module ... 22 chip core group ...3.3a classification test device ... 4