TWM438015U - High performance dual port SRAM - Google Patents

Description

M438015 V. New description: [New technical field] This creation is about a high-performance static random access memory (SRAM), especially an effective double-station static random access Access memory memory standby performance and effectively improve the static noise margin (SNM), and can reduce the leakage current and can solve the double-bit SRAM write with a single bit line. Logic 1 difficult double-click static random access memory. [Prior Art] Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into non-volatile (n〇nv〇latile) memory and volatile memory according to whether it can save data after the power is turned off, and the non-volatile memory is stored. The data does not disappear due to power off or interruption, and the data stored in volatile memory is removed as the power is turned off or interrupted. Common volatile memory devices include dynamic memory access memory (dram) and static random access memory (SRAM). Dynamic random access memory (dram) has the advantages of small area and low price, but it must be updated from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. The operation of the large-scale missing 1 anti-ground static state-of-sale access memory (SRAM) is relatively simple and does not require updating operations. Therefore, it has the advantages of high speed and low power consumption. μ eight SRAM is the mainstream. This is due to the fact that the SRAM has a small standby current and the machine time is extended as much as possible. At present, the semi-guided weaving system of the electronic scales of the action of the squaring rights is suitable for continuous talk time and continuous waiting.

A conventional static random access memory (SRAM) such as a u-memory array, the memory array is 5 M438015 plurality of rows of memory cells, and a plurality of columns of memory cells The memory cell and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WLi, WL2, etc.), each word line corresponding to a plurality of columns One column of the memory cell; and a bit line pairs (BL!, BLBi. "BLm, BLBm, etc.") each bit line pair corresponds to one of the plurality of rows of memory cells, And each bit line pair is composed of one bit line (BL1...BLm) and one complementary bit line (BLB^.BLBm). Figure lb shows 6T static random access memory ( Schematic diagram of the circuit of the SRAM), where the 'PMOS transistors (P1) and (P2) are called load transistors (i〇a (j transistor), NMOS bodies (Ml) and (M2) are called drives Driving transistor, NMOS transistor (M3) and 9 are called access transistors, WL is Word line, and BL and BLB are bit line and complementary bit line, respectively. Since the SRAM cell requires 6 transistors, and drives the transistor and accesses. The ratio of current drive capability between transistors (ie, cell ratio) is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price. The 6T static random access memory shown in Figure 1b The HSPICE transient state of the body cell during the write operation is the result of the simulation analysis, as shown in Fig. 2, which is simulated by the level 49 model and using TSMC 0.18 micro-meter CM〇S process parameters. One way of counting the number of transistors in a static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a 5T static random access cell with only a single bit line. The circuit diagram, compared with the 6 Τ static random access memory cell of Figure 1, the 5 Τ SRAM cell is one less than the 6 Τ SRAM cell and less — Strip line, but the 5" static random access memory cell The problem of writing logic 1 is quite difficult without changing the channel width to length ratio of the PMOS electric cell bodies P1 and 1*2 and the NMOS transistors Mb M2 and M3. Consider the case where node A on the left side of the memory cell originally stores logic 0. 'Because the charge of node A is only transmitted from the write bit line (WBL) alone, it is difficult to cover the previously written logic in node A because of M438015. Write as logic 1. Figure 5 shows the 5T SRAM cell, the HSPICE transient analysis simulation result during the write operation. As shown in Figure 4, it uses the 丨evel 49 model and uses TSMC 0.18 micron CMOS process parameters. Simulated by the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem in writing logic 1 which is quite difficult.

So far, there have been many techniques for a 5T static random access memory cell having a single bit line, for example, 'I. Carlson et al.,'' A high density, low leakage, 5T

j SRAM for embedded caches, M Solid-State Circuits Conference, 2004. ESSCIRC φ 2004. Proceeding of the 30th European, ρρ·215-218, 2004·) 5T SRAM due to the redesign of the second driving power in the unit cell The channel width-to-length ratio of the crystal, the two-loaded transistor, and an access transistor solves the problem of difficulty in writing logic 1, thereby causing damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus Affected by process variation; Non-Patent Document 2 (M. Wieckowski et al.,, A novel five-transistor (5T) SRAM cell for high performance cache, IEEE Conference on SOC, pp. 1001-1002, 2005.) The 5T SRAM is due to the fact that a long channel length access transistor is placed between the two load transistors in the unit cell to solve the problem of writing logic 1 and the lack of access speed is reduced; 3 (June 1986, No. TWM358390) The "Static SRAM" for "reducing the power supply voltage during write operation" can effectively solve the problem of writing logic 1, ... Operation time The lack of effective discharge path, there is a missing resulting in lower write speed and / or high-speed operation memory capacity. Next, we discuss the static random access memory (SRAM) and double-ended architecture. The 6T static random access memory (SRAM) cell in Figure lb is the static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same-to-bit line, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capability, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). Electric 7 M438015 path 'Where WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is write word line, RWL is read word line), Make the area of the memory cell greatly increase 'If we can simplify the structure of the memory cell, so that one bit line is responsible for the read action' and the other bit line is responsible for the write action, then design the double-tap static random When accessing the memory, the memory cell does not need to add two transistors and one Bit line, the memory cell area so that many will be reduced. The conventional double-twisted static random access memory cell does not use this method because the problem of writing logic 1 cannot be achieved as described above. A technique for reducing the standby current has been proposed so far, for example, "Double-band Static Random Access Memory with Discharge Path" proposed in Patent Document 4 (No. TW M393773, December 1999), Patent Document 5 ( "Static random access memory" proposed by TWI307890, March 21, 1998, "Static random access memory (SRAM) with clamped" proposed in Patent Document 6 (US Pat. No. 7,382,674 B2, June 3, 1997) "source potential in standby mode", "Static random access memory device and method of reducing standby": Patent Document 7 (Japanese Patent No. US7254〇85 B2) "811^ employing virtual rail scheme stable against various process-voltage-temperature variations", September 19, 1995; No. 8711031782, Non-Patent Document 9 (Tae-Hyoung Kim et al., A Voltage Scalable 0.26) V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode^, IEEE Journal of Solid-State Circuits., Vol. 64, pp 1785 - 1795, 2009.) ^iij^:8TSRAMaA#^-^JXl^l〇 (Ding-Ming Kwai, M Odeling of SRAM Standby Current by Three-Parameter Lognormal

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Workshop on Memory Technology, pp 77 - 82, Aug. 31 2009-Sept. 2 2009.) The proposed SRAM 'The patent documents or non-patent documents are used in standby mode by all memory cells. The source voltage of the driving transistor (ie, the NMOS transistors M1 and M2 of the first graph) is raised from the original ground voltage to a predetermined voltage higher than the ground voltage, and 8 M438015 is sought to reduce the standby operation. However, since the predetermined voltage is generated only by charging the parasitic electric material by the leakage current of the transistor, the static random access memory enters the standby mode at a very slow speed, and thus the lack of standby performance is reduced: That is, the patent documents or non-patent documents lack a standby start circuit to cause the static random access memory to quickly enter the standby mode. In view of this, the main purpose of this creation is to propose a high-performance dual-static static random access memory that can effectively cause the static random access memory to enter the standby mode quickly, and thus effectively improve the static random memory. Take the memory standby performance. φ The second objective of this creation is to propose a high-performance dual-static static random access memory that can effectively improve the static noise margin (SNM) of double-static static random access memory. A further object of the present invention is to provide a high-performance dual-static static random access memory capable of effectively avoiding the existence of a double-埠 static random access memory cell with a single bit line by a control circuit. Writing logic 1 is quite a difficult problem. [New content] This creation proposes a high-performance dual-static static random access memory, which mainly includes a 5 memory array, a plurality of control circuits (2) and a standby start circuit (3), the memory Array • The column consists of a complex column of memory cells and a plurality of rows of memory cells, each column of memory cells - a control circuit is provided, and each memory cell (1) includes a first inversion a second inverter (composed of a second PMOS transistor P2 and a second NMOS transistor M2) An access transistor (consisting of a third NMOS transistor M3), a first and second read transistor (M4 and M5)' - a third inverter (controlled by a first PMOS transistor) Pci is composed of a first NMOS control transistor MCI and a fourth inverter (composed of a second PM 〇s control transistor (PC2) and a second NMOS control transistor (MC2)). Each control unit is connected to a source of the first NMOS transistor (M1) and a source of the second NMOS transistor (M2) of each memory cell of the corresponding column memory cell, so as to cope with Different 9 M438015 operating modes control the source voltage of the first-nm 〇s transistor (M1) and the secret voltage of the second transistor (M2), thereby effectively preventing writing difficulties when writing a human mode The problem is that the leakage current can be effectively reduced in the standby mode, while the original electrical characteristics can be maintained in other modes. Furthermore, a back gate of the first NM〇s transistor (M1) in each memory cell is connected to an output of the third inverter, and the second NM is The back gate of the s transistor (M2) and the back gate of the third nmos transistor (M3) are both connected to the output terminal of the fourth inverter to effectively improve the double-turn static random access memory. Static Noise Margin (SNM). In addition, by the design of the standby starting circuit (3), the static random access memory can be effectively pushed into the standby mode quickly, and thus the standby performance of the static random access memory is greatly improved. [Embodiment] According to the above main object, the present invention proposes a high-performance dual-static static random access memory, which mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows. The memory cell is composed of a memory cell and each row of memory cells including a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); and a standby start circuit (3), the standby start circuit (3) • prompts the static random access memory to enter the standby mode quickly, so as to effectively improve the standby performance of the dual-static static random access memory. * For the sake of explanation, the high-performance dual-static SRAM shown in Figure 6 is written with only one memory cell (1), one write word line (WWL), and one write. A bit line (WBL), a control circuit (2), and a standby start circuit (3) are described as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor pi and a first NMOS transistor M1) and a second inverter (by a second PMOS device) The crystal P2 is composed of a second NMOS transistor M2, a third inverter (composed of a first M438015 mos control transistor ρα and a first surface os control transistor), and a fourth inversion (by - second PMOS (four) transistor? (: 2 and _ second 〇 s_ transistor MC2) ... third NMOS transistor (M3), a first read transistor (M4) and - The first access transistor (M5), wherein the first inverter and the second inverter are in an alternating coupling connection, that is, the output of the first inverter (ie, node A) is connected to the The input of the second inverter, and the output of the second inverter (ie, the node phantom is connected to the input of the first inverter), and the input of the first-inverter (node A) is used Store the data of the SRA]V^ cell and the second inversion S (ϋB) is used to store the inverted data of the SRAM cell. The second read transistor (M5) is the secret Extremely divergent Connected to a ground voltage, an output of the second inverter (node B) and a source of the first read transistor (M4); a source and a gate of the first read transistor (M4) The pole and the immersion are respectively connected to the sum of the second read transistor (M5), the read word line (RWL) and the read bit line (RBL). Please refer to 帛6 again. Ffl 'The third counter (four) wheel is connected to the output of the inverter (node A), and forms a second control node (B2) at the output of the third inverter, and the fourth inverter The input is connected to the output of the second inverter (node B), and forms a first control node (B1) at the output of the fourth inverter; the third nmos transistor (M3) is coupled to φ Connected between the node (A) and the write bit line (WBL), and the back gate is connected to the first control node (B1), and the gate is connected to the write word Yuan line (WWL). It is worth noting here that the output of the third inverter (ie, the second control node B2) is connected to the back gate of the first NMOS transistor (M1), and the fourth Inverter output (ie first The control node B1) is connected to the back gate of the second NMOS transistor (M2) in addition to the back gate of the third NMOS transistor (M3). Please refer to FIG. 6 for the control circuit (2). ) is a fourth NM〇s transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), and an eighth NMOS device. Crystal (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a tenth 11 M438015 two NMOS transistor (M29), one a third PMOS transistor (P21), a fourth pM〇s transistor (P22), a fifth inverter (121), a first delay circuit (di), and a write control signal (CTL) . The source of the fourth NMOS transistor (M21) is connected to the drain of the seventh NMOS transistor (M24), and the gate is connected to the drain and connected to a first low voltage node (VL1); The source, the gate and the drain of the fifth NMOS transistor (M22) are respectively connected to a ground voltage, an inverted standby mode control signal (/s) and a second; a low voltage node (%2); a source, a gate and a gate of the sixth NMOS transistor (M23) are respectively connected to the second low voltage node (VL2), a standby mode control signal (s) and the φ first low voltage node (VL1) The source of the seventh NMOS transistor (M24) is connected to the ground voltage, and the gate is connected to the drain and connected to the source of the fourth transistor (from ^); the eighth NMOS transistor a source, a gate and a drain of (M25) are respectively connected to the first low voltage node (VL1), the reverse standby mode control signal (/s) and the ninth 〇8 transistor (M26) a drain; the source of the ninth NMOS transistor (M26) is connected to a ground voltage ' and the gate is connected to the drain and connected to the eighth NMOS transistor (^ 5) a drain; a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to a ground voltage, a drain of the eleventh NMOS transistor (M28), and the ninth NMOS a gate of a crystal φ (M26); a source, a gate and a drain of the eleventh NMOS transistor (M28) are respectively connected to the drain of the twelfth NMOS transistor (M29), the write control a signal (CTL) and a gate of the tenth NMOS transistor (M27), a drain of the third pM〇s transistor (p21), and a drain of the fourth PMOS transistor (P22); the twelfth The source, the gate and the drain of the nmos transistor (M29) are respectively connected to a ground voltage, an output end of the fifth inverter (K1) and a source of the tenth-deleted transistor (Μ28); The input of the fifth anti-suppression (121) is connected to the output of the first delay circuit (D1), and the output of the fifth inverter (121) is connected to the gate of the tenth-NMOS transistor (M29) The input of the first delay circuit (D1) is connected to the write control signal (CTL) and the gate of the third PMOS transistor (P21) and the gate of the eleventh NMOS transistor (M28); The third pM s The source of the transistor (p21) 12 M438015 The pole, the gate and the drain are respectively connected to a power supply voltage (vDD), the write control signal (CTL), and the fourth PMOS transistor (P22). a pole and a tenth electrode of the tenth transistor (M28); a source, a gate and a gate of the fourth PMOS transistor (P22) are respectively connected to the power supply voltage (VDD), the fifth inversion The output of the device (Ι2ι) is the drain of the third PMOS transistor (P21) and the drain of the eleventh nmos transistor (M28). It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal -(S) via an inverter. The control circuit (2) is designed to control the voltage level of the first low voltage node point (1) and the second low voltage node (VL2) according to different operation modes, in the write mode , the source voltage of the driving transistor (ie, the first transistor M1) that is closer to the write bit line (WBL) in the selected unit cell (ie, the first low voltage node %1:) is in an initial period ( The initial period is set to be higher than the ground voltage by one of the first delay time provided by the first delay circuit (D1) and the sum of the falling delay times provided by the fifth inverter (121). a pre-voltage (ie, the gate-source voltage vGS (M26) of the ninth NMOS transistor (M26)), and another driving transistor in the selected cell (ie, the first NM〇s transistor M2) The source voltage (ie, the second low voltage node VL2) is set to a ground voltage to prevent difficulty in writing logic, and in the standby mode, the source voltage of the driving transistor in all memory cells is set to The grounding voltage is one of the second predetermined voltages (ie, the criticality of the fourth NMOS transistor (M21) The voltage V· and the sum of the threshold voltages v_ of the seventh nm 〇S transistor (M24), '+VTM24)' to reduce the leakage current; and in other modes, the driving transistor in the memory cell The source voltage of ' is set to ground voltage to maintain read stability. The detailed operating voltage level is shown in Table 1. 13

The write control signal (CTL) in Table 1 can also be simply a write word line (WWL), and can be a Write Enable (referred to as a fine) signal and a corresponding writer. Word line) The result of the AND gate operation of the signal, at which time the write control signal is only written when the write enable (WE) « number and the corresponding word line (milk) signal are both logic high. (CTL) is logically high. Please refer to FIG. 6 again. The standby start circuit (3) is composed of a fifth pM〇s transistor (p31), a sixth PMOS transistor (P32), a sixth inverter (1) 3), and a second delay. The circuit (D2) is composed of. a source, a gate and a drain of the fifth PM〇s transistor (p31) are respectively connected to the power supply voltage (vDD), the inverted standby mode control signal (/s) and the sixth PMOS transistor a source of (P32); a source, a gate and a drain of the sixth PMOS transistor (p32) are respectively connected to a drain of the fifth PMOS transistor (P31), and the sixth inverter (133) And an output of the sixth low voltage node (VL1); an input of the sixth inverter (133) is coupled to an output of the second delay circuit (〇2), and the sixth inverter (133) The output is connected to the gate of the sixth PMOS transistor (P32); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the second delay circuit (D2) The output is coupled to the input of the sixth inverter (133). The working principle of the preferred embodiment of the present invention is as follows. The main purpose of the third inverter and the fourth inverter is to increase the memory cell. Static noise margin, for the sake of brevity, the description of the third inverter and the fourth inverter will be omitted here): (I) write mode (writemode) before the write operation starts, the write The control signal (c-hole) is at a logic low level such that the first MOS transistor is turned on (〇N), and the tenth-moving s-transistor (Gu) is turned off (Yangyang, so node C is logic high) The logic crest node c turns on the tenth NMOS transistor (M27)' and causes the low voltage node (vli) to be grounded. During the initial period of the write operation (the initial period is the first The sum of the delay-delay time provided by the delay circuit (di) and the delay delay time provided by the m(5) is 'the write control signal (CTL) is a logic high level, and the write inversion delay The control signal (/CTL) is still at a logic high level, making the third pM〇s transistor The cut-off of the NMQS transistor (should) is turned on, since the write-inversion thief control signal (/CTL) is still at a logic high level in the initial lying position, thus making the twelfth 电 电 transistor (M29) Turning on. The fourth PMOS transistor (P22) is turned off and causes node c to be a logic low level, and the logic low level node C turns off the trait NM 〇S transistor (10) 7) and causes the low voltage node (VL1) ) is equal to the gate voltage VGS (M26) of the ninth job transistor (M26), thereby effectively preventing the problem of writing logic 1 difficult. Finally, after the initial period of the write operation, since the write control signal (CTL) is at a logic high level and the write inverted delay control signal (/CXL) is at a logic low level, the second PMOS is The crystal (P21) is turned off, the first NMOS transistor (M28) is turned on, the twelfth NMOS transistor (M29) is turned off, the fourth PMOS transistor (P22) is turned on, and the node C is at a logic high level. The logic high level node c turns on the tenth NMOS transistor (M27)' and causes the low voltage node (^丨) to be grounded. Next, how the preferred embodiment of the present embodiment of the present invention performs the write operation according to the four write states of the SRAM SRAM. (1) The node Α originally stores the logic 〇, but now wants to write the logic 〇:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NM 〇 S M438015 transistor (M1) is turned on (0N). Since the first Lancome 8 transistor (5) u is (10), the write word line (WWL) is turned from L〇w (ground voltage) to High (electrical voltage VDD) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third _8 transistor (M3) is turned off (OFF) Turning to ON (ON), at this time, because the write bit line (wbl) is the ground voltage, the node A is discharged, and the logic (4) write action is completed until the end of the write cycle. (2) Node A originally stores the logic 〇, but now wants to write logic j: Before the write operation occurs (the write word line ~^ is the ground voltage), the first NM〇s transistor (Ml ) is on (on). Since the first wake-up 8 transistor (M1) is (10), when the write operation starts, the word line d) is twisted by L〇w (ground voltage) (the power supply voltage VDD), the node The voltage of A rises following the voltage of the write word line (WWL). When the voltage of the write word line (WWL) is greater than the threshold voltage of the third nm 〇s transistor (milk), the third NMOS transistor (M3) is turned from off (OFF) to on (on) At this time, since the write bit line (WBL) is High (the power supply voltage Vdd), and φ because the first NM〇S transistor (M1) is still ON and the node B is still at the voltage level In order to connect to the initial state of the voltage level of the power supply voltage (Vdd), the first pm S transistor P1 is still OFF (OFF) and the node A is fast toward a divided voltage level. Charging, the divided voltage level is equal to (Rj^+R^) / (Rm3+Rmi + Rm25+Rm26) multiplied by the power supply voltage (VDD), wherein the RMS represents the XNM〇s transistor (M3) The on-resistance equivalent resistance, the RM1 represents the on-resistance equivalent resistance of the first NMOS transistor (M1), and the table represents the on-resistance equivalent resistance of the eighth NMOS transistor (M25), and the ninth transistor is represented (M26) is the equivalent resistance, because the third nmos transistor (m3) is still operating in the saturation region and the first NMOS transistor (Ml) is still working. In the triode region, although the conduction equivalent M438015 resistance (Rk〇) of the third NMOS transistor (M3) is much larger than the on-resistance equivalent (Rmi) of the first nmos transistor (M1), However, since the ninth NMOS transistor (M26) is diode-connected, a source voltage equal to the source voltage of the ninth nm 电s transistor can be provided at the first low voltage node (VL1). The voltage level of VGs_, the result of the voltage division value presented by node A, the voltage value will be more than the voltage of the node A of the conventional 5T·'random memory cell of FIG. ; a lot of. The higher (4) voltage level is sufficient for the second sinker transistor (10) to conduct: then 'so that node B is discharged to a lower voltage level, the lower voltage level of the node B will cause The on-resistance equivalent (Rmi) of the first NMOS transistor (M1) exhibits a higher resistance Lu value. The higher resistance value of the first NMOS transistor (M1) will obtain a higher voltage at the node a. Level, the higher voltage level of the node A is again caused by a second inverter (composed of the second PMOS transistor P2 and the second NM〇S transistor M2), so that the node b is lower The voltage level, the lower voltage level of the node B is again passed through a first inverter (composed of the first PMOS transistor P1 and the first nm 晶体S, the crystal M1), so that the node a obtains more At the high voltage level, according to this cycle, the node A can be charged to the power supply voltage (VDD)' to complete the logic 1 write operation. It is worth noting here that 'the first low voltage node W is only between the initial period of the write logic i, and has a voltage equal to the gate source voltage VGS (M26) of the λ ΝΜΟ δ transistor. Level. (2) Node A originally stores the logic 丨, but now wants to write logic 1: Before the write operation occurs (the write word line WWL is grounded), the first pM〇s transistor (pi) To be on (0N). When the word line (WL) is from L〇w (grounded electric illusion to High (the electric hybrid lining M Vdd), and the financial line (muscle) (four) pressure is greater than the critical voltage of the three-sided transistor (M3), The third transistor (M3) is turned off (〇 is turned on (ON); at this time, because the write bit line (WBL) is qing (the power supply is VDD) 'and g is the The first -pM〇s transistor (ρι) is still 〇N, so the power of the node A will be maintained at the voltage level of the power supply voltage (Vdd) until the write cycle is 17 M438015 beam. It is worth noting here. The 'the first low voltage node' has a voltage level equal to the threshold voltage of the fourth (10) transistor (M21) after writing the logic. (4) Node A originally stores the logic! Write logic 〇: Before the write operation occurs (the write word line WWL is grounded, the first pM〇s transistor (P1) is turned on (〇N). When the write word is used The line is turned from (grounded ink) to High (the power supply voltage Vdd), and the electric* ink of the write word line (wwl) is greater than the threshold voltage of the first pass 8 transistor (M3) The third NM〇s transistor: is turned from off (〇FF) to turned on (ON), because the write bit line ([) _ is Low (ground voltage), the node a will be And the first low voltage node () discharges to complete the logic 0 write operation until the end of the write cycle. It is worth noting that the first low-voltage node (VU) is after writing the logic The level of the ground voltage is the same. The preferred embodiment of the present invention is not shown in Fig. 6. The transient analysis of the service is performed during the writing operation, as shown in Fig. 7, which is based on the ievel 49 model and uses tsmc (four) micron. (10)^ The process parameters are added to the _ gambling effect. The high-performance dual-static SRAM proposed by this creation can improve the first low-voltage node by writing logic! The voltage level is effective to avoid the problem that it is difficult to write the logic 1 in the double-transition random access memory cell with a single-bit line. . . . (> (11) Standby mode At this time, the standby mode control signal (8) is a logic high level, and the inverted standby mode control (4) (6) is The inverted standby mode control signal (6) of the logic low level can make the fifth touch s transistor (help) of the (4) circuit (2) and the eighth circumference s electric = ^25) cut off (OFF) ), and the logical high scale scales the control number (8) ^ secret six NMOS transistor (office) conduction _, at this time the sixth surface electricity L (which round) use, shame can be turned on First, the NMOS electrical body (10) 3) 'so that the voltage level of the first low power node ^ is equal to the gift of the wire two-display point (VL2), and the electrical contacts are equal to M438015 The sum of the threshold voltage of the fourth NMOS transistor (bribe) and the threshold voltage (Vtm24) of the seventh NMOS transistor (Μ24), that is, the voltage level of the v_+v plane. Next, how to reduce the leakage current when creating a standby mode (standbym〇de), please refer to Section 6 ® '6th _There are various leakages generated when the thief is selected as the thief type. !, 12, 13, and 14, which assume SRAM cells

The output of the first-inverter (ie, node A) is logic Lqw (it is worth noting here that the voltage of the second low voltage secret (heart) is held in the thin 〇s The voltage level of the sum of the threshold voltages (Vtm2i + _) of the transistor (M21) and the seventh (10) transistor (M24), so that the voltage level of the node A is the logic Lgw is also maintained at the voltage level of the V诵_ The output of the second inverter (ie, node B) is a logic-torque supply voltage VDD). Please refer to the previous technique in Figure 5 and the creation of the figure in Figure 6. The comparison between the static random state memory and the leakage motor proposed in Figure 5 is the first thing about the flow. The leakage current l ' of the third NM〇S transistor (M3): the voltage level of the node A is maintained at the potential level of the ν· + drain when the mode is created in the standby mode, and it is assumed that the xiao character is written. The line (penetration) is set to the grounding voltage when it is in the face-to-face mode. Therefore, the third transistor (5) of the present invention has a negative source voltage % of negative value, and the fifth mode of the art is 〇s transistor. M3) _ source voltage I ▲; Gate Induced Drain Leakage, GIDL) The age of the 3rd (4) and 3 (8) figures of the _5119 patent on March 8th is for the NMOS transistor. In other words, when the gate source voltage is _〇ι volt, the sub-critical current induces 1% of the sub-critical current when the voltage is G volts. Therefore, the second voltage is caused by the GIDL effect. The leakage current 11 of the (10) transistor (M3) is much smaller than that of the fifth body d (M3); and the 'source of the third ship (10) is the source of the electron. VDS pressure power supply voltage v for the voltage level of anti von m zygomatic in her nervous V_ + V_ of

Thunder (four) w cut wire 5 ® 叮 static random access memory NMOS day and day no source group ds is equal to the power supply voltage Vdd, according to the immersion trigger energy 19 M438015 barrier down (Drain-Induced Barrier Lowering, referred to as The DIBL) effect, the leakage current 1丨 of the third NMOS transistor (M3) flowing through the creation caused by the DIBL effect is also smaller than that of the prior art NMOS transistor (M3) of FIG. 5; The leakage current I 该 of the third NMOS transistor (M3) is much smaller than that of the prior art NMOS transistor (M3) of FIG. Next, regarding the leakage current 12 flowing through the first PMOS transistor (P1), the source of the first pM〇S transistor (P1) is the power supply voltage (Vdd) due to the standby mode; The drain of a PMOS transistor (P1) is maintained at the voltage level of the Vtm21+Vtm24, φ. Therefore, the source drain voltage VSD of the first PMOS transistor (P1) is the power supply voltage (VDD). Deducting the voltage level of the Vti^+Vt^4, in contrast to the standby mode, the source drain voltage vSD of the PMOS transistor (P1) of the prior art is equal to the power supply voltage (VDD) 'according to DIBL Effect, so the leakage current 2 flowing through the first PMOS transistor (Pi) will be smaller than that of the PMOS transistor (P1) of the prior art of FIG. 5; finally, regarding the flow through the second NMOS transistor (M2) Leakage current I3, since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the Vtm2i + Vtm24 in the standby mode, the voltage level of the node A is also maintained at the voltage level of the VTivm + VTNm. And the voltage level of the node B is equal to the φ power supply voltage (Vdd) and the second NMOS transistor (M2) The bottom is the ground voltage, so the base-source voltage VBS of the second NMOS transistor (M2) of the present invention is a negative value, and the source voltage VDS of the second NMOS transistor (M2) is the power supply voltage. (Vdd) deducting the voltage level of the Vtm2i + Vtm24'. In the standby mode, the base-source voltage VBS of the NMOS transistor (M2) of the prior art of FIG. 5 is equal to 0, and the source of the NMOS transistor (M2) The pole voltage VDS is equal to the power supply voltage (VDD). According to the body effect and the DIBL effect, the leakage current 13 flowing through the second NMOS transistor (M2) of the present invention is much smaller than that of the prior art of FIG. Transistor (M2). Finally, regarding the leakage current L» flowing through the first read transistor (M4), the reading mode of the dual-bit static random access memory and the conventional 8T dual-static static random access memory of the present invention is 20 The M4J8015 is different and the read bit line (RBL) in the standby mode of the dual-static SRAM can be set to the ground voltage, while the conventional double-static static random access memory is used to prevent the node B. The voltage level drops, and the read bit line (RBL) in the standby mode is set to the power supply voltage (VDD), so there is no comparison of the leakage current flowing through the first read transistor (M4) Ϊ4°. The above analysis shows that the dual-static SRAM proposed by the present invention can effectively reduce leakage current in the standby mode. The comparison between the preferred embodiment of the present invention shown in FIG. 6 and the leakage current of the conventional FIG. 5 FIG. 8 static random access memory in the standby mode (ie, the sum of &, 12 and 13) is as shown in Table 2, It is simulated by level 49 model and using TSMC 0.18 micron CMOS process parameters. It can be seen from Table 2 that the process TT, SS and FF, the two-dimensional static random access memory proposed in this paper and the traditional 6T static random access The memory reduces leakage current by 90.7%, 31.5%, and 87.3%, respectively. Table 2 Leakage current comparison process and temperature Conventional 8T SRAM (PA) SRAM (pA) reduction percentage (%) of the present invention TT 22.2203 2.0576 90.7 SS 1.6191 1.1091 31.5 FF 309.2402 39.3803 _ · - 87.3 (III) Read mode (Readmode) According to the two kinds of stored data states of the double-static SRAM cell, how the Shuangqi static random access memory of FIG. 6 completes the reading operation. (1) Node A stores logic 前 before the read operation occurs (the read word line RWL is a ground voltage), and the second NMOS transistor (M2) is turned off (OFF), the second PMOS transistor (p2) is ON (ON), and Node B is High (power supply voltage VDD). When the read operation starts, the read word line (RWL) is changed from Low (ground voltage) to High (power supply voltage Vdd), and when the read word line (RWL) voltage is greater than the first When the threshold voltage of the transistor is read, the first read transistor (M4) is turned from off (OFF) to on (〇N), 21 M438015 at this time, since the node B is High (power supply voltage Vdd), The second read transistor (M5) is turned on (ON), and therefore, the read bit line (RBL), the first read transistor (M4), and the second read power A current path is formed between the crystal and the ground, and the current path reduces the voltage level of the read bit line (RBL), thereby sensing the data stored in the node A and completing the logic 0. Read action. (2) Node A stores logic 1 Before the read operation occurs, (the read word line RWL is the ground voltage), the second NMOS transistor (M2) is turned on (〇N), and the second PMOS transistor (P2) is cutoff (〇FF) and node B is Low (ground voltage). When the read operation starts, the read word line RWL is converted from a Low (ground voltage) to a twist block (power supply voltage Vdd), and when the voltage of the read word line (RWL) is greater than the first When the threshold voltage of the transistor (M4) is read, the first read transistor (M4) is turned from off (OFF) to on (ON), and since the node B is Low (ground voltage), the first The second read transistor (M5) is off, and therefore, is not in the read bit line (RBL), the first read transistor (M4), and the second read transistor (M5) And forming a current path between the grounds, and as a result, the voltage level of the read bit line (rbl) can be smoothly maintained in the High (power supply voltage VDD) state, thereby sensing the node A storage logic 1 The data, and complete the logic 1 read action. Then, 'how the standby start circuit (3) in Fig. 6 causes the SRAM to quickly enter the standby mode' to effectively improve the standby performance of the SRAM: (1) before entering the standby mode. The inverted standby mode control signal (/S) is a logic distortion, and the logic high inverted standby mode control signal (/S) causes the fifth PM 〇s transistor (p31) to be turned off (OFF), and makes the sixth The PM0S transistor (P32) is turned on (〇N); (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the logic Low is in the standby mode control signal (/S) Making the fifth pM〇s transistor (p31) conductive (ON)' only during the initial period of the standby mode (the initial period is one of the second delay times provided by the second delay circuit (D2) and the The sixth PMOS transistor (P32) is still turned ON (the sum of the rising delay times provided by the sixth inverter (B3)), so that the first low voltage node (VL1) can quickly reach the fourth NMOS The threshold voltage of the transistor (M21) (Vtm21) 22 M438015 and the seventh NM The sum of the critical light (vLi) of the OS transistor (M24), that is, the voltage level of 乂 fine + Vt^4, that is, the static random access memory can quickly enter the standby mode.曰The most inversion of the second inverter and the fourth inverter in Figure 6 how to add memory: the static noise margin of the cell, please refer to Figure 6, the third inverter The output (ie, the second control node B2) is coupled to the fth of the -nmos transistor (M1), and the output of the fourth inverter (ie, the first control node B1) is coupled to the third transistor (10). The gate of the f is also connected to the back gate of the second NM〇s transistor (M2). It is worth noting here that the third inverter and the fourth inverter are both connected between the secondary power supply voltage (Vddl) and the ground voltage, and the voltage of the power supply county voltage (VDDL) is touched. The scale size is set to be less than the cutinvohage of the parasitic diode between the back gate and the source of the first NMOS transistor (M1) and the back of the second nm〇s transistor (M2) Limiting the smaller of the cutoff voltage of the parasitic diode between the closed pole and the source, and defining the first PMOS control transistor (PC1) and the second pM〇s for the paste to achieve the setting The threshold voltage of the transistor (pc2) is smaller than the voltage level of the power supply voltage (Vddl). How to increase the static noise margin when the monthly static random access memory is in the hold state (h〇ld State) (1) Assuming that the output of the first-inverter in the SRAM cell (ie node A) is logic Low, the first control node (B1) is the logic l〇w of the ground voltage, and the second control node ( B2) is the logic level of the voltage level of the secondary power supply voltage (Vddl), according to the ontology effect 'The second control node (B2) of the logic High will reduce the critical electric house of the first electro-ceramic climbing body (M1), and the lower threshold voltage can increase the node a to logic [(10) - static noise margin (1) Assuming that the output of the first inverter in the SRAM cell (ie node A) is a logical torsion sand' then the first control node 'point (B1) is the voltage level of the secondary power supply voltage (Vddl) Logic High, and the second control node (B2) is the logic L 〇 w of the ground voltage, according to the ontology effect 'the logic _ control node (B1) will reduce the second ship (10) transistor (M2) The threshold voltage, the lower threshold voltage can increase the static noise margin of node a. Then, by observing the back gate of the third transistor 3 (M3), the static random access memory is explained. How to increase the static noise margin when the body is in the write operation: (1) Assuming that the output of the first-inverter in the pre-SRAM cell (ie, node A) is logic_, then the first 23 M438015 control node ( B1) is the logic High of the voltage level of the secondary power supply voltage (VDDL), according to the ontology effect Therefore, the threshold voltage of the third NM〇S transistor (M3) at this time is smaller than the threshold voltage of the NMOS transistor (M3) of the prior art of FIG. 5, and the lower threshold voltage helps to increase the writing by the logic 1. Entering the static noise margin of logic 0; (2) assuming that the output of the first inverter (ie, node A) in the pre-SRAM cell is logic Low, the first control node (B1) is the ground voltage Logic Low, at this time, the back NMOS voltage of the third NMOS transistor (M3) is the same: in the 5th prior art, the back-electrode voltage of the 电8 transistor (M3), which will have the third The same static noise margin as the previous technique. • The present invention has been specifically described and described in its preferred embodiments, and it is obvious to those skilled in the art that any form or detail may be modified without departing from the spirit of the present invention. Therefore, all changes in the relevant technical specifications are included in the scope of the patent application of this creation. 24 M438015 [Simple description of the drawing] The first drawing shows the conventional static random access memory; the lb is a schematic circuit diagram showing the conventional 6T static random access memory unit cell; the second figure shows the conventional 6T Schematic diagram of the write operation of the SRAM cell; Figure 3 shows the circuit diagram of the conventional 5T SRAM cell; Figure 4 shows the conventional 5T SRAM Schematic diagram of the write operation of the cell; Fig. 5 is a schematic diagram showing the circuit of the conventional 8-inch dual-static SRAM cell; Figure 6 is a schematic diagram showing the circuit proposed in the preferred embodiment of the present invention; 7 is a timing chart showing the write operation of the preferred embodiment of the present invention. [Description of main component symbols] Ρ1 First PMOS transistor M1 First NMOS transistor M3 Third NMOS transistor WBL Write bit line B Inverting storage node S Standby mode control signal VL1 First low voltage node M21 Fourth NMOS transistor M23 sixth NMOS transistor M25 eighth NMOS transistor P2 second PMOS transistor M2 second NMOS transistor WWL write word line A storage node V〇d power supply voltage / S inverting standby mode control Signal VL2 second low voltage node M22 fifth NMOS transistor M24 seventh NMOS transistor M26 ninth NMOS transistor 25 M438015

M27 Tenth NMOS transistor M28 Eleventh NMOS transistor M29 Twelfth NMOS transistor P21 Third PMOS transistor P22 Fourth PMOS transistor 1 SRAM cell 2 Control circuit 3 Standby startup circuit Ιι Leakage current h Leakage current I3 Leakage current I4 Leakage current M4 First read transistor M5 Second read transistor BLB Complementary bit line BLrBLm Bit line WL]· WLn word line CTL Write control signal / CTL Write inversion delay control Signal V〇dl Low power supply voltage D1 First delay circuit D2 Second delay circuit 121 Fifth inverter 133 Sixth inverter P31 Fifth PMOS transistor P32 Sixth PMOS transistor MCI First NMOS control transistor MC2 Second NMOS control transistor PCI first PMOS control transistor PC2 second PMOS control transistor c node GND ground BLBj BLB, complementary bit line B1 first control node B2 second control node MBfMBk memory block 26

Claims (1)

M438015 VI. Scope of Application: 1. A high-performance double-static static random access memory, comprising: - a memory array, which is composed of a plurality of memory cells and a plurality of memory cells. Composition, each column of memory cells and each row of memory cells contain a complex number = body cell (1); u a plurality of control cells (2), each column of memory cells set a control circuit (2) a standby start circuit (3) 'The standby start circuit (3) prompts the SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the SRAM, where 'Every A memory cell (1) further comprises: an inverter consisting of a first PMOS transistor (P1) and a first NMOS transistor (M1) connected to the first inverter A power supply voltage (Vdd) is connected between a first low voltage node (VL1); a second inverter ' is connected by a second PMOS transistor (P2) and a second NMOS transistor (M2) Composition 'the second inverter is connected to the power supply voltage (Vdd) and a second low Between the voltage nodes (VL2); a storage node (A) formed by the output of the first inverter; an inverting storage node (B) connected by the output of the second inverter Forming a third NMOS transistor (M3) connected between the storage node (A) and a corresponding one of the write bit lines (WBL), and the gate is connected to the corresponding one of the write characters a wire (WWL); a first access transistor (M4), the source, the gate and the drain of the first read transistor (M4) are respectively connected to the second read power a drain of the crystal (M5), a read word line (RWL) and a read bit line (RBL); and the second read transistor (M5), the second read power The source, the gate and the drain of the crystal (M5) are respectively connected to a ground voltage, an output of the second inverter (node B) and a source of the second read transistor (M5); The three inverters are composed of a first PMOS control transistor (PC1) and a first NMOS control 27 M438015 transistor (MCI) connected to the primary power supply voltage (VDDL) and Between the ground voltages, and the input end of the third inverter is connected to the storage node (A); a fourth inverter is controlled by a second PMOS control transistor (PC2) and a second NMOS a transistor (MC2) connected between the secondary power supply voltage (VDDL) and a ground voltage, and an input end of the fourth inverter is connected to the inverting storage node ( B); a first control node (B1) formed by the output of the fourth inverter, and connected to the back gate of the second NMOS transistor (M2) and the third a back gate of the NMOS transistor (M3); a second control node (B2) formed by the output of the third inverter and connected to the back gate of the first NMOS transistor (M1) Wherein the first inverter and the second inverter are in an alternately coupled connection, that is, the output of the first inverter (ie, storage node A) is connected to the input of the second inverter And the output of the second inverter (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit 2) further comprising: a fourth NMOS transistor (M21), a fifth NM 〇S transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a first NMOS transistor (M28), a twelfth NMOS transistor (M29), a a third PMOS transistor (P21), a fourth pM0S transistor (P22), a fifth inverter (121), a first delay circuit (D1), and a write control signal (CTL); The source of the fourth NMOS transistor (M21) is connected to the bottom of the seventh transistor 8 (M24), and the gate is connected to the impurity and connected to the first low ink node. (VL1); the fifth NMOSf: the source, the gate and the drain of the crystal (M22), respectively connected to the ground voltage, the -inverting standby mode control signal (8) and the second low-power point (VL2); The source, the _ and the drain of the sixth NMOS transistor (M23) are respectively connected to the second low (four) point (VL2), the - standby mode control signal (8) and the first low voltage (VL1); 28 M438015The source of the seventh cis 08 transistor (M24) is connected to the grounded electric house, and the gate is connected to the drain and connected to the fourth NMOS transistor (the source of the M2D; the / NMOS transistor) a source, a gate and a drain of (M25) are respectively connected to the first low voltage node (VL1), the reverse standby mode control signal (6) and the ninth (10) transistor (M26); The source of the ninth NMOS transistor (M26) is connected to the ground voltage, and the gate is connected to the drain and connected to the terminal of the eighth NMOS transistor (M25); '. Fresh ten NMOSf; crystal ( M27) source, secret and immersion (4) connected to the ground voltage, the eleventh NMOS transistor (M28) and the ninth facet 8 transistor (M26); the gate; _ the 帛The source, gate and drain of the eleven-sided 08 transistor (M28) are respectively connected to the drain of the twelfth NMOS transistor (M29), the write control signal (CTL) and the tenth NM〇 a gate of the S transistor (M27), a gate of the third (10) transistor (p21), and a gate of the fourth PMOS transistor (P22); the twelfth NMOS transistor (M29) The source, the gate and the drain are respectively connected to a ground voltage, an output end of the fifth inverter (121) and a source of the _______ NMOS transistor (M28); the fifth inverter ( The input of 121) is connected to the output of the first delay circuit (D1), and the output of the fifth inverter (121) is connected to the gate of the twelfth transistor; and the fourth PMOS transistor ( a gate of P22); an input of the first delay circuit (D1) is connected to the write control signal (CrL) and a gate of the third PMOS transistor (P21) and the eleventh nmos transistor (Μ% The gate: the source, the gate and the drain of the PM0S transistor (P21) are respectively connected to the power supply voltage (VDD), the control signal (CTL), and the fourth pm〇S a drain of the crystal (P22) and a drain of the eleventh NMOS transistor (M28); and a source, a gate and a drain of the fourth PMOS transistor (P22) are respectively connected to the power supply voltage ( VDD), an output of the fifth inverter (121) and a drain of the third pM〇s transistor (p21) and a drain of the eleventh NMOS transistor (M28); The startup circuit (3) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the fourth nmos power 29 M438015 during an initial period of entering the standby mode. The high-performance dual-static SRAM, wherein the threshold voltage of the first PMOS control transistor (PC1) and the second PMOS control transistor (PC2) is set to be smaller than the The voltage level of the power supply voltage (VDDL) is large 31