M425290 五、新型說明： 【新型所屬之技術領域】 本新型是有關於一種電子顯示裝置，且特別是有關於 一種液晶顯示面板。 【先前技術】 液晶顯示面板是現代顯示技術中的主流。習知之液晶 顯示面板中，用以晝素陣列之兩側皆有獨立的電路板來分 • 別控制源極驅動晶片以及閘極驅動晶片。但是近來為成本 上的考量，常採用設置於源極驅動晶片單侧之電路板達到 同時控制源極驅動晶片以及閘極驅動晶片的效果。然而未 設置電路板之間極驅動晶片*需要以走線進行連接以獲付 電路板的控制訊號。 但是由於這些走線訊號繁多，且各走線訊號之電壓亦 不盡相同，若重要的訊號線由於外力壓迫或是日久腐蝕而 發生斷線，則容易使閘極驅動晶片無法獲得訊號，造成顯 • 示的異常。而走線之間的斷裂，將在外力的持續施加或腐 蝕的持續進行下進而影響到外圍的其他走線，使訊號的傳 輸受到的影響更為嚴重。 因此，如何設計一個新的液晶顯示面板，以增加走線 間的穩固性，進而使閘極驅動晶片間的訊號傳輸維持一定 的品質，乃為此一業界亟待解決的問題。 【新型内容】 4 因此’本新型之一態樣是在提供一種液晶顯示面板， ^ a .畫素陣列、控制電路、複數第—驅動晶片、複數第 -驅動晶片以及走線結構。第―驅動晶片形成於晝素陣列 之第侧邊並電f生連接於控制電路，俾根據控制電路之第 一控制訊號分別傳送第-驅動訊號至畫素陣列。第二驅動 曰曰片形成於畫料列相鄰第—侧邊之第二側邊，俾根據控 fj電路之第-控制訊號分別傳送第二驅動訊號至晝素陣 列。走線結構包含：複數走線及複數中空間隔。走線用以 使第二驅動晶片互相串聯以及使第二驅動晶片電性連接於 第-驅動晶片至少其中之一，以使第二驅動晶片藉由走線 接收控制電路之第二控制訊號，其巾各走線包含形成於其 上之絕緣層。t空間隔形成於每二走線之絕緣層間。 依據本新型一實施例，第一驅動晶片分別為源極驅動 晶片，第一驅動訊號為資料驅動訊號，第二驅動晶片分別 為閘極驅動晶片，第二驅動訊號為閘極開啟控制訊號。 依據本新型另一實施例，其中各走線更包含形成於絕 緣層上之保護層。 依據本新型又一實施例，第一驅動晶片及第二驅動晶 片藉由薄膜覆晶封裝（chip on film ; COF)技術形成於畫 素陣列之玻璃基板周圍之複數薄膜上。 依據本新型再一實施例，其中第一驅動晶片及第二驅 動晶片藉由玻璃覆晶封裝（chiponglass ; COG)技術形成 於畫素陣列之玻璃基板上。 依據本新型更具有之一實施例，其中走線與第二驅動 晶片及第一驅動晶片至少其中之一之相接處更分別包含貫 5 M425290 穿絕T層之複數接觸墊，以與第二驅動晶片及第一驅動晶 片至少其中之一之複數引腳進行電性連接。其中接觸墊之 材質為氧化銦錫（Indium tin oxide ; ΙΤΟ )。 依據本新型再具有之一實施例，其中絕緣層之材質為 矽氮化物或矽氡化物。走線之材質為金屬。 依據本新型一實施例，控制電路為時序控制模組。 應用本新型之優點係在於藉由在走線間的絕緣層形成 中二間隔，使覆蓋於走線上之絕緣層各自獨立，而輕易地 • 達到上述之目的。 【實施方式】 請參照第1圖。第1圖為本新型一實施例中，液晶顯 示面板1之俯視圖。液晶顯示面板1包含：晝素陣列1〇、 控制電路12、複數第一驅動晶片14、複數第二驅動晶片 16以及走線結構18。 畫素陣列10形成於一基板100上，並包含複數晝素單 鲁元（未繪示）。控制電路12於一實施例中，可為時序控制 模組（timing controller ; TCOM)。於其他實施例中，控制 電路12亦可能將其他的模組如縮放控制器（scaler)、類比 數位轉換器（analog digital converter; ADC)等模組整合 在一起。 第一驅動晶片14於本實施例中為源極驅動晶片，形成 於畫素陣列10之第一側邊101並電性連接於控制電路12。 第二驅動晶片16於本實施例中為閘極驅動晶片，形成於畫 素陣列10相鄰第一側邊101之第二側邊103。於本實施例 6 M425290 中，第一驅動晶片14以及第二驅動晶片16是藉由薄膜覆 晶封裝（chip on film ; COF )技術形成於晝素陣列10之基 板100周圍之複數薄膜102上。需注意的是，第一驅動晶 片14及第二驅動晶片16之數目於不同實施例中可依需求 進行調整，不為第1圖中所繪示的數目所限。 第一驅動晶片14根據控制電路12之第一控制訊號（未 繪示）分別傳送第一驅動訊號（未繪示）至晝素陣列10。 而第二驅動晶片16根據控制電路12之第二控制訊號（未 繪示）分別傳送第二驅動訊號（未繪示）至畫素陣列10。 第一控制訊號與第二控制訊號於一實施例中可為時序控制 訊號，或依控制電路12設計之不同而為不同形式的控制訊 號。於本實施例中，第一驅動訊號是資料驅動訊>虎，而第 二驅動訊號則為閘極開啟控制訊號。因此，舉例來說，在 弟 驅動晶片14及第二驅動晶16接收到來自控制電路 12的控制訊號後，可由第二驅動晶片16傳送閘極開啟控 制訊號使晝素陣列10中相應的畫素單元之閘極打開，並由 第一驅動晶片14傳送資料驅動訊號至晝素單元中，以使畫 素單元據以顯示正確的資料。 需注意的是，於本實施例中，控制電路12僅形成於第 一驅動晶片14 一側。因此，第一驅動晶片14可直接與控 制電路12電性連接以接收第一控制訊號，以根據第一控制 訊號來傳送第一驅動訊號晝素陣列10。而第二驅動晶片16 則需要藉由走線結構18以接收來自控制電路12之第二控 制訊號。 請同時參照第2A圖。第2A圖為本新型一實施例中， 7 M425290 第1圖之走線結構18沿A-A’線段之截面側視圖。走線結 構18包含：走線20及中空間隔22。 走線20用以使第二驅動晶片π互相串聯以及使第二 驅動晶片16電性連接於第一驅動晶片14至少其中之一。 由第1圖可知’於本實施例中第二驅動晶片16除藉由走線 2s〇互相串聯外’更與第一驅動晶片14中最接近第二驅動 曰曰片16者相電性連接。因此，控制電路12可以透過第一 驅動b曰片14以及走線2〇的連接，使第二驅動晶片16接收 •控制電路12之第二控制訊號。各走線20上更包含形成於 其上之絕緣層24。於一實施例中，走線2〇之材質為金屬， 而絕緣層24之材質為錢化物或⑦氧化物。於另—實施例 中，如第2B圖所示，走線2〇上更包含形成於絕緣層24 上的保護層26，以提供走線2〇更佳的抗餘性或抗壓性。 中空間隔22形成於每立走線20之絕緣層24間。於一 實施例中，形成走線20之製程是依序於基板1〇〇上沉積金 屬走線,20及絕緣層24 (及/或保護層％)。而藉由在絕緣 •層24形成於走線20上後，對走線20間的絕緣層24進行 餘刻’即可形成申空間隔22。 中空間隔22結構之形成，可使各走線2〇上的絕緣層 24各自獨立。因此在外力造成絕緣層24破損亦或製程 膜質不佳的情形下，重要的走線2G _金屬同時裸露在相 鄰區域的機率將大幅降低，因此，走線2G間彼此發生電腐 蝕的機率也隨之降低，提升液晶顯示面板1之良率。 一請參照第3圖。第3圖為本新型另一實施例中，液晶 顯不面板1之俯視圖。液晶顯示面板丨包含：晝素陣列1〇、 8M425290 V. New description: [New technical field] The present invention relates to an electronic display device, and more particularly to a liquid crystal display panel. [Prior Art] The liquid crystal display panel is the mainstream in modern display technology. In the conventional liquid crystal display panel, a separate circuit board is provided on both sides of the pixel array to control the source driving chip and the gate driving chip. However, in recent cost considerations, it is common to use a circuit board disposed on one side of the source drive chip to simultaneously control the effect of the source drive wafer and the gate drive wafer. However, the pole drive chip between the boards is not provided. * It is necessary to connect with the traces to obtain the control signals of the board. However, due to the large number of these signals, and the voltage of each of the trace signals is not the same, if the important signal line is broken due to external force or corrosion, it is easy to make the gate drive chip unable to obtain the signal, resulting in The display is abnormal. The break between the traces will affect the other traces of the periphery due to the continuous application of external force or the continuation of corrosion, which will make the transmission of the signal more serious. Therefore, how to design a new liquid crystal display panel to increase the stability between the traces and maintain the signal transmission between the gate drive wafers is an urgent problem to be solved in the industry. [New content] 4 Therefore, one aspect of the present invention is to provide a liquid crystal display panel, a pixel array, a control circuit, a plurality of first-drive wafers, a plurality of first-drive wafers, and a wiring structure. The first driving chip is formed on the first side of the pixel array and electrically connected to the control circuit, and respectively transmits the first driving signal to the pixel array according to the first control signal of the control circuit. The second driving cymbal is formed on the second side of the adjacent side of the drawing column, and the second driving signal is respectively transmitted to the pixel array according to the first control signal of the control fj circuit. The routing structure includes: a plurality of traces and a plurality of hollow spaces. The wiring is used to connect the second driving chips to each other and to electrically connect the second driving chip to at least one of the first driving chips, so that the second driving chip receives the second control signal of the control circuit by the routing, Each trace of the towel includes an insulating layer formed thereon. The t-space is formed between the insulating layers of each of the two traces. According to an embodiment of the invention, the first driving chip is a source driving chip, the first driving signal is a data driving signal, the second driving chip is a gate driving chip, and the second driving signal is a gate opening control signal. According to another embodiment of the present invention, each of the traces further comprises a protective layer formed on the insulating layer. According to still another embodiment of the present invention, the first driving chip and the second driving wafer are formed on a plurality of films around the glass substrate of the pixel array by a film on film (COF) technique. According to still another embodiment of the present invention, the first driving chip and the second driving wafer are formed on the glass substrate of the pixel array by a chip-on-glass (COG) technique. According to another embodiment of the present invention, wherein the intersection of the trace and the at least one of the second driver wafer and the first driver wafer respectively comprises a plurality of contact pads of 5 M425290 through the T layer, and the second The plurality of pins of at least one of the driving chip and the first driving chip are electrically connected. The contact pad is made of indium tin oxide (ΙΤΟ). According to still another embodiment of the present invention, the material of the insulating layer is tantalum nitride or germanide. The material of the wire is metal. According to an embodiment of the invention, the control circuit is a timing control module. The advantage of the application of the present invention is that the above-mentioned purpose is easily achieved by forming the insulating layer between the traces to make the insulating layers covering the traces independent. [Embodiment] Please refer to Figure 1. Fig. 1 is a plan view showing a liquid crystal display panel 1 in an embodiment of the present invention. The liquid crystal display panel 1 includes a pixel array 1A, a control circuit 12, a plurality of first driving wafers 14, a plurality of second driving wafers 16, and a wiring structure 18. The pixel array 10 is formed on a substrate 100 and includes a plurality of halogen elements (not shown). In one embodiment, the control circuit 12 can be a timing controller (TCOM). In other embodiments, the control circuit 12 may also integrate other modules such as a scaler, an analog digital converter (ADC), and the like. The first driving wafer 14 is a source driving wafer in this embodiment, and is formed on the first side 101 of the pixel array 10 and electrically connected to the control circuit 12. The second driver wafer 16 is a gate driver wafer in this embodiment, and is formed on the second side 103 of the adjacent first side 101 of the pixel array 10. In the sixth embodiment M425290, the first driving wafer 14 and the second driving wafer 16 are formed on the plurality of thin films 102 around the substrate 100 of the halogen array 10 by a film on film (COF) technique. It should be noted that the number of the first driving chip 14 and the second driving chip 16 can be adjusted according to requirements in different embodiments, and is not limited by the number shown in FIG. The first driving chip 14 respectively transmits a first driving signal (not shown) to the pixel array 10 according to the first control signal (not shown) of the control circuit 12. The second driving chip 16 respectively transmits a second driving signal (not shown) to the pixel array 10 according to the second control signal (not shown) of the control circuit 12. The first control signal and the second control signal may be timing control signals in an embodiment, or different types of control signals depending on the design of the control circuit 12. In this embodiment, the first driving signal is a data driving signal, and the second driving signal is a gate opening control signal. Therefore, for example, after the control chip 14 and the second driving crystal 16 receive the control signal from the control circuit 12, the gate driving control signal can be transmitted from the second driving chip 16 to make the corresponding pixel in the pixel array 10. The gate of the cell is turned on, and the data driving signal is transmitted from the first driving chip 14 to the pixel unit, so that the pixel unit displays the correct data. It should be noted that in the present embodiment, the control circuit 12 is formed only on the side of the first driving wafer 14. Therefore, the first driving chip 14 can be directly connected to the control circuit 12 to receive the first control signal to transmit the first driving signal pixel array 10 according to the first control signal. The second driver chip 16 needs to pass through the trace structure 18 to receive the second control signal from the control circuit 12. Please also refer to Figure 2A. Fig. 2A is a cross-sectional side view of the wire structure 18 of Fig. 1 of Fig. 1 along the line A-A' in the first embodiment of the present invention. The trace structure 18 includes a trace 20 and a hollow spacer 22. The traces 20 are used to connect the second drive wafers π to each other and to electrically connect the second drive wafers 16 to at least one of the first drive wafers 14. As can be seen from Fig. 1, in the present embodiment, the second driving wafers 16 are electrically connected to the second driving die 16 in the first driving wafer 14 except that the wirings 2s are connected in series with each other. Therefore, the control circuit 12 can cause the second driving chip 16 to receive the second control signal of the control circuit 12 through the connection of the first driving b-chip 14 and the wiring 2〇. Each of the traces 20 further includes an insulating layer 24 formed thereon. In one embodiment, the material of the trace 2 is metal, and the material of the insulating layer 24 is money or 7 oxide. In another embodiment, as shown in Fig. 2B, the trace 2 更 further includes a protective layer 26 formed on the insulating layer 24 to provide better resistance or resistance to the traces. Hollow spaces 22 are formed between the insulating layers 24 of each of the traces 20. In one embodiment, the process of forming traces 20 is to deposit metal traces, 20 and insulating layer 24 (and/or protective layer %) on substrate 1 . By forming the insulating layer 24 on the trace 20, the insulating layer 24 between the traces 20 is left in place to form the void interval 22. The hollow spacer 22 structure is formed such that the insulating layers 24 on the respective traces 2 are independent of each other. Therefore, in the case where the external force causes the insulation layer 24 to be damaged or the process film quality is not good, the probability that the important trace 2G_metal is exposed to the adjacent region at the same time is greatly reduced, and therefore, the probability of electric corrosion between the traces 2G is also high. Accordingly, the yield of the liquid crystal display panel 1 is improved. Please refer to Figure 3. Fig. 3 is a plan view showing a liquid crystal display panel 1 in another embodiment of the present invention. The liquid crystal display panel 丨 includes: a halogen array 1 〇, 8
M425290 控制電路12、複數第一驅動晶片14、複數第二驅動晶片 16以及走線結構18。 於本實施例中，第一驅動晶片14以及第二驅動晶片 16是藉由玻璃覆晶封裝（chip 〇n glass ; c〇G)技術形成於 晝素陣列10之玻璃基板100上。第一驅動晶片14與控制 電路12間可藉由軟性電路板120電性連接，以使第一驅動 晶片14接收控制電路12之第一控制訊號。而第二驅動晶 片16則藉由走線結構18相串聯以及與第一驅動晶片14電 •性連接，以透過軟性電路板120、第一驅動晶片14及走線 結構18接收控制電路π之第二控制訊號。 請參照第4圖。第4圖為本新型一實施例中，第3圖 之走線結構18沿B-B’線段之截面侧視圖。走線結構π包 含：走線20及中空間隔22。 於本實施例中，走線20在與第一驅動晶片14相接處， 即走線結構18沿B-B’線段之處，更分別包含貫穿絕緣層 24之接觸墊40。接觸墊40用以與第一驅動晶片14之引腳 φ (未緣示）進行電性連接。於一實施例中’接觸塾40之材 質為氧化鋼錫（Indium tin oxide ; IT0 )’以達到電性連接 之功效。並且，走線20在與第二驅動晶片16相接處亦可 形成此接觸墊40以與第二驅動晶片16之引腳進行電性連 接。 因此，本實施例中之中空間隔22將接觸墊4〇與引腳 連接處之絕緣層24斷開，可使各走線20上的絕緣層24各 自獨立。因此在外力造成絕緣層24破損，亦或製程膜質不 佳的情形下，接觸墊40與引腳金屬同時裸露在相鄰區域的 9 M425290 機率將大幅降低，因此，走線20間彼此發生電腐蝕的機率 也隨之降低，提升液晶顯示面板1之良率。 需注意的是，第4圖中的結構，亦可應用於第1圖中 之走線20與第一驅動晶片14或第二驅動晶片16所在的薄 膜102的引腳上。而第4圖中的結構，亦可形成如第2B 圖所繪示之保護層26。各實施例之特徵及結構在不衝突的 情況下，可以相互組合，不為上述圖式繪示所限。 應用本新型之優點係在於藉由在走線間的絕緣層形成 φ 中空間隔，使覆蓋於走線上之絕緣層各自獨立，而輕易地 達到上述之目的。 雖然本新型已以實施方式揭露如上，然其並非用以限 定本新型，任何熟習此技藝者，在不脫離本新型之精神和 範圍内，當可作各種之更動與潤飾，因此本新型之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本新型之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之說明如下： 第1圖為本揭示内容一實施例中，液晶顯示面板之俯 視圖； 第2A圖為本揭示内容一實施例中，第1圖之走線結 構沿A-A’線段之截面侧視圖； 第2B圖為本揭示内容另一實施例中，第1圖之走線結 構沿A-A’線段之截面侧視圖； M425290 第3圖為本揭示内容另一實施例中，液晶顯示面板之 俯視圖；以及 第4圖為本揭示内容一實施例中，第3圖之走線結構 沿B-B’線段之戴面側視圖。 【主要元件符號說明】 1 ： 液晶顯不面板 10 ： 晝素陣列 100 :基板 101 :第一侧邊 102 :薄膜 103 :第二側邊 12 ： 控制電路 120 :軟性電路板 14 第·一驅動晶片 16 ： 苐二驅動晶片 18 走線結構 20 ： 走線 22 中空間隔 24 ： 絕緣層 26 保護層 40 ： 接觸墊 11M425290 control circuit 12, a plurality of first drive wafers 14, a plurality of second drive wafers 16, and a trace structure 18. In the present embodiment, the first driving wafer 14 and the second driving wafer 16 are formed on the glass substrate 100 of the halogen array 10 by a glass flip chip (c〇G) technique. The first driving chip 14 and the control circuit 12 can be electrically connected by the flexible circuit board 120, so that the first driving chip 14 receives the first control signal of the control circuit 12. The second driving chip 16 is connected in series by the routing structure 18 and electrically connected to the first driving chip 14 to receive the control circuit π through the flexible circuit board 120, the first driving chip 14 and the routing structure 18. Two control signals. Please refer to Figure 4. Fig. 4 is a cross-sectional side view of the wiring structure 18 of Fig. 3 taken along the line B-B' in the embodiment of the present invention. The trace structure π includes: trace 20 and hollow spacer 22. In the present embodiment, the traces 20 are at the junction with the first driver wafer 14, that is, the trace structure 18 along the B-B' line segment, and further comprise contact pads 40 extending through the insulating layer 24, respectively. The contact pad 40 is electrically connected to the pin φ (not shown) of the first driving wafer 14. In one embodiment, the material of the contact crucible 40 is indium tin oxide (IT0) to achieve electrical connection. Moreover, the contact pad 40 can also be formed at the junction with the second driving wafer 16 to be electrically connected to the pins of the second driving wafer 16. Therefore, the hollow spacers 22 in this embodiment disconnect the contact pads 4 and the insulating layer 24 at the pin connections, so that the insulating layers 24 on the respective traces 20 are independent. Therefore, in the case where the external force causes the insulation layer 24 to be damaged, or the process film quality is not good, the probability that the contact pad 40 and the lead metal are exposed at the same time in the adjacent region will be greatly reduced, and therefore, the traces 20 are electrically corroded with each other. The probability of this is also reduced, and the yield of the liquid crystal display panel 1 is improved. It should be noted that the structure in Fig. 4 can also be applied to the leads of the trace 20 in Fig. 1 and the film 102 where the first driver wafer 14 or the second driver wafer 16 is located. The structure in Fig. 4 can also form the protective layer 26 as shown in Fig. 2B. The features and structures of the embodiments may be combined with each other without conflict, and are not limited by the above drawings. The advantage of applying the novel is that the above-mentioned purpose is easily achieved by forming a hollow space of φ between the traces to make the insulating layers covering the traces independent. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make various changes and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious, the description of the drawings is as follows: FIG. 1 is a liquid crystal display according to an embodiment of the present disclosure. 2A is a cross-sectional side view of the wiring structure of FIG. 1 along line A-A' in the embodiment of the disclosure; FIG. 2B is another embodiment of the disclosure, FIG. FIG. 3 is a plan view of a liquid crystal display panel in another embodiment of the present disclosure; and FIG. 4 is a third embodiment of the present disclosure. The side view of the trace structure of the figure along the B-B' line. [Main component symbol description] 1 : Liquid crystal display panel 10 : Alizarin array 100 : Substrate 101 : First side 102 : Film 103 : Second side 12 : Control circuit 120 : Flexible circuit board 14 First drive wafer 16 : 驱动 2 driver wafer 18 wiring structure 20 : trace 22 hollow interval 24 : insulating layer 26 protective layer 40 : contact pad 11