M393817 .t L 五、新型說明： ， 【新型所屬之技術領域】· 本創作係關於一種晶片天線，尤指利用多層陶瓷材料 疊合之方式，以將天線夾置於内層，同時，透過複數個對 地電容負载而實現天線縮小化，係適合應用於内藏式天線 的一種具有電容性負載之晶片天線。 【先前技術】 隨著通訊科技之發達’通訊產品之體積亦越趨輕薄短 小，因此，通訊產品内可用以配置各類電子元件之空間， 亦相當地有限，故’通訊產品内之各類電子元件，其體積 大小亦相對地必須設計成更加地輕薄短小。 天線為通訊產品所必備之電子元件，藉由天線，通訊 產品才得以收發訊號。然而，為了搭配產品之外形美觀， 目前大多數的通訊產品捨棄了舊式外露天線之設計，轉而 採用内建天線之設計，因此，體積相對較小之陶瓷天線即 逐漸地被開發完成，並大量地被應用於通訊產品之中。 請參閱第一圖，係一種習用之陶瓷天線之立體圖，於 該習用之陶竞天線之立體圖，係在兩相鄰基板上分別製作 金屬線段，並透過相鄰基板上所形成之灌孔（via)相互連 接，構成-螺旋狀之天線元件 '然而，上述習知技術之製 作’需#由相鄰基板上所形成之灌孔才能彡成不同基板間 電f生之相互連接’如此勢必增加打孔與填孔之製作程序， 4 M393817 -t i 不但增加製程時間與步驟，亦會降低產品良率。 目前’上述該習知的陶，瓷天線係被應用於内建天線設 计之通sfl產品之中，然而’習知的陶瓷天線係具有下列之 缺點： 1.¾知技術透過相鄰基板上所形成之灌孔（via)相互連 接，增加製程時間與步驟。 2·習知技術之灌孔（Via )，係達成不同基板間電性之相互 # 連接，增加打孔與填孔之製作程序，會降低產品良率。 3. 習知技術無使用能量耦合方式相互連接易因填孔不實 而使灌孔（Via)斷裂，進而導致電氣特性不佳。 4. 省知技術生產製程費時且步驟繁瑣，不符合快速生產之 產業需求。 因此，本案之創作人有鑑於上述習知的陶瓷天線，其 仍具許多缺失與不足，故極力加以改良創新終於研發完 成本創作之一種具有電容性負载之晶片天線。 【新型内容】 本創作之主要目的’在於提出一種具有電容性負載之 晶片天、線，其利用多層陶曼材料疊合之方 <，以將天線炎 置於内層，則可避免天線受到氧化或破壞，並且，透過複 數個對地電容負载，得以實現天線縮小化。 因此，為了達到上述之目的，本案創作人提出一種具 有電容性負載之晶片天線，其包括： 5M393817 .t L V. New description: , [New technical field] · This creation is about a wafer antenna, especially the method of stacking multiple layers of ceramic materials to place the antenna clip on the inner layer, and at the same time, through multiple The antenna is reduced in capacitance to the ground, and is a chip antenna having a capacitive load suitable for use in a built-in antenna. [Prior Art] With the development of communication technology, the volume of communication products has become lighter and thinner. Therefore, the space available for configuring various types of electronic components in communication products is also quite limited. Therefore, various types of electronic products in communication products. The size of the component must also be designed to be relatively light, thin and short. The antenna is an electronic component necessary for communication products. With the antenna, the communication product can transmit and receive signals. However, in order to match the appearance of the product, most of the communication products have abandoned the design of the old outdoor open circuit and switched to the design of the built-in antenna. Therefore, the relatively small ceramic antenna is gradually developed. It is widely used in communication products. Please refer to the first figure, which is a perspective view of a conventional ceramic antenna. The stereoscopic view of the conventional Taojing antenna is made by forming a metal line segment on two adjacent substrates and passing through a hole formed on the adjacent substrate (via). Connected to each other to form a helical antenna element. However, the above-mentioned prior art fabrication requires that the holes formed by the adjacent substrates can be connected to each other to form a mutual connection between the different substrates. Hole and fill hole production procedures, 4 M393817 -ti not only increase process time and steps, but also reduce product yield. At present, the above-mentioned conventional ceramic and porcelain antennas are used in the sfl products of the built-in antenna design. However, the conventional ceramic antenna system has the following disadvantages: 1.3⁄4 knowing technology is transmitted through adjacent substrates. The formed vias are interconnected to increase process time and steps. 2. The conventional technique of filling holes (Via) is to achieve the mutual connection between the different substrates, and increase the manufacturing process of punching and filling, which will reduce the product yield. 3. Conventional techniques are not connected by energy coupling, and it is easy to break the via hole due to the unfilled hole, which leads to poor electrical characteristics. 4. It is known that the technical production process is time-consuming and cumbersome, and does not meet the industrial needs of rapid production. Therefore, the creators of the present case have many defects and shortcomings in view of the above-mentioned conventional ceramic antennas, and therefore, it is finally improved and innovated to finally develop a chip antenna having a capacitive load. [New content] The main purpose of this creation is to propose a wafer day and line with a capacitive load, which uses a layer of multi-layered Tauman material overlay to place the antenna inflammation in the inner layer to avoid oxidation of the antenna. Or destroy, and through a plurality of capacitive loads to the ground, the antenna can be reduced. Therefore, in order to achieve the above objectives, the creator of the present invention proposed a chip antenna having a capacitive load, which includes:
AUJ :別17 居—第一電極層基板，該第一電極層基板之-第-電極 m表面具有複數個上端電極，，以作為連接電極； 令―第一接地層基板’係以其—第—接地層表面疊合於 广電極層基板之一第二電極層表面，該第一接地層表 具有一第一接地電極； —耦合層基板，係以其一第—耦合層表面疊合於該第 接地層基板之一第二接地層表面，該第一耦合層表面具 一電容耦合電極； 八輻射層基板，係以其-第-輻射層表面疊合於該耦 s:基板之一第二耦合層表面’該第一輻射層表面具有一 輻射電極及一第二輻射電極，該第一輻射電極其中一 ~為訊號輸人端’而第二輻射電極其中—端為接地端； -第二接地層基板，係以其一第三接地層表面疊合於 〆輪射層基板之一第二輻射層表面，該第三接地層表面具 有—第二接地電極； —第二電極層基板’係以其-第三電極層表面叠合於 :第二接地層之一第四接地層表面’該第二電極層基板之 一第四電極層表面具有複數個下端電極，以作為連接電 極；及 複數個側壁導電層，係用以將該複數個上端電極、該 複數個下端電極、及該第一接地電極相互連接，以及，將 複數個上端電極、複數個下端電極、及該第一轄射電極相 6 M393817 互連接，以及，將複數個上 工碼苇極、複數個下端電極、及 該第二輻射電極相互連接，， 以及，將複數個上端電極、複 數個下端電極、及該篦-垃 該第一接地電極相互連接，JL，該複數 個側壁導電層、複數個上端 上知電極、及複數個下端電極，可 共同形成複數個外部端電極，以供焊接，而可將該晶片天 線配置於其-應用電路裝置之上，並將該複數個外部端電AUJ: the first electrode layer substrate, the first electrode layer substrate has a plurality of upper electrode electrodes on the surface of the first electrode layer as a connection electrode; the first ground layer substrate is made of the same - the surface of the ground layer is superposed on the surface of one of the second electrode layers of the wide electrode layer substrate, the first ground layer has a first ground electrode; the coupling layer substrate is superposed on the surface of a first coupling layer a second ground layer surface of the first ground layer substrate, the first coupling layer surface has a capacitive coupling electrode; and the eight radiation layer substrate is superposed on the surface of the first radiation layer to the coupling s: one of the substrate The surface of the coupling layer has a radiation electrode and a second radiation electrode, wherein the first radiation electrode has a signal input end and the second radiation electrode has a ground end; The grounding layer substrate is superposed on the surface of a second grounding layer of the first layer of the grounding layer, the surface of the third grounding layer has a second grounding electrode; the second electrode layer substrate With its - third electrode layer surface stack And a surface of the fourth ground layer of the second ground layer. The surface of the fourth electrode layer has a plurality of lower electrodes as a connection electrode; and a plurality of sidewall conductive layers are used to a plurality of upper electrodes, the plurality of lower electrodes, and the first ground electrodes are connected to each other, and a plurality of upper electrodes, a plurality of lower electrodes, and the first urging electrode phase 6 M393817 are interconnected, and a top working dipole, a plurality of lower electrodes, and the second radiating electrode are connected to each other, and a plurality of upper electrodes, a plurality of lower electrodes, and the first ground electrodes are connected to each other, JL, The plurality of sidewall conductive layers, the plurality of upper terminal electrodes, and the plurality of lower electrodes may jointly form a plurality of external terminal electrodes for soldering, and the wafer antenna may be disposed on the application circuit device, and Electricizing the plurality of external terminals
極分別連接-訊號輸人端與複數個接地端，以將訊號饋入 該第-輻射電極’並將該第二輻射電極、第—及二接地電 極接地。 【實施方式】 為了能夠更清楚地描述本創作所提出之一種具有電容 性負載之晶片天線，以下將配合圖示，詳盡說明本創作之 較佳實施例。 請參閱第二圖’係本創作之一種具有電容性負載之晶 片天線之立體圖，該一種具有電容性負載之晶片天線1， 係由多層陶瓷基板所疊合而成，該一種具有電容性負栽之 晶片天線1係包括：一第一電極層基板u、一第一接地層 基板1 2、 耗合層基板1 3、-—賴射層基板14、一第二接 地層基板15、一第二電極層基板16、四個側壁導電層（ 171、172、173、174)、及一標記ι13，其中，該第一電極 層基板U、該第一接地層基板12、該耦合層基板13、該 輻射層基板14、該第二接地層基板15、該第二電極層基板 M393817 -«. « 16係使用低溫共燒陶瓷技術所製作而成，而該四個側壁導 電層（1 7 1、1 72、1 73、1 74 )則係透過端銀製程技術所製 • 作而成。 明參閱第二圖，係該一種具有電容性負載之晶片天線 之分解圖，該-種具有電容性負載之晶片天線】，其天線 結構分別依序由上而下係包括有： 一第一電極層基板π係具有一第一電極層表面lu與 •-第二電極層表面112’該第-電極層表面m與該第二電 極層表面112為相對面’且，第一電極層表面1U之上設 有四個上端電極及該標記113,該四個上端電極係分別為 -第-上端電極114、一第二上端電極115、一第三上端電 極116、及一第四上端電極117，以作為連接電極，而標記 113則可供辨識該具有電容性負載之晶片天線i之方向性。 一第一接地層基板12係具有一第一接地層表面121與 一第二接地層表面122,該第一接地層表面121與該第二 接地層表面122為相對面，該第一接地層基板12係以其第 一接地層表面丨21疊合於該第二電極層表面112，且，第 一接地層表面121之上設有一第一接地電極123 ^ 一耦合層基板13係具有一第一耦合層表面131與一第 二耦合層表面132,該第一耦合層表面131與該第二耦合 層表面132為相對面，該耦合層基板13係以其第一耦合層 表面131疊合於該第二接地層表面122 ’且，第一耦合層 8 M393817The poles respectively connect the signal input terminal and the plurality of ground terminals to feed the signal to the first radiation electrode and ground the second radiation electrode, the first and second ground electrodes. [Embodiment] In order to more clearly describe a wafer antenna having a capacitive load proposed by the present invention, a preferred embodiment of the present invention will be described in detail below with reference to the drawings. Please refer to the second figure, which is a perspective view of a chip antenna having a capacitive load. The chip antenna 1 having a capacitive load is formed by laminating a plurality of ceramic substrates, and the capacitor has a capacitive load. The chip antenna 1 includes: a first electrode layer substrate u, a first ground layer substrate 1 2, a consuming layer substrate 13 , a ray layer substrate 14 , a second ground layer substrate 15 , and a second An electrode layer substrate 16, four sidewall conductive layers (171, 172, 173, 174), and a mark ι13, wherein the first electrode layer substrate U, the first ground layer substrate 12, the coupling layer substrate 13, the The radiation layer substrate 14, the second ground layer substrate 15, and the second electrode layer substrate M393817 - «. « 16 are fabricated using low temperature co-fired ceramic technology, and the four sidewall conductive layers (1 7 1, 1 72, 1 73, 1 74 ) is made by the end silver process technology. Referring to FIG. 2, an exploded view of the chip antenna having a capacitive load, the antenna antenna having a capacitive load, wherein the antenna structures are sequentially included from the top to the bottom: a first electrode The layer substrate π has a first electrode layer surface lu and a second electrode layer surface 112'. The first electrode layer surface m and the second electrode layer surface 112 are opposite sides and the first electrode layer surface 1U There are four upper electrodes and the mark 113, and the four upper electrodes are a first-upper electrode 114, a second upper electrode 115, a third upper electrode 116, and a fourth upper electrode 117, respectively. As the connection electrode, the mark 113 can be used to identify the directivity of the wafer antenna i having a capacitive load. A first ground layer substrate 12 has a first ground layer surface 121 and a second ground layer surface 122. The first ground layer surface 121 and the second ground layer surface 122 are opposite sides. The first ground layer substrate The first grounding layer surface 丨21 is superposed on the second electrode layer surface 112, and a first grounding electrode 123 is disposed on the first grounding layer surface 121. A coupling layer substrate 13 has a first The coupling layer surface 131 and the second coupling layer surface 132 are opposite to the second coupling layer surface 132, and the coupling layer substrate 13 is superposed on the first coupling layer surface 131 thereof. Second ground plane surface 122 'and, first coupling layer 8 M393817
• t I 表面之上設有一電容耦合電極U3。 • 一輻射層基板14係具有一第一輻射層表面141與一第 . 一輻射層表面142，該第一輻射層表面141與該第二輻射 層表面142為相對面，該輻射層基板14係以其第—輻射層 表面141疊合於該第二耦合層表面132，且，第一輻射層 表面141之上設有一第一輻射電極143與一第二輻射電極 144 ’且’實施本創作之時，若係使用兩個輻射層基板14， 鲁則可於不同一個輻射層基板14之第一輻射層表面141之 上，刀別形成第一輻射電極143與第二輻射電極144。 一第二接地層基板15係具有一第三接地層表面151與 一第四接地層表面152,該第三接地層表面151與該第四 接地層表面152為相對面，該第二接地層基板15係以其第 三接地層表面151疊合於該第二輻射層表面142，且，第 三接地層表面151之上設有一第二接地電極153。 第一電極層基板16係具有一第三電極層表面161與 一第四電極層表面162，該第三電極層表面161與該第四 電極層表面162為相對面，該第二電極層基板“係以其第 三電極層表面161疊合於該第四接地層表面152，且，第 四電極層表面162之上設有四個下端電極，係分別為一第 -下端電極163、-第二下端電極164、_第三下端電極 165、及一第四下端電極166，以作為連接電極。 "月繼續參閱第一圖與第二圖，該四個側壁導電層係分 別為一第一側壁導電屏 曰171、一第二側壁導電層172、一第 三側壁導電層173、及—相 第四側壁導電層174，其中，該第 一側壁導電層i 7 1係 用以將第一上端電極114、第一下端 電極163、與該第一韧以 轄射電極143相互連接，又該第二側• A capacitive coupling electrode U3 is placed over the surface of t I . A radiation layer substrate 14 has a first radiation layer surface 141 and a first radiation layer surface 142. The first radiation layer surface 141 is opposite to the second radiation layer surface 142. The radiation layer substrate 14 is The first radiation layer surface 141 is superposed on the second coupling layer surface 132, and a first radiation electrode 143 and a second radiation electrode 144 ' are disposed on the first radiation layer surface 141 and the present invention is implemented. When two radiation layer substrates 14 are used, Lu may be formed on the first radiation layer surface 141 of the different radiation layer substrates 14 to form the first radiation electrode 143 and the second radiation electrode 144. A second ground layer substrate 15 has a third ground layer surface 151 and a fourth ground layer surface 152. The third ground layer surface 151 is opposite to the fourth ground layer surface 152. The second ground layer substrate is opposite. The 15th layer has a third ground layer surface 151 superposed on the second radiation layer surface 142, and a second ground electrode 153 is disposed on the third ground layer surface 151. The first electrode layer substrate 16 has a third electrode layer surface 161 and a fourth electrode layer surface 162. The third electrode layer surface 161 is opposite to the fourth electrode layer surface 162. The second electrode layer substrate is The third electrode layer surface 161 is superposed on the fourth ground layer surface 152, and the fourth electrode layer surface 162 is provided with four lower end electrodes, which are respectively a first-lower end electrode 163 and a second The lower electrode 164, the third lower electrode 165, and the fourth lower electrode 166 are used as the connection electrodes. "Continue to refer to the first and second figures, respectively, the four sidewall conductive layers are respectively a first sidewall a conductive screen 171, a second sidewall conductive layer 172, a third sidewall conductive layer 173, and a fourth sidewall conductive layer 174, wherein the first sidewall conductive layer 71 is used to connect the first upper electrode 114. The first lower end electrode 163 is connected to the first torrefaction electrode 143, and the second side is further
壁導電層172係用以腺楚 L 將第一上端電極115、第二下端電極 164、與該第二轄射雷 電極1 44相互連接，又該第三側壁導電 層1 73係用以將第三The wall conductive layer 172 is used to connect the first upper electrode 115, the second lower electrode 164, and the second pillar lightning electrode 1 44 to each other, and the third sidewall conductive layer 73 is used to three
—上端電極UG、第三下端電極165、與 該第一、第二接地雷搞 电極123、1 53相互連接，又該第四側壁 導電層174係用以胳 將第四上端電極11 7、第四下端電極166、 第 第一接地電極123、153相互連接，另外，四個 側壁導電層（171、172、"3、174)、四個上端電極（114、 U5、116、117)、與四個下端電極（163、164、165、166)，- the upper electrode UG, the third lower electrode 165, and the first and second ground lightning electrodes 123, 153 are connected to each other, and the fourth sidewall conductive layer 174 is used to tie the fourth upper electrode 11 The fourth lower electrode 166 and the first ground electrode 123 and 153 are connected to each other, and further, four sidewall conductive layers (171, 172, "3, 174), four upper electrode (114, U5, 116, 117), With four lower electrodes (163, 164, 165, 166),
可分別地共同形成四個外部端電極（18卜182、183、184)， 該四個外部端電極（181、182、183、184)經過電鍍之後， 可供直接焊接，而可將該—種具有電容性貞載之晶片天線 1烊接於其一應用電路裝置之上；此外，透過四個外部端 電極（181、182、183、.184)可焊接一訊號輸入端與三個 接地端，用以將訊號饋入第一輻射電極143，並將第二輻 射電極144、第一及第二接地電極接地123、153。 請再同時參閱第二圖與第三圖，於上述該一種具有電 谷性負載之晶片天線1，其中，該第一側壁導電層m係 連接該第一上端電極114與該第一下端電極163而形成一 10 M393817 -* » 外部端電極181’其可以焊接之方式，連接該訊號輸 入端，以將訊號輸入端之訊號，饋入第一輻射電極143。 '該第二側壁導電層172係、連接該第二上端電極115、與該 第二下端電極164而形成一第二外部端電極182，其可以 焊接之方式，連接該接地端，以將第二輻射電極144接地。 而該第三側壁導電4 173係、連接該第三上端電極116與該 第三下端電極165而形成一第三外部端電極183，其可以 #谭接之方式，連接該接地端，以冑第一、第二接地電極123、 153接地。此外，該第四側壁導電層174係連接該第四上 端電極117與該第四下端電極166而形成一第四外部端電 極184，其可以焊接之方式，連接該接地端，以將第一、 第一接地電極123、153接地。 另外，於上述該一種具有電容性負載之晶片天線丄， 參其中，該四個上端電極（1H、II5、110、U7)、該第一接 地電極123、電谷糕合電極133、第一輻射電極第二 輻射電極144與該第二接地電極153、及該四個下端電極 (163、164、165、166)，係以印刷電路板技術將其分別形 成於該第電極層基板11、該第一接地層基板12、該耦合 層基板13、該輻射層基板14、該第二接地層基板15及該 第二電極層基板16之上，接著，透過由上而下疊合第一電 極層基板11、第—接地層基板12、耦合層基板13、輻射 層基板14、第二接地層基板15及第二電極層基板16之後， 11 M393817 再透過端銀製程技術形成該四個側壁導電層（171、172、 173、174)，最後，將該四裀外部端電極（181、182、183、 184)進行一般電鍍程序之後’如此’ 一種具有電容性負載 之晶片天線1即被製作完成，其製作過程係相當地簡易與 快速，且，其完成品之長度為3.2mm、寬度為丨6mm、及 高度（厚度）為1.2mm，係具有輕薄短小之優點。 並且，上述該具有電容性負載之晶片天線丨藉由疊合 該第一電極層基板11、該第一接地層基板12、該耦合層基 板13、該輻射層基板14、該第二接地層基板15及該第二 電極層基板16之方式，以將第一接地層基板12、耦合層 基板13、輻射層基板14、第二接地層基板ι5夾置於第一 電極層基板11與第二電極層基板16之間，如此，可避免 作為天線之該第一接地電極123、電容耦合電極133、第一 輕射電極143、第二輻射電極144、第二接地電極ι53，因 長期曝露在外而氧化’或者受到外力而損壞。另外，訊號 輪入端透過該第一外部端電極181將訊號饋入第一輻射電 極143之後，是以能量耦合之方式，將訊號傳輸至第二輻 射電極144’並搭配第一、二輻射電極} 43、144與第一、 第二接地電極123、153之間的對地電容負載，進而共同激 發形成一操作頻段，以達到天線收發訊號之效能。其中， 第一、二輻射電極143、144與第一、第二接地電極123、 153之間分別各形成一對地電容負載，具有降低天線共振 12 M393817 頻率之功用，接著，再藉由適當地調整電容耦合電極133 與第一、第二輻射電極143’、144之間的串接電容阻抗（ Xc)’使得一種具有電容性負載之晶片天線1於高頻傳輸之 時’較易達成阻抗匹配，進而可有效地降低其共振頻率， 且’亦能夠縮小天線尺寸。 為了證明本創作之該一種具有電容性負載之晶片天線 1之可操作頻寬大小，係適用於IEEE802.1 1b/g與Bluetooth (藍芽）之頻段操作，請參閱第四圖，係一種晶片測試電 路裝置之俯視圖，如第四圖所示，於一晶片測試電路裝置 6之上’係將該一種具有電容性負載之晶片天線1以表面 黏著之方式’焊接於一玻纖基板61之上，該玻纖基板61 之上表面62係為接地面，且，玻纖基板61之上表面62週 圍’係鑽設有許多的灌孔（Via ) 621，該灌孔（via) 621 係為了將玻纖基板61之上表面62與其下表面連接，以形 成完全接地之情況。玻纖基板61之上表面62更設有一非 接地區63與—共面波導64,該非接地區63之上焊接有一 種具有電容性負載之晶片天線1’一種具有電容性負載之 晶片天線1並與該共面波導64電性連接，如此，即完成該 種具有電容性負載之晶片天線之測試電路裝置6。請參 閱第五圖’係該一種具有電容性負載之晶片天線之測試結 果圖’其中’—種具有電容性負载之晶片天線1的中心頻 率fc約位於2.45 GHz，且，一種具有電容性負載之晶片天 13 M393817 叫 . 線1於頻率2.37GHz與2.5 5GHz附近，係分別具有一最小 操作頻率fmin與一最大操作頻率fmax，因此，可以得知其 操作頻寬為180MHz，係適用於IEEE802.11b/g與Bluetooth (藍芽）之頻帶操作。故’經由上述一種具有電容性負載 之晶片天線1之測試結果，可以得知本創作之一種具有電 今性負載之晶片天線1係可作為通訊產品之内建天線。 上述已對本創作之實施例作了相當完整之揭露，因 此，綜合上述’可得知本創作係具有下列之優點： 1.本創作藉由疊合第一電極層基板、第一接地層基板、耦 合層基板、輻射層基板、第二接地層基板與第二電極層 基板，而將天線夾置於内層，以避免天線受到氧化或破 壞。 .不同於奚知技術利用灌孔（Via )來傳遞訊號，本創作係 透過月b篁耦合之方式，於第-輻射電極與第二輻射電極 之間傳遞訊號。 3.本創作可藉由第一 二輻射電極與第一 第二接地電極 之間的對地電容負 當地調整電容耦合 接電容阻抗（Xc )， 於高頻傳輪之時， 低其共振頻率，且 載，來降低天線共振頻率，並藉由適 電極與第一、第二輻射電極之間的串 使得一種具有電容性負载之晶片天線 較易達成阻抗匹配，進而可有效地降 ’亦能约縮小天線尺寸。 4.本創作係透過印 刷電路板技術、 多層陶瓷材料疊合方 式、與端銀製程技術製作而成，其製作過程係相當地簡 易與决速’且元成品之長度為3 2mm、寬度為i 6腿、 门度（厚度）4 1,2mm，係具有輕薄短小之優點。 =上述之詳細說明係針對本創作之一可行實施例之具體 S准該實施例並非用以限制本創作之專利範圍，凡未 脫離本創作技藝精神所為之等效實施或變更，均應包含於 本案之專利範圍中。 【圖式簡單說明】 第圖係、#習用之陶;£天線 第一圖係本創作之一種具有電容性負載之晶片天線之 立體圖； 第三圖 第四圖 第五圖 係-種具有電容性負載之晶片天線之分解圖； 係一種晶片測試電路裝置之俯視圖； 係種具有電容性負載之晶片天線之測試結果 圖0 15 M393817 【主要元件符號說明】 1 一種具有電容性’ 11 第一電極層基板 111 第一電極層表面 112 第二電極廣表面 113 標記 114 第一上端電極 115 第二上端電極 116 第三上端電極 117 第四上端電極 12 第一接地層基板 121 第一接地層表面 122 第二接地層表面 123 第一接地電極 13 耦合層基板 131 第一搞合層表面 132 第二耦合層表面 133 電容耦合電極 14 輻射層基板 141 第一輻射層表面 142 第二輻射層表面 143 第一輻射電極 J6 第二輻射電極 . 第二接地層基板‘ 第三接地層表面 第四接地層表面 第二接地電極 第二電極層基板 第三電極層表面 第四電極層表面 第一下端電極 第二下端電極 第三下端電極 第四下端電極 第一側壁導電層 第二側壁導電層 第三側壁導電層 第四側壁導電層 第一外部端電極 第二外部端電極 第三外部端電極 第四外部端電極 ·~種具有電容性負載之晶片天線之測試電路裝 置 17 M393817 61 玻纖基板 62 玻纖基板之上表面 621 灌孔（Via) 63 非接地區 64 共面波導 f〇 中心頻率 fmax 最大操作頻率 fm i n 最小操作頻率Four external terminal electrodes (18, 182, 183, 184) may be separately formed, and the four external terminal electrodes (181, 182, 183, 184) may be directly soldered after being plated, and the same may be used. The chip antenna 1 having a capacitive load is connected to one of the application circuit devices; in addition, a signal input terminal and three ground terminals can be soldered through the four external terminal electrodes (181, 182, 183, .184). The signal is fed into the first radiation electrode 143, and the second radiation electrode 144, the first and second ground electrodes are grounded 123, 153. Referring to the second and third figures, the above-mentioned wafer antenna 1 having an electric valley load, wherein the first sidewall conductive layer m is connected to the first upper electrode 114 and the first lower electrode 163 is formed as a 10 M393817 -* » external terminal electrode 181' which can be soldered to the signal input terminal to feed the signal input terminal to the first radiation electrode 143. The second sidewall conductive layer 172 is connected to the second upper electrode 115 and the second lower electrode 164 to form a second external terminal electrode 182, which can be soldered to connect the ground to the second The radiation electrode 144 is grounded. The third sidewall conductive layer 173 is connected to the third upper terminal electrode 116 and the third lower terminal electrode 165 to form a third external terminal electrode 183, which can be connected to the ground terminal. 1. The second ground electrodes 123, 153 are grounded. In addition, the fourth sidewall conductive layer 174 is connected to the fourth upper terminal electrode 117 and the fourth lower terminal electrode 166 to form a fourth external terminal electrode 184, which can be soldered to connect the ground terminal to The first ground electrodes 123, 153 are grounded. In addition, in the above-described wafer antenna having a capacitive load, the four upper electrodes (1H, II5, 110, U7), the first ground electrode 123, the electric grid electrode 133, and the first radiation The electrode second radiation electrode 144 and the second ground electrode 153, and the four lower end electrodes (163, 164, 165, 166) are respectively formed on the first electrode layer substrate 11 by a printed circuit board technology. a ground layer substrate 12, the coupling layer substrate 13, the radiation layer substrate 14, the second ground layer substrate 15 and the second electrode layer substrate 16, and then, the first electrode layer substrate is superposed by being stacked from top to bottom. 11. After the first ground layer substrate 12, the coupling layer substrate 13, the radiation layer substrate 14, the second ground layer substrate 15, and the second electrode layer substrate 16, the 11 M393817 is further formed by the end silver process technology to form the four sidewall conductive layers ( 171, 172, 173, 174), finally, after performing the general plating process on the four external electrode (181, 182, 183, 184), a wafer antenna 1 having a capacitive load is completed. The production process is quite Easily and quickly, and its complete length of the product of 3.2mm, a width of Shu 6mm, 1.2mm and a height (thickness), the system having advantages of compact size. And the chip antenna having the capacitive load is stacked by the first electrode layer substrate 11, the first ground layer substrate 12, the coupling layer substrate 13, the radiation layer substrate 14, and the second ground layer substrate. And the second electrode layer substrate 16 is configured to sandwich the first ground layer substrate 12, the coupling layer substrate 13, the radiation layer substrate 14, and the second ground layer substrate ι5 on the first electrode layer substrate 11 and the second electrode Between the layer substrates 16, the first ground electrode 123, the capacitive coupling electrode 133, the first light-emitting electrode 143, the second radiation electrode 144, and the second ground electrode ι53, which are the antennas, can be prevented from being oxidized due to long-term exposure. 'Or damaged by external forces. In addition, after the signal wheel-in terminal feeds the signal into the first radiation electrode 143 through the first external terminal electrode 181, the signal is transmitted to the second radiation electrode 144 ′ in an energy coupling manner and is matched with the first and second radiation electrodes. The capacitance load to ground between the first and second ground electrodes 123 and 153 is further excited to form an operating frequency band to achieve the performance of the antenna for transmitting and receiving signals. Wherein, the first and second radiation electrodes 143, 144 and the first and second ground electrodes 123, 153 respectively form a pair of capacitive loads, which have the function of reducing the frequency of the antenna resonance 12 M393817, and then, by appropriate Adjusting the series capacitance (Xc)' between the capacitive coupling electrode 133 and the first and second radiation electrodes 143', 144 makes it easier to achieve impedance matching when a wafer antenna 1 having a capacitive load is transmitted at a high frequency In turn, the resonant frequency can be effectively reduced, and 'the antenna size can also be reduced. In order to prove the operational bandwidth of the chip antenna 1 having the capacitive load of the present invention, it is applicable to the frequency band operation of IEEE802.1 1b/g and Bluetooth, please refer to the fourth figure, which is a chip. A top view of the test circuit device, as shown in the fourth figure, is mounted on a wafer test circuit device 6 by soldering a chip antenna 1 having a capacitive load to a glass substrate 61 by surface adhesion. The upper surface 62 of the glass fiber substrate 61 is a ground plane, and a plurality of filling holes (Via) 621 are formed around the upper surface 62 of the glass fiber substrate 61. The via 621 is for The upper surface 62 of the glass substrate 61 is joined to its lower surface to form a completely grounded condition. The upper surface 62 of the glass substrate 61 is further provided with a non-contact region 63 and a coplanar waveguide 64. The non-connected region 63 is soldered with a chip antenna 1 having a capacitive load and a chip antenna 1 having a capacitive load. The coplanar waveguide 64 is electrically connected to the test circuit device 6 of the chip antenna having the capacitive load. Please refer to the fifth figure 'Test Results of the Chip Antenna with Capacitive Load'. The center frequency fc of the wafer antenna 1 with capacitive load is about 2.45 GHz, and one has a capacitive load. Wafer Day 13 M393817 is called. Line 1 has a minimum operating frequency fmin and a maximum operating frequency fmax near the frequency of 2.37GHz and 2.5 5GHz. Therefore, it can be known that its operating bandwidth is 180MHz, which is applicable to IEEE802.11b. /g operates in the band of Bluetooth. Therefore, through the above test result of the wafer antenna 1 having a capacitive load, it can be known that the wafer antenna 1 having an electric load of the present invention can be used as a built-in antenna of a communication product. The above embodiments of the present invention have been fairly completely disclosed. Therefore, it is known that the present invention has the following advantages: 1. The present invention is formed by laminating a first electrode layer substrate, a first ground layer substrate, The coupling layer substrate, the radiation layer substrate, the second ground layer substrate and the second electrode layer substrate are disposed on the inner layer to prevent the antenna from being oxidized or destroyed. Unlike the technique of using the filling hole (Via) to transmit signals, the present invention transmits signals between the first radiation electrode and the second radiation electrode by means of a monthly b篁 coupling. 3. The creation can negatively adjust the capacitive coupling capacitance (Xc) by the capacitance to the ground between the first two radiation electrodes and the first second ground electrode, and at the high frequency transmission, the resonance frequency is low, and Loading, to reduce the antenna resonance frequency, and by using a string between the appropriate electrode and the first and second radiation electrodes, a chip antenna having a capacitive load can easily achieve impedance matching, thereby effectively reducing Antenna size. 4. The creation department is made by printed circuit board technology, multi-layer ceramic material superposition method and end silver process technology. The production process is quite simple and speed-determined. The length of the finished product is 32 mm and the width is i. 6 legs, door (thickness) 4 1,2mm, is the advantage of light and thin. The detailed description above is intended to be a specific embodiment of the present invention. It is not intended to limit the scope of the patents, and the equivalent implementations or modifications of the present invention should be included in The patent scope of this case. [Simple diagram of the diagram] The first diagram, the #cooked pottery; the first antenna of the antenna is a perspective view of a chip antenna with capacitive load; the third figure, the fourth figure, the fifth figure, the type of capacitance An exploded view of the wafer antenna of the load; a top view of a wafer test circuit device; test results of a chip antenna with a capacitive load. Figure 0 15 M393817 [Explanation of main component symbols] 1 A capacitive first layer of '11 Substrate 111 First electrode layer surface 112 Second electrode wide surface 113 Marker 114 First upper end electrode 115 Second upper end electrode 116 Third upper end electrode 117 Fourth upper end electrode 12 First ground layer substrate 121 First ground layer surface 122 Second Ground layer surface 123 first ground electrode 13 coupling layer substrate 131 first engaging layer surface 132 second coupling layer surface 133 capacitive coupling electrode 14 radiation layer substrate 141 first radiation layer surface 142 second radiation layer surface 143 first radiation electrode J6 second radiation electrode. second ground layer substrate' third ground layer surface fourth ground layer surface Ground electrode second electrode layer substrate third electrode layer surface fourth electrode layer surface first lower end electrode second lower end electrode third lower end electrode fourth lower end electrode first side wall conductive layer second side wall conductive layer third side wall conductive layer Four side wall conductive layer first outer end electrode second outer end electrode third outer end electrode fourth outer end electrode · test circuit device with a capacitive load of the wafer antenna 17 M393817 61 glass substrate 62 above the glass substrate Surface 621 Filling (Via) 63 Non-connected area 64 Coplanar waveguide f〇 Center frequency fmax Maximum operating frequency fm in Minimum operating frequency