M343914 八、新型說明： 【新型所屬之技術領域】 本創作係關於一種堆疊晶體之打線封裝結構，特別是關於一種 具有一橋接晶片之堆疊晶體之打線封裝結構。 【先前技術】 現今，由於各種電子產品已逐漸趨向小型化、低成本、高效能、 高腳數等特性，因此利用封裝結構内各晶片（Die)之堆疊技術 馨（Stacked)所形成的客製化封裝結構，更是封裝結構中的一波主力趨 勢。 由於I知的堆疊封裝（staeked package on package，PoP)結構具 有與各種元件架構相容之特性，因而更能夠在封裝結構中提供良好 的配置靈活性；再者’由於堆疊封裝結構中的單一封裝層更可在堆 疊前做完整之測試’因此亦可大幅提高整體封裝結構之良率。因 此’現今各封裝產業係廣泛地利用堆疊封裝作為一主要之封裝結 構。 Φ 明參考第1圖’為習知堆疊晶體之打線封裝結構10示意圖， 如第1圖所示’習知的堆疊晶體之打線封裝結構1〇係包含一第一 晶片101、一第二晶片102、一導線架1〇3、複數條導線104al04b， 其中第一晶片101可為一快閃記憶體，而第二晶片1〇2則可為一控 制晶片，且堆疊晶體之打線封裝結構10尚具有位於左側之引腳架 103a以及位於右側之引腳架1〇3b。第一晶片1〇1係藉由黏著劑 (Epoxy Glue)105a黏著於導線架1〇3所具有之一晶片墊（Die pad， 未顯不）上表面。第二晶片1〇2藉由黏著劑（Ep〇xy Glue)1〇5b黏著、 堆疊於第一晶片ιοί之上表面，接著，再藉由打線（wire B〇nding) 5 M343914 技術，利用導線104a、l〇4b使第一晶片1(Π、第二晶片1〇2、導線 •架103以及引腳架l〇3a、l〇3b作電性連接，從而使堆疊晶體之打 線封裝結構10内、外部完成電性連接，進行電氣訊號之傳遞。 然而，如第1圖所示，堆疊晶體之打線封裝結構1〇右側可藉 由導線104b使第一晶片1〇1、第二晶片1〇2以及引腳架i〇3b實現 電性連接；惟，堆疊晶體之打線封裝結構1〇左侧卻無法藉由導線 10軺使第二晶片102以及引腳架103a實現電性連接，其主要原因 即在於第一晶片101之面積要比第二晶片1〇2之面積大許多。例 鲁如：一般快閃記憶體之面積，即第一晶片101之面積多為7xl2mm 或10x16mm左右，但控制晶片之面積，即第二晶片1〇2之面積則 多為3x3mm左右，當需要由第二晶片1〇2之上表面打線至引腳架 103a時，由於第二晶片1〇2與引腳103a間之距離太遠，打線技術 使用之導線細，最長之打線距離有所限制，如果打線距離太長將可 能導致導線塌落或偏移，導致封裝良率降低。一般而言，雖然使用 較粗之導線能延長打線距離，惟，考慮可靠度、產品壽命等問題， 業界打線距離多以4.5mm左右作限制為佳。 馨 然而’雖可於第二晶片1〇2與引腳l〇3a之間的第一晶片ιοί 上表面另設置一基板，以分段打線的方式，利用導線使第二晶片 102先電性連接至該基板，再利用導線使該基板與引腳1〇3a作電 性連接，但由於基板與晶片之材質迥異，因此熱膨脹係數具有相當 大的差異，一般而言，晶片的熱膨脹係數在23ppm/〇c左右，而基 板的熱膨脹係數則約為18ppm/°C，因此當溫度出現變化時，堆疊 晶體之打線封裝結構10則可能因不一致的熱膨脹效應而出現變形 的現象，同時於基板上產生一剪應力以使得基板達到一降伏點 (yield point)而產生破裂，進而對堆疊晶體之打線封裝結構1〇產生 嚴重的破壞。 6 M343914 再者，當然亦能以覆晶封裝即可解決前述問題，惟覆晶封裝之 成本高達打線封裝之數倍，實際上多運用於高階、複雜之封裝。 因此，確有必要提供一種堆疊晶體之打線封裝結構，能利用一 橋接晶片，當堆疊晶片面積差異大時，仍能使用堆疊晶體之打線封 裝結構之可行性。 【新型内容】M343914 VIII. New Description: [New Technology Field] This paper is about a wire-wound package structure for stacked crystals, especially for a wire-bonding package structure with a stacked crystal of a bridged wafer. [Prior Art] Nowadays, since various electronic products have gradually become smaller, lower-cost, high-efficiency, and higher in number of feet, the customer-made system is formed by stacking chips of various wafers (Die) in the package structure. The packaging structure is a wave of main trends in the package structure. Since the known slotted package on package (PoP) structure has the characteristics of being compatible with various component architectures, it can provide good configuration flexibility in the package structure; and again, due to the single package in the stacked package structure. The layer can be fully tested before stacking', so it can also greatly improve the yield of the overall package structure. Therefore, today's packaging industries make extensive use of stacked packages as a major package structure. Φ Referring to FIG. 1 is a schematic view of a wire-wound package structure 10 of a conventional stacked crystal. As shown in FIG. 1 , a conventional stacked crystal wire-bonding package structure 1 includes a first wafer 101 and a second wafer 102. a lead frame 1〇3, a plurality of wires 104al04b, wherein the first wafer 101 can be a flash memory, and the second wafer 1〇2 can be a control wafer, and the stacked crystal wire package structure 10 still has The lead frame 103a on the left side and the lead frame 1〇3b on the right side. The first wafer 1〇1 is adhered to the upper surface of one of the wafer pads (not shown) by the adhesive (Epoxy Glue) 105a. The second wafer 1〇2 is adhered by an adhesive (Ep〇xy Glue)1〇5b, stacked on the upper surface of the first wafer ιοί, and then by wire B〇nding 5 M343914 technology, using the wire 104a L〇4b electrically connects the first wafer 1 (the second wafer 1 2, the wire holder 103, and the lead frames 10a, 3b, 3b) so that the stacked crystals are wound in the package structure 10, Externally, the electrical connection is completed, and the electrical signal is transmitted. However, as shown in FIG. 1 , the first wafer 1 〇 1 and the second wafer 1 〇 2 can be made by the wire 104b on the right side of the wire-bonding package structure 1 of the stacked crystal. The lead frame i〇3b is electrically connected; however, the wire-wrap structure of the stacked crystal 1 is on the left side, but the second chip 102 and the lead frame 103a cannot be electrically connected by the wire 10, the main reason is that The area of the first wafer 101 is much larger than the area of the second wafer 1 。 2. For example, the area of the general flash memory, that is, the area of the first wafer 101 is about 7 x 12 mm or about 10 x 16 mm, but the area of the control wafer is That is, the area of the second wafer 1〇2 is about 3x3mm, when needed When the upper surface of the second wafer 1〇2 is wired to the lead frame 103a, since the distance between the second wafer 1〇2 and the lead 103a is too far, the wire used in the wire bonding technique is thin, and the longest wire distance is limited. If the wire distance is too long, it may cause the wire to collapse or shift, resulting in a decrease in the package yield. Generally speaking, although the use of thicker wires can extend the wire distance, considering the reliability, product life and other issues, the industry is working. The distance is preferably limited to about 4.5 mm. However, the substrate may be provided with a substrate on the upper surface of the first wafer ιοί between the second wafer 1〇2 and the pin 〇3a, in a segmented manner. The second wafer 102 is electrically connected to the substrate by using a wire, and the substrate is electrically connected to the lead 1〇3a by using a wire. However, since the material of the substrate and the wafer are different, the coefficient of thermal expansion has a considerable difference. In general, the thermal expansion coefficient of the wafer is about 23 ppm/〇c, and the thermal expansion coefficient of the substrate is about 18 ppm/°C. Therefore, when the temperature changes, the wiring structure of the stacked crystal 10 may not be The deformation phenomenon occurs due to the thermal expansion effect, and a shear stress is generated on the substrate to cause the substrate to reach a yield point to cause cracking, thereby causing severe damage to the wire-wound package structure of the stacked crystal. 6 M343914 Furthermore, of course, the above problems can be solved by flip chip packaging, but the cost of the flip chip package is up to several times that of the wire package, and is actually applied to high-order and complicated packages. Therefore, it is necessary to provide a stacked crystal. The wire-bonding structure can utilize a bridged wafer, and when the difference in the area of the stacked wafers is large, the feasibility of using the stacked crystal wire-bonding structure can still be used. [New content]
為解決上述問題，本創作之主要目的係提供一種堆疊晶體之打 線封裝結構，利用一橋接晶片，當堆疊之晶片面積差異大時，仍能 適用於打線技術封裝。 根據本創作之主要目的，提供一種堆疊晶體之打線封裝結構， 包含一第一晶片，一第二晶片以及一第三晶片，第一晶片設置於一 導線架上，與堆疊晶體之打線封裝結構外部作電性連接。第二晶片 設置於第一晶片之上表面與第一晶片作電性連接，用以控制第一晶 片與堆疊晶體之打線封裝結構外部作電性連接之動作。第三晶片亦 設置於第一晶片之上表面，與第二晶片作電性連接，以使第二晶片 與接近第三晶片之堆疊晶體之打線封裝結構外部作電性連接。 是以，藉由本創作之堆疊晶體之打線封裝結構，能利用一橋接 晶片，當堆疊之晶片面積差異大時，仍能適用於打線技術封裝。 然而，為讓本創作之上述目的、特徵、和優點能更明顯易懂， 下文特舉幾個較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 請參考第2圖，為根據本創作實施例之堆疊晶體之打線封裝結 構20示意圖。如圖中所示，本發明之堆疊晶體之打線封裝結構20 包含一第一晶片201、一第二晶片202、一第三晶片206、一導線 M343914 架203以及複數條導線204a、204b、204c，堆疊晶體之打線封裝結 構20尚具有位於左侧之引腳架203a以及位於右側之引腳架203b， 引腳架203a、203b係用以電性連接至設置於堆疊晶體之打線封裝 結構20外部之電子元件或電路板（未顯示）。第一晶片201可為一 快閃記憶體，利用黏著劑205a黏著於導線架203之上表面，並藉 由打線（Wire Bonding)技術，利用導線204a、204c使第一晶片201 與引腳架203a、203b作電性連接，使第一晶片201可經由導線 204a、204c與堆疊晶體之打線封裝結構20外部進行電氣訊號之傳 遞。 第二晶片202可為一控制晶片，且利用黏著劑205b黏著、堆 疊於第一晶片201上表面，藉由打線技術，利用導線204c使第二 晶片202與第一晶片201作電性連接，用以控制第一晶片201與堆 疊晶體之打線封裝結構20外部作電性連接之動作。 第三晶片206為一内部僅具有複數條傳導線之一橋接晶片。第 三晶片206利用黏著劑205c黏著、堆疊於第一晶片201之上表面， 藉由打線技術，利用導線204b，使第二晶片202與第三晶片206 作電性連接。再著，藉由打線技術利用導線204a，使第三晶片206 與第一晶片201間、第三晶片206與引腳架203a間作電性連接， 從而使第二晶片202與接近第三晶片206之引腳架203a作電性連 接。使得第三晶片206能透過第三晶片206、引腳架203a之橋接 與堆疊晶體之打線封裝結構20外部之電子元件或電路板作電性連 接。 綜上所述，即便堆疊晶體之打線封裝結構20中第一晶片 201(快閃記憶體）與第二晶片202 (控制晶片）兩者之面積差異太 大，仍可藉由本創作之第三晶片206以達到完整之電性連接，且由 於第三晶片206之材質係與第一晶片201及該第二晶片202之材質 8 M343914 相同，當溫度出現變化時，該等晶片均具有一致的熱膨脹效應，因 此不易使得堆疊晶體之打線封裝結構20出現變形的現象，進而提 高堆疊晶體之打線封裝結構20之可靠度以及使用壽命。再者，第 三晶片206主要係作為第二晶片202與較遠一侧之引腳架203a間 之橋接，當堆疊晶片面積差異大時，利用分段打線之方式縮短打線 距離，實現本創作堆疊晶體之打線封裝結構20。又，第三晶片206 係作橋接用途，無需複雜線路，因此第三晶片206的製程可以採用 較低技術的晶圓製程，無須採用昂貴之覆晶封裝，進而降低封裝成 【圖式簡單說明】 第1圖係繪示習知堆疊晶體之打線封裝結構示意圖。 第2圖係繪示根據本創作實施例之堆疊晶體之打線封裝結構 示意圖。 【主要元件符號說明】In order to solve the above problems, the main purpose of the present invention is to provide a wire-packaging structure for stacked crystals, which can be applied to a wire-bonding technology package when a stacked wafer area is large. According to the main object of the present invention, a wire bonding package structure for stacking a crystal includes a first wafer, a second wafer and a third wafer. The first wafer is disposed on a lead frame and is external to the wire-bonding package structure of the stacked crystal. Make an electrical connection. The second wafer is electrically connected to the first wafer on the upper surface of the first wafer for controlling the electrical connection between the first wafer and the wiring structure of the stacked crystal. The third wafer is also disposed on the upper surface of the first wafer, and is electrically connected to the second wafer to electrically connect the second wafer to the outside of the wire-bonding package structure of the stacked crystals adjacent to the third wafer. Therefore, with the wire-wrapping structure of the stacked crystal of the present invention, a bridge wafer can be utilized, and when the wafer area of the stack is large, it can still be applied to the wire bonding technology package. However, in order to make the above objects, features, and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings are described below. [Embodiment] Please refer to Fig. 2, which is a schematic view of a wire bonding package structure 20 of a stacked crystal according to the present embodiment. As shown in the figure, the wire bonding package structure 20 of the stacked crystal of the present invention comprises a first wafer 201, a second wafer 202, a third wafer 206, a wire M343914 frame 203, and a plurality of wires 204a, 204b, 204c. The wire package structure 20 of the stacked crystal has a lead frame 203a on the left side and a lead frame 203b on the right side. The lead frame 203a, 203b is electrically connected to the outside of the wire package structure 20 disposed on the stacked crystal. Electronic component or board (not shown). The first wafer 201 can be a flash memory, adhered to the upper surface of the lead frame 203 by an adhesive 205a, and the first wafer 201 and the lead frame 203a are made by wires 204a, 204c by wire bonding technology. 203b is electrically connected to enable the first wafer 201 to transmit electrical signals via the wires 204a, 204c and the wiring package structure 20 of the stacked crystal. The second wafer 202 can be a control wafer, and is adhered and stacked on the upper surface of the first wafer 201 by an adhesive 205b. The second wafer 202 is electrically connected to the first wafer 201 by using a wire 204c. The action of electrically connecting the first wafer 201 to the outside of the wire bonding package 20 of the stacked crystal is controlled. The third wafer 206 is a bridge wafer having only one of a plurality of conductive lines inside. The third wafer 206 is adhered to the upper surface of the first wafer 201 by the adhesive 205c, and the second wafer 202 and the third wafer 206 are electrically connected by the wire bonding technique using the wire 204b. Then, the wire 204a is used to electrically connect the third wafer 206 and the first wafer 201, and between the third wafer 206 and the lead frame 203a, so that the second wafer 202 and the third wafer 206 are close to each other. The lead frame 203a is electrically connected. The third wafer 206 can be electrically connected to the electronic component or circuit board outside the wire-bonding package structure 20 of the stacked crystal through the bridge of the third wafer 206 and the lead frame 203a. In summary, even if the area difference between the first wafer 201 (flash memory) and the second wafer 202 (control wafer) in the wire bonding package structure 20 of the stacked crystal is too large, the third wafer of the present invention can still be used. 206 to achieve a complete electrical connection, and since the material of the third wafer 206 is the same as that of the first wafer 201 and the second wafer 202, 8 M343914, the wafers have a uniform thermal expansion effect when the temperature changes. Therefore, it is difficult to cause the deformation of the wire-bonding package structure 20 of the stacked crystal, thereby improving the reliability and the service life of the wire-bonding package structure 20 of the stacked crystal. Furthermore, the third wafer 206 is mainly used as a bridge between the second wafer 202 and the lead frame 203a on the far side. When the difference in the area of the stacked wafer is large, the wire bonding distance is shortened by means of segmented wire bonding, thereby realizing the creative stacking. The wire bonding structure 20 of the crystal. Moreover, the third wafer 206 is used for bridging purposes, and no complicated wiring is required. Therefore, the third wafer 206 can be processed by a lower-tech wafer process without using an expensive flip chip package, thereby reducing the package into a simple description. FIG. 1 is a schematic view showing the structure of a wire bonding package of a conventional stacked crystal. 2 is a schematic view showing a wire bonding package structure of a stacked crystal according to the present embodiment. [Main component symbol description]
10、20 101 > 201 102 、 202 103 > 203 103a、103b、203a、203b 堆疊晶體之打線封裝結構 第一晶片 第二晶片 導線架 引腳架 104a ' 104b、204a、204b ' 204c 導線 105a、105b、205a、205b、205c 黏著劑 206 第三晶片10, 20 101 > 201 102 , 202 103 > 203 103a, 103b, 203a, 203b wire bonding package structure for stacking the first wafer second wafer lead frame lead frame 104a '104b, 204a, 204b' 204c wire 105a, 105b, 205a, 205b, 205c adhesive 206 third wafer