TWM305963U - Ball grid array package structure - Google Patents

Ball grid array package structure Download PDF

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Publication number
TWM305963U
TWM305963U TW095212417U TW95212417U TWM305963U TW M305963 U TWM305963 U TW M305963U TW 095212417 U TW095212417 U TW 095212417U TW 95212417 U TW95212417 U TW 95212417U TW M305963 U TWM305963 U TW M305963U
Authority
TW
Taiwan
Prior art keywords
substrate
ball grid
grid array
package structure
wafer
Prior art date
Application number
TW095212417U
Other languages
Chinese (zh)
Inventor
Cheng-Pin Chen
Wen-Jeng Fan
Li-Chih Fang
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW095212417U priority Critical patent/TWM305963U/en
Publication of TWM305963U publication Critical patent/TWM305963U/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

M305963 八、新型說明: 【新型所屬之技術領域】 本創作係有關一種半導體封裝結構,特別是提供一種球拇__ grid array,BGA)封裝結構。 【先前技術】 1C構裝係屬半導體產業的後段加工製程,可分為晶圓切割、 • 黏晶、銲線 '封膠、印字、包裝,主要是將前製程加工完成晶圓 上1C予以分割成晶片,黏晶、並加上外接引腳及包覆。而其封 裝體主要是提供一個引接的介面,内部電性訊號亦可透過封裝材 料將t連接到系統,並提供晶片免於受外力與水、濕氣、化學物 之破壞與腐#等並增加其機械性質。 封膠過程中,模具係置於具有半導體晶片或電子元件之基板上,再將 液邊封裝材料注入模具之模穴中,使封裝材料密封住基板上晶片或電子元 件以形成-完全氣密之封膠體,待封膠體硬化之後再進行賴完成封膠製 程。 _ 然而’隨著薄形封裝技術的發展,薄形基板面積大且厚度薄,由於封 裝基板與封裝材料間的熱膨脹係數不同,於封膠(molding)或洪烤(师 molding cure)製程中,隨溫度變化而產生不同膨服量或收縮量容易導致 封I基板產生應力而翹曲(warpage)影響後續製程,如背印製程(B射 process)去框製私與熱猶環試驗(她柯故肌〇 更甚者’ _翹曲過大則會使其内晶片破裂(_k)或電子元件損壞。有 鑑於此,如何克服上述問題解決封裝製程中基板的赵曲問題以艮重要的。 M305963 【新型内容】 有紐此,本創作係針對上述之困擾,提出 之強化凸塊改善基板結構強度之球柵陣列封裝結構。㈣版·成 本創作目的之-係提供一種球拇陣列封裝結 烘烤製程中基板的翹曲變形。 政減乂封衣 化凸目==編—種瓣麵結構,躺基板底部強 化凸塊之使用,強化基板構強度,可戦於封絲財因溫度變化導 致封裝基板產生應力而翹曲(warpage)影響後續製程。M305963 VIII. New Description: [New Technology Field] This creation is about a semiconductor package structure, in particular, a ball __ grid array (BGA) package structure. [Prior Art] 1C structure belongs to the semiconductor industry's back-end processing process, which can be divided into wafer cutting, • die bonding, wire bonding 'sealing, printing, packaging, mainly to divide the 1C on the wafer before the pre-process processing. Form the wafer, bond the crystal, and add external pins and cladding. The package mainly provides a lead-in interface, and the internal electrical signal can also connect t to the system through the packaging material, and provide the wafer from external force and water, moisture, chemical damage and rot # and increase Its mechanical properties. During the encapsulation process, the mold is placed on a substrate having a semiconductor wafer or an electronic component, and the liquid-side encapsulating material is injected into the cavity of the mold to seal the wafer or electronic component on the substrate to form a completely airtight The encapsulant is subjected to a sealing process after the gel is hardened. _ However, with the development of thin packaging technology, the thin substrate has a large area and a thin thickness. Due to the difference in thermal expansion coefficient between the package substrate and the packaging material, in the molding or molding process, Different expansion or shrinkage with temperature changes can easily lead to stress on the I substrate and warpage affects subsequent processes, such as the back-print process (B-process) to frame the private and thermal loop test (she Ke Therefore, even if the tendon is too large, the inner wafer will be broken (_k) or the electronic components will be damaged. In view of this, how to overcome the above problems to solve the problem of the substrate in the packaging process is important. M305963 The new content] In this case, the author proposes a ball grid array package structure that enhances the structural strength of the substrate by reinforcing the bumps. (4) Edition·The purpose of cost creation is to provide a ball thumb array package baking process The warpage deformation of the middle substrate. The reduction of the 乂 乂 化 = = = = 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编 编The change causes stress on the package substrate and warpage affects subsequent processes.

為了 it到上述目的,本創作—實_之球柵陣列職結構,包 括· 一基板,其巾基板上表面係具狂少—晶片承載區取基板下表面設 有稷數個電性接點;複數個晶片,係設置於⑼承載區域上料性連接電 ^接點/複數m孔,係貫穿基板並設置於⑼承倾域之周緣;一封裝 賴,係包覆晶片填滿通孔並於基板下表面形成一強化凸塊於晶片承載區 域周緣;以及複數個導電球,係分別設置於電性接點上。 底下藉由具體實施例配合所附的圖式詳加說明,當更容易瞭解本創作 之目的、技術内容、特點及其所達成之功效。In order to achieve the above purpose, the creation-real ball grid array structure includes: a substrate, the upper surface of the towel substrate is mad--the wafer bearing area is provided with a plurality of electrical contacts on the lower surface of the substrate; The plurality of wafers are disposed on the (9) load-bearing area of the load-bearing connection/multiple m-holes, which are penetrated through the substrate and disposed on the periphery of the (9) bearing-dipping domain; a package is coated with the wafer to fill the through-hole and The lower surface of the substrate forms a reinforcing bump on the periphery of the wafer carrying region; and a plurality of conductive balls are respectively disposed on the electrical contacts. The purpose of the present invention, the technical content, the features, and the effects achieved by the present invention will be more readily understood by the specific embodiments and the accompanying drawings.

【實施方式】 —第1圖所示為根據本創作球栅陣列封裝結構一實施例之剖面示意圖, 如第1圖所示,於本實施例中,此球栅陣列封裝結構包括:一基板1〇,基 板10上表面係具有至少一晶片承載區域(圖上未標示)且基板1〇下表面 設有複數電性接點30 ;複數個晶片20,係設置於晶片承載區域上且電性 連接笔生接點3〇 ;複數個通孔μ,係貫穿基板1〇並設置於晶片承載區域 之周緣;一封裝膠體40,係包覆晶片20填滿通孔16並於基板10下表面 形成一強化凸塊42於晶片承載區域周緣;以及複數個導電球32,係分別 設置於電性接點30上。 M305963 ,於上=實施例中,基板10之材質係為聚亞醯胺(Pdynmde)、破璃、 氧化*呂環氧树脂、氧化鈹與彈性物(el搶露)之任一為主要構成 另,封裝膠體40之材質係由環氧樹脂(epGxy)為主要構成材料,電性拉 點30係為金屬材質之薛墊,而導電球32係為導電錫球。 接績上述說明,第2圖所示為根據本創作球柵陣列封裝 實施例之仰視示意圖,而第i圖係為第2圖之从剖線之剖面示相: 第2圖所不,於本實施例中,封裝膠體填滿通孔“於基板忉 面形成強化凸塊42,強化凸塊42係位於晶片承倾域12之周^[Embodiment] FIG. 1 is a cross-sectional view showing an embodiment of a ball grid array package structure according to the present invention. As shown in FIG. 1 , in the embodiment, the ball grid array package structure includes: a substrate 1 The upper surface of the substrate 10 has at least one wafer bearing area (not shown) and the lower surface of the substrate 1 is provided with a plurality of electrical contacts 30; the plurality of wafers 20 are disposed on the wafer carrying area and electrically connected The plurality of through holes μ are formed through the substrate and disposed on the periphery of the wafer carrying region; an encapsulant 40 is filled with the through holes 16 and formed on the lower surface of the substrate 10 The reinforcing bumps 42 are on the periphery of the wafer carrying region; and a plurality of conductive balls 32 are respectively disposed on the electrical contacts 30. M305963, in the above embodiment, the material of the substrate 10 is any one of polydecylamine, glaze, oxidized ruthenium epoxy resin, ruthenium oxide and elastomer (el robbing). The material of the encapsulant 40 is mainly composed of epoxy resin (epGxy), the electrical pull point 30 is a metal material, and the conductive ball 32 is a conductive tin ball. According to the above description, FIG. 2 is a bottom view of the embodiment of the ball grid array package according to the present invention, and the i-th image is a cross-sectional view of the cross-sectional line of FIG. 2: FIG. In the embodiment, the encapsulant fills the via hole to form a reinforcing bump 42 on the surface of the substrate, and the reinforcing bump 42 is located on the periphery of the wafer substrate 12

於封裝膠體區域14之範圍内,此強化凸塊42係由複數個條狀凸塊 所構成。通孔16之形狀可呈圓形、橢圓形、多邊形、條形( ; 或具多弧度之形狀。 第3圖與第4圖所示為根據本創作球柵陣列封裝結構不同實施例之 ,示意圖,如第3圖所示,於本實施例中,此強化凸塊42係、由複數個 ®形條狀凸塊所構成。請參閱第4圖所示,於本實施例中,此強化凸 塊42則是依L形條狀凸塊所構成。於本創作中,晶片係利用—细 間距球栅陣列封裝技術、-超細間距球柵陣列封裝技術、—微型球拇陣列 封裝技術與-窗口贿栅_縣技狀任—設置於⑼承賴域η上。 本創作所揭示之球栅陣列封裝結構,於封裝顧灌膠時,基板及晶 片係置入-模穴中進行壓模灌膠,然後,將封裝勝體注入此模穴中 ^裝膠體將“與基板包覆並露出基板下表面的電性接點,且此封裝膠體 牙過填滿每-通纽滿在蝴朗,接著進行轉(eurmg)步雜封裝膠體 5完全,硬化後將其取出,此時穿設在通孔的封裝膠體則基板下表面形 成強化凸塊’之後將複轉電球設置於基板下表面並分職性連接至每一 電性接點,如此即完成此球柵陣列封裝結構的製程。 綜合上述,本創作利用封裝膠體所形成之強化凸塊改善基板結構 強度’可有效減少職烘烤製財基㈣祕變形,並齡基板底部強 匕凸塊之使用5!化基板的結構強度,可避免於封裝製程中因溫度變化導 7 M3 05963 致封衣基板產生應力而魅曲(warpage)影響後續製程。本創作之強化 凸塊係由壓模灌膠時之封裝膠體形成,可在既有封裝製程中同時 凡成,無須增加製程或是額外之成本花費,在提高良率之外亦可 降低生產成本。 以上所述之實施例僅係為說明本創作之技術思想及特點,其 1的在使熟習此項技藝之人士能夠瞭解本創作之内容並據以實 苑’當不能以之限定本創作之專利範圍,即大凡依本創作所揭示 之精神所作之均等變化或修飾,仍應涵蓋在本創作之專利範圍 【圖式簡單說明】 第1圖所示為根據本創作球栅陣列封裝結構—實施例之剖面示意圖。 第2圖所示為根縣創作球柵_«結構另-實施例之仰視示意圖。 弟3圖所示為根據本創作球柵_封裝結構又-實施例之仰視示意圖。 弟4圖所示為根據本創作球__錄構再-實施例之仰視示意圖。 【主要元件符號說明】 10基板 12 晶片承載區域 14 封裝膠體區域 16 通孔 20晶片 30電性接點 32 導電球 40封裝膠體 1強化凸塊Within the scope of the encapsulation colloid region 14, the reinforcing bumps 42 are comprised of a plurality of strip bumps. The shape of the through hole 16 may be a circular shape, an elliptical shape, a polygonal shape, a strip shape (or a shape having a plurality of radians). FIGS. 3 and 4 show different embodiments according to the present inventive ball grid array package structure. As shown in FIG. 3, in the present embodiment, the reinforcing bump 42 is composed of a plurality of TM strip bumps. Referring to FIG. 4, in the embodiment, the reinforcing bump is used. Block 42 is formed by L-shaped strip bumps. In this creation, the wafer system utilizes fine pitch ball grid array packaging technology, ultra-fine pitch ball grid array packaging technology, micro-ball thumb array packaging technology and The window bribe _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Glue, then, the packaged body is injected into the cavity, and the colloid will "cover the electrical contact with the substrate and expose the lower surface of the substrate, and the encapsulant of the encapsulation is filled with each pass-through." Then, the eurmg step is used to enclose the encapsulant 5 completely, and after hardening, it is taken out. The encapsulating colloid of the through hole forms a reinforcing bump on the lower surface of the substrate, and then the re-turning electric ball is disposed on the lower surface of the substrate and is connected to each electrical contact in a divided manner, thereby completing the process of the ball grid array package structure. In the above, the present invention utilizes the reinforced bump formed by the encapsulant to improve the structural strength of the substrate, which can effectively reduce the deformation of the base of the baking system, and the structural strength of the substrate can be improved by using a strong bump at the bottom of the substrate. Avoid the temperature change in the packaging process. 7 M3 05963 causes the sealing substrate to generate stress and the warpage affects the subsequent process. The reinforced bump of this creation is formed by the encapsulant during the molding of the glue, which can be In the packaging process, it is not necessary to increase the process or additional cost, and the production cost can be reduced in addition to the improvement of the yield. The embodiments described above are only for explaining the technical idea and characteristics of the creation, In order to enable those who are familiar with the art to understand the content of this creation and according to the real garden, it is not possible to limit the scope of the patent of this creation, that is, the disclosure of the original by this creation The equivalent changes or modifications made by God should still be covered by the patent scope of this creation [Simple Description of the Drawings] Figure 1 is a schematic cross-sectional view of the ball grid array package structure according to the present embodiment. Root County creates a ball grid _«Structure and another embodiment of the bottom view. The brother 3 shows a schematic view of the ball grid _ package structure according to the present embodiment. The brother figure 4 shows the ball according to the creation __ The bottom view of the recording re-implementation. [Main component symbol description] 10 substrate 12 wafer bearing area 14 encapsulation colloid area 16 through hole 20 wafer 30 electrical contact 32 conductive ball 40 encapsulant colloid 1 reinforcement bump

Claims (1)

M305963 九、申請專利範圍: 1. 一種球柵陣列封裝結構,包含: 設ίίί個板上絲係具有至少"'晶片承_域脑基板下表面 複數個晶#,係設置承倾域± 複=?貫穿該基板並設置於該晶片== 複數個導電球,係分別設置於該些電性接點上。 構成Λ。1 、氧化銘、環氧樹脂、氧化鈹與彈性物之至少任-所 3· ㈣1娜⑽卩蝴㈣構,㈣些電性接點 觀孔之形 5. ==旨==編陣列封裝結構,其™ 球柵陣列封裝結構,其中該強化凸塊 7:===r 9· 與—㈣球柵 9M305963 IX. Patent application scope: 1. A ball grid array package structure, comprising: 设 ί 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 ' ' 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑 脑=? Through the substrate and disposed on the wafer == a plurality of conductive balls are respectively disposed on the electrical contacts. Constitute. 1. Oxidation, epoxy resin, yttria and elastomers at least - (3) 1 Na (10) 卩 butterfly (four) structure, (4) some electrical contact points of the shape of the hole 5. = = purpose = = array array structure , a TM ball grid array package structure, wherein the reinforcement bump 7: ===r 9· and - (4) ball grid 9
TW095212417U 2006-07-14 2006-07-14 Ball grid array package structure TWM305963U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI567891B (en) * 2015-01-30 2017-01-21 矽品精密工業股份有限公司 Whole layout structure of package substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI567891B (en) * 2015-01-30 2017-01-21 矽品精密工業股份有限公司 Whole layout structure of package substrate

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