M273083 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種晶片封裝結構改良，特別指一種具 有接地及屏蔽結構且可作為電源面，而能降低電氣雜訊干 擾，並増進穩定性及速率之晶片封裝結構改良。 【先前技術】 任何電子產品在運作使用時，均會產電磁波干擾（M273083 8. Description of the new type: [Technical field to which the new type belongs] This creation relates to the improvement of a chip package structure, especially a grounding and shielding structure that can be used as a power source surface, which can reduce electrical noise interference and improve stability and Improved chip package structure. [Previous technology] When any electronic product is in operation, it will generate electromagnetic wave interference (
Electromagnetic Interference，EMI)、雜訊（Noise，包括 如散彈雜訊、閃爍雜訊、突波雜訊、熱雜訊、分配雜訊等 )及高溫等情形，其中大部分雜訊的產生，係源於電磁波 干擾的情況’因而影響電子系統的穩定性；惟電磁波干擾 並不能完全克服，係必需透過該電子元件適當的電路規化 或屏蔽、接地等結構設計，使電磁波干擾降低至標準數值 之下，以達成電磁相容設計目的。 習知的封裝晶片結構，通常為一晶墊上置設有一晶片 ’於§亥晶片兩側設有可對外導通電性之導線架，其中該導 線架係為複數引腳排列構成，俾選定於晶片其接點及導線 _ 架之複數引腳間設有金線連接，並於該晶片外部設有一絕 緣性的封膠體，藉該封膠體保護晶片、金線等内部元件， 同時達成固定作用。上揭習知的晶片封裝結構，並無防止 電磁波干擾之結構設計，因此在降低電磁波干擾目的下， 即難以符合現今電子產品其電磁相容之高標準要求。 【新型内容】 本創作主要目的，係在提供一種晶片封裝結構改良， 特別係藉以晶片整體封裝結構改良，俾達成電氣雜訊隔絕 、降低電磁波干擾、增進穩定性及傳輸速率等效果。 依上述目的，本創作之實施内容包括晶片、導線架、 5 M273083 導線、黏著層及導體層等所組成，令一外部具有封膠體勺 覆之晶片，於該晶片二側或四周設有複數引腳排列構= 導線架，令各引腳内接電端以導線與晶片作電性連接， 其外接電端係彎折延伸至封膠體外部下方，並選定各排而 腳頂面或底面或二面設有-黏著層，藉該黏著=定3 體層，令該導體層由引腳内接電端延伸覆蓋至外接電端， 並另設有一導電體與晶片或任意一引腳作電性連接，使节 導體層成為降低電氣干擾之屏蔽結構及接地面或電源面了 俾達成電氣雜訊隔絕、降低電磁波干擾、電磁相容^以及 | 能增進穩定性及速率之效果。 【實施方式】 茲依附圖實施例將本創作之結構特徵及其他之作用、 目的詳細說明如下： 如附圖所示，本創作所為之『晶片封裝結構改良』，係 包括晶片1、導線架2、導線3、黏著層4及導體層5等 所組成，其中： 晶片1，如第一圖及第二圖所示，係為習知半導體材 料所製成之電子元件，於選定面設有複數電訊接點1彳，藉 > 電訊接點11經由下述導線架2可與外界作電性連接，其外 圍並設有一絕緣性封膠體12包覆密封； ^ 導線架2，如第一圖、第三圖及第四圖所示，係為金 屬材料沖壓呈二排平行或四排矩陣陣列之複數條狀引腳21 所構成，各引腳21分別具有一内接電端211，以及一彎折狀 之外接電端212，藉該内接電端21彳可與晶片丄之電訊接點 11電性連接，而外接電端212可與外界電路板等設備作電性 連接； 導線3，如第一圖所示，係使該晶片工之電訊接點仞 可與導線架2各引腳21内接電端211形成電性連接之金屬 M273083 導體，例如金線等； 4著層4 ’ |閱第二圖所示’係可為—種液態乾燥後 可形成黏固之物質（膠水等）或膠帶等，並具有絕緣特性 者； 導體層5，如第-圖所示，係可為一片狀金屬板或金 屬膜，並令其構成可覆蓋導線架2各排引腳21頂面或底面 之彎折片結構； 藉此，參閱第一圖及第二圖所示，令該外部具有封膠 體12包覆之晶>；χ二側或四周設有複數引腳21排列構成之 導線架2，令各引腳21内接電端21彳分別以以導線3與晶片 1之電訊接點11作電性連接，而其外接電端2彳2係彎折延伸 至封膠體12外部下方，並選定該導線架2各排引腳^頂面 設有一黏著層4，藉該黏著層4固定一導體層5，使該導 體層5由引腳21頂面内接電端211整片延伸覆蓋至外接電 端212,並於導體層5另設有—導電體5彳（例如使用金線或 令該導體層5設-凸部作連接）與晶片i之電訊接點⑴戈 任意一引腳21作電性連接，使該導體層5成為降低電氣干 擾之屏蔽結構及接地面（Ground plane)或電源面（powe「 plane)’俾達成本創作封裝晶片之電氣雜訊隔絕、降低電 磁波干擾、電磁相容，以及能增進穩定性及速率之效果。 請參閱第五圖所示，本創作亦可僅選定各排引腳21底 面设有一黏著層4，藉該黏著層4固定一導體層5，使該 導體層5由引腳21底面内接電端211整片延伸覆蓋至外接 電端212,並於導體層5另設有一導電體μ與晶片丄之電訊 接點11或任意一引腳21作電性連接，使該導體層5成為降 低電氣干擾之屏蔽結構及接地面（Grounc| plane)或電源 面（Power plane)。或如第六圖所示亦可同時選定各排引 腳21頂面及底面設有一黏著層4，藉該黏著層4分別固定 M273083 211整片mm 及底面内接電端 ^ 申覆盍至外接電端2彳2 ’並於各個導體層$另設 有、一電體51與晶片；[之電訊接點11或任意_引腳21作電 性連接’使該導體層5成為降低電氣干擾之屏蔽結構及: 地面（Ground plane)或電源面（Power plane)，以、 上述之功效。 适成 另者，請參閱第七圖所示，本創作該導體層5不以整 片延伸覆蓋於各排引腳21為限，亦可使導體層5構成為複 數條片狀，藉此分別覆蓋於各個引21之頂面、底面或頂面 及底面均加以覆蓋，且各片導體層5均與晶片丄之電訊接 點11或任意一引腳21作電性連接，使各導體層5成為降低 電氣干擾之屏蔽結構及接地面（Ground plane)或電源面 (Power plane)，亦能獲致相同效果。 綜上所述，本創作『晶片封裝結構改良』，已確具實用 性與創作性，其手段之運用亦出於新穎無疑，且功效與設 計目的誠然符合’已稱合理進步至明。為此，依法提出新 型專利申請，惟懇請鈞局惠予詳審，並賜准專利為禱， 至感德便。 M273083 【圖式簡單說明】 第一圖為本創作導體層覆蓋引腳頂面之立 第一圖為本創作導體層覆蓋引腳了貢 -二回 叫 < 斷面不意圖 第三圖為本創作導線架二排引腳之封裝之示意圖。 第四圖為本創作導線架四排引腳之封裝之示意圖。 第五圖為本創作導體層覆蓋引腳底面之斷面示意圖 第六圖為本創作導體層覆蓋引腳二面之斷面示意圖 〇 〇 第七圖為本創作導體層另一實施例之立體示意圖。 電訊接點11 ; 導線架2 ; 引腳21 ; 外接電端212 ; 黏著層4 ; 【主要元件符號說明】 晶片1， 封膠體1 2 ; 内接電端211 ; 導線3 ; 導體層5 ; 導電體51 ; 9Electromagnetic Interference (EMI), noise (including noise such as shot noise, flicker noise, surge noise, thermal noise, distribution noise, etc.) and high temperature. The situation caused by electromagnetic wave interference 'thus affects the stability of the electronic system; however, electromagnetic wave interference cannot be completely overcome. It is necessary to reduce the electromagnetic wave interference to a standard value through the appropriate circuit design or shielding, grounding and other structural design of the electronic component. To achieve the purpose of electromagnetic compatibility design. The conventional package chip structure usually includes a chip on a crystal pad, and a lead frame capable of external conductivity is provided on both sides of the chip. The lead frame is composed of a plurality of pin arrays, and is selected on the chip. The contacts and the plurality of pins of the lead frame are provided with gold wire connections, and an insulating sealing compound is provided outside the chip, and the chip, gold wires and other internal components are protected by the sealing compound, and at the same time, the fixing effect is achieved. The conventional chip packaging structure disclosed above does not have a structural design to prevent electromagnetic wave interference, so it is difficult to meet the high electromagnetic compatibility requirements of today's electronic products for the purpose of reducing electromagnetic wave interference. [New content] The main purpose of this creation is to provide a chip package structure improvement, especially to improve the overall package structure of the chip, to achieve electrical noise isolation, reduce electromagnetic interference, improve stability and transmission rate and other effects. According to the above purpose, the implementation content of this creation consists of a wafer, a lead frame, 5 M273083 wires, an adhesive layer and a conductor layer, etc., so that a wafer with an encapsulating gel coat on the outside is provided with multiple leads on or around the wafer. Pin arrangement = lead frame, so that the internal electrical terminals of each pin are electrically connected to the chip by wires, and the external electrical terminals are bent to extend below the outside of the sealing gel, and each row is selected with the top or bottom of the foot or two An -adhesive layer is provided on the surface, and the conductor layer is extended from the internal electrical terminal of the pin to the external electrical terminal by the adhesive layer, and a conductor is electrically connected to the chip or any pin. , Make the node conductor layer a shielding structure and ground plane or power plane to reduce electrical interference, achieve electrical noise isolation, reduce electromagnetic wave interference, electromagnetic compatibility ^ and | can improve the stability and speed effect. [Embodiment] The following describes the structural features and other functions and purposes of the creation in detail according to the embodiments of the drawings: As shown in the drawings, the "chip package structure improvement" for the creation includes the chip 1, the lead frame 2 , Conductor 3, adhesive layer 4 and conductor layer 5, etc., among which: Wafer 1, as shown in the first and second figures, is an electronic component made of conventional semiconductor materials. The telecommunication contact 1 彳, the telecommunication contact 11 can be electrically connected to the outside via the lead frame 2 described below, and an insulating sealing compound 12 is provided on the periphery of the telecommunication contact 11 to cover and seal; ^ the lead frame 2, as shown in the first figure As shown in Figures 3, 4 and 4, they are formed by punching metal materials into a parallel or quadruple matrix array of a plurality of strip pins 21, each of which has an internal electrical terminal 211, and a The bent external electrical terminal 212 can be electrically connected to the telecommunication contact 11 of the chip 借 through the internal electrical terminal 21, and the external electrical terminal 212 can be electrically connected to the external circuit board and other equipment; As shown in the first figure, it is the telecommunication contact of the chipmaker. A metal M273083 conductor, such as a gold wire, which can form an electrical connection with the electrical terminal 211 of each lead 21 of the lead frame 2; 4 layers 4 '| See the second figure' can be a liquid after drying Forms a solid substance (glue, etc.) or tape, etc., and has insulation properties; The conductor layer 5, as shown in the figure-can be a piece of metal plate or metal film, and its structure can cover the lead frame 2 The bent piece structure of the top surface or bottom surface of each row of pins 21; by this, referring to the first and second figures, the exterior is provided with a crystal encapsulated by the sealing compound 12 > A lead frame 2 having a plurality of pins 21 arranged so that each pin 21 is electrically connected to an electrical terminal 21 彳 by a wire 3 and a telecommunication contact 11 of a chip 1 for electrical connection, and an external electrical terminal 2 彳 2 is Bend to the outside of the sealing compound 12 and select the pins of each row of the lead frame 2. An adhesive layer 4 is provided on the top surface of the lead frame 2, and a conductor layer 5 is fixed by the adhesive layer 4 so that the conductor layer 5 is supported by the pins 21. The entire in-plane electrical terminal 211 extends to cover the external electrical terminal 212, and is additionally provided on the conductor layer 5-a conductor 5 彳 (for example, using gold wire or The conductor layer 5 is provided with a convex part for connection) and is electrically connected to any one of the pins 21 of the telecommunication contact of the chip i, so that the conductor layer 5 becomes a shielding structure and a ground plane or a power source for reducing electrical interference. The plane (powe "plane") is used to create the package's electrical noise isolation, reduce electromagnetic interference, electromagnetic compatibility, and improve stability and speed. Please refer to the fifth figure, this creation can only be An adhesive layer 4 is selected on the bottom surface of each row of pins 21, and a conductor layer 5 is fixed by the adhesive layer 4, so that the conductor layer 5 extends from the entire electrical terminal 211 in the bottom surface of the pin 21 to the external electrical terminal 212, and A conductive body μ is further provided on the conductive layer 5 to be electrically connected to the telecommunication contact 11 or any pin 21 of the chip 使, so that the conductive layer 5 becomes a shielding structure and a ground plane (Grounc | Power plane. Alternatively, as shown in the sixth figure, the top and bottom surfaces of each row of pins 21 can be selected at the same time and an adhesive layer 4 can be selected at the same time. The adhesive layer 4 can be used to fix the entire M273083 211 mm and the electrical terminals on the bottom surface. The electric terminal 2 彳 2 'is also provided on each conductor layer, an electric body 51 and a chip; [the telecommunication contact 11 or any of the _ pins 21 are electrically connected' makes the conductor layer 5 to reduce electrical interference Shielding structure and: Ground plane or Power plane, with the above-mentioned effects. It is suitable to refer to the seventh figure. In this creation, the conductor layer 5 is not limited to the entire piece extending to cover the rows of pins 21, and the conductor layer 5 can also be formed into a plurality of pieces, thereby respectively The top surface, bottom surface, or top and bottom surfaces of each lead 21 are covered, and each piece of the conductor layer 5 is electrically connected to the telecommunication contact 11 of the chip or any one of the pins 21, so that each conductor layer 5 Shielding structures and ground planes or power planes that reduce electrical interference can also achieve the same effect. In summary, the "Chip Package Structure Improvement" of this creation is indeed practical and creative, and the use of its means is novel and undoubted, and the efficacy and design purpose are indeed in line with it ', which has been said to be reasonable progress to the clear. To this end, a new patent application was submitted in accordance with the law, but Jun Bureau is kindly requested to review it carefully and grant the patent as a prayer. M273083 [Schematic description] The first picture shows the top surface of the conductor layer covered by the creative conductor. The first picture shows the conductor pin covered by the creative conductor layer. Create a schematic diagram of the package of the two rows of lead frames. The fourth figure is a schematic diagram of the packaging of the four-row pins of the lead frame. The fifth figure is a schematic diagram of the cross section of the creative conductor layer covering the bottom surface of the pin. The sixth figure is the schematic diagram of the cross section of the creative conductor layer covering the second surface of the pin. . Telecommunications contact 11; lead frame 2; pin 21; external electrical terminal 212; adhesive layer 4; [Description of main component symbols] Chip 1, sealant 12; internal electrical terminal 211; lead 3; conductor layer 5; conductive Body 51; 9