TWM244580U - Stack structure of chip package - Google Patents

Description

M244580

This new technology belongs to a chip packaging structure, and in particular, a stacked chip packaging structure. Previous technology k > ik integrated circuit (IC) process technology

The integration degree of the internal circuits of the Japanese and Japanese films (continuously rising upwards, thus greatly increasing the number of transistors in the internal circuits of IC chips, and gradually reducing the cross-sections of the internal circuits of IC chips f ° Therefore, when the IC chip is in operation, the internal circuit of the chip will generate a large amount of heat, which will cause the temperature of the 1C chip itself to continue to rise. It is worth noting that when the temperature of the IC chip itself exceeds In the normal operating temperature range, the internal circuit of the IC chip may be subject to calculation errors, temporary failure, or permanent damage. Therefore, IC packages (packages) must provide a medium for the external connection of the signal from the IC chip. 'It is also necessary to provide appropriate protection and good heat dissipation performance, so that the temperature of the IC chip in operation can be properly controlled to avoid exceeding its normal operating temperature range. Wireb ο nding is common ) Type of chip packaging structure and § 'In order to meet the needs of heat dissipation, the conventional technology is usually beneficial. Empty

A white die (dummy die) or a metal block with good thermal conductivity is used as the thermal conductive block, and the thermal block is stacked on the functional die to reduce the thermal conductivity of the functional die. Thermal impedance on the path, so that the thermal energy generated by the functional chip during operation,

I0387twf.ptd Page 8 M244580 5. Creation Instructions (2) It can be quickly conducted to the surface of the chip packaging structure and dissipated to the outside atmosphere. Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional stacked chip package structure. In terms of wire bonding (W / B) type chip packaging structure 1 0 0, 'chip packaging structure 1 0 0 mainly includes a carrier 1 1 0, a chip 1 2 0, a heat sink 1 3 0, a rubber Layer 1 40, multiple wires 150, and sealant 160. First, the “carrier 1 1 0” is, for example, a substrate (substrat; e) or a lead frame (here, the carrier no is represented by a substrate). The carrier 11 has a carrier surface 112 and a plurality of joints. Pads 114, and these bonding pads 114 are all disposed on the bearing surface 112 of the carrier Π0. In addition, the chip 120 has an active surface 122 and a corresponding back surface 1 2 4, and the chip 120 is attached to the carrier 1 1 0 with its back surface 1 2 4 and a glue layer 1 4 2. The bearing surface 1 1 2, and the wafer 1 2 0 further has a plurality of metal pads 126, which are disposed on the active surface 1 2 2 of the wafer 120. In addition, the heat sink block 130 is, for example, a blank wafer or a metal block with good thermal conductivity. The heat sink block 130 has a joint surface 1 32, and the heat sink block 130 uses its joint surface 132 and passes through another rubber layer. 140, and the active surface 1 2 2 attached to the wafer 120. Finally, these wires 1 50 are electrically connected to one of the metal pads 1 2 6 to one of the corresponding bonding pads 1 1 4 respectively, and the sealant 1 6 0 covers the chip 1 2 0 and the heat sink 1 30 and these wires 150. Please also refer to Figure 1 'under the influence of mechanical processing. The heat sink 1 30 usually has a rectangular cube shape, so that the joint surface 132 (that is, the bottom surface) of the heat sink 1 30 is usually orthogonal to the heat sink 130. Side 134 (that is, the angle between the joint surface 132 and the side 134 is usually 90 degrees), resulting in a heat sink

10387twf.ptd Page 9 M244580 V. Creative Instructions (3) The bottom periphery of 1 3 0 is prone to stress concentration. Therefore, when the chip package structure 100 is subjected to the rma 1 stress test, such as a Temperature Cycle Test (TCT) or a Thermal Shock Test (TST), due to the heat dissipation block itself, Generated repetitive heat; tension shrinkage and bending movement, so a stress concentration ring is generated at the bottom periphery of the heat sink 130, which will cause a protective layer (not shown) of the active surface 1 2 2 of the chip i 2 〇 The phenomenon of cracking may even destroy the wiring (not shown) under the protective layer, and then cause the function of the chip 丨 / 〇 to fail. Please refer to FIG. 1 as well. In order to improve the elastic buffering between the wafer 12 and the heat sink 13o, it can be achieved by increasing the thickness of the rubber layer 4o. It should be noted that because the thermal impedance coefficient of the rubber layer 140 is greater than the thermal impedance coefficient of 埶 130, increasing the thickness of the rubber layer 140 will affect the thermal resistance H of the heat conduction path of the 楹 a chip 12G. For its own heat dissipation requirements, the thickness of the four layers 14 () and ^ is less than a certain pre- ^ value, so that the thickness of the ㈣ layer ^ around the edge of the page is still small, so that the phenomenon of ^ 12 () being damaged by the bottom is still Cannot be resolved. In view of this, the new content of W Lisuo, the purpose of this creative package structure, is to greatly reduce the second :: provide-a stack of wafer concentration process $, so that the table of the wafer: the bottom peripheral stress effectively extend the wafer Package structure: "I: to the stress's damage, so it can be based on the above purpose of this creation,"; propose a stacked I »M244580 5. Creation instructions (4) Package structure, which has a carrier, a chip, a glue Material layer, a heat sink and an adhesive. First, the carrier has a bearing surface and a plurality of bonding pads, and these bonding pads are arranged on the bearing surface of the carrier. In addition, the wafer has an active surface and a corresponding back surface, and the wafer is arranged on the bearing surface of the carrier with the back surface, and the wafer further has a plurality of metal pads arranged on the active surface of the wafer. In addition, the glue layer is arranged on the active surface of the wafer, and the heat sink has a joint surface, and the heat sink is based on the joint surface, and is attached to the active surface of the wafer through the glue layer, and the joint surface includes a central surface. And a plurality of chamfer surfaces, and the chamfer surfaces surround the periphery of the central surface and are respectively connected to the periphery of the central surface, and the angle between the central surface and one of the chamfer surfaces ^ is less than 90 degrees. Finally, the wires are electrically connected to one of the metal pads to one of the corresponding bonding pads, respectively, and the encapsulant covers the chip, the heat sink and the wires.

According to the preferred embodiment of the present invention, the portion of the rubber layer between the one of the corner surfaces and the active surface is thicker than the portion of the rubber layer between the central surface and the active surface. In addition, the chamfered surfaces are planes or curved surfaces. When the chamfered surfaces are curved surfaces, the angle between one of the chamfered surfaces and the central surface is less than 90 degrees. In addition, the carrier system can be a substrate or a lead frame, and the heat sink can be a blank wafer, a metal block, or a graphite block. P Also based on the above purpose of this creation, this creation also proposes a stacked chip packaging structure, which has a chip, an adhesive layer, a heat sink, multiple pins, and an adhesive. First, the wafer has an active surface, and the wafer further has a plurality of metal pads, which are disposed on the active surface of the wafer. In addition, glue

10387twf.ptd Page 11 M244580 V. Creation instructions (5) The material layer is arranged on the active surface of the chip, and the heat sink block has a joint surface, and the heat sink block uses the joint surface and is attached to the chip through the glue layer. Active surface, and the joint surface includes a central surface and a plurality of chamfer surfaces, and these chamfer surfaces surround the periphery of the central surface and are connected to the periphery of the central surface, respectively, and the central surface and one of these chamfer surfaces The included angle is less than 90 degrees. In addition, one end of these pins is respectively connected to one of these metal pads, and the sealant covers at least a part of the chip, the heat sink and the part of these pins. According to the preferred embodiment of this creation, the sealant exposes the back of the wafer. In addition, the portion of the rubber layer between one of the corner surfaces and the active surface is thicker than the portion of the rubber layer between the central surface and the active surface. In addition, the chamfered surfaces are planes or curved surfaces. When the chamfered surfaces are curved surfaces, the angle between one of the chamfered surfaces and the central surface is less than 90 degrees. Also based on the above purpose of this creation, this creation proposes a stacked chip packaging structure, which mainly includes a wafer, a rubber layer and a stacked structure. The wafer has an active surface, and the rubber layer is disposed on the active surface of the wafer. In addition, the stacked structure has a bonding surface, and the stacked structure system uses the bonding surface and is attached to the active surface of the wafer through a glue layer, and the bonding surface includes a central surface and a plurality of lead angle surfaces, and these lead angles The planes surround the periphery of the central plane and are respectively connected to the peripheral edges of the central plane, and the angle between the central plane and one of the angled planes is less than 90 degrees. According to the preferred embodiment of the present invention, the portion of the rubber layer between the corner surfaces and the active surface is thicker than the portion of the rubber layer between the central surface and the active surface. In addition, these corner surfaces are flat or curved

10387twf.ptd Page 12 M244580 V. Creation Instructions (6) Surfaces. When these lead surfaces are curved surfaces, the angle between the local lead surface and the central surface is less than 90 degrees. In addition, the stacked structure system is a blank wafer, a heat sink, or a functional wafer. In addition, the chip further has a plurality of metal pads, which are arranged on the active surface of the chip, and the stacked chip package structure further includes a carrier, a plurality of wires and an adhesive, wherein the carrier has a carrier surface and a plurality of bonding pads. And the bonding pads are arranged on the bearing surface of the carrier, and the chip is arranged on the back of the bearing surface of the carrier, and the wires are electrically connected to one of the metal pads to one of the corresponding bonding pads, respectively. The encapsulant covers the wafer, the stacked structure, and these wires. Based on the above, the stack-type chip packaging structure of the present invention mainly forms a plurality of corner surfaces at the bottom periphery of the stacked structure, so the rubber content at the bottom periphery of the stacked structure can be increased. Therefore, when the chip package structure is subjected to a thermal stress test, the rubber layer at the bottom periphery of the stacked structure will provide appropriate elastic buffering, thereby greatly reducing the degree of stress concentration generated at the bottom periphery of the stacked structure to avoid the chip The surface layer is damaged by stress improperly, so the service life of the chip package structure can be effectively extended. In order to make the above-mentioned purpose, features, and advantages of this creation more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed descriptions such as τ 丨 · implementation, please refer to FIG. 2 Α, It shows a schematic cross-sectional view of a first stacked chip package structure according to a preferred embodiment of the present invention. The chip package structure 20 0 mainly includes a carrier 2 10, a chip 2 2 0, a heat sink 2 3 0, a rubber layer 2 4 0, a plurality of wires 2 50, and a sealant 2 60. First, the carrier 210 is, for example, a substrate or

10387twf.ptd Page 13 M244580 V. Creation instructions (7) Lead frame, etc. (here, the carrier 2 is a substrate), the carrier 2 has a bearing surface 212 and a plurality of bonding pads 214, The bonding pads 214 / are all disposed on the bearing surface 2 1 2 of the carrier 2 10. In addition, the wafer 22 has two active surfaces 22 2 and a corresponding one of the back surfaces 224, and the wafer 22 is attached to the bearing surface 212 of the carrier 21 with its back surface 2 24 and a glue layer 142 through. The wafer 220 further has a plurality of metal pads 226 disposed on the active surface 222 of the wafer 220. In addition, the heat dissipation block 23 0 is, for example, a blank wafer, a metal block or a graphite block with good thermal conductivity, and the heat dissipation block 230 has a bonding surface 232 ′, and the heat dissipation block 2 3 0 uses its bonding surface 23 2 through another adhesive. Material layer 24

The active surface 222 attached to the chip 220, wherein the material of the rubber layer 24 is, for example, epoxy resin. Finally, these wires 250 are electrically connected to one of the metal pads 2 2 6 to one of the corresponding bonding pads 214 respectively, and the sealant 260 covers the chip 220, the heat sink 23 ° and these wires. 250.一 凊 Also referring to FIG. 2A, the joint surface 232 of the heat sink 230 includes a middle

The central surface 232a and a plurality of corner surfaces 232b (such as a partially enlarged area in FIG. 2A). It is worth noting that these corner surfaces 23 2b surround the periphery of the central surface f32a and are connected to the periphery of the central surface 23 2a, respectively, and the angle between the central surface 232a and any of the corner surfaces 232b is less than 90 degrees. And the plurality of side surfaces 234 of the heat sink 23 are connected indirectly to the central surface 232a via the corner surfaces 232b. In other words, the central surface 232 of the heat sink 230 is indirectly connected to the corner surfaces 232b '.中心 面 232a. Therefore, the height of the guide angle surface Mη relative to the active surface 222 is greater than the height of the center surface 232a relative to the active surface 222, which means that the guide angle surface 232b will be farther from the center surface 232a.

10387 丨 wf.ptd Page 14 M244580 V. Creative Instructions (8) From the active surface 222. As mentioned above, when the bonding surface 2 3 2 of the heat sink 2 3 0 passes through the rubber layer 2 4 0 and is attached to the active surface 2 2 2 of the chip 2 2 0, the corner surface 232b is relatively The height of the surface 222 is greater than the height of the central surface 232a relative to the active surface 222, so that the portion of the rubber layer 240 between the corner surface 2 3 2b and the active surface 2 2 2 will be thicker than the rubber layer A portion of 240 between the central surface 232a and the active surface 222 increases the thickness of a part of the rubber layer 24o at the bottom periphery of the heat sink 230. Therefore, when the chip package structure 2000 is subjected to the thermal stress test, the repeated thermal shrinkage and bending movement generated by the chip package structure 2000 itself can use the corner surface 232b of the heat dissipation block 230 and the chip Part of the rubber layer 2 40 between the active surfaces 222 of 220 provides appropriate elastic cushioning, thereby greatly reducing the degree of stress concentration at the bottom periphery of the heat sink 2 30 to prevent the surface layer of the wafer 22 0 from being damaged by stress. Please also refer to Figs. 2A and 2B, where Fig. 2B shows the wafer package structure of Fig. 2A, and the corner surface of the heat dissipation block is a schematic sectional view. As shown in FIG. 2A, in addition to the lead surface 232b being a flat surface, as shown in FIG. 2B, the lead surface 2 3 2b may also be a curved surface, which can also reduce the stress generated on the bottom periphery of the heat sink 2 30. Degree of concentration. It is worth noting that, since the curved surface can also be regarded as a surface composed of a plurality of continuous connected planes, when the corner surface 232b is a curved surface, the local corner surface 232b can be regarded as a plane. Therefore, when the "corner surface 232b is a curved surface", the angle between the local corner surface 232b and the central surface is also smaller than 90 degrees. Please also refer to Figures 2A, 2B, and 3, of which Figure 3 shows the creation

10387twf.Ptd Page 15 M244580 V. Creative Instructions (9) A cross-sectional schematic diagram of the second stacked chip package structure of the preferred embodiment. The wafer package structure 200 in FIGS. 2A and 2B is compared with the wafer package structure 300 in FIG. 3. The wafer package structure 200 in FIGS. 2A and 2B is based on the substrate 1 ′ as a carrier. Device 2 1 0, and the chip package structure 3 0 of FIG. 3 is based on, the lead frame "as the carrier 3 1 0. As shown in Fig. 3, when the carrier 3 1 0 is a lead frame, It usually has a die pad 31 〇a and multiple leads 310b, and the chip 32 0 and the heat sink 3 3 0 are sequentially stacked.

On the chip holder 3 1 0 a, and one end of these pins 3 1 0 b respectively provides a bonding pad 3 3 4 for wire bonding, and the wires 3 5 0 are electrically connected to one of the metal pads 326 to It corresponds to one of these bonding pads 314. In addition, the sealing compound 360 covers the chip 320, the heat sink 330, these wires 360, and a part of the carrier 310 (that is, the chip holder 310a and the part of the pin 31ob). It is worth noting that 'the design of the joint surface 332 of the heat sink 330 is the same as the design of the joint surface 232 of Figs. 2A and 2B, both of which include a central surface (2 32a) and multiple corner surfaces (232b), The corner surface (232b) also includes a flat surface and a curved surface, so it will not be repeated here.

Please refer to FIGS. 2A, 2B, and 4 at the same time, and FIG. 4 shows a schematic cross-sectional view of a third stacked chip package structure according to the preferred embodiment of the present invention. Compared with the chip package structure 200 of FIGS. 2A and 2B and the chip package structure 400 of FIG. 4, the chip package structure 300 is a kind of “lead on chip (LOC)”. The chip package type has no carrier arrangement. As shown in FIG. 4, the chip package structure 400 does not pass through the wires 3 5 0 in FIG. 3, but directly utilizes a plurality of pins 41 1 and a plurality of terminals respectively connected to the active surface 422 of the chip 420. Metal pad 426. In addition, the heat sink

M244580 Fifth, the joint surface 432 of the creation instruction (430) is also attached to the active surface 4 2 2 of the wafer 4 2 through the rubber layer 44. In addition, the sealing compound 460 covers the local chip 420, the heat sink 430, and the local pins 4 丨 1, and the sealing compound 460 can expose the back surface 4 2 4 of the chip 4 2 0. It is worth noting that since the design of the joint surface 432 of the heat sink 430 is the same as the design of the joint surface 232 of Figs. 2A and 2β, 'both include a central surface (232a) and a plurality of angled surfaces (232b)' and The corner surface (232b) also includes a flat surface and a curved surface, so it will not be repeated here. In order to meet the requirements of System in Package (SIP), multiple functional chips can still be stacked on the carrier. Please refer to Figure 5 for a schematic cross-sectional view of the fourth stacked chip package structure created in this work. The chip package structure 500 includes a carrier 51o, a (functional) wafer 520, a (functional) wafer 57o, an adhesive layer 54o, a wire 55o, and a sealant 560. The chip package structure 5 0 0 is a functional chip 52 0 b instead of the heat sink 2 30, and the metal pad 576 of the active surface 572 of the chip 570 is electrically connected to the carrier 51 5 through a wire 5 50. The bonding pads 514 of the bearing surface 512. It is worth noting that, since the back surface 574 of the wafer 57 is the same as the bonding surface 232 of the heat sink 230 of FIG. 28, the wafer 57 () is attached to the wafer 52 with the back surface 574 and the glue layer 540 as the sub-layer. The active surface 522 of 〇 will increase the thickness of the rubber layer 54 () at the bottom periphery of the wafer 570, which is relative to the thickness of the rubber layer 54 (0) at the bottom center of the wafer 570. Please refer to FIG. 5B for a cross-sectional schematic diagram of the stacked chip package structure of FIG. 5A with a pad inserted between the two chips. As far as the crystal package structure 502 is concerned, a pad can be inserted between the chip 5 2 0 and the chip 5 7 0

M244580 V. Creative Instructions (11) Block 5 8 0 is used to raise the chip 5 70 to prevent the back of the chip 5 70 from touching the wire 5 5 0 and causing a short circuit between the wires 5 5 0. It is worth noting that the top and bottom edges of the pad 5 8 0 can also form a corner surface, so that the thickness of the peripheral edge of the rubber layer 5 4 0 is greater than the thickness of its center, so that the rubber layer of uneven thickness Provides proper elastic cushioning in structure. In addition, the pad 580 can be a blank wafer, a metal block, a graphite block, or made of other materials. The stacked chip packaging structure of this creation can be sequentially stacked from multiple stacked structures (such as functional wafers, blank wafers, metal blocks, graphite blocks or pads), and any two adjacent stacks The thickness of the rubber layer between the structures can be changed as the adjacent surfaces of the stacked structures form undulations. In particular, a plurality of chamfered surfaces can be formed on the bottom periphery of one of the two stacked structures. The rubber layer that is partly located at the bottom periphery of the stacked structure is thicker than the rubber layer that is partly located at the bottom center of the stacked structure, so it can provide appropriate elastic cushioning in structure. To sum up, the stacked chip packaging structure of this creation only needs to form multiple lead angles simply by machining on the bottom periphery of the stacked structure (such as a blank wafer, a metal block, a graphite block, or a functional wafer). Surface to increase the relative distance between the bottom periphery of the stacked structure and the active surface of the wafer, thereby increasing the thickness > of the rubber layer at the bottom periphery of the stacked structure, which is relative to the adhesive at the bottom center of the stacked structure In terms of the thickness of the material layer, it is not necessary to increase the thickness of the rubber layer at the bottom periphery of the stacked structure by comprehensively increasing the overall thickness of the rubber layer. Therefore, when the wafer packaging structure is subjected to a thermal stress test, the rubber layer on the bottom periphery of the stacked structure will provide appropriate elastic buffering, thereby greatly reducing the stack structure.

10387twf.ptd Page 18 M244580 V. Creative Instructions (12) The degree of stress concentration at the bottom periphery to prevent the surface of the wafer (especially the active surface of the wafer) from being damaged by stress improperly, so it can effectively extend the structure of the chip package. Service life. In addition, the stacking chip package structure of this creation can be applied to " wire bonding (W / B) π-type chip package structure, and can also be applied to the "lead on chip (LOC)" type Chip package structure, or it can be applied to π system single package (SI P) type chip package structure. Although this creation has been disclosed above with a preferred embodiment, it is not intended to limit the creation, anyone familiar with this technique Those who do not depart from the spirit and scope of this creation should make some changes and retouching. Therefore, the protection scope of this creation shall be determined by the scope of the attached patent application.

10387twf.ptd Page 19 M244580 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a conventional stacked chip package structure. FIG. 2A is a schematic cross-sectional view of a first stacked chip package structure according to a preferred embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of the chip package structure of FIG. 2A. FIG. 3 is a schematic cross-sectional view of a second stacked chip package structure according to a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a third stacked wafer sealing structure according to a preferred embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a fourth stacked chip package structure of the present invention. FIG. 6 is a schematic cross-sectional view of the stacked chip package structure of FIG. 5 with a pad inserted between the two chips. Schematic votives and promises 100 chip package structure 1 10 Carrier 1 12 Carrying surface 1 14 Bonding pad 120 Wafer 122 Active surface 124 Back surface 126 Metal pad 130 Dispersion block 132 Bonding surface 140 Rubber layer 142 Rubber layer 150 lead 160 sealant 200 chip package structure 210 carrier 212 carrier surface 214 bonding pad

10387twf.ptd Page 20 M244580 Schematic description 2 2 0: Chip 2 22: Active surface 2 24: Back surface 2 2 6: Metal 塾 2 3 0: Heat sink 2 3 2: Joint surface 2 3 2a: Central surface 2 3 2b: corner surface 24 0: rubber layer 242 rubber layer 2 50: wire 260 sealant 3 0: chip package structure 310 carrier 310a • wafer base 310b: pin 312: carrier surface 314 :: bonding Pad 3 2 0: Wafer 3 22:: Active surface 324: Back face 3 2 6:: Metal pad 3 3 0: Heat sink 3 32:: Joint surface 340 ·· Rubber layer 342:: Rubber layer 3 5 0: Lead 3 6 0:: Sealant 40 0: Chip package structure 411: I pin 42 0: Chip 422:: Active surface 42 4: Back surface 426: Metal pad 43 0: Heat sink 432: Joint surface 440: Rubber layer 442: Rubber layer 46 0: Sealant 50 0 ~ 5 0 2: Chip package structure 510 Carrier 512: Carrying surface 514 Bonding pad 52 0: (functional) wafer 522 Active surface 524: Back 526 metal pad

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Claims (1)

M244580 VI. Scope of patent application 1 A stacked chip package structure, including: a carrier having a carrier surface and a plurality of bonding pads, and the bonding pads are arranged on the carrier surface of the carrier; a chip, It has an active surface and a corresponding back surface, and the wafer is arranged on the bearing surface of the carrier with the back surface, and the wafer further has a plurality of metal pads arranged on the active surface of the wafer; a rubber material; A heat dissipating block having a bonding surface, and the heat dissipating block is attached to the active surface of the wafer through the glue layer, and the bonding The plane includes a central plane and a plurality of chamfer planes, and the chamfer planes surround the periphery of the central plane and are respectively connected to the periphery of the central plane. The central plane and one of the chamfer planes. The included angle is less than 90 degrees; a plurality of wires are electrically connected to one of the metal pads to one of the corresponding bonding pads respectively; and an adhesive covering the chip, the heat sink and the wire. 2. The stacked chip package structure according to item 1 of the scope of the patent application, wherein a portion of the rubber layer between the corner surfaces and the active surface is thicker than the rubber layer at the center Between the surface and the active surface. 3. The stacked chip package structure described in item 1 of the patent application scope, wherein the corner surfaces are flat. 4. The stacked chip package structure according to item 1 of the scope of the patent application, wherein the corner surfaces are curved surfaces, and the angle between one of the corner surfaces and the central surface is less than 90 degrees. 10387twf.ptd Page 23 M244580 6. Scope of patent application 5. The stacked chip package structure described in item 1 of the patent application scope, wherein the carrier is one of a substrate and a lead frame. 6. The stacked chip package structure described in item 1 of the scope of patent application, wherein the heat sink is one of a blank chip, a metal block, and a graphite block--〇7.-A stacked chip package structure, including: A wafer having an active surface, and the wafer further having a plurality of metal pads arranged on the active surface of the wafer; a glue layer arranged on the active surface of the wafer; a heat sink having a bonding surface And the heat sink is attached to the active surface of the chip by the joint surface and through the glue layer, and the joint surface includes a central surface and a plurality of lead surfaces, and the lead surfaces are It surrounds the periphery of the central surface and is respectively connected to the periphery of the central surface, and the angle between the central surface and one of the lead angle surfaces is less than 90 degrees; a plurality of pins, one of which Are respectively overlapped to one of the metal pads; and a piece of glue covering at least a part of the chip, the heat sink and the pins. 8. The stacked chip package structure as described in item 7 of the patent application scope, wherein the sealant exposes the back surface of the wafer. 9. The stacked chip package structure according to item 7 of the scope of the patent application, wherein a portion of the rubber layer between the corner surfaces and the active surface is thicker than the rubber layer at the center Between the surface and the active surface. 10387twf.ptd Page 24 M244580 6. Scope of patent application 1 0. The stacked chip package structure described in item 7 of the scope of patent application, wherein the corner surfaces are flat. Π. The stacked chip package structure described in item 7 of the scope of the patent application, wherein the corner surfaces are curved surfaces, and the angle between the one of the corner surfaces and the central surface is less than 90 degrees . 1 2. The stacked chip package structure described in item 7 of the scope of the patent application, wherein the heat sink block is one of a blank chip, a metal block, and a graphite block— 〇1 3. — A stacked chip package structure, at least It includes: a wafer with an active surface; a rubber layer disposed on the active surface of the wafer; and a stacked structure with a bonding surface, and the stacked structure system uses the bonding surface and passes through the rubber Layer is attached to the active surface of the chip, and the joint surface includes a central surface and a plurality of corner surfaces, and the corner surfaces are around the periphery of the center surface and are connected to the center surface respectively. The peripheral edge, and the angle between the central surface and one of the corner surfaces is less than 90 degrees. 1 4. The stacked chip package structure described in item 13 of the scope of patent application, wherein the portion of the rubber layer between the corner surfaces and the active surface is thicker than that of the rubber layer. A portion between the central surface and the active surface. 1 5. The stacked chip package structure according to item 13 of the scope of the patent application, wherein the corner surfaces are flat. 16. The stacked chip package structure according to item 13 of the scope of patent application, wherein the corner surfaces are curved surfaces, and one of the corner surfaces is partially 10387twf.ptd Page 25 M244580 6. Scope of patent application The included angle with the central plane is less than 90 degrees. 1 7. The stacked chip package structure according to item 13 of the scope of the patent application, wherein the stacked structure system is one of a blank chip, a heat sink and a functional chip. 1 8. The stacked wafer sealing structure described in item 13 of the scope of patent application, wherein the wafer further has a plurality of metal pads, which are arranged on the active surface of the wafer, and the stacked wafer packaging structure further includes : A carrier having a bearing surface and a plurality of bonding pads, the bonding pads are arranged on the bearing surface of the carrier, and the wafer is arranged on the bearing surface of the carrier with the back surface; a plurality of Each of the wires is electrically connected to one of the metal pads to one of the bonding pads corresponding to the metal pads; and a piece of glue covers the chip, the stacked structure and the wires. 10387twf.ptd Page 26