TWI847730B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a first thin film redistribution layer, a plurality of first connecting members, a second thin film redistribution layer, a plurality of second connecting members, a filling glue layer, a chip and a plurality of solder balls. The first connecting members are disposed on a first surface of the first thin film redistribution layer. The second connecting members are disposed on a third surface of the second thin film redistribution layer. The second connecting members are respectively connected to the first connecting members, so that the second thin film redistribution layer is bonded to the first thin film redistribution layer. The filling glue layer is filled between the first thin film redistribution layer and the second thin film redistribution layer, and covers the first connecting members and the second connecting members. The chip is disposed on a second surface of the first thin film redistribution layer. The solder balls are disposed on a fourth surface of the second thin film redistribution layer.

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a semiconductor packaging structure and a manufacturing method thereof.

Multilayer thin film redistribution layers are usually used as heterogeneous integration substrates. Thin film redistribution layers on glass substrates are prone to high stress and warping, so currently only two or three metal layers and two or three dielectric layers can be set on the glass substrate. In other words, the number of circuit layers in the thin film redistribution layer will not exceed three layers at most, thus limiting the application range of thin film redistribution layers and preventing them from being expanded to more complex systems.

The present invention provides a semiconductor package structure and a manufacturing method thereof, which can have more than three layers of thin film redistribution layers and has a simple manufacturing process.

The semiconductor packaging structure of the present invention includes a first film redistribution layer, a plurality of first connectors, a second film redistribution layer, a plurality of second connectors, a filling glue layer, a chip and a plurality of solder balls. The first film redistribution layer has a first surface and a second surface opposite to each other. The first connector is disposed on the first surface of the first film redistribution layer. The second film redistribution layer has a third surface and a fourth surface opposite to each other. The second connector is disposed on the third surface of the second film redistribution layer, wherein the second connectors are respectively connected to the first connectors, so that the second film redistribution layer is bonded to the first film redistribution layer. The filling glue layer is filled between the first film redistribution layer and the second film redistribution layer, and covers the first connector and the second connector. The chip is disposed on the second surface of the first film redistribution layer. The solder ball is disposed on the fourth surface of the second thin film redistribution layer.

In one embodiment of the present invention, the semiconductor package structure further includes a plurality of third connectors disposed on the second surface of the first thin film redistribution layer. The chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface, and the chip includes a plurality of fourth connectors disposed on the active surface. The fourth connectors are respectively connected to the third connectors, so that the chip is bonded to the first thin film redistribution layer.

In an embodiment of the present invention, each of the third connectors includes a pad and a conductive post. The pad is disposed on the second surface of the first film redistribution layer, and the conductive post is located between the pad and each of the fourth connectors of the chip.

In one embodiment of the present invention, the semiconductor package structure further includes a packaging gel body, which covers the third connector, the fourth connector, and the active surface, the back surface and the surrounding surface of the chip. The edge of the packaging gel body is aligned with the edge of the filling gel layer.

In one embodiment of the present invention, the semiconductor package structure further includes a primer covering the third connector, the fourth connector and the active surface of the chip, and exposing the back surface and surrounding surface of the chip.

In one embodiment of the present invention, the number of layers of the first thin film redistribution layer is different from the number of layers of the second thin film redistribution layer.

In one embodiment of the present invention, the number of layers of the first thin film redistribution layer is the same as the number of layers of the second thin film redistribution layer.

In one embodiment of the present invention, the semiconductor package structure further includes a plurality of connection pads and a solder barrier layer. The connection pads are disposed on the fourth surface of the second film redistribution layer and are electrically connected to the second film redistribution layer. The solder barrier layer is disposed on the fourth surface of the second film redistribution layer and has a plurality of openings. The openings expose a portion of the connection pads, and solder balls are respectively located in the openings and connected to the connection pads exposed by the openings.

In an embodiment of the present invention, the extending direction of each of the first connecting members is opposite to the extending direction of each of the second connecting members.

In one embodiment of the present invention, the wiring density of the first thin film redistribution layer is denser than the wiring density of the second thin film redistribution layer.

In one embodiment of the present invention, the first thin film redistribution layer includes a plurality of first redistribution wiring layers and a first support ring surrounding the first redistribution wiring layer. The second thin film redistribution layer includes a plurality of second redistribution wiring layers and a second support ring surrounding the second redistribution wiring layer. The first support ring and the second support ring are connected together through a first connector and a second connector.

The manufacturing method of the semiconductor package structure of the present invention includes the following steps. A first thin film redistribution layer is formed on a first carrier. A first release film is disposed on the first carrier, and the first thin film redistribution layer has a first surface and a second surface opposite to each other. The first release film is located between the second surface of the first thin film redistribution layer and the first carrier. A plurality of first connectors are formed on the first surface of the first thin film redistribution layer. A second thin film redistribution layer is formed on a second carrier. A second release film is disposed on the second carrier, and the second thin film redistribution layer has a third surface and a fourth surface opposite to each other. The second release film is located between the fourth surface of the second thin film redistribution layer and the second carrier. A plurality of second connectors are formed on the third surface of the second thin film redistribution layer. The second connectors are connected to the first connectors respectively, so that the second thin film redistribution layer is bonded to the first thin film redistribution layer. A filling adhesive layer is filled between the first thin film redistribution layer and the second thin film redistribution layer, wherein the filling adhesive layer covers the first connector and the second connector. The first carrier and the first release film are removed to expose the second surface of the first thin film redistribution layer. A chip is arranged on the second surface of the first thin film redistribution layer. The second carrier and the second release film are removed to expose the fourth surface of the second thin film redistribution layer. A plurality of solder balls are arranged on the fourth surface of the second thin film redistribution layer.

In one embodiment of the present invention, before removing the second carrier and the second release film, the first carrier and the first release film are removed and a chip is placed on the second surface of the first thin film redistribution layer.

In one embodiment of the present invention, the manufacturing method of the above-mentioned semiconductor package structure also includes forming a plurality of third connectors on the second surface of the first thin film redistribution layer after removing the first carrier and the first release film. Each third connector includes a pad and a conductive column. The pad is arranged on the second surface of the first thin film redistribution layer, and the conductive column is located on the pad. The chip has an active surface and a back surface opposite to each other and a surrounding surface connecting the active surface and the back surface, and the chip includes a plurality of fourth connectors arranged on the active surface. When the chip is set on the second surface of the first thin film redistribution layer, the fourth connectors are respectively connected to the third connectors, so that the chip is bonded to the first thin film redistribution layer.

In one embodiment of the present invention, the method for manufacturing the semiconductor package structure further includes forming a packaging glue body to cover the third connector, the fourth connector, and the active surface, the back surface and the surrounding surface of the chip before removing the second carrier and the second release film. The edge of the packaging glue body is aligned with the edge of the filling glue layer.

In one embodiment of the present invention, the manufacturing method of the semiconductor package structure further includes forming a plurality of connection pads separated from each other on the fourth surface of the second thin film redistribution layer after removing the second carrier and the second release film, wherein the connection pads are electrically connected to the second thin film redistribution layer. Forming a soldering protection layer on the fourth surface of the second thin film redistribution layer. The soldering protection layer has a plurality of openings to expose a portion of the connection pads. When setting solder balls on the fourth surface of the second thin film redistribution layer, the solder balls are respectively located in the openings and connected to the connection pads exposed by the openings.

In one embodiment of the present invention, before removing the first carrier and the first release film, the second carrier and the second release film are removed and solder balls are placed on the fourth surface of the second thin film redistribution layer.

In one embodiment of the present invention, the manufacturing method of the semiconductor package structure further includes forming a plurality of connection pads separated from each other on the fourth surface of the second thin film redistribution layer after removing the second carrier and the second release film, wherein the connection pads are electrically connected to the second thin film redistribution layer. Forming a soldering protection layer on the fourth surface of the second thin film redistribution layer. The soldering protection layer has a plurality of openings to expose a portion of the connection pads. When setting solder balls on the fourth surface of the second thin film redistribution layer, the solder balls are respectively located in the openings and connected to the connection pads exposed by the openings.

In one embodiment of the present invention, the manufacturing method of the above-mentioned semiconductor package structure also includes forming a plurality of third connectors on the second surface of the first thin film redistribution layer after removing the first carrier and the first release film. Each third connector includes a pad and a conductive column. The pad is arranged on the second surface of the first thin film redistribution layer, and the conductive column is located on the pad. The chip has an active surface and a back surface opposite to each other and a surrounding surface connecting the active surface and the back surface, and the chip includes a plurality of fourth connectors arranged on the active surface. When the chip is set on the second surface of the first thin film redistribution layer, the fourth connectors are respectively connected to the third connectors, so that the chip is bonded to the first thin film redistribution layer.

In an embodiment of the present invention, the manufacturing method of the semiconductor package structure further includes forming a primer to cover the third connector, the fourth connector and the active surface of the chip. The primer exposes the back side and the surrounding surface of the chip.

In one embodiment of the present invention, the material of the base glue is different from the material of the filling glue.

In one embodiment of the present invention, the number of layers of the first thin film redistribution layer is different from the number of layers of the second thin film redistribution layer.

In one embodiment of the present invention, the number of layers of the first thin film redistribution layer is the same as the number of layers of the second thin film redistribution layer.

In an embodiment of the present invention, the extending direction of each of the first connecting members is opposite to the extending direction of each of the second connecting members.

In one embodiment of the present invention, the wiring density of the first thin film redistribution layer is denser than the wiring density of the second thin film redistribution layer.

In one embodiment of the present invention, the first thin film redistribution layer includes a plurality of first redistribution wiring layers and a first support ring surrounding the first redistribution wiring layer. The second thin film redistribution layer includes a plurality of second redistribution wiring layers and a second support ring surrounding the second redistribution wiring layer. The first support ring and the second support ring are connected together through a first connector and a second connector.

Based on the above, in the design of the semiconductor package structure of the present invention, the second connectors located on the second thin film redistribution layer are respectively connected to the first connectors located on the first thin film redistribution layer, so that the second thin film redistribution layer is bonded to the first thin film redistribution layer, thereby forming a multi-layer thin film redistribution layer of at least three layers, and the process is simple.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

FIG. 1A to FIG. 1I are cross-sectional schematic diagrams of a method for manufacturing a semiconductor package structure according to an embodiment of the present invention. Regarding the method for manufacturing a semiconductor package structure of this embodiment, first, referring to FIG. 1A , a first thin film redistribution layer 110 is formed on a first carrier 10. A first release film 12 is disposed on the first carrier 10, and the first thin film redistribution layer 110 has a first surface S1 and a second surface S2 opposite to each other. The first release film 12 is located between the second surface S2 of the first thin film redistribution layer 110 and the first carrier 10.

In detail, in the present embodiment, the first carrier 10 is, for example, a temporary substrate, wherein the material of the first carrier 10 can be made of glass, plastic, silicon, metal or other suitable materials, as long as the material can support the structure formed thereon in the subsequent process. In some embodiments, the first release film 12 (for example, a light to heat conversion film or other suitable de-bonding layer) applied on the first carrier 10 can increase the releasability of the subsequently formed structure from the first carrier 10 in the subsequent de-bonding process. Alternatively, the first release film 12 can be omitted.

As shown in FIG1A , a first thin-film redistribution layer 110 may be formed on a first carrier 10, wherein the first thin-film redistribution layer 110 includes a plurality of first redistribution wiring layers 112 (schematically showing two first redistribution wiring layers 112), a plurality of first dielectric layers 114 (schematically showing three first dielectric layers 114), and a plurality of first conductive vias 116. The first redistribution wiring layers 112 and the first conductive vias 116 buried in the first dielectric layers 114 may be collectively regarded as a fine redistribution circuit of the first thin-film redistribution layer 110.

In some embodiments, the material of the first redistribution line layer 112 and the first conductive via 116 may be or may include copper, gold, nickel, aluminum, platinum, tin, metal alloy, a combination thereof, or other suitable conductive materials. The first dielectric layers 114 are stacked on each other, and the material of the first dielectric layers 114 may be or may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), inorganic dielectric materials (e.g., silicon oxide, silicon nitride, etc.) or other suitable electrical insulating materials.

In some embodiments, a first redistribution wiring layer 112 may be formed over the first carrier 10 using a metallic deposition process, a lithography and etching process, or other suitable techniques. In some embodiments, the first redistribution wiring layer 112 near the bottom level of the first carrier 10 includes a plurality of conductive pads (not shown) for a subsequent element-mounting process. Next, a first dielectric layer 114 having an opening may be formed over the first carrier 10 to cover the first redistribution wiring layer 112 using, for example, a coating process, a lithography and etching process, or other suitable techniques. The opening of the first dielectric layer 114 may expose at least a portion of the first redistribution wiring layer 112 for further electrical connection. Optionally, the first dielectric layer 114 is formed before forming the first redistribution wiring layer 112. Subsequently, a conductive material may be formed in the opening of the first dielectric layer 114 using plating, deposition, or other suitable processes to form a first conductive via 116. The term "conductive via" may be an element that provides vertical electrical connection between layers and penetrates the plane of one or more adjacent layers. When the conductive material is formed in the opening, the conductive material may also be formed on the top surface of the first dielectric layer 114, and then the conductive material on the top surface of the first dielectric layer 114 may be patterned to form another first redistribution wiring layer 112. The first redistribution wiring layer 112 on the top surface of the first dielectric layer 114 may include conductive lines and pads. The first redistribution wiring layer 112 may be referred to as a patterned conductive layer with fine line/space wiring.

The above steps may be repeated so that the first redistribution wiring layer 112 and the first dielectric layer 114 are alternately stacked, and the first conductive via 116 is buried in the first dielectric layer 114. The first conductive via 116 may form an electrical connection and a physical connection between the first redistribution wiring layers 112 in different layers. In some embodiments, the first thin film redistribution layer 110 is a stack of layers with fine line/space routing. It should be noted that the first thin film redistribution layer 110 shown in FIG. 1A is only exemplary, and a redistribution wiring structure with more or fewer layers may be formed according to the needs of the circuit design.

Continuing to refer to FIG. 1A , the first thin-film redistribution layer 110 includes a first surface S1 and a second surface S2 facing each other, wherein the second surface S2 faces the first carrier 10. The first conductive via 116 and the first dielectric layer 114 at the second surface S2 of the first thin-film redistribution layer 110 may be substantially flush. In some embodiments, the first redistribution wiring layer 112 may be formed at the top surface of the uppermost layer in the first dielectric layer 114. In this case, the first surface S1 includes the first redistribution wiring layer 112 and the uppermost first dielectric layer 114. In some embodiments, the first conductive via 116 tapers toward the first carrier 10. The thickness of the first thin-film redistribution layer 110 may be in the range of about 2 μm to about 10 μm. Although other values are possible depending on product requirements/process recipes.

Next, please continue to refer to FIG. 1A to form a plurality of first connectors 120 on the first surface S1 of the first thin film redistribution layer 110. The first connector 120 is, for example, a pillar portion formed on the first surface S1 of the first thin film redistribution layer 110, wherein the diameter of the first connector 120 gradually decreases in the direction away from the first surface S1, but is not limited thereto. In another embodiment, the diameter of the first connector 120 may also gradually increase in the direction away from the first surface S1. In this embodiment, the first connector 120 and the first conductive via 116 may be formed by coating during the same step. Optionally, after forming the first thin film redistribution layer 110, the first connector 120 is formed separately (or placed on the first thin film redistribution layer 110). In some embodiments, the material of the first connector 120 includes copper, gold, nickel, aluminum, platinum, tin, a combination thereof, an alloy thereof, or another suitable conductive material. It should be noted that the number of first connectors 120 shown here is for illustrative purposes only and does not constitute a limitation of the present invention.

Next, referring to FIG. 1B , a second thin film redistribution layer 130 is formed on the second carrier 20. A second release film 22 is disposed on the second carrier 20, and the second thin film redistribution layer 130 has a third surface S3 and a fourth surface S4 opposite to each other. The second release film 22 is located between the fourth surface S4 of the second thin film redistribution layer 130 and the second carrier 20, wherein the fourth surface S4 faces the second carrier 20, and the second carrier 20 is, for example, a temporary substrate. The second thin film redistribution layer 130 includes a plurality of second redistribution wiring layers 132 (schematically showing two second redistribution wiring layers 132), a plurality of second dielectric layers 134 (schematically showing three second dielectric layers 134), and a plurality of second conductive vias 136.

It should be noted that the materials of the second carrier 20 and the second release film 22 are the same or similar to those of the first carrier 10 and the first release film 12, and the manufacturing method and material of the second thin film redistribution layer 130 are the same or similar to those of the first thin film redistribution layer 110. Please refer to the description of the first carrier 10, the first release film 12 and the first thin film redistribution layer 110, which will not be repeated here.

Next, please refer to FIG. 1B again, and a plurality of second connectors 140 are formed on the third surface S3 of the second thin film redistribution layer 130. The second connector 140 is, for example, a pillar portion formed on the third surface S3 of the second thin film redistribution layer 130, wherein the diameter of the second connector 140 gradually decreases in the direction away from the third surface S3, but is not limited thereto. In another embodiment, the diameter of the second connector 140 may also gradually increase in the direction away from the third surface S3. In this embodiment, the second connector 140 and the second conductive via 136 may be plated during the same step. Optionally, after the second thin film redistribution layer 130 is formed, the second connector 140 is formed separately (or placed on the second thin film redistribution layer 130). In some embodiments, the material of the second connector 140 includes copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, or another suitable conductive material. It should be noted that the number of the second connectors 140 shown here is only for illustrative purposes and does not constitute a limitation of the present invention.

Next, please refer to FIG. 1B again, the third surface S3 of the second film redistribution layer 130 faces the first surface S1 of the first film redistribution layer 110, so that the second connectors 140 are respectively connected to the first connectors 120, so that the second film redistribution layer 130 is bonded to the first film redistribution layer 110. Here, the second connector 140 is structurally connected and electrically connected to the first connector 120, wherein the second connector 140 can be connected in alignment with the first connector 120, or, connected in a staggered manner, which is not limited here. The first film redistribution layer 110 is electrically connected to the second film redistribution layer 130 through the first connector 120 and the second connector 140.

Here, the number of layers of the first thin film redistribution layer 110 (including the number of circuit layers and the number of dielectric layers) is the same as the number of layers of the second thin film redistribution layer 130, that is, the number of layers of the thin film redistribution layer 110 and the second thin film redistribution layer 130 are symmetrical, but not limited thereto. In particular, the wiring density of the first thin film redistribution layer 110 is denser than the wiring density of the second thin film redistribution layer 130, and the extension direction of the second conductive via 136 is opposite to the extension direction of the first conductive via 116, and the extension direction of the first connector 120 (from top to bottom) is opposite to the extension direction of the second connector 140 (from bottom to top), but not limited thereto.

Next, referring to FIG. 1C , a filling adhesive layer 150 is filled between the first film redistribution layer 110 and the second film redistribution layer 130, wherein the filling adhesive layer 150 covers the first connector 120 and the second connector 140 for protection. For example, a dispensing process of an underfill material may be performed, and then a curing process may be performed to form the filling adhesive layer 150. For example, the filling adhesive layer 150 fills the gap between the first surface S1 of the first film redistribution layer 110 and the third surface S3 of the second film redistribution layer 130 to surround, cover, and cover the first connector 120 and the second connector 140.

Next, referring to FIG. 1C and FIG. 1D , the first carrier 10 and the first release film 12 are removed to expose the second surface S2 of the first thin film redistribution layer 110. For example, external energy (e.g., heat and/or pressure, etc.) is applied to the first release film 12 between the first thin film redistribution layer 110 and the first carrier 10, so that the first release film 12 is separated from the first thin film redistribution layer 110. Other suitable processes (e.g., mechanical removing, etching, grinding, etc.) may be used to remove the temporary first carrier 10 and the first release film 12. Optionally, a cleaning process is performed on the second surface S2 of the first thin film redistribution layer 110 to remove the residue of the first release film 12. The bottom surface of the first conductive via 116 flush with the lowermost layer of the first dielectric layer 114 on the second surface S2 may be exposed for further electrical connection after de-bonding.

Next, referring to FIG. 1E , a plurality of third connectors 160 are formed on the second surface S2 of the first thin film redistribution layer 110. Each third connector 160 includes a pad 162 and a conductive post 164, wherein the pad 162 is disposed on the second surface S2 of the first thin film redistribution layer 110 and is electrically connected to the first conductive via 116. The conductive posts 164 are respectively located on the pads 162, and the conductive posts 164 are electrically connected to the first thin film redistribution layer 110 through the pads.

Next, please refer to FIG. 1F , a chip 170 is disposed on the second surface S2 of the first thin film redistribution layer 110, wherein the chip 170 has an active surface 171 and a back surface 173 opposite to each other and a peripheral surface 175 connecting the active surface 171 and the back surface 173, and the chip 170 includes a plurality of fourth connectors 172 disposed on the active surface 171. The fourth connectors 172 of the chip 170 are respectively connected to the conductive posts 164 of the third connectors 160, so that the chip 170 is bonded to the first thin film redistribution layer 110. Here, the chip 170 is electrically connected to the first thin film redistribution layer 110 in a flip chip bonding manner.

Next, referring to FIG. 1G , a packaging body 180a is formed to cover the third connector 160, the fourth connector 172, and the active surface 171, the back surface 173, and the peripheral surface 175 of the chip 170. In other words, the packaging body 180a completely covers the chip 170, and the edge of the packaging body 180a is substantially aligned with the edge of the filling glue layer 150, the edge of the first film redistribution layer 110, and the edge of the second film redistribution layer 130, but not limited thereto.

Next, please refer to FIG. 1G and FIG. 1H at the same time, remove the second carrier 20 and the second release film 22, and expose the fourth surface S4 of the second thin film redistribution layer 130. That is, before removing the second carrier 20 and the second release film 22 in this embodiment, the first carrier 10 and the first release film 12 have been removed and the chip 170 has been placed on the second surface S2 of the first thin film redistribution layer 110. Here, the removal of the second carrier 20 and the second release film 22 is the same as the above-mentioned removal of the first carrier 10 and the first release film 12. Please refer to the above-mentioned removal of the first carrier 10 and the first release film 12, and no further description is given here.

Afterwards, referring to FIG. 1I , a plurality of connection pads 185 separated from each other are formed on the fourth surface S4 of the second thin film redistribution layer 130, wherein the connection pads 185 are located on the outermost second dielectric layer 134 and are electrically connected to the outermost second conductive vias 136 of the second thin film redistribution layer 130. Next, a solder-proof layer 190 is formed on the fourth surface S4 of the second thin film redistribution layer 130, wherein the solder-proof layer 190 is located on the outermost second dielectric layer 134 and has a plurality of openings 192 to expose a portion of each connection pad 185.

Finally, please refer to FIG. 1I again, and set the solder balls 195 on the fourth surface S4 of the second film redistribution layer 130. The solder balls 195 are respectively located in the openings 192 of the anti-soldering layer 190 and structurally connected and electrically connected to the connection pads 185 exposed by the openings 192. The chip 170 can be electrically connected to the external circuit (not shown) through the third connector 160, the first film redistribution layer 110, the first connector 120, the second connector 140, the second film redistribution layer 130, the pads 185 and the solder balls 195 in sequence. At this point, the production of the semiconductor package structure 100a has been completed.

It should be noted that in another embodiment not shown, the second carrier 20 and the second release film 22 may be removed and the connecting pads 185 and the solder balls 195 may be arranged on the fourth surface S4 of the second thin film redistribution layer 130 before removing the first carrier 10 and the first release film 12, which still falls within the scope of protection of the present invention.

Structurally, please refer to FIG. 1I again. The semiconductor package structure 100a of this embodiment includes a first thin film redistribution layer 110, a first connector 120, a second thin film redistribution layer 130, a second connector 140, a filling glue layer 150, a chip 170, and a solder ball 195. The first thin film redistribution layer 110 has a first surface S1 and a second surface S2 opposite to each other, and includes a second first redistribution circuit layer 112, a third first dielectric layer 114, and a plurality of first conductive vias 116. The first connector 120 is disposed on the first surface S1 of the first thin film redistribution layer 110. The second thin film redistribution layer 130 has a third surface S3 and a fourth surface S4 opposite to each other, and includes two second redistribution wiring layers 132, three second dielectric layers 134, and a plurality of second conductive vias 136. The second connectors 140 are disposed on the third surface S3 of the second thin film redistribution layer 130, wherein the second connectors 140 are respectively connected to the first connectors 120, so that the second thin film redistribution layer 130 is bonded to the first thin film redistribution layer 110. Here, the number of layers of the first redistribution wiring layer 112 is the same as the number of layers of the second redistribution wiring layer 132, and the number of layers of the first dielectric layer 114 is the same as the number of layers of the second dielectric layer 134, but the present invention is not limited thereto. The filling adhesive layer 150 is filled between the first thin film redistribution layer 110 and the second thin film redistribution layer 130 and covers the first connector 120 and the second connector 140. The chip 170 is disposed on the second surface S2 of the first thin film redistribution layer 110. The solder ball 195 is disposed on the fourth surface S4 of the second thin film redistribution layer 130.

Furthermore, in the present embodiment, the semiconductor package structure 100a further includes a third connector 160 disposed on the second surface S2 of the first thin film redistribution layer 110, wherein the third connector 160 includes a pad 162 and a conductive column 164. The chip 170 has an active surface 171 and a back surface 173 opposite to each other and a peripheral surface 175 connecting the active surface 171 and the back surface 173, and the chip 170 includes a fourth connector 172 disposed on the active surface 171. The fourth connector 172 is respectively connected to the third connector 160, so that the chip 170 is bonded to the first thin film redistribution layer 110. The pad 162 is disposed on the second surface S2 of the first thin film redistribution layer 110, and the conductive column 164 is located between the pad 162 and the fourth connector 172 of the chip 170.

In addition, the semiconductor package structure 100a of the present embodiment further includes a packaging gel 180a, which covers the third connector 160, the fourth connector 172 and the active surface 171, the back surface 173 and the peripheral surface 175 of the chip 170. The edge of the packaging gel 180a is aligned with the edge of the filling gel layer 150. In addition, the semiconductor package structure 100a further includes a connection pad 185 and a solder barrier layer 190. The connection pad 185 is disposed on the fourth surface S4 of the second thin film redistribution layer 130, and is structurally and electrically connected to the second conductive via 136 on the outermost side of the second thin film redistribution layer 130. The solder-proof layer 190 is disposed on the fourth surface S4 of the second redistribution layer 130 and has an opening 192, wherein the opening 192 exposes a portion of the connection pad 185. Solder balls 195 are respectively located in the openings 192 of the solder-proof layer 190 and structurally and electrically connected to the connection pad 185 exposed by the openings 192.

In short, in the manufacturing method of the semiconductor package structure 100a of the present embodiment, the second connectors 140 located on the second thin film redistribution layer 130 are respectively connected to the first connectors 120 located on the first thin film redistribution layer 110, so that the second thin film redistribution layer 130 is bonded to the first thin film redistribution layer 110, thereby forming a multi-layer thin film redistribution layer of at least three layers. Compared with the conventional thin film redistribution layer that can only form no more than three layers of circuits on a glass carrier, the manufacturing method of the semiconductor package structure 100a of the present embodiment has the advantage of simple process and is not limited to the limitation that only two or three layers of metal can be set on the conventional glass carrier. Furthermore, in this embodiment, the first thin film redistribution layer 110 with a denser wiring density is bonded to the chip 170, and the second thin film redistribution layer 130 with a sparser wiring density is bonded to the solder ball 195, thereby forming a fan-out circuit structure. In addition, since the semiconductor package structure 100a of this embodiment can have at least three layers of multi-layer thin film redistribution layers, it can be applied and expanded to more complex systems.

It should be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

2A to 2F are cross-sectional schematic diagrams of partial steps of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. The method for manufacturing a semiconductor package structure of this embodiment is similar to the method for manufacturing a semiconductor package structure described above, and the difference between the two is that after the step of FIG. 1C, that is, after filling the filling glue layer 150 between the first thin film redistribution layer 110 and the second thin film redistribution layer 130, please refer to FIG. 1C and FIG. 2A at the same time, remove the second carrier 20 and the second release film 22, and expose the fourth surface S4 of the second thin film redistribution layer 130.

Next, referring to FIG. 2B , separate connection pads 185 are formed on the fourth surface S4 of the second thin film redistribution layer 130 , wherein the connection pads 185 are located on the outermost second dielectric layer 134 of the second thin film redistribution layer 130 and are electrically connected to the outermost second conductive vias 136 of the second thin film redistribution layer 130 .

2B , a solder barrier layer 190 is formed on the fourth surface S4 of the second redistribution layer 130 . The solder barrier layer 190 is located on the second dielectric layer 134 at the outermost side of the second redistribution layer 130 , and the solder barrier layer 190 has an opening 192 to expose a portion of the connection pad 185 .

Next, referring to FIG. 2C , solder balls 195 are disposed on the fourth surface S4 of the second redistribution layer 130 . The solder balls 195 are respectively located in the openings 192 of the solder-proof layer 190 and structurally and electrically connected to the connection pads 185 exposed by the openings 192 .

Next, please refer to FIG. 2C and FIG. 2D simultaneously, the first carrier 10 and the first release film 12 are removed to expose the second surface S2 of the first thin film redistribution layer 110. In other words, before removing the first carrier 10 and the first release film 12 in this embodiment, the second carrier 20 and the second release film 22 are removed and the solder balls 195 are placed on the fourth surface S4 of the second thin film redistribution layer 130.

Next, referring to FIG. 2D , a third connector 160 is formed on the second surface S2 of the first thin film redistribution layer 110 . The third connector 160 includes a pad 162 and a conductive post 164 . The pad 162 is disposed on the second surface S2 of the first thin film redistribution layer 110 , and the conductive post 164 is located on the pad 162 .

2E, a chip 170 is placed on the second surface S2 of the first thin film redistribution layer 110, wherein the fourth connectors 172 of the chip 170 are respectively connected to the conductive posts 164 of the third connectors 160, so that the chip 170 is bonded to the first thin film redistribution layer 110. Here, the chip 170 is electrically connected to the first thin film redistribution layer 110 by flip chip bonding.

Finally, referring to FIG. 2F , a primer 180b is formed to cover the third connector 160, the fourth connector 172 and the active surface 171 of the chip 170, wherein the primer 180b exposes the back surface 173 and the surrounding surface 175 of the chip 170, which can have a better heat dissipation effect. Here, the material of the primer 180b can be the same as or different from the material of the filling colloid 150, and is not limited here. At this point, the manufacturing method of the semiconductor package structure 100b has been completed.

It should be noted that in another embodiment not shown, before removing the second carrier 20 and the second release film 22, the first carrier 10 and the first release film 12 may be removed, the chip 170 may be placed on the second surface S2 of the first thin film redistribution layer 110, and the base glue 180b may be formed. This still falls within the scope of protection of the present invention.

Structurally, please refer to FIG. 1I and FIG. 2F at the same time. The semiconductor package structure 100b of this embodiment is similar to the semiconductor package structure 100a of FIG. 1I. The difference between the two is that in this embodiment, the packaging glue 180a is not used, but the bottom glue 180b is used. In detail, the bottom glue 180b covers the third connector 160, the fourth connector 172 and the active surface 171 of the chip 170, and exposes the back side 173 and the surrounding surface 175 of the chip 170. Since the bottom glue 180b does not completely cover the chip 170, the semiconductor package structure 100b of this embodiment can have a better heat dissipation effect.

FIG3 is a cross-sectional schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Please refer to FIG1I and FIG3 simultaneously. The semiconductor package structure 100c of this embodiment is similar to the semiconductor package structure 100a of FIG1I. The difference between the two is that in this embodiment, the number of layers of the first thin film redistribution layer 110 is different from the number of layers of the second thin film redistribution layer 130c. Specifically, the first thin film redistribution layer 110 of this embodiment includes two first redistribution wiring layers 112 and three first dielectric layers 114, while the second thin film redistribution layer 130c includes one second redistribution wiring layer 132c and two second dielectric layers 134c. In other words, the number of layers of the first thin film redistribution layer 110 and the second thin film redistribution layer 130c are not symmetrical. Here, the second thin film redistribution layer 130c and the first thin film redistribution layer 110 can form a multi-layer thin film redistribution layer of at least three layers after being bonded, so it can be applied and expanded to more complex systems.

FIG4 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG2F and FIG4 simultaneously. The semiconductor package structure 100d of this embodiment is similar to the semiconductor package structure 100b of FIG2F. The difference between the two is that in this embodiment, the number of layers of the first thin film redistribution layer 110d is different from the number of layers of the second thin film redistribution layer 130. Specifically, the first thin film redistribution layer 110d of this embodiment includes a first redistribution wiring layer 112d and a second first dielectric layer 114d, and the second thin film redistribution layer 130 includes a second second redistribution wiring layer 132 and a third second dielectric layer 134c. That is, the number of layers of the first thin film redistribution layer 110d is not symmetrical with the number of layers of the second thin film redistribution layer 130. Here, the second thin film redistribution layer 130 and the first thin film redistribution layer 110d can be bonded to form a multi-layer thin film redistribution layer of at least three layers, so it can be applied and expanded to more complex systems.

FIG5 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG4 and FIG5 simultaneously. The semiconductor package structure 100e of this embodiment is similar to the semiconductor package structure 100d of FIG4. The difference between the two is that in this embodiment, the semiconductor package structure 100e further includes a redistribution layer 155, including a plurality of third redistribution wiring layers 156 (schematically showing two third redistribution wiring layers 156), a plurality of third dielectric layers 157 (schematically showing three third dielectric layers 157) and a plurality of third conductive vias 158. The third redistribution wiring layer 156 and the third dielectric layer 157 are alternately stacked, and the third redistribution wiring layer 156 is electrically connected through the third conductive via 158. Here, the thickness of each third dielectric layer 157 is greater than the thickness of each second dielectric layer 134 and the thickness of each first dielectric layer 114d, wherein the material of the third dielectric layer 157 is, for example, prepreg (PP) or Ajinomoto Build Up Film (ABF), but is not limited thereto.

In addition, the connectors 142 are respectively connected to the connectors 122, so that the second film redistribution layer 130 is joined to the redistribution layer 155. The filling rubber layer 152 is filled between the second film redistribution layer 130 and the redistribution layer 155, wherein the filling rubber layer 152 covers the connectors 122 and the connectors 142 for protection. Here, the extending direction of the connector 142 (from bottom to top) is opposite to the extending direction of the connector 122 (from top to bottom). The wiring density of the first film redistribution layer 110d is denser than the wiring density of the second film redistribution layer 130, and the wiring density of the second film redistribution layer 130 is denser than the wiring density of the redistribution layer 155. The line width and line spacing of the third redistribution wiring layer 156 are greater than the line width and line spacing of the first redistribution wiring layer 112 d and the line width and line spacing of the second redistribution wiring layer 132 .

FIG6 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG1I and FIG6 simultaneously. The semiconductor package structure 100f of this embodiment is similar to the semiconductor package structure 100a of FIG1I. The difference between the two is that: in this embodiment, the first thin film redistribution layer 110f further includes a first supporting ring P1 surrounding the first redistribution wiring layer 112, and the second thin film redistribution layer 130f further includes a second supporting ring P2 surrounding the second redistribution wiring layer 132, wherein the first supporting ring P1 and the second supporting ring P2 are connected together through the first connector 120 and the second connector 140. Here, the first supporting ring P1 and the second supporting ring P2 can be used as supports to increase the overall structural strength, and can also be used as alignment marks or grounding rings.

FIG7 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG1I and FIG7 simultaneously. The semiconductor package structure 100g of this embodiment is similar to the semiconductor package structure 100a of FIG1I. The difference between the two is that: in this embodiment, the thickness of each second dielectric layer 134g is greater than the thickness of each first dielectric layer 114, and the material of the second dielectric layer 134g is, for example, prepreg (PP) or Ajinomoto Build Up Film (ABF), but is not limited thereto. The wiring density of the first thin film redistribution layer 110 is denser than that of the second thin film redistribution layer 130g, and the line width and line spacing of the second redistribution wiring layer 132g are greater than those of the first redistribution wiring layer 112.

In summary, in the design of the semiconductor package structure of the present invention, the second connectors located on the second thin film redistribution layer are respectively connected to the first connectors located on the first thin film redistribution layer, so that the second thin film redistribution layer is bonded to the first thin film redistribution layer, thereby forming a multi-layer thin film redistribution layer of at least three layers, and the manufacturing process is simple.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10: first carrier 12: first release film 20: second carrier 22: second release film 100a, 100b, 100c, 100d, 100e, 100f, 100g: semiconductor package structure 110, 110d, 110f: first thin film redistribution layer 112, 112d: first redistribution wiring layer 114, 114d: first dielectric layer 116: first conductive via 120: first connector 122, 142: connector 130, 130c, 130f, 130g: second thin film redistribution layer 132, 132c, 132g: second redistribution wiring layer 134, 134c, 134g: second dielectric layer 136, 136g: second conductive via 140: second connector 150, 152: filling glue layer 155: redistribution layer 156: third redistribution line layer 157: third dielectric layer 158: third conductive via 160: third connector 162: pad 164: conductive column 170: chip 171: active surface 172: fourth connector 173: back surface 175: peripheral surface 180a, 180b: packaging glue 185: connection pad 190: anti-soldering layer 192: opening 195: solder ball S1: first surface S2: second surface S3: third surface S4: fourth surface P1: first support ring P2: second support ring

Figures 1A to 1I are cross-sectional schematic diagrams of a method for manufacturing a semiconductor package structure according to an embodiment of the present invention. Figures 2A to 2F are cross-sectional schematic diagrams of partial steps of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. Figure 3 is a cross-sectional schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Figure 4 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Figure 5 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Figure 6 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Figure 7 is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of the present invention.

100a:Semiconductor packaging structure

110: First film redistribution layer

112: First redistribution circuit layer

114: First dielectric layer

116: First conductive via

120: First connecting piece

130: Second film redistribution layer

132: Second distribution line layer

134: Second dielectric layer

136: Second conductive via

140: Second connecting piece

150: Filling glue layer

160: Third connecting piece

162:Pad

164: Conductive column

170: Chip

171: Active side

172: Fourth connecting piece

173:Back

175:Surrounding surface

180a: Packaging colloid

185:Connection pad

190: Anti-welding layer

192: Open mouth

195: Shotgun

S1: First surface

S2: Second surface

S3: Third surface

S4: Fourth surface

Claims (10)

A semiconductor package structure includes: a first thin film redistribution layer having a first surface and a second surface opposite to each other; a plurality of first connectors disposed on the first surface of the first thin film redistribution layer; a second thin film redistribution layer having a third surface and a fourth surface opposite to each other; a plurality of second connectors disposed on the third surface of the second thin film redistribution layer, wherein the second connectors are respectively connected to the first connectors, so that the second thin film redistribution layer is bonded to the first thin film redistribution layer. On the film redistribution layer, the pad spacing of the second surface of the first film redistribution layer is smaller than the pad spacing of the fourth surface of the second film redistribution layer; a plurality of third connectors are arranged on the fourth surface of the second film redistribution layer; a redistribution layer has two opposite surfaces; and a plurality of fourth connectors are arranged on one of the two surfaces of the redistribution layer, wherein the fourth connectors are respectively connected to the third connectors, so that the redistribution layer is bonded to the second film redistribution layer. The semiconductor package structure as described in claim 1 further includes: a filling glue layer, which is filled between the first film redistribution layer and the second film redistribution layer and covers the first connectors and the second connectors. A semiconductor package structure as described in claim 1, wherein the number of layers of the first film redistribution layer is similar to the number of layers of the second film redistribution layer, and the number of layers of the first film redistribution layer is at most one layer more than the number of layers of the second film redistribution layer. A semiconductor package structure as described in claim 1, wherein the number of layers of the first thin film redistribution layer is the same as the number of layers of the second thin film redistribution layer. The semiconductor package structure as described in claim 1 further comprises: a plurality of connection pads, which are separately arranged on the other of the two surfaces of the redistribution layer and are electrically connected to the redistribution layer; and a solder-proof layer, which is arranged on the other of the two surfaces of the redistribution layer and has a plurality of openings, wherein the openings expose a portion of the connection pads. A semiconductor package structure as described in claim 1, wherein the first thin film redistribution layer includes a plurality of first conductive vias, the second thin film redistribution layer includes a plurality of second conductive vias, and the extension direction of the second conductive vias is opposite to the extension direction of the first conductive vias. A semiconductor package structure as described in claim 1, wherein the wiring density of the first thin film redistribution layer is denser than the wiring density of the second thin film redistribution layer. The semiconductor package structure as described in claim 1, wherein the first thin film redistribution layer includes multiple first redistribution circuit layers and a first support ring surrounding the first redistribution circuit layers, and the second thin film redistribution layer includes multiple second redistribution circuit layers and a second support ring surrounding the second redistribution circuit layers, and the first support ring and the second support ring are connected together through the first connectors and the second connectors. A semiconductor package structure as described in claim 1, wherein the first thin film redistribution layer includes a plurality of first dielectric layers, the second thin film redistribution layer includes a plurality of second dielectric layers, and the redistribution layer includes a plurality of third dielectric layers, and the thickness of each third dielectric layer is greater than the thickness of each second dielectric layer and the thickness of each first dielectric layer. A semiconductor package structure as described in claim 9, wherein the material of each third dielectric layer is a film formed of Ajinomoto.