TW202341381A - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a first thin film redistribution layer, a plurality of first connecting members, a second thin film redistribution layer, a plurality of second connecting members, a filling glue layer, a chip and a plurality of solder balls. The first connecting members are disposed on a first surface of the first thin film redistribution layer. The second connecting members are disposed on a third surface of the second thin film redistribution layer. The second connecting members are respectively connected to the first connecting members, so that the second thin film redistribution layer is bonded to the first thin film redistribution layer. The filling glue layer is filled between the first thin film redistribution layer and the second thin film redistribution layer, and covers the first connecting members and the second connecting members. The chip is disposed on a second surface of the first thin film redistribution layer. The solder balls are disposed on a fourth surface of the second thin film redistribution layer.

Description

Semiconductor packaging structure and manufacturing method

The present invention relates to a packaging structure and a manufacturing method thereof, and in particular, to a semiconductor packaging structure and a manufacturing method thereof.

Multilayer thin film redistribution layers are often used as heterogeneous integration substrates. The thin film redistribution layer on the glass carrier is prone to high stress and warpage, so currently only two or three layers of metal and two or three layers of dielectric layers can be installed on the glass carrier. In other words, the circuit layers in the thin film redistribution layer will not exceed three layers at most, thus limiting the application range of the thin film redistribution layer and failing to expand to more complex systems.

The invention provides a semiconductor packaging structure and a manufacturing method thereof, which can have more than three layers of multi-layer film redistribution layers and has a simple manufacturing process.

The semiconductor packaging structure of the present invention includes a first film redistribution layer, a plurality of first connectors, a second film redistribution layer, a plurality of second connectors, a filling glue layer, a chip and a plurality of solder joints. ball. The first film redistribution layer has a first surface and a second surface opposite to each other. The first connecting member is disposed on the first surface of the first film redistribution layer. The second film redistribution layer has a third surface and a fourth surface opposite to each other. The second connectors are disposed on the third surface of the second film redistribution layer, wherein the second connectors are respectively connected to the first connectors, so that the second film redistribution layer is joined to the first film redistribution layer. The filling glue layer is filled between the first film redistribution layer and the second film redistribution layer, and covers the first connecting member and the second connecting member. The wafer is disposed on the second surface of the first thin film redistribution layer. The solder ball is disposed on the fourth surface of the second film redistribution layer.

In an embodiment of the present invention, the above-mentioned semiconductor packaging structure further includes a plurality of third connectors arranged on the second surface of the first thin film redistribution layer. The chip has an opposite active surface and a back surface and a surrounding surface connecting the active surface and the back surface, and the chip includes a plurality of fourth connectors arranged on the active surface. The fourth connecting members are respectively connected to the third connecting members, so that the chip is bonded to the first thin film redistribution layer.

In an embodiment of the present invention, each of the above-mentioned third connecting members includes a contact pad and a conductive post. The contact pads are disposed on the second surface of the first film redistribution layer, and the conductive pillars are located between the contact pads and each fourth connection member of the chip.

In an embodiment of the present invention, the above-mentioned semiconductor packaging structure further includes a packaging colloid covering the third connector, the fourth connector, and the active surface, back surface and surrounding surface of the chip. The edge of the encapsulating glue is flush with the edge of the filling glue layer.

In an embodiment of the present invention, the above-mentioned semiconductor packaging structure further includes a base glue that covers the third connector, the fourth connector and the active surface of the chip, and exposes the backside and surrounding surface of the chip.

In an embodiment of the present invention, the number of layers of the first film redistribution layer is different from the number of layers of the second film redistribution layer.

In an embodiment of the present invention, the number of layers of the first film redistribution layer and the number of layers of the second film redistribution layer are the same.

In an embodiment of the present invention, the above-mentioned semiconductor packaging structure further includes a plurality of connection pads and a solder mask layer. The connection pad is disposed on the fourth surface of the second thin film redistribution layer and is electrically connected to the second thin film redistribution layer. The solder resist layer is disposed on the fourth surface of the second film redistribution layer and has a plurality of openings. The opening exposes part of the connection pad, and the solder balls are respectively located in the opening and connected to the connection pad exposed by the opening.

In an embodiment of the present invention, the extending direction of each first connecting member is opposite to the extending direction of each second connecting member.

In an embodiment of the present invention, the wiring density of the first thin film redistribution layer is denser than the wiring density of the second thin film redistribution layer.

In an embodiment of the present invention, the above-mentioned first thin film redistribution layer includes a plurality of first redistribution circuit layers and a first support ring surrounding the first redistribution circuit layer. The second thin film redistribution layer includes a plurality of second redistribution circuit layers and a second support ring surrounding the second redistribution circuit layer. The first support ring and the second support ring are butted together through the first connecting member and the second connecting member.

The method for manufacturing a semiconductor packaging structure of the present invention includes the following steps. Form a first thin film redistribution layer on the first carrier. A first release film is disposed on the first carrier plate, and the first film redistribution layer has a first surface and a second surface opposite to each other. The first release film is located between the second surface of the first film redistribution layer and the first carrier plate. A plurality of first connectors are formed on the first surface of the first film redistribution layer. Form a second thin film redistribution layer on the second carrier. A second release film is disposed on the second carrier plate, and the second film redistribution layer has a third surface and a fourth surface opposite to each other. The second release film is located between the fourth surface of the second film redistribution layer and the second carrier plate. A plurality of second connectors are formed on the third surface of the second film redistribution layer. The second connecting members are connected to the first connecting members respectively, so that the second film redistribution layer is joined to the first film redistribution layer. A filling glue layer is filled between the first film redistribution layer and the second film redistribution layer, wherein the filling glue layer covers the first connecting member and the second connecting member. The first carrier plate and the first release film are removed to expose the second surface of the first film redistribution layer. A chip is disposed on the second surface of the first film redistribution layer. The second carrier plate and the second release film are removed to expose the fourth surface of the second film redistribution layer. A plurality of solder balls are disposed on the fourth surface of the second film redistribution layer.

In one embodiment of the present invention, before removing the second carrier plate and the second release film, the first carrier plate and the first release film are first removed and the wafer is placed on the second layer of the first film redistribution layer. On the surface.

In one embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor packaging structure further includes forming a plurality of third connectors on the second surface of the first thin film redistribution layer after removing the first carrier board and the first release film. superior. Each third connection member includes a pad and a conductive post. The contact pads are disposed on the second surface of the first film redistribution layer, and the conductive pillars are located on the contact pads. The chip has an opposite active surface and a back surface and a surrounding surface connecting the active surface and the back surface, and the chip includes a plurality of fourth connectors arranged on the active surface. When the chip is placed on the second surface of the first thin film redistribution layer, the fourth connectors are connected to the third connectors respectively, so that the chip is bonded to the first thin film redistribution layer.

In an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor packaging structure further includes, before removing the second carrier board and the second release film, forming an encapsulating colloid to cover the third connector, the fourth connector and the The active side, backside and surrounding surfaces of the wafer. The edge of the encapsulating glue is flush with the edge of the filling glue layer.

In an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor packaging structure further includes, after removing the second carrier board and the second release film, forming a plurality of connection pads separated from each other on a fourth layer of the second thin film redistribution layer. On the surface, the connection pads are electrically connected to the second film redistribution layer. A solder mask layer is formed on the fourth surface of the second film redistribution layer. The solder mask has openings to expose portions of the connection pads. When the solder balls are disposed on the fourth surface of the second film redistribution layer, the solder balls are respectively located in the openings and connected to the connection pads exposed by the openings.

In one embodiment of the present invention, before removing the first carrier plate and the first release film, the second carrier plate and the second release film are first removed and solder balls are disposed on the second film redistribution layer. Four on the surface.

In an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor packaging structure further includes, after removing the second carrier board and the second release film, forming a plurality of connection pads separated from each other on a fourth layer of the second thin film redistribution layer. On the surface, the connection pads are electrically connected to the second film redistribution layer. A solder mask layer is formed on the fourth surface of the second film redistribution layer. The solder mask has openings to expose portions of the connection pads. When the solder balls are disposed on the fourth surface of the second film redistribution layer, the solder balls are respectively located in the openings and connected to the connection pads exposed by the openings.

In one embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor packaging structure further includes forming a plurality of third connectors on the second surface of the first thin film redistribution layer after removing the first carrier board and the first release film. superior. Each third connection member includes a pad and a conductive post. The contact pads are disposed on the second surface of the first film redistribution layer, and the conductive pillars are located on the contact pads. The chip has an opposite active surface and a back surface and a surrounding surface connecting the active surface and the back surface, and the chip includes a plurality of fourth connectors arranged on the active surface. When the chip is placed on the second surface of the first thin film redistribution layer, the fourth connectors are connected to the third connectors respectively, so that the chip is bonded to the first thin film redistribution layer.

In an embodiment of the present invention, the method for manufacturing the semiconductor packaging structure further includes forming a base glue to cover the third connector, the fourth connector and the active surface of the chip. The primer exposes the backside of the wafer and surrounding surfaces.

In an embodiment of the present invention, the material of the above-mentioned primer is different from the material of the filling colloid.

In an embodiment of the present invention, the number of layers of the first film redistribution layer is different from the number of layers of the second film redistribution layer.

In an embodiment of the present invention, the number of layers of the first film redistribution layer and the number of layers of the second film redistribution layer are the same.

In an embodiment of the present invention, the extending direction of each first connecting member is opposite to the extending direction of each second connecting member.

In an embodiment of the present invention, the wiring density of the first thin film redistribution layer is denser than the wiring density of the second thin film redistribution layer.

In an embodiment of the present invention, the above-mentioned first thin film redistribution layer includes a plurality of first redistribution circuit layers and a first support ring surrounding the first redistribution circuit layer. The second thin film redistribution layer includes a plurality of second redistribution circuit layers and a second support ring surrounding the second redistribution circuit layer. The first support ring and the second support ring are butted together through the first connecting member and the second connecting member.

Based on the above, in the design of the semiconductor packaging structure of the present invention, the second connectors located on the second film redistribution layer are respectively connected to the first connectors located on the first film redistribution layer, so that the second film redistribution layer By being bonded to the first film redistribution layer, at least three or more multi-layer film redistribution layers can be formed, and the process is simple.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

1A to 1I are schematic cross-sectional views of a method for manufacturing a semiconductor packaging structure according to an embodiment of the present invention. Regarding the manufacturing method of the semiconductor packaging structure of this embodiment, first, please refer to FIG. 1A to form a first thin film redistribution layer 110 on the first carrier 10 . A first release film 12 is disposed on the first carrier plate 10 , and the first film redistribution layer 110 has a first surface S1 and a second surface S2 opposite to each other. The first release film 12 is located between the second surface S2 of the first film redistribution layer 110 and the first carrier 10 .

Specifically, in this embodiment, the first carrier 10 is, for example, a temporary substrate, and the material of the first carrier 10 can be glass, plastic, silicon, or metal. or other suitable materials, as long as the material can support the structure formed on it in subsequent processes. In some embodiments, the first release film 12 (eg, light to heat conversion film or other suitable de-bonding layer) applied on the first carrier 10 can The releasability of the subsequently formed structure from the first carrier 10 is increased in a subsequent de-bonding process. Alternatively, the first release film 12 can be omitted.

As shown in FIG. 1A , a first thin film redistribution layer 110 may be formed above the first carrier 10 , where the first thin film redistribution layer 110 includes multiple layers of first redistribution circuit layers 112 (schematically showing two layers of first layer redistribution circuits). Distribution circuit layer 112), a multi-layer first dielectric layer 114 (three first dielectric layers 114 are schematically shown) and a plurality of first conductive vias 116. The first redistribution wiring layer 112 and the first conductive vias 116 buried in the first dielectric layer 114 may collectively be regarded as fine redistribution circuits of the first thin film redistribution layer 110 .

In some embodiments, the materials of the first redistribution circuit layer 112 and the first conductive via 116 may be or may include copper, gold, nickel, aluminum, platinum. ), tin, metal alloy, combinations thereof or other suitable conductive materials. The first dielectric layers 114 are stacked on each other, and the material of the first dielectric layer 114 may be or may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole ( polybenzoxazole (PBO), inorganic dielectric materials (for example, silicon oxide (silicon oxide), silicon nitride (silicon nitride), etc.) or other suitable electrical insulating materials.

In some embodiments, a metal deposition process, a lithography and etching process, or other suitable techniques may be used to form the first redistribution circuit layer 112 above the first carrier 10 . In some embodiments, the first redistribution circuit layer 112 at a bottom level near the first carrier board 10 includes a plurality of conductive pads (not shown) for subsequent element mounting processes. -mounting process). Next, a coating process, a photolithography and etching process or other suitable techniques may be used to form a first dielectric layer 114 with an opening above the first carrier 10 to cover the first carrier 10 . A redistribution circuit layer 112. The opening of the first dielectric layer 114 may expose at least a portion of the first redistribution wiring layer 112 for further electrical connection. Optionally, the first dielectric layer 114 is formed before forming the first redistribution circuit layer 112 . Subsequently, plating, deposition, or other suitable processes may be used to form conductive material in the openings of the first dielectric layer 114 to form the first conductive vias 116 . The term "conductive via" may be an element that provides a vertical electrical connection between layers and penetrates the plane of one or more adjacent layers. When forming the conductive material in the opening, the conductive material may also be formed on the top surface of the first dielectric layer 114 and then patterned on the top surface of the first dielectric layer 114 to form another layer of the conductive material. A redistribution circuit layer 112. The first redistribution line layer 112 on the top surface of the first dielectric layer 114 may include conductive lines and pads. The first redistribution wiring layer 112 may be referred to as a patterned conductive layer with fine line/space wiring.

The above steps may be repeatedly performed, so that the first redistribution line layer 112 and the first dielectric layer 114 are alternately stacked, and the first conductive via 116 is buried in the first dielectric layer 114 . The first conductive vias 116 may form electrical and physical connections between the first redistribution wiring layers 112 in different layers. In some embodiments, the first thin film redistribution layer 110 is a stack of layers with fine line/space routing. It should be noted that the first thin film redistribution layer 110 shown in FIG. 1A is only exemplary, and more or fewer layers of redistribution structures may be formed according to the needs of circuit design.

Please continue to refer to FIG. 1A , the first thin film redistribution layer 110 includes a first surface S1 and a second surface S2 that are opposite to each other, wherein the second surface S2 faces the first carrier plate 10 . The first conductive via 116 and the first dielectric layer 114 at the second surface S2 of the first thin film redistribution layer 110 may be substantially flush. In some embodiments, the first redistribution wiring layer 112 may be formed at the top surface of the uppermost layer in the first dielectric layer 114 . In this case, the first surface S1 includes the first redistribution wiring layer 112 and the uppermost first dielectric layer 114 . In some embodiments, the first conductive via 116 tapers toward the first carrier 10 . The thickness of the first thin film redistribution layer 110 may range from about 2 μm to about 10 μm. Although other values are possible depending on product requirements/process recipes.

Next, please continue to refer to FIG. 1A to form a plurality of first connectors 120 on the first surface S1 of the first thin film redistribution layer 110 . The first connecting member 120 is, for example, a pillar portion formed on the first surface S1 of the first film redistribution layer 110, where the diameter of the first connecting member 120 gradually decreases in a direction away from the first surface S1, But it is not limited to this. In another embodiment, the diameter of the first connecting member 120 may also gradually increase in a direction away from the first surface S1. In this embodiment, the first connection member 120 and the first conductive via 116 may be plated during the same step. Optionally, after forming the first film redistribution layer 110, the first connector 120 is formed separately (or placed on the first film redistribution layer 110). In some embodiments, the material of the first connector 120 includes copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, or another suitable conductive material. It should be noted that the number of the first connecting members 120 shown here is for illustrative purposes only and does not constitute a limitation on the present invention.

Next, please refer to FIG. 1B to form a second thin film redistribution layer 130 on the second carrier 20 . A second release film 22 is disposed on the second carrier plate 20 , and the second film redistribution layer 130 has a third surface S3 and a fourth surface S4 opposite to each other. The second release film 22 is located between the fourth surface S4 of the second film redistribution layer 130 and the second carrier plate 20 , where the fourth surface S4 faces the second carrier plate 20 , and the second carrier plate 20 is, for example, a temporary substrate. The second thin film redistribution layer 130 includes multiple layers of second redistribution circuit layers 132 (schematically showing two layers of second redistribution circuit layers 132), multiple layers of second dielectric layers 134 (schematically showing three layers of second dielectric layers). layer 134) and a plurality of second conductive vias 136.

It should be noted that the materials of the second carrier plate 20 and the second release film 22 are the same or similar to those of the first carrier plate 10 and the first release film 12 , and the manufacturing method of the second film redistribution layer 130 is the same as that of the first carrier plate 10 and the first release film 12 . The material is the same as or similar to the manufacturing method and material of the first film redistribution layer 110 . Please refer to the description of the first carrier plate 10 , the first release film 12 and the first film redistribution layer 110 , and will not be described again here. .

Next, please refer to FIG. 1B again to form a plurality of second connectors 140 on the third surface S3 of the second film redistribution layer 130 . The second connecting member 140 is, for example, a pillar portion formed on the third surface S3 of the second film redistribution layer 130, where the diameter of the second connecting member 140 gradually decreases in a direction away from the third surface S3. But it is not limited to this. In another embodiment, the diameter of the second connecting member 140 may also gradually increase in a direction away from the third surface S3. In this embodiment, the second connection member 140 and the second conductive via 136 may be plated during the same step. Optionally, the second connector 140 is formed separately (or placed on the second film redistribution layer 130) after the second film redistribution layer 130 is formed. In some embodiments, the material of the second connector 140 includes copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, or another suitable conductive material. It should be noted that the number of the second connecting members 140 shown here is for illustrative purposes only and does not constitute a limitation on the present invention.

Next, please refer to FIG. 1B again, the third surface S3 of the second film redistribution layer 130 faces the first surface S1 of the first film redistribution layer 110, so that the second connectors 140 are connected to the first connectors respectively. 120, so that the second film redistribution layer 130 is bonded to the first film redistribution layer 110. Here, the second connecting member 140 is structurally connected and electrically connected to the first connecting member 120. The second connecting member 140 may be aligned with the first connecting member 120, or may be connected in a misaligned manner, which is not specified here. limit. The first film redistribution layer 110 is electrically connected to the second film redistribution layer 130 through the first connection member 120 and the second connection member 140 .

Here, the number of layers of the first thin film redistribution layer 110 (including the number of circuit layers and the number of dielectric layers) is the same as the number of layers of the second thin film redistribution layer 130 , that is, the number of layers of the first thin film redistribution layer 110 and the second thin film redistribution layer 130 are the same. The number of redistribution layers 130 is symmetrical, but is not limited to this. In particular, the wiring density of the first thin film redistribution layer 110 is denser than the wiring density of the second thin film redistribution layer 130 , and the extension direction of the second conductive via hole 136 is opposite to the extension direction of the first conductive via hole 116 , and the second conductive via hole 136 extends in a direction opposite to that of the first conductive via hole 116 . The extending direction of the first connecting member 120 (eg, upward and downward) is opposite to the extending direction of the second connecting member 140 (eg, downward and downward), but is not limited to this.

Next, please refer to FIG. 1C , a filling glue layer 150 is filled between the first film redistribution layer 110 and the second film redistribution layer 130 , wherein the filling glue layer 150 covers the first connecting member 120 and the second connecting member 140 for protection. For example, a dispensing process of underfill material may be performed, and then a curing process may be performed to form the filler layer 150 . For example, the filling glue layer 150 fills the gap between the first surface S1 of the first film redistribution layer 110 and the third surface S3 of the second film redistribution layer 130 to surround, cover, and encapsulate the first surface S1 of the first film redistribution layer 130 . The connecting piece 120 and the second connecting piece 140 .

Next, please refer to FIG. 1C and FIG. 1D simultaneously to remove the first carrier plate 10 and the first release film 12 to expose the second surface S2 of the first thin film redistribution layer 110 . For example, by applying external energy (for example, heat and/or pressure, etc.) to the first release film 12 located between the first film redistribution layer 110 and the first carrier plate 10, the first release film 12 is connected to the first release film 12. The first film redistribution layer 110 is delaminated. Other suitable processes (eg, mechanical removing, etching, grinding, etc.) may be used to remove the temporary first carrier 10 and the first release film 12 . Optionally, a cleaning process is performed on the second surface S2 of the first film redistribution layer 110 to remove residues of the first release film 12 . The bottom surface of the first conductive via 116 flush with the lowermost layer of the first dielectric layer 114 on the second surface S2 may be exposed for further electrical connection after de-bonding.

Next, referring to FIG. 1E , a plurality of third connectors 160 are formed on the second surface S2 of the first thin film redistribution layer 110 . Each third connection member 160 includes a pad 162 and a conductive post 164 , wherein the pad 162 is disposed on the second surface S2 of the first film redistribution layer 110 and is electrically connected to the first conductive via 116 . The conductive pillars 164 are respectively located on the pads 162, and the conductive pillars 164 are electrically connected to the first thin film redistribution layer 110 through the pads.

1F, the chip 170 is placed on the second surface S2 of the first thin film redistribution layer 110. The chip 170 has an opposite active surface 171 and a back surface 173, and a surrounding area connecting the active surface 171 and the back surface 173. surface 175 , and the chip 170 includes a plurality of fourth connectors 172 disposed on the active surface 171 . The fourth connecting members 172 of the chip 170 are connected to the conductive pillars 164 of the third connecting member 160 respectively, so that the chip 170 is bonded to the first thin film redistribution layer 110 . Here, the chip 170 is electrically connected to the first thin film redistribution layer 110 through flip-chip bonding.

Next, please refer to FIG. 1G , an encapsulant 180 a is formed to cover the third connector 160 , the fourth connector 172 , and the active surface 171 , the back surface 173 and the surrounding surface 175 of the chip 170 . That is to say, the packaging colloid 180a completely covers the chip 170, and the edges of the packaging colloid 180a are substantially flush with the edges of the filling adhesive layer 150, the edges of the first film redistribution layer 110 and the second film redistribution layer 130. edge, but not limited thereto.

Next, please refer to FIG. 1G and FIG. 1H simultaneously to remove the second carrier plate 20 and the second release film 22 to expose the fourth surface S4 of the second thin film redistribution layer 130 . That is to say, before removing the second carrier plate 20 and the second release film 22 in this embodiment, the first carrier plate 10 and the first release film 12 have been removed and the chip 170 has been placed on the first film redistribution layer. 110 on the second surface S2. Here, the second carrier plate 20 and the second release film 22 are removed in the same manner as the above-mentioned removal of the first carrier plate 10 and the first release film 12. Please refer to the above-mentioned removal of the first carrier plate 10 and the first release film 12. The method of the release film 12 will not be described again here.

1I, a plurality of separate connection pads 185 are formed on the fourth surface S4 of the second film redistribution layer 130, wherein the connection pads 185 are located on the outermost second dielectric layer 134 and are connected to the second dielectric layer 134. The outermost second conductive via hole 136 of the thin film redistribution layer 130 is electrically connected. Next, a solder mask 190 is formed on the fourth surface S4 of the second film redistribution layer 130 , wherein the solder mask 190 is located on the outermost second dielectric layer 134 and has a plurality of openings 192 for exposure. A portion of each connection pad 185 is removed.

Finally, please refer to FIG. 1I again, and solder balls 195 are disposed on the fourth surface S4 of the second film redistribution layer 130 . The solder balls 195 are respectively located in the openings 192 of the solder mask 190 and are structurally connected and electrically connected to the connection pads 185 exposed by the openings 192 . The chip 170 can be connected to the outside through the third connection member 160 , the first film redistribution layer 110 , the first connection member 120 , the second connection member 140 , the second film redistribution layer 130 , the pads 185 and the solder balls 195 in sequence. Circuits (not shown) are electrically connected. At this point, the fabrication of the semiconductor packaging structure 100a has been completed.

It should be noted that in another embodiment not shown, the second carrier plate 20 and the second release film may also be removed before the first carrier plate 10 and the first release film 12 are removed. 22 and arranging the connection pads 185 and the solder balls 195 on the fourth surface S4 of the second film redistribution layer 130, this still belongs to the scope of protection of the present invention.

Structurally, please refer to FIG. 1I again. The semiconductor packaging structure 100a of this embodiment includes a first thin film redistribution layer 110, a first connector 120, a second thin film redistribution layer 130, a second connector 140, and a filling adhesive layer. 150, chip 170 and solder ball 195. The first thin film redistribution layer 110 has an opposite first surface S1 and a second surface S2, and includes two layers of first redistribution circuit layers 112, three layers of first dielectric layers 114, and a plurality of first conductive vias 116. The first connector 120 is disposed on the first surface S1 of the first film redistribution layer 110 . The second thin film redistribution layer 130 has an opposite third surface S3 and a fourth surface S4, and includes two layers of second redistribution circuit layers 132, three layers of second dielectric layers 134, and a plurality of second conductive vias 136. The second connectors 140 are disposed on the third surface S3 of the second film redistribution layer 130, where the second connectors 140 are respectively connected to the first connectors 120, so that the second film redistribution layer 130 is joined to the first film redistribution layer. On the cloth layer 110. Here, the number of layers of the first redistribution circuit layer 112 is the same as the number of layers of the second redistribution circuit layer 132, and the number of layers of the first dielectric layer 114 is the same as the number of layers of the second dielectric layer 134, but they are not This is the limit. The filling glue layer 150 is filled between the first film redistribution layer 110 and the second film redistribution layer 130 and covers the first connecting member 120 and the second connecting member 140 . The wafer 170 is disposed on the second surface S2 of the first thin film redistribution layer 110 . The solder ball 195 is disposed on the fourth surface S4 of the second thin film redistribution layer 130 .

Furthermore, in this embodiment, the semiconductor packaging structure 100a further includes a third connector 160 disposed on the second surface S2 of the first film redistribution layer 110, where the third connector 160 includes a pad 162 and a conductive pillar. 164. The wafer 170 has an opposite active surface 171 and a back surface 173 and a surrounding surface 175 connecting the active surface 171 and the back surface 173 , and the wafer 170 includes a fourth connecting member 172 disposed on the active surface 171 . The fourth connecting members 172 are respectively connected to the third connecting members 160 so that the chip 170 is bonded to the first thin film redistribution layer 110 . The contact pad 162 is disposed on the second surface S2 of the first thin film redistribution layer 110 , and the conductive pillar 164 is located between the contact pad 162 and the fourth connection member 172 of the chip 170 .

In addition, the semiconductor packaging structure 100a of this embodiment also includes a packaging colloid 180a covering the third connector 160, the fourth connector 172, the active surface 171, the back surface 173 and the surrounding surface 175 of the chip 170. The edge of the encapsulating glue 180a is flush with the edge of the filling glue layer 150. In addition, the semiconductor package structure 100a also includes connection pads 185 and a solder mask 190. The connection pad 185 is disposed on the fourth surface S4 of the second thin film redistribution layer 130 and is structurally and electrically connected to the outermost second conductive via 136 of the second thin film redistribution layer 130 . The solder resist layer 190 is disposed on the fourth surface S4 of the second film redistribution layer 130 and has an opening 192 , wherein the opening 192 exposes part of the connection pad 185 . The solder balls 195 are respectively located in the openings 192 of the solder mask 190 and are structurally and electrically connected to the connection pads 185 exposed by the openings 192 .

In short, in the manufacturing method of the semiconductor packaging structure 100a of this embodiment, the first connectors located on the first thin film redistribution layer 110 are respectively connected through the second connectors 140 located on the second thin film redistribution layer 130 120, so that the second film redistribution layer 130 is bonded to the first film redistribution layer 110, thereby forming at least three or more multi-layer film redistribution layers. Compared with the conventional method which can only form a thin film redistribution layer of no more than three layers of circuits on a glass substrate, the manufacturing method of the semiconductor packaging structure 100a of this embodiment has the advantage of a simple process and is not limited to the conventional method. Only two or three layers of metal can be placed on the glass substrate. Furthermore, in this embodiment, the first thin film redistribution layer 110 with a relatively dense wiring density is bonded to the chip 170, and the second thin film redistribution layer 130 with a relatively sparse wiring density is bonded to the solder balls 195, thereby forming a fan-out. Fan-out line structure. In addition, since the semiconductor packaging structure 100a of this example can have at least three or more multi-layer thin film redistribution layers, it can be applied and expanded to more complex systems.

It must be noted here that the following embodiments follow the component numbers and part of the content of the previous embodiments, where the same numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be repeated in the following embodiments.

2A to 2F are schematic cross-sectional views of partial steps of a method for manufacturing a semiconductor packaging structure according to another embodiment of the present invention. The manufacturing method of the semiconductor packaging structure of this embodiment is similar to the manufacturing method of the semiconductor packaging structure mentioned above. The difference between the two is that after the step of FIG. 1C , the filling glue layer 150 is filled in the first film redistribution layer 110 and the After the two film redistribution layers 130 are removed, please refer to FIGS. 1C and 2A simultaneously to remove the second carrier plate 20 and the second release film 22 to expose the fourth surface S4 of the second film redistribution layer 130 .

Next, please refer to FIG. 2B to form separate connection pads 185 on the fourth surface S4 of the second thin film redistribution layer 130 , wherein the connection pads 185 are located on the outermost second dielectric layer 134 of the second thin film redistribution layer 130 , and is electrically connected to the outermost second conductive via hole 136 of the second thin film redistribution layer 130 .

Next, please refer to FIG. 2B again to form a solder resist layer 190 on the fourth surface S4 of the second film redistribution layer 130 . The solder mask layer 190 is located on the outermost second dielectric layer 134 of the second film redistribution layer 130 , and the solder mask layer 190 has an opening 192 to expose part of the connection pad 185 .

Next, referring to FIG. 2C , solder balls 195 are disposed on the fourth surface S4 of the second thin film redistribution layer 130 . The solder balls 195 are respectively located in the openings 192 of the solder mask 190 and are structurally and electrically connected to the connection pads 185 exposed by the openings 192 .

Next, please refer to FIG. 2C and FIG. 2D simultaneously to remove the first carrier plate 10 and the first release film 12 to expose the second surface S2 of the first thin film redistribution layer 110 . In other words, before removing the first carrier plate 10 and the first release film 12 in this embodiment, the second carrier plate 20 and the second release film 22 have been removed and the solder balls 195 have been placed on the second film redistribution layer 130 The fourth surface is S4.

Next, please refer to FIG. 2D again to form a third connection member 160 on the second surface S2 of the first thin film redistribution layer 110 . The third connection member 160 includes a pad 162 and a conductive post 164 . The contact pads 162 are disposed on the second surface S2 of the first film redistribution layer 110 , and the conductive pillars 164 are located on the contact pads 162 .

2E, the chip 170 is placed on the second surface S2 of the first thin film redistribution layer 110, in which the fourth connectors 172 of the chip 170 are respectively connected to the conductive pillars 164 of the third connector 160, so that the chip 170 Joined to the first film redistribution layer 110. Here, the chip 170 is electrically connected to the first thin film redistribution layer 110 through flip-chip bonding.

Finally, please refer to FIG. 2F, a base glue 180b is formed to cover the third connector 160, the fourth connector 172 and the active surface 171 of the chip 170, wherein the base glue 180b exposes the backside 173 of the chip 170 and the surrounding surface 175. Can have better heat dissipation effect. Here, the material of the base glue 180b may be the same as or different from the material of the filling colloid 150, and is not limited thereto. At this point, the method of manufacturing the semiconductor packaging structure 100b has been completed.

It should be noted that in another embodiment not shown, the first carrier plate 10 and the first release film 12 may have been removed before the second carrier plate 20 and the second release film 22 are removed. Placing the chip 170 on the second surface S2 of the first thin film redistribution layer 110 and forming the primer 180b still fall within the scope of protection of the present invention.

Structurally, please refer to FIG. 1I and FIG. 2F at the same time. The semiconductor packaging structure 100b of this embodiment is similar to the semiconductor packaging structure 100a of FIG. 1I. The difference between the two is that in this embodiment, no packaging colloid 180a is used. It uses base glue 180b. In detail, the primer 180b covers the third connector 160 , the fourth connector 172 and the active surface 171 of the chip 170 , and exposes the backside 173 and surrounding surface 175 of the chip 170 . Since the base glue 180b does not completely cover the chip 170, the semiconductor packaging structure 100b of this embodiment can have a better heat dissipation effect.

FIG. 3 is a schematic cross-sectional view of a semiconductor packaging structure according to an embodiment of the present invention. Please refer to FIG. 1I and FIG. 3 at the same time. The semiconductor packaging structure 100c of this embodiment is similar to the semiconductor packaging structure 100a of FIG. 1I. The difference between the two is that in this embodiment, the number of layers of the first thin film redistribution layer 110 is different. The number of layers in the second film redistribution layer 130c. Specifically, the first thin film redistribution layer 110 of this embodiment includes two layers of first redistribution circuit layers 112 and three layers of first dielectric layers 114, while the second thin film redistribution layer 130c includes one layer of second redistribution The circuit layer 132c and the two second dielectric layers 134c. That is to say, the number of layers of the first thin film redistribution layer 110 and the second thin film redistribution layer 130c is not symmetrical. Here, after the second film redistribution layer 130c and the first film redistribution layer 110 are combined, a multi-layer film redistribution layer of at least three layers can be formed, so that it can be applied and expanded to more complex systems.

FIG. 4 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. Please refer to FIG. 2F and FIG. 4 at the same time. The semiconductor packaging structure 100d of this embodiment is similar to the semiconductor packaging structure 100b of FIG. 2F. The difference between the two is that in this embodiment, the number of layers of the first thin film redistribution layer 110d is different. The number of layers of the second film redistribution layer 130. Specifically, the first thin film redistribution layer 110d of this embodiment includes a first redistribution circuit layer 112d and two layers of first dielectric layers 114d, while the second thin film redistribution layer 130 includes two layers of second redistribution layers. The circuit layer 132 and the three-layer second dielectric layer 134c. That is to say, the number of layers of the first thin film redistribution layer 110d and the second thin film redistribution layer 130 is not symmetrical. Here, after the second film redistribution layer 130 and the first film redistribution layer 110d are combined, a multi-layer film redistribution layer of at least three layers can be formed, so that it can be applied and expanded to more complex systems.

FIG. 5 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. Please refer to FIG. 4 and FIG. 5 at the same time. The semiconductor packaging structure 100e of this embodiment is similar to the semiconductor packaging structure 100d of FIG. 4. The difference between the two is that in this embodiment, the semiconductor packaging structure 100e also includes a redistribution layer 155. It includes multiple third redistribution circuit layers 156 (schematically showing two third redistribution circuit layers 156), multiple third dielectric layers 157 (schematically showing three third dielectric layers 157) and a plurality of third dielectric layers 157. Three conductive vias 158. The third redistribution circuit layer 156 and the third dielectric layer 157 are alternately stacked, and the third redistribution circuit layer 156 is electrically connected through the third conductive via 158 . Here, the thickness of each third dielectric layer 157 is greater than the thickness of each second dielectric layer 134 and the thickness of each first dielectric layer 114d, wherein the material of the third dielectric layer 157 is, for example, prepreg. (prepreg, PP) or Ajinomoto Build up Film (ABF), but is not limited to this.

In addition, the connecting members 142 are connected to the connecting members 122 respectively, so that the second film redistribution layer 130 is joined to the redistribution layer 155 . The filling glue layer 152 is filled between the second film redistribution layer 130 and the redistribution layer 155 , wherein the filling glue layer 152 covers the connector 122 and the connector 142 for protection. Here, the extending direction of the connecting member 142 (from bottom to top) is opposite to the extending direction of the connecting member 122 (from top to bottom). The wiring density of the first thin film redistribution layer 110d is denser than the wiring density of the second thin film redistribution layer 130, and the wiring density of the second thin film redistribution layer 130 is denser than the wiring density of the redistribution layer 155. The line width and line spacing of the third redistribution circuit layer 156 are greater than the line width and line spacing of the first redistribution circuit layer 112d and the line width and line spacing of the second redistribution circuit layer 132.

FIG. 6 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. Please refer to FIG. 1I and FIG. 6 at the same time. The semiconductor packaging structure 100f of this embodiment is similar to the semiconductor packaging structure 100a of FIG. 1I. The difference between the two is that in this embodiment, the first thin film redistribution layer 110f also includes a surrounding A first support ring P1 of a redistribution circuit layer 112, and the second thin film redistribution layer 130f also includes a second support ring P2 surrounding the second redistribution circuit layer 132, wherein the first support ring P1 and the second support ring The ring P2 is connected to the second connecting member 140 through the first connecting member 120 . Here, in addition to being used as supports to increase the overall structural strength, the first support ring P1 and the second support ring P2 can also be used as alignment marks or grounding rings.

FIG. 7 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. Please refer to FIG. 1I and FIG. 7 at the same time. The semiconductor packaging structure 100g of this embodiment is similar to the semiconductor packaging structure 100a of FIG. 1I. The difference between the two is that in this embodiment, the thickness of each second dielectric layer 134g is greater than The thickness of each first dielectric layer 114 and the material of the second dielectric layer 134g are, for example, prepreg (PP) or Ajinomoto Build up Film (ABF), but this is not used as a limit. The wiring density of the first thin film redistribution layer 110 is denser than the wiring density of the second thin film redistribution layer 130g, and the line width and line spacing of the second redistribution circuit layer 132g are greater than the line width and line spacing of the first redistribution circuit layer 112 distance.

To sum up, in the design of the semiconductor packaging structure of the present invention, the second connectors located on the second film redistribution layer are respectively connected to the first connectors located on the first film redistribution layer, so that the second film redistribution layer The cloth layer is bonded to the first film redistribution layer, thereby forming at least three or more multi-layer film redistribution layers, and the manufacturing process is simple.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10: First carrier board 12:The first release film 20: Second carrier board 22: Second release film 100a, 100b, 100c, 100d, 100e, 100f, 100g: semiconductor packaging structure 110, 110d, 110f: first film redistribution layer 112, 112d: The first redistribution line layer 114, 114d: first dielectric layer 116: First conductive via 120: First connector 122, 142: Connector 130, 130c, 130f, 130g: second film redistribution layer 132, 132c, 132g: second redistribution line layer 134, 134c, 134g: second dielectric layer 136, 136g: Second conductive via 140:Second connector 150, 152: Filling glue layer 155:Redistribution layer 156: The third redistribution line layer 157:Third dielectric layer 158:Third conductive via 160:Third connector 162: Pad 164:Conductive pillar 170:wafer 171: Active side 172:Fourth connector 173:Back 175:surrounding surface 180a, 180b: Encapsulating colloid 185:Connection pad 190: Solder mask 192:Open your mouth 195: Solder ball S1: first surface S2: Second surface S3: Third surface S4: The fourth surface P1: first support ring P2: Second support ring

1A to 1I are schematic cross-sectional views of a method for manufacturing a semiconductor packaging structure according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views of partial steps of a method for manufacturing a semiconductor packaging structure according to another embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a semiconductor packaging structure according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a semiconductor packaging structure according to another embodiment of the present invention.

100a: Semiconductor packaging structure

110: First film redistribution layer

112: First redistribution line layer

114: First dielectric layer

116: First conductive via

120: First connector

130: Second film redistribution layer

132: Second redistribution line layer

134: Second dielectric layer

136: Second conductive via

140:Second connector

150: Filling glue layer

160:Third connector

162: Pad

164:Conductive pillar

170:wafer

171: Active side

172:Fourth connector

173:Back

175:surrounding surface

180a: Encapsulating colloid

185:Connection pad

190: Solder mask

192:Open your mouth

195: Solder ball

S1: first surface

S2: Second surface

S3: Third surface

S4: The fourth surface

Claims (10)

A semiconductor packaging structure including: A first thin film redistribution layer has a first surface and a second surface opposite to each other; A plurality of first connectors arranged on the first surface of the first film redistribution layer; a second thin film redistribution layer having an opposite third surface and a fourth surface; A plurality of second connectors are arranged on the third surface of the second film redistribution layer, wherein the second connectors are respectively connected to the first connectors, so that the second film redistribution layer is joined to On the first thin film redistribution layer, the pad spacing on the second surface of the first thin film redistribution layer is smaller than the pad spacing on the fourth surface of the second thin film redistribution layer; A plurality of third connectors are arranged on the fourth surface of the second film redistribution layer; A redistribution layer with two opposing surfaces; and A plurality of fourth connectors are arranged on one of the two surfaces of the redistribution layer, wherein the fourth connectors are respectively connected to the third connectors, so that the redistribution layer is joined to the second Film redistribution layer. The semiconductor packaging structure as described in claim 1 further includes: A filling glue layer is filled between the first film redistribution layer and the second film redistribution layer, and covers the first connecting members and the second connecting members. The semiconductor packaging structure of claim 1, wherein the number of layers of the first thin film redistribution layer is similar to the number of layers of the second thin film redistribution layer, and the number of layers of the first thin film redistribution layer is greater than that of the second thin film redistribution layer. The number of redistribution layers is at most one more. The semiconductor packaging structure of claim 1, wherein the number of layers of the first thin film redistribution layer is the same as the number of layers of the second thin film redistribution layer. The semiconductor packaging structure as described in claim 1 further includes: A plurality of connection pads are separately arranged on the fourth surface of the second thin film redistribution layer and are electrically connected to the second thin film redistribution layer; and A solder mask layer is disposed on the other of the two surfaces of the redistribution layer and has a plurality of openings, wherein the openings expose part of the connection pads. The semiconductor packaging structure of claim 1, wherein the first thin film redistribution layer includes a plurality of first conductive vias, the second thin film redistribution layer includes a plurality of second conductive vias, and the second conductive vias The extension direction of the hole is opposite to the extension direction of the first conductive via hole. The semiconductor packaging structure of claim 1, wherein the wiring density of the first thin film redistribution layer is denser than the wiring density of the second thin film redistribution layer. The semiconductor packaging structure of claim 1, wherein the first thin film redistribution layer includes a plurality of first redistribution circuit layers and a first support ring surrounding the first redistribution circuit layers, and the second thin film redistribution layer The fabric layer includes multiple layers of second redistribution circuit layers and a second support ring surrounding the second redistribution circuit layers. The first support ring and the second support ring pass through the first connectors and the second support rings. The connectors are butted together. The semiconductor packaging structure of claim 1, wherein the first thin film redistribution layer includes a plurality of first dielectric layers, the second thin film redistribution layer includes a plurality of second dielectric layers, and the redistribution layer includes A plurality of third dielectric layers, the thickness of each third dielectric layer is greater than the thickness of each second dielectric layer and the thickness of each first dielectric layer. The semiconductor packaging structure according to claim 9, wherein the material of each third dielectric layer is an Ajinomoto film.