TWI847547B - Memory structure and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a memory structure includes forming a hard mask layer on a spacer structure, wherein the spacer structure is located on a bit line structure, a lower electrode of the bit line structure is located in a first dielectric layer, and an upper electrode of the bit line structure is located in a second dielectric layer; removing the spacer structure not covered by the hard mask layer; removing the hard mask layer by using oxygen and ammonia as etching gases, wherein after removing the hard mask layer, an oxide layer is formed on a sidewall of the upper electrode, a top surface of the lower electrode, and a top surface and a sidewall of the spacer structure; and forming a spacer layer on the oxide layer.

Description

Memory structure and manufacturing method thereof

The present disclosure relates to a memory structure and a method for manufacturing the memory structure.

In the process of memory structure manufacturing, a carbon hard mask is used to define the memory bit line, and can be removed using oxygen-based plasma etching in subsequent processes. Although oxygen-based plasma etching can effectively remove the carbon hard mask, it will oxidize the interface between the upper and lower electrodes of the bit line, increasing the resistance of the bit line.

Although hydrogen and nitrogen can be used as etching gases to avoid oxidation of the interface between the upper electrode and the lower electrode, plasma etching using hydrogen and nitrogen as etching gases makes the surface functional groups of the memory structure without oxygen, resulting in a decrease in the growth rate of the spacer layer formed subsequently, increasing the time cost of producing memory devices.

One technical aspect of the present disclosure is a method for manufacturing a memory structure.

According to some embodiments of the present disclosure, a method for manufacturing a memory structure includes forming a hard mask layer on a spacer structure, wherein the spacer structure is located on a bit line structure, a lower electrode of the bit line structure is located in a first dielectric layer, and an upper electrode of the bit line structure is located in a second dielectric layer; removing the spacer structure not covered by the hard mask layer; using oxygen and ammonia as etching gases to remove the hard mask layer, wherein after removing the hard mask layer, an oxide layer is formed on the sidewalls of the upper electrode of the bit line structure, the top surface of the lower electrode, the top surface and sidewalls of the spacer structure, and the top surface and sidewalls of the second dielectric layer; and forming the spacer layer on the oxide layer.

In some embodiments, after the hard mask layer is removed by using oxygen and ammonia as etching gases, there is no oxide layer between the lower electrode and the upper electrode of the bit line structure.

In some embodiments, after the hard mask layer is removed by using oxygen and ammonia as etching gases, there is no oxide layer between the upper electrode of the bit line structure and the spacer structure.

In some embodiments, the volume ratio of oxygen to ammonia is in the range of 1:4 to 2:3.

In some embodiments, the use of oxygen and ammonia as etching gases to remove the hard mask layer is performed using reactive ion etching at a power in the range of 3000 watts to 5000 watts.

In some embodiments, the forming of the spacer layer on the oxide layer makes the thickness of the spacer layer greater than the thickness of the oxide layer.

In some embodiments, the material of the hard mask layer includes carbon.

Another technical aspect of the present disclosure is a memory structure.

According to some embodiments of the present disclosure, a memory structure includes a first dielectric layer, a second dielectric layer, a bit line structure, a spacer structure, an oxide layer, and a spacer layer. The second dielectric layer is located on the first dielectric layer and has an opening. The bit line structure has a lower electrode and an upper electrode. The lower electrode is located in the first dielectric layer. The upper electrode is located on the lower electrode and in the opening of the second dielectric layer. The spacer structure is located on the bit line structure. The oxide layer covers the top surface and side walls of the second dielectric layer facing the opening, the side walls of the upper electrode of the bit line structure, the top surface of the lower electrode, and the top surface and side walls of the spacer structure. The spacer layer covers the oxide layer.

In some embodiments, the oxide layer does not have a portion between the lower electrode and the upper electrode and a portion between the bit line structure and the spacer structure.

In some implementations, the material of the spacer layer includes nitride.

In the above-mentioned embodiment of the present disclosure, since oxygen and ammonia are used as etching gases to remove the hard mask layer in the manufacturing method of the memory structure, an oxide layer is formed on the side walls of the upper electrode, the top surface of the lower electrode, the top surface and side walls of the spacer structure, and the top surface and side walls of the second dielectric layer, and then the spacer layer can be formed on the oxide layer. Therefore, in addition to removing the hard mask layer, the above-mentioned manufacturing method can also increase the growth rate of the spacer layer through the functional groups of the oxide layer, so as to reduce the time cost of producing components and meet mass production requirements.

The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a flow chart of a method for manufacturing a memory structure according to some embodiments of the present disclosure. The method for manufacturing a memory structure comprises the following steps. In step S1, a hard mask layer is formed on a spacer structure, wherein the spacer structure is located on a bit line structure, a lower electrode of the bit line structure is located in a first dielectric layer, and an upper electrode of the bit line structure is located in a second dielectric layer. Then, in step S2, the spacer structure not covered by the hard mask layer is removed. Then, in step S3, oxygen and ammonia are used as etching gases to remove the hard mask layer, wherein after removing the hard mask layer, an oxide layer is formed on the sidewalls of the upper electrode of the bit line structure, the top surface of the lower electrode, the top surface and sidewalls of the spacer structure, and the top surface and sidewalls of the second dielectric layer. Then, in step S4, a spacer layer is formed on the oxide layer.

In some implementations, the method for manufacturing a memory structure may further include other steps between any two of the above steps, steps before step S1, and steps after step S4. In addition, steps S1 to S4 may each include multiple detailed steps. In the following description, at least steps S1 to S4 are described.

FIG. 2 to FIG. 6 illustrate cross-sectional views of a method for manufacturing a memory structure 100 (see FIG. 6 ) according to some embodiments of the present disclosure at an intermediate stage. Referring to FIG. 2 , the spacer structure 120 is located on the bit line structure 130. The lower electrode 131 of the bit line structure 130 is located in the first dielectric layer 140, and the lower electrode 131 and the first dielectric layer 140 are in contact with each other. The upper electrode 132 of the bit line structure 130 is located on the lower electrode 131 and in the opening 152 of the second dielectric layer 150, and the upper electrode 132 is in contact with the second dielectric layer 150. The patterned hard mask layer 110 may be formed on the spacer structure 120 to expose a portion 122 of the spacer structure 120 to define the width of the spacer structure 120 and the width of the upper electrode 132 of the bit line structure 130.

3 , the portion 122 of the spacer structure 120 not covered by the hard mask layer 110 may then be removed so that the width of the spacer structure 120 is substantially the same as the width of the hard mask layer 110. In some embodiments, the material of the hard mask layer 110 may include carbon, and the material of the spacer structure 120 may include a nitride dielectric. Therefore, the portion 122 of the spacer structure 120 not covered by the hard mask layer 110 may be removed using reactive-ion etching having a selectivity between the hard mask layer 110 and the spacer structure 120. In addition, the upper electrode 132 of the bit line structure 130 located below the portion 122 of the spacer structure 120 can be removed, so that the width of the upper electrode 132, the width of the spacer structure 120, and the width of the hard mask layer 110 are substantially the same, and the sidewall of the second dielectric layer 150 facing the opening 152 is separated from the sidewall of the upper electrode 132 of the bit line structure 130 and has a distance therebetween, and the opening 152 of the second dielectric layer 150 can expose the top surface of the lower electrode 131. In some embodiments, the bottom of the sidewall of the second dielectric layer 150 facing the opening 152 may be curved, so that the cross-sectional profile of the opening 152 of the second dielectric layer 150 is wider at the top and narrower at the bottom, so as to facilitate the subsequent deposition of materials (such as nitride) in the opening 152 .

Referring to FIGS. 4 and 5 together, the hard mask layer 110 may then be removed by reactive ion etching using oxygen (O ₂ ) and ammonia (NH ₃ ) as etching gas G. In some embodiments, since the material of the hard mask layer 110 may include carbon, and oxygen may react with carbon to generate carbon dioxide, the etching gas G may effectively remove the hard mask layer 110. After the hard mask layer 110 is removed, the top surface and sidewalls of the spacer structure 120, the top surface of the lower electrode 131 of the bit line structure 130, the sidewalls of the upper electrode 132, and the top surface and sidewalls of the second dielectric layer 150 may be oxidized by the oxygen in the etching gas G to form an oxide layer 160. In some embodiments, the volume ratio of oxygen to ammonia in the etching gas G is in the range of 1:4 to 2:3, and the power of the reactive ion etching is in the range of 3000 W to 5000 W. Compared with conventional oxygen-based plasma etching (O-based plasma etching), the reactive ion etching using a specific volume ratio of oxygen to ammonia as the etching gas G can avoid oxidation of the interface between the layers, so that there is no oxide layer 160 between the lower electrode 131 and the upper electrode 132 of the bit line structure 130, and there is no oxide layer 160 between the upper electrode 132 of the bit line structure 130 and the spacer structure 120. As a result, the formation of the oxide layer 160 will not affect the resistance of the bit line structure 130, and its conductivity and signal transmission speed can be maintained.

Referring to FIG. 6 , after the oxide layer 160 is formed, a spacer layer 170 may be formed on the oxide layer 160 to obtain the memory structure 100. In some embodiments, the material of the spacer layer 170 may include nitride. Since the functional groups of the oxide layer 160 can bond with the nitride, the growth rate of the spacer layer 170 can be increased. In this way, it is beneficial to increase the output efficiency of the memory structure 100, so as to reduce the time cost and meet the mass production requirements. In this embodiment, the step of forming the spacer layer 170 on the oxide layer 160 can make the thickness of the spacer layer 170 greater than the thickness of the oxide layer 160.

In the following description, the structural connection relationship of the memory structure 100 will be further explained.

As shown in FIG. 6 , the memory structure 100 includes a first dielectric layer 140, a second dielectric layer 150, a bit line structure 130, a spacer structure 120, an oxide layer 160, and a spacer layer 170. The second dielectric layer 150 is located on the first dielectric layer 140 and has an opening 152. The bit line structure 130 has a lower electrode 131 and an upper electrode 132. The lower electrode 131 is located in the first dielectric layer 140 and is surrounded by the first dielectric layer 140, and the top surface of the lower electrode 131 and the top surface of the first dielectric layer 140 may be coplanar. The upper electrode 132 is located on the lower electrode 131 and in the opening 152 of the second dielectric layer 150. The bottom of the second dielectric layer 150 facing the sidewall of the opening 152 extends toward the top surface of the lower electrode 131. The spacer structure 120 is located on the bit line structure 130. The spacer structure 120 and the bit line structure 130 overlap in the vertical direction. The oxide layer 160 covers the top surface of the second dielectric layer 150 and the sidewall facing the opening 152, the sidewall of the upper electrode 132 of the bit line structure 130, the top surface of the lower electrode 131 of the bit line structure 130, and the top surface and sidewall of the spacer structure 120. The spacer layer 170 covers the oxide layer 160 and is disposed along the oxide layer 160. Since the spacer layer 170 covers the oxide layer 160, and the functional groups of the oxide layer 160 can increase the growth rate of the spacer layer 170, the output efficiency of the memory structure 100 can be increased to reduce the time cost and meet the mass production requirements. In this embodiment, the thickness of the spacer layer 170 is greater than the thickness of the oxide layer 160. The memory structure 100 can be applied to dynamic random access memory (DRAM) or other semiconductor devices.

In some embodiments, the oxide layer 160 of the memory structure 100 has no portion between the lower electrode 131 and the upper electrode 132 and no portion between the bit line structure 130 and the spacer structure 120. In this way, the oxide layer 160 does not affect the resistance of the bit line structure 130, and its conductivity and signal transmission speed can be maintained.

In addition, the material of the spacer structure 120 of the memory structure 100 may include a nitride dielectric, the material of the lower electrode 131 of the bit line structure 130 may include polysilicon, the material of the upper electrode 132 may be tungsten, the materials of the first dielectric layer 140 and the second dielectric layer 150 may include a nitride dielectric, and the material of the spacer layer 170 is nitride, but this is not intended to limit the present disclosure. Since the functional groups of the oxide layer 160 can bond with the nitride, the growth rate of the spacer layer 170 can be increased. In this way, it will be beneficial to improve the output efficiency of the memory structure 100, reduce time costs, and meet mass production requirements.

In some embodiments, the width of the spacer structure 120 is substantially the same as the width of the upper electrode 132 of the bit line structure 130, and the width of the spacer structure 120 is smaller than the width of the lower electrode 131 of the bit line structure 130. In some embodiments, the sidewalls of the spacer structure 120 are substantially aligned with the sidewalls of the upper electrode 132 in the vertical direction, and the sidewalls of the upper electrode 132 and the top surface and sidewalls of the lower electrode 131 may define a stepped surface. The width of the opening 152 of the second dielectric layer 150 is greater than the width of the upper electrode 132, so that the sidewalls of the upper electrode 132 do not contact the sidewalls of the second dielectric layer 150 facing the opening 152.

In summary, since oxygen and ammonia are used as etching gases G in the manufacturing method of the memory structure 100 to remove the hard mask layer 110, an oxide layer 160 is formed on the side walls of the upper electrode 132, the top surface of the lower electrode 131, the top surface and side walls of the spacer structure 120, and the top surface and side walls of the second dielectric layer 150, and then the spacer layer 170 can be formed on the oxide layer 160. Therefore, in addition to removing the hard mask layer 110, the aforementioned manufacturing method can also increase the growth rate of the spacer layer 170 through the functional groups of the oxide layer 160, so as to reduce the time cost of producing components and meet mass production requirements.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: memory structure 110: hard mask layer 120: spacer structure 122: part 130: bit line structure 131: lower electrode 132: upper electrode 140: first dielectric layer 150: second dielectric layer 152: opening 160: oxide layer 170: spacer layer G: etching gas S1, S2, S3, S4: steps

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a flow chart of a method for manufacturing a memory structure according to some embodiments of the disclosure. FIGS. 2 to 6 illustrate cross-sectional views of intermediate stages of a method for manufacturing a memory structure according to some embodiments of the disclosure.

S1: Steps

S2: Step

S3: Step

S4: Step

Claims (10)

A method for manufacturing a memory structure, comprising: forming a hard mask layer on a spacer structure, wherein the spacer structure is located on a bit line structure, a lower electrode of the bit line structure is located in a first dielectric layer, and an upper electrode of the bit line structure is located in a second dielectric layer; removing the spacer structure not covered by the hard mask layer; using an oxygen gas and an ammonia gas as an etching gas to remove the hard mask layer, wherein after removing the hard mask layer, an oxide layer is formed on the sidewalls of the upper electrode of the bit line structure, the top surface of the lower electrode, the top surface and sidewalls of the spacer structure, and the top surface and sidewalls of the second dielectric layer; and A spacer layer is formed on the oxide layer. The method for manufacturing a memory structure as described in claim 1, wherein after using the oxygen gas and the ammonia gas as the etching gas to remove the hard mask layer, there is no oxide layer between the lower electrode and the upper electrode of the bit line structure. The method for manufacturing a memory structure as described in claim 1, wherein after using the oxygen gas and the ammonia gas as the etching gas to remove the hard mask layer, there is no oxide layer between the upper electrode of the bit line structure and the spacer structure. A method for manufacturing a memory structure as described in claim 1, wherein the volume ratio of the oxygen gas to the ammonia gas is in the range of 1:4 to 2:3. A method for manufacturing a memory structure as described in claim 1, wherein using the oxygen gas and the ammonia gas as the etching gas to remove the hard mask layer is a reactive ion etching method with a power in the range of 3000 watts to 5000 watts. A method for manufacturing a memory structure as described in claim 1, wherein the spacer layer is formed on the oxide layer so that the thickness of the spacer layer is greater than the thickness of the oxide layer. A method for manufacturing a memory structure as described in claim 1, wherein the material of the hard mask layer includes carbon. A memory structure includes: a first dielectric layer; a second dielectric layer, located on the first dielectric layer and having an opening; a bit line structure, having a lower electrode and an upper electrode, wherein the lower electrode is located in the first dielectric layer, and the upper electrode is located on the lower electrode and in the opening of the second dielectric layer; a spacer structure, located on the bit line structure; an oxide layer, covering the top surface of the second dielectric layer and the sidewalls facing the opening, the sidewalls of the upper electrode of the bit line structure, the top surface of the lower electrode, and the top surface and sidewalls of the spacer structure; and a spacer layer, covering the oxide layer. A memory structure as described in claim 8, wherein the oxide layer has no portion between the lower electrode and the upper electrode and no portion between the bit line structure and the spacer structure. A memory structure as described in claim 8, wherein the material of the spacer layer includes nitride.

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