TWI842520B - Asymmetric half-bridge flyback converter power supply and its control circuit - Google Patents

Abstract

Provided is an asymmetric half-bridge flyback converter power supply and a control circuit thereof. The control circuit is configured to: after an upper transistor changes from an on state to an off state and before it changes from an off state to an on state, based on an upper transistor control signal for controlling the on and off state of the upper transistor, generate a first turn-on control signal for controlling the lower transistor to change from an off state to an on state for the first time; based on a demagnetization characteristic signal for characterizing the demagnetization condition of the transformer, generate a first turn-on control signal for controlling the lower transistor to change from an off state to an on state for the first time. A first turn-off control signal for controlling the lower transistor to change from the on state to the off state for the first time is generated; a re-conduction control signal for controlling the lower transistor to change from the off state to the on state again is generated based on the demagnetization characteristic signal and the output feedback signal representing the output voltage of the asymmetric half-bridge flyback converter power supply; and a re-turn-off control signal for controlling the lower transistor to change from the on state to the off state again is generated based on the demagnetization characteristic signal.

Description

Asymmetric half-bridge flyback converter power supply and its control circuit

The present invention relates to the field of circuits, and more specifically to an asymmetric half-bridge flyback converter power supply and its control circuit.

A switching power supply, also known as an alternating current power supply or a switching converter, is a type of power supply. The function of a switching power supply is to convert a voltage level into the voltage or current required by the user through different forms of architecture (for example, fly-back architecture, buck architecture, or boost architecture, etc.).

According to a control circuit for an asymmetric half-bridge flyback converter power supply according to an embodiment of the present invention, wherein the asymmetric half-bridge flyback converter power supply includes an upper transistor, a lower transistor, and a transformer, the control circuit is configured to: after the upper transistor changes from an on state to an off state and before it changes from an off state to an on state: based on an upper transistor control signal for controlling the on and off state of the upper transistor, generate a first turn-on control signal for controlling the lower transistor to change from an off state to an on state for the first time; based on A demagnetization characteristic signal is used to characterize the demagnetization condition of the transformer, and a first turn-off control signal is generated for controlling the lower transistor to change from the on state to the off state for the first time; a re-conduction control signal is generated for controlling the lower transistor to change from the off state to the on state again based on the demagnetization characteristic signal and the output feedback signal characterizing the output voltage of the asymmetric half-bridge flyback converter power supply; and a re-turn-off control signal is generated based on the demagnetization characteristic signal for controlling the lower transistor to change from the on state to the off state again.

According to the asymmetric half-bridge flyback converter power supply of the embodiment of the present invention, it includes the above-mentioned control circuit for the asymmetric half-bridge flyback converter power supply.

100: Switch the power on or off

400: Asymmetric half-bridge flyback converter power supply

402,404: Circuit part

AC: alternating current

C1: Capacitor

comp: comparator

Coss: The sum of the parasitic capacitances of the upper transistor Q1 and the lower transistor Q2

Cr: resonant capacitor

CV_off: Power-on transistor shutdown control signal

DCM_on: mode/frequency control signal

down_off,dem_off: first turn off the control signal

down_on: first turn-on control signal

FB: Output feedback signal (voltage)

gate_down: down transistor control signal

gate_up: power-on transistor control signal

HB: Voltage

I1: Current

I _Do : Secondary current of transformer T

I _Lm : primary side magnetizing current of transformer T

I _Lr: primary resonant current of transformer T

In_zvs: Negative current amplitude

INV: Demagnetization characteristic signal (voltage)

Ip: forward peak current

Lm: primary side magnetic inductance

Lp: primary side inductance

Lr: primary side leakage sense

Ls: Secondary inductance

Naux: Number of auxiliary winding turns

Q1 gate: The power-on transistor control signal used to control the on and off of the power-on transistor Q1.

Q1: Power-on transistor

Q2 gate: The lower transistor control signal used to control the on and off of the lower transistor Q2.

Q2: Lower transistor

Rcs: Inductive flow measurement resistance

S1, S2: switch

T: Transformer

t0,t1,t2,t3,t4,t5,t6: time

td: resonance period

Tdcm, Tdem, Tzvs: duration

TL431: Voltage regulator

Tzvs_ENA: Turn on the enable signal again

up_on: Power-on transistor conduction control signal

V1: First sampling signal (voltage)

V2: Second sampling signal (voltage)

V3: The third sampling signal (voltage)

V4: The fourth sampling signal (voltage)

V5: The fifth sampling signal (voltage)

Vaux: Auxiliary winding voltage

Vcs: current characteristic signal (voltage)

Vin: Input voltage

Vm: duration-related signal (voltage)

Vo: output voltage

Vref: reference voltage (reference signal)

Vs:HB voltage difference

ZVS_comp: compensation control signal (compensation voltage)

ZVS_off: Turn off the control signal again

ZVS_on: Turn on the control signal again

The present invention can be better understood from the following description of the specific implementation of the present invention in combination with the drawings, wherein: FIG1 shows a schematic diagram of the topological structure of a traditional asymmetric half-bridge flyback converter power supply.

FIG2 shows the operating waveforms of multiple signals when the switching power supply shown in FIG1 operates in the critical conduction mode.

FIG3 shows the operating waveforms of multiple signals when the switching power supply shown in FIG1 operates in a discontinuous conduction mode.

FIG4 shows a circuit schematic diagram of a control circuit for an asymmetric half-bridge flyback converter power supply according to an embodiment of the present invention.

FIG5 shows a circuit schematic diagram of an example circuit implementation of the zero voltage switching (ZVS) enabling module shown in FIG4.

FIG6 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the enable signal Tzvs_ENA is turned on again and is in the enabled state.

FIG7 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the enable signal Tzvs_ENA is turned off again and is in a non-enabled state.

FIG8 shows a circuit schematic diagram of an example circuit implementation of the ZVS calculation module shown in FIG4.

FIG9 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the voltage V3 in the ZVS calculation module is higher than the reference voltage Vref.

FIG10 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the voltage V3 in the ZVS calculation module is lower than the reference voltage Vref.

FIG11 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the voltage V3 in the ZVS calculation module is equal to the reference voltage Vref.

FIG12 shows a circuit schematic diagram of another example circuit implementation of the ZVS calculation module shown in FIG4.

The features and exemplary embodiments of various aspects of the present invention are described in detail below. In the detailed description below, many specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but covers any modification, substitution and improvement of elements, components and algorithms without departing from the spirit of the present invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary ambiguity of the present invention.

1)個臨界導通模式加1個非連續導通模式的迴圈方式工作或者持續工作於非連續導通模式。 FIG1 shows a schematic diagram of the topological structure of a conventional asymmetric half-bridge flyback converter power supply. In the switching power supply 100 shown in FIG1 , the zero voltage conduction (ZVS) of the upper transistor Q1 and the lower transistor Q2 can be achieved through the resonance of the resonant capacitor Cr and the primary inductor Lp and the primary leakage inductor Lr of the transformer T. Typically, the switching power supply 100 shown in FIG1 operates in the critical conduction mode (CRM) when the system is overloaded, and in the discontinuous conduction mode (DCM) when the system is lightly loaded, and can be operated according to n(n

1) It works in a loop mode of one critical conduction mode plus one discontinuous conduction mode or continuously works in discontinuous conduction mode.

FIG2 shows operating waveforms of multiple signals when the switching power supply shown in FIG1 operates in a critical conduction mode, wherein: Q1 gate represents an upper transistor control signal for controlling the on and off of an upper transistor Q1, Q2 gate represents a lower transistor control signal for controlling the on and off of a lower transistor Q2, I _Lr represents a primary side resonant current of the transformer T, I _Do represents a secondary side current of the transformer T, and HB voltage represents a voltage at a midpoint between the upper transistor Q1 and the lower transistor Q2.

As shown in FIG. 1 and FIG. 2 , the working process of the switching power supply 100 shown in FIG. 1 in the critical conduction mode is as follows: at time t0, the on-state transistor Q1 changes from the off state to the on state, and the input voltage Vin charges the primary-side magnetizing inductance Lm (Lm=Lp+Lr) of the transformer T through the resonant capacitor Cr, and the primary-side resonant current I _Lr of the transformer T rises positively; at time t1, the on-state transistor Q1 changes from the on state to the off state, and the circuit for charging the primary-side magnetizing inductance Lm of the transformer T by the input voltage Vin is disconnected. Since the current in the inductor cannot suddenly change, the primary-side resonant current I Lr of the transformer T rises positively. _Lr discharges the parasitic capacitance of the lower transistor Q2 and charges the parasitic capacitance of the upper transistor Q1. The HB voltage drops to 0V, and the body diode of the lower transistor Q2 changes from the off state to the on state. At t2, the lower transistor Q2 changes from the off state to the on state to achieve zero-voltage conduction. After that, the resonant capacitor Cr resonates with the primary leakage inductance Lr of the transformer T. The primary resonant current I _Lr of the transformer T drops to 0A and then increases negatively. At the same time, the transformer T is demagnetized, and the primary excitation current I _Lm of the transformer T decreases linearly. At t3, the primary resonant current I _Lr of the transformer T resonates to the primary excitation current I _Lm is also large, the demagnetization of transformer T is completed, and the secondary current I _Do of transformer T returns to 0A. After that, the resonant capacitor Cr discharges to the primary magnetizing inductor Lm of transformer T through the lower transistor Q2, and the primary resonant current I _Lr of transformer T increases negatively; at t4, the lower transistor Q2 changes from the on state to the off state, and the circuit for the resonant capacitor Cr to discharge to the primary magnetizing inductor Lm of transformer T is disconnected. Since the current in the inductor cannot change suddenly, the primary resonant current I _Lr discharges the parasitic capacitance of the upper transistor Q1 and charges the parasitic capacitance of the lower transistor Q2. The HB voltage rises to the input voltage Vin, and the body diode of the upper transistor Q1 changes from the off state to the on state. At t5, the upper transistor Q1 changes from the off state to the on state, thereby achieving zero-voltage conduction.

FIG3 shows operating waveforms of multiple signals when the switching power supply shown in FIG1 operates in a discontinuous conduction mode, wherein: Q1 gate represents an upper transistor control signal for controlling the on and off of an upper transistor Q1, Q2 gate represents a lower transistor control signal for controlling the on and off of a lower transistor Q2, I _Lr represents a primary side resonant current of the transformer T, I _Do represents a secondary side current of the transformer T, and HB voltage represents a voltage at a midpoint between the upper transistor Q1 and the lower transistor Q2.

As shown in FIG. 1 and FIG. 3 , the operation process of the switching power supply 100 shown in FIG. 1 in the discontinuous conduction mode is as follows: at time t0, the on-state transistor Q1 changes from the off state to the on state, and the input voltage Vin charges the primary-side magnetizing inductance Lm (Lm=Lp+Lr) of the transformer T through the resonant capacitor Cr, and the primary-side resonant current I _Lr of the transformer T rises positively; at time t1, the on-state transistor Q1 changes from the on state to the off state, and the circuit for charging the primary-side magnetizing inductance Lm of the transformer T by the input voltage Vin is disconnected. Since the current in the inductor cannot suddenly change, the primary-side resonant current I Lr of the transformer T rises positively. _Lr discharges the parasitic capacitance of the lower transistor Q2 and charges the parasitic capacitance of the upper transistor Q1. The HB voltage drops to 0V, and the body diode of the lower transistor Q2 changes from the off state to the on state. At t2, the lower transistor Q2 changes from the off state to the on state, thereby realizing zero-voltage conduction. After that, the resonant capacitor Cr resonates with the primary leakage inductance Lr of the transformer T. The primary resonant current I _Lr of the transformer T drops to 0A and then increases negatively. At the same time, the primary magnetizing current I _Lm decreases; at t3, the lower transistor Q2 changes from the on state to the off state, and the resonant circuit of the resonant capacitor Cr and the primary leakage inductance Lr of the transformer T is broken. Then, the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2 resonates with the primary magnetizing inductance Lm of the transformer T; if the resonance amplitude of the HB voltage is not large enough and the resonance peak value cannot reach the input voltage Vin, then at t4, the lower transistor Q2 needs to change from the off state to the on state again, and the resonant capacitor Cr discharges to the primary magnetizing inductance Lm of the transformer T through the lower transistor Q2, and the primary resonant current I of the transformer T _Lr increases negatively; at t5, the lower transistor Q2 changes from the on state to the off state, and the circuit for the resonant capacitor Cr to discharge to the primary side magnetizing inductance Lm of the transformer T is broken. The primary side magnetizing inductance Lm of the transformer T resonates with the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2. Since the current in the inductance cannot change suddenly, the primary side resonant current I _Lr of the transformer T discharges the parasitic capacitance of the upper transistor Q1 and charges the parasitic capacitance of the lower transistor Q2. If the primary side resonant current I If _Lr is large enough, the HB voltage will rise to the input voltage Vin, and the body diode of the power-on transistor Q1 will change from the off state to the on state; at t6, the power-on transistor Q1 changes from the off state to the on state, thereby achieving zero-voltage conduction.

When the switching power supply 100 shown in FIG1 operates in the discontinuous conduction mode, whether the lower transistor Q2 can achieve zero voltage conduction at time t2 depends on the forward peak current Ip of the primary side resonant current I _Lr of the transformer T when the upper transistor Q1 changes from the on state to the off state. Even when the system is lightly loaded, the forward peak current Ip is sufficient to make the HB voltage resonate to 0V, so the lower transistor Q2 can definitely achieve zero voltage turn-on; whether the upper transistor Q1 can achieve zero voltage conduction at time t6 depends on the primary side resonant current I Lr of the transformer T when the lower transistor Q2 changes from the on state to the off state again at time t5. The negative current amplitude In_zvs of _Lr depends on the duration Tzvs of the lower transistor Q2 being in the off state after the duration Tdcm. The shorter Tzvs is, the smaller the negative current amplitude In_zvs is, and the smaller the resonant energy of the primary-side excitation inductance Lm of the transformer T and the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2 during t5-t6. If the resonant energy is too small, the upper transistor Q1 will not be able to achieve zero-voltage conduction. The longer Tzvs is, the larger the negative current amplitude In_zvs is, and the greater the resonant energy of the primary-side excitation inductance Lm of the transformer T and the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2 during t5-t6. Although the greater the resonant energy, the easier it is for the upper transistor Q1 to achieve zero-voltage conduction, there will be energy loss during the resonance process, and the greater the resonant energy, the more energy will be lost. On the other hand, the larger the negative current amplitude In_zvs is, the larger the forward peak current Ip is required to keep the output constant, which will cause the upper transistor Q1 to lose more when it changes from the on state to the off state. Therefore, a too long Tzvs time will lead to lower efficiency. Therefore, Tzvs needs to be controlled so that the upper transistor Q1 can just achieve zero voltage conduction.

In view of the above situation, a control circuit for an asymmetric half-bridge flyback converter power supply according to an embodiment of the present invention is proposed. When the asymmetric half-bridge flyback converter power supply operates in a discontinuous conduction mode, the control circuit can control the duration Tzvs of the lower transistor Q2 being in the on state again, and control the negative current amplitude In_zvs of the primary side resonant current I _Lr of the transformer T when the lower transistor Q2 changes from the on state to the off state again, so that when the system is lightly loaded, the upper transistor Q1 can still achieve zero voltage conduction, and there is no waste of resonant energy, thereby ensuring the optimal light load efficiency.

FIG4 shows a circuit schematic diagram of a control circuit for an asymmetric half-bridge flyback converter power supply according to an embodiment of the present invention. As shown in FIG4 , the control circuit for an asymmetric half-bridge flyback converter power supply 400 according to an embodiment of the present invention includes a circuit portion 402 for controlling the on and off state of an upper transistor Q1 and a circuit portion 404 for controlling the on and off state of a lower transistor Q2, wherein: the circuit portion 402 is configured to control the on and off state of an upper transistor Q1 based on an output feedback signal FB representing an output voltage Vo of the asymmetric half-bridge flyback converter power supply 400, a current characterization representing a resonant current of the primary side of the transformer T, and a current characterization representing a resonant current of the primary side of the transformer T. The circuit part 404 is configured to generate the lower transistor control signal gate_down based on the output feedback signal FB, the demagnetization characteristic signal INV that characterizes the demagnetization condition of the transformer T, and the upper transistor control signal gate_up.

As shown in FIG. 4 , in some embodiments, the circuit portion 402 is further configured to generate a power-on transistor control signal gate_up by the following processing: generating a power-on transistor off control signal CV_off based on the output feedback signal FB and the current characteristic signal Vcs (e.g., by comparing the voltage division signal of the output feedback signal FB with the current characteristic signal Vcs); generating a power-on transistor on control signal up_on based on the down transistor control signal gate_down; and generating a power-on transistor control signal gate_up based on the power-on transistor off control signal CV_off and the power-on transistor on control signal up_on.

As shown in FIG. 4 , in some embodiments, the circuit portion 404 is further configured to generate a down transistor control signal gate_down by the following processing after the up transistor Q1 changes from the on state to the off state and before it changes from the off state to the on state: based on the up transistor control signal gate_up, generate a first turn-on control signal down_on for controlling the down transistor Q2 to change from the off state to the on state for the first time; based on the demagnetization characteristic signal INV, generate a first turn-on control signal gate_up for controlling the down transistor Q2 to change from the off state to the on state for the first time; The first turn-off control signal down_off is generated to control the lower transistor Q2 to change from the on state to the off state for the first time; based on the demagnetization characteristic signal INV and the output feedback signal FB, a re-conduction control signal ZVS_on (not shown in the figure) is generated to control the lower transistor Q2 to change from the off state to the on state again; and based on the demagnetization characteristic signal INV, a re-turn-off control signal ZVS_off is generated to control the lower transistor Q2 to change from the on state to the off state again. Here, the lower transistor control signal gate_down is generated based on the first turn-on control signal down_on, the first turn-off control signal down_off, the re-conduction control signal ZVS_on, and the re-turn-off control signal ZVS_off.

As shown in FIG. 4 , in some embodiments, the circuit portion 404 is further configured to generate a re-conduction control signal ZVS_on by the following processing: based on the demagnetization characteristic signal INV, a re-conduction enable signal Tzvs_ENA is generated for controlling whether the lower transistor Q2 is allowed to change from the off state to the on state again; based on the output feedback signal FB, a mode/frequency control signal DCM_on is generated for controlling at least one of the operating mode and the operating frequency of the asymmetric half-bridge flyback converter power supply 400; and based on the re-conduction enable signal Tzvs_ENA and the mode/frequency control signal DCM_on, a re-conduction control signal ZVS_on is generated.

As shown in FIG. 4 , in some embodiments, after the first predetermined time period starting from the moment when the upper transistor control signal gate_up controls the upper transistor Q1 to change from the on state to the off state, the first turn-on control signal down_on controls the lower transistor Q2 to change from the off state to the on state. After the second predetermined time period starting from the moment when the lower transistor control signal gate_down controls the lower transistor Q2 to change from the on state to the off state, the upper transistor turn-on control signal up_on controls the upper transistor Q1 to change from the off state to the on state.

Specifically, in the asymmetric half-bridge flyback converter power supply 400 shown in FIG4 : the output voltage Vo generates a voltage FB (i.e., an output feedback signal FB) after passing through a resistor divider and TL431 and an optocoupler; after the on-state transistor Q1 changes from an off state to an on state, the input voltage Vin charges the primary-side magnetizing inductance Lm of the transformer T through the resonant capacitor Cr, and the primary-side resonant current I of the transformer T _Lr rises positively, and the voltage Vcs (i.e., the current characteristic signal Vcs) on the current flow sensing resistor Rcs increases; when the voltage Vcs on the current flow sensing resistor Rcs is higher than the voltage at the midpoint between the upper transistor Q1 and the lower transistor Q2 (i.e., the HB voltage) after voltage division, the upper transistor shutdown control signal CV_off changes from a low level to a high level, and the upper transistor Q1 changes from an on state to an off state; after the upper transistor Q1 changes from an on state to an off state, the primary resonant current I of the transformer T _Lr discharges the parasitic capacitance of the lower transistor Q2 and charges the parasitic capacitance of the upper transistor Q1. The HB voltage drops to 0V, and the body diode of the lower transistor Q2 changes from the off state to the on state. The dead time module starts timing the fixed dead time at the moment when the upper transistor Q1 changes from the on state to the off state, and then controls the lower transistor Q2 to change from the off state to the on state, realizing the zero voltage turn-on of the lower transistor Q2. ; The voltage INV (i.e., demagnetization characteristic signal INV) on the auxiliary winding side of the transformer T is sent to the first shutdown control signal down_off generated by the demagnetization detection module to control the lower transistor Q2 from the on state to the off state, and the primary side magnetizing inductance Lm of the transformer T resonates with the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2; the voltage INV is sent to the re-conduction enable signal generated by the ZVS enable module The signal Tzvs_ENA controls whether the lower transistor Q2 is allowed to change from the off state to the on state again; the voltage FB is sent to the mode/frequency module after voltage division to generate the mode/frequency control signal DCM_on to limit the working state and working frequency of the asymmetric half-bridge flyback converter power supply 400 (for example, the mode/frequency control signal DCM_on can reduce the system working state when the system load is reduced). operating frequency); when the mode/frequency control signal DCM_on flips, if the re-enabling enable signal Tzvs_ENA is enabled, the lower transistor Q2 changes from the off state to the on state again; after the voltage INV is sent to the ZVS calculation module to generate the re-off control signal ZVS_off to control the lower transistor Q2 to change from the on state to the off state again, the primary resonant current I _Lr discharges the parasitic capacitance of the upper transistor Q1 and charges the parasitic capacitance of the lower transistor Q2. The HB voltage rises to the input voltage Vin, and the body diode of the upper transistor Q1 changes from the off state to the on state. At this time, the dead time module starts timing the fixed dead time at the moment when the lower transistor Q2 changes from the on state to the off state, and then controls the upper transistor Q1 to change from the off state to the on state, realizing the upper transistor Q1 is turned on at zero voltage; when the mode/frequency control signal DCM_on flips, if the enable signal Tzvs_ENA is turned off again, the lower transistor Q2 will no longer change from the off state to the on state. After the dead time module generates a fixed dead time delay, it controls the upper transistor Q1 to change from the off state to the on state when the HB voltage resonates to the highest value, thereby realizing zero voltage turn-on of the upper transistor Q1. It should be noted that zero voltage turn-on does not necessarily mean that the voltage difference before and after the switch is turned on is 0V. As long as it is a lower voltage value, it belongs to zero voltage turn-on.

After the first shutdown control signal down_off generated by the demagnetization detection module controls the lower transistor Q2 to change from the on state to the off state, the primary side excitation inductance Lm of the transformer T and the sum of the parasitic capacitances Coss of the upper transistor Q1 and the lower transistor Q2 resonate. The resonant circuit includes the resonant capacitance Cr of the transformer T, and the resonant capacitance Cr is much larger than the sum of the parasitic capacitances Coss of the upper transistor Q1 and the lower transistor Q2 ^. The voltage across the resonant capacitance Cr is N.Vo. If there is no negative current in the resonant circuit at the initial moment, the resonant center value of the HB voltage is ^N.Vo , and the resonant amplitude is also ^N.Vo. Therefore, the highest resonant voltage can reach ^2N.Vo. If Vin<2N ^. Vo, the upper transistor Q1 can be basically turned on at zero voltage without controlling the lower transistor Q2 to change from the off state to the on state again.

FIG5 shows a circuit schematic diagram of an example circuit implementation of the ZVS enable module shown in FIG4. As shown in FIG5, in some embodiments, the ZVS enable module is configured to: generate a first sampling signal V1 by sampling the demagnetization characteristic signal INV during the period when the upper transistor Q1 is in the on state and the lower transistor Q2 is in the off state; generate a second sampling signal V2 by sampling the demagnetization characteristic signal INV during the period when the upper transistor Q1 is in the off state and the lower transistor Q2 is in the on state; and generate a re-conduction enable signal Tzvs_ENA by comparing the first sampling signal V1 and the second sampling signal V2.

As shown in Figures 4 and 5, the voltage INV is sampled by the sampling unit to generate voltages V1 and V2 (i.e., the first sampling signal V1 and the second sampling signal V2). The voltage V1 = m1. (Vin-N˙Vo) is a voltage proportional to the magnetizing voltage (Vin-N.Vo) obtained by sampling when the upper transistor Q1 is in the on state and the lower transistor Q2 is in the off state. The voltage V2 = m2. N. Vo is a voltage proportional to the demagnetization voltage (N.Vo) sampled when the upper transistor Q1 is in the off state and the lower transistor Q2 is in the on state; the voltages V1 and V2 are compared after simple calculation conversion by the operation comparison unit or directly compared to generate a re-conduction enable signal Tzvs_ENA for controlling whether the lower transistor Q2 is allowed to change from the off state to the on state again.

FIG6 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the re-conduction enable signal Tzvs_ENA is in the enabled state, wherein: Q1 gate represents the upper transistor control signal for controlling the on and off of the upper transistor Q1, Q2 gate represents the lower transistor control signal for controlling the on and off of the lower transistor Q2, I _Lr represents the primary side resonant current of the transformer T, DCM_on represents the mode/frequency control signal, ZVS_off represents the re-turn-off control signal, and INV represents the demagnetization characteristic signal.

As shown in FIG4 and FIG6 , when the enable signal Tzvs_ENA is turned on again and is in the enabled state, the working process of the asymmetric half-bridge flyback converter power supply 400 shown in FIG4 is as follows: at t0, the upper transistor Q1 changes from the off state to the on state, the primary resonant current I _Lr of the transformer T rises positively, and the voltage Vcs on the current flow sensing resistor Rcs increases; when the voltage Vcs on the current flow sensing resistor Rcs increases to a voltage higher than the FB voltage, at t1, the upper transistor Q1 changes from the on state to the off state, and since the current in the inductor cannot suddenly change, the primary resonant current I Lr of the transformer T increases. _Lr discharges the parasitic capacitance of the lower transistor Q2 and charges the parasitic capacitance of the upper transistor Q1. The HB voltage drops to 0V, and the body diode of the lower transistor Q2 changes from the off state to the on state. At t2, the first turn-on control signal down_on flips, and the lower transistor Q2 changes from the off state to the on state, thereby realizing zero-voltage turn-on. After that, the resonant capacitor Cr resonates with the primary leakage inductance Lr of the transformer T. At the same time, the transformer T is demagnetized, and the primary magnetizing current I of the transformer T is _Lm decreases; at t3, the first shutdown control signal dem_off flips, and the lower transistor Q2 changes from the on state to the off state. After that, the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2 resonates with the primary side excitation inductance Lm of the transformer T, and the resonance period is td; at t4, the mode/frequency control signal DCM_on flips, and the turn-on enable signal Tzvs_ENA is in the enabled state, and the lower transistor Q2 changes from the off state to the on state again. The resonant capacitor Cr discharges to the primary side excitation inductance Lm of the transformer T through the lower transistor Q2, and the primary side resonant current I of the transformer T _Lr increases in a negative direction; at t5, the control signal ZVS_off is turned off again, and the lower transistor Q2 changes from the on state to the off state again. The circuit of the resonant capacitor Cr discharging to the primary side magnetizing inductance Lm of the transformer T is broken, and the primary side magnetizing inductance Lm of the transformer T resonates with the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2. Since the current in the inductor cannot change suddenly, the primary side resonant current I of the transformer T _Lr discharges the parasitic capacitance of the upper transistor Q1 and charges the parasitic capacitance of the lower transistor Q2. The HB voltage rises to the input voltage Vin, and the body diode of the upper transistor Q1 changes from the off state to the on state. At t6, the upper transistor conduction control signal up_on flips, and the upper transistor Q1 changes from the off state to the on state again, thereby achieving zero-voltage conduction.

FIG7 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the re-enable signal Tzvs_ENA is in a non-enabled state, wherein: Q1 gate represents an upper transistor control signal for controlling the on and off of the upper transistor Q1, Q2 gate represents a lower transistor control signal for controlling the on and off of the lower transistor Q2, I _Lr represents the primary side resonant current of the transformer T, DCM_on represents a mode/frequency control signal, ZVS_off represents a re-enable control signal, and INV represents a demagnetization characteristic signal.

As shown in FIG. 4 and FIG. 7 , when the enable signal Tzvs_ENA is turned off again, the working process of the asymmetric half-bridge flyback converter power supply 400 shown in FIG. 4 is as follows: at t0, the upper transistor Q1 changes from the off state to the on state, the primary resonant current I _Lr of the transformer T rises positively, and the voltage Vcs on the current flow sensing resistor Rcs increases; when the voltage Vcs on the current flow sensing resistor Rcs increases to a voltage higher than the FB voltage, at t1, the upper transistor Q1 changes from the on state to the off state, and since the current in the inductor cannot suddenly change, the primary resonant current I Lr of the transformer T increases. _Lr discharges the parasitic capacitance of the lower transistor Q2 and charges the parasitic capacitance of the upper transistor Q1. The HB voltage drops to 0V, and the body diode of the lower transistor Q2 changes from the off state to the on state. At t2, the first turn-on control signal down_on flips, and the lower transistor Q2 changes from the off state to the on state, thereby realizing zero-voltage turn-on. After that, the resonant capacitor Cr resonates with the primary leakage inductance Lr of the transformer T. At the same time, the transformer T is demagnetized, and the primary magnetizing current I of the transformer T is _Lm decreases; at t3, the first shutdown control signal dem_off flips, and the lower transistor Q2 changes from the on state to the off state. After that, the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2 and the primary side excitation inductance Lm of the transformer T resonate, and the resonance period is td; at t4, the mode/frequency control signal DCM_on flips, and the turn-on enable signal Tzvs_ENA is in the non-enabled state, and the lower transistor Q2 no longer changes from the off state to the on state; at t5, the upper transistor turn-on control signal up_on flips, and the upper transistor Q1 changes from the off state to the on state again, thereby realizing low-voltage turn-on.

FIG8 shows a circuit schematic diagram of an example circuit implementation of the ZVS calculation module shown in FIG4. As shown in FIG8, in some embodiments, the ZVS calculation module is configured to: generate a third sampling signal V3 by sampling the demagnetization characteristic signal INV, wherein the third sampling signal V3 can reflect the voltage at the midpoint between the upper transistor Q1 and the lower transistor Q2 before the upper transistor Q1 changes from the off state to the on state (i.e., the HB voltage) or before and after the upper transistor Q1 changes from the off state to the on state. The voltage at the midpoint between the upper transistor Q1 and the lower transistor Q2 (i.e., the HB voltage) changes in amplitude; the compensation control signal ZVS_comp is generated by integrating the difference between the third sampling signal V3 and the reference signal Vref (i.e., the reference voltage Vref); and the re-off control signal ZVS_off is generated by comparing the compensation control signal ZVS_comp and the predetermined ramp signal.

As shown in FIG4 and FIG8, the voltage INV is sampled by the sampling unit to generate the voltage V3 (i.e., the third sampling signal V3), and the voltage V3 is proportional to the difference between the HB voltages before and after the on-state of the on-state transistor Q1 changes from the off state to the on-state, or is proportional only to the HB voltage before the on-state transistor Q1 changes from the off state to the on-state, and the reference voltage Vref can be either a set fixed voltage or generated by the sampling unit sampling the voltage INV during the on-state of the on-state transistor Q1. The voltage V3 and the reference voltage Vref are sent to the integrator together to generate the compensation voltage ZVS_comp (i.e., the compensation control signal ZVS_comp). The compensation voltage ZVS_comp is compared with the predetermined ramp voltage generated by the ramp generator to determine the turn-off moment of the lower transistor Q2 (i.e., the duration of the on-state). This method can accurately control the HB voltage difference before and after the upper transistor Q1 changes from the off state to the on state, and control the on-state voltage of the upper transistor Q1 to the target value. The on-state voltage of the upper transistor Q1 is not 0V for the best efficiency, so the target value is usually a voltage higher than 0V.

FIG9 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the voltage V3 in the ZVS calculation module is higher than the reference voltage Vref, wherein: Q1 gate represents the upper transistor control signal for controlling the on and off of the upper transistor Q1, Q2 gate represents the lower transistor control signal for controlling the on and off of the lower transistor Q2, I _Lr represents the primary side resonant current of the transformer T, ZVS_comp represents the compensation voltage, INV represents the voltage INV, and HB voltage represents the voltage at the midpoint between the upper transistor Q1 and the lower transistor Q2.

As shown in Figure 4 and Figure 9, when the voltage V3 is higher than the reference voltage Vref, the HB voltage difference Vs before and after the upper transistor Q1 changes from the off state to the on state is higher than the target value, the compensation voltage ZVS_comp rises, and the duration Tzvs of the lower transistor Q2 being in the on state again becomes longer, so the HB voltage difference before and after the upper transistor Q1 changes from the off state to the on state will become lower until it reaches the target value.

FIG10 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the voltage V3 in the ZVS calculation module is lower than the reference voltage Vref, wherein: Q1 gate represents the upper transistor control signal for controlling the on and off of the upper transistor Q1, Q2 gate represents the lower transistor control signal for controlling the on and off of the lower transistor Q2, I _Lr represents the primary side resonant current of the transformer T, ZVS_comp represents the compensation voltage, INV represents the voltage INV, and HB voltage represents the voltage at the midpoint between the upper transistor Q1 and the lower transistor Q2.

As shown in Figure 4 and Figure 10, when the voltage V3 is lower than the reference voltage Vref, the HB voltage difference Vs before and after the upper transistor Q1 changes from the off state to the on state is lower than the target value, the compensation voltage ZVS_comp decreases, and the duration Tzvs of the lower transistor Q2 being in the on state again becomes shorter, so the HB voltage difference before and after the upper transistor Q1 changes from the off state to the on state becomes higher until it reaches the target value.

FIG11 shows the operating waveforms of multiple signals in the switching power supply shown in FIG4 when the voltage V3 in the ZVS calculation module is equal to the reference voltage Vref, wherein: Q1 gate represents the upper transistor control signal for controlling the on and off of the upper transistor Q1, Q2 gate represents the lower transistor control signal for controlling the on and off of the lower transistor Q2, I _Lr represents the primary side resonant current of the transformer T, ZVS_comp represents the compensation voltage, INV represents the voltage INV, and HB voltage represents the voltage at the midpoint between the upper transistor Q1 and the lower transistor Q2.

As shown in Figure 4 and Figure 11, when the voltage V3 is equal to the reference voltage Vref, the HB voltage difference Vs before and after the upper transistor Q1 changes from the off state to the on state is equal to the target value, the compensation voltage ZVS_comp remains unchanged, and the duration Tzvs of the lower transistor Q2 being in the on state again remains unchanged, so the HB voltage difference before and after the upper transistor Q1 changes from the off state to the on state will be stable at the target value.

After the lower transistor Q2 changes from the on state to the off state and before the upper transistor Q1 changes from the off state to the on state, the resonance between the sum of the parasitic capacitances Coss of the upper transistor Q1 and the lower transistor Q2 and the primary side excitation magnetic inductance Lm of the transformer T, the negative current required for the HB voltage to resonate to the input voltage Vin can be calculated.

I _{n_zvs} ² According to the law of conservation of energy:

I _{n_zvs} ²

Therefore, the negative current required for the on-state transistor Q1 to achieve zero voltage conduction is:

The duration of the lower transistor Q2 being in the on state again is:

Through linear fitting, we get:

，td為上電晶體Q1及下電晶體Q2的寄生電容與變壓器T的一次側勵磁電感Lm的諧振週期。 in,

, td is the resonant period of the parasitic capacitance of the upper transistor Q1 and the lower transistor Q2 and the primary side magnetizing inductance Lm of the transformer T.

FIG12 shows a circuit schematic diagram of another example circuit implementation of the ZVS calculation module shown in FIG4. As shown in FIG. 12 , in some embodiments, the ZVS calculation module is configured to: generate a fourth sampling signal V4 by sampling the demagnetization characteristic signal INV when the upper transistor Q1 is in the on state and the lower transistor Q2 is in the off state; generate a fifth sampling signal V5 by sampling the demagnetization characteristic signal INV when the upper transistor Q1 is in the off state and the lower transistor Q2 is in the on state; generate a duration-related signal Vm related to the duration Tzvs of the lower transistor Q2 being in the on state again by controlling the charging of the predetermined capacitor C1 based on the fifth sampling signal V5 and the re-conduction control signal ZVS_on; and generate a re-off control signal ZVS_off based on the fourth sampling signal V4 and the duration-related signal Vm.

As shown in FIG. 12 , in some embodiments, the ZVS calculation module is further configured to generate a duration-related signal Vm (i.e., voltage Vm) by the following processing: using a voltage-controlled current source to generate a charging current I1 proportional to the fifth sampling signal V5; and using a re-conduction control signal ZVS_on to control the charging current I1 to charge the predetermined capacitor C1. For example, the re-conduction control signal ZVS_on is used to control the switch S1 to be in a conducting state during the period when the lower transistor Q2 is in a conducting state again, thereby controlling the charging current I1 to charge the predetermined capacitor C1 during the period when the lower transistor Q2 is in a conducting state again, until the voltage Vm is higher than the voltage V4 and the re-turn-off control signal ZVS_off changes from a low level to a high level. At this time, the control signal ZVS_off is turned off again to control the switch S2 from the off state to the on state, so that the predetermined capacitor C1 is discharged to prepare for the next charging.

As shown in Figure 4 and Figure 12, the voltage INV is sampled by the sampling unit to generate voltages V4 and V5 (i.e., the fourth sampling signal V4 and the fifth sampling signal V5), wherein V4=m3. (Vin-N.Vo) is the voltage proportional to the magnetizing voltage (Vin-N.Vo) obtained by sampling when the upper transistor Q1 is in the on state and the lower transistor is in the off state, and V5=m4. N.Vo is the voltage proportional to the demagnetizing voltage (N.Vo) obtained by sampling when the upper transistor Q1 is in the off state and the lower transistor Q2 is in the on state.

，C1、m1、m2、k均為內部參數，只需讓

即可剛好實現上電晶體Q1的零電壓導通。

既可通過外部設置調整讓等式滿足，也可通過退磁表徵信號INV檢測諧振週期td自動調節來實現上電晶體Q1的零電壓導通，優化系統輕載效率。 It should be noted that the sampling unit in the ZVS calculation module can be shared with the sampling unit in the ZVS enable module. In this case, m3=m1, m4=m2, V4=V1, V5=V2. The voltage V5 is converted into the current I1 (I1=k.V3) through the voltage-controlled current source. During the period when the lower transistor Q2 is in the on state again, the current I1 charges the capacitor C1 to generate the voltage Vm. The voltage Vm and V4 are compared to determine the turn-off moment of the lower transistor Q2 (that is, the duration of the lower transistor Q2 being in the on state again). Here, the duration of the lower transistor Q2 being in the on state again is

, C1, m1, m2, k are all internal parameters, just let

This can just achieve zero-voltage turn-on of the upper transistor Q1.

The equation can be satisfied through external adjustment, or the resonant period td can be automatically adjusted by detecting the demagnetization characteristic signal INV to achieve zero-voltage turn-on of the upper transistor Q1 and optimize the light-load efficiency of the system.

The present invention may be implemented in other specific forms without departing from its spirit and essential features. For example, the algorithm described in a specific embodiment may be modified, and the system architecture does not deviate from the basic spirit of the present invention. Therefore, the present embodiments are considered to be exemplary rather than restrictive in all aspects, the scope of the present invention is defined by the attached claims rather than the above description, and all changes that fall within the meaning and scope of equivalents of the claims are therefore included in the scope of the present invention.

400: Asymmetric half-bridge flyback converter power supply

402,404: Circuit part

AC: alternating current

comp: comparator

Cr: resonant capacitor

CV_off: Power-on transistor shutdown control signal

DCM_on: mode/frequency control signal

down_off: Turn off the control signal for the first time

down_on: first turn-on control signal

FB: Output feedback signal (voltage)

gate_down: down transistor control signal

gate_up: power-on transistor control signal

HB: Voltage

I _Do : Secondary current of transformer T

I _Lr : primary resonant current of transformer T

INV: Demagnetization characteristic signal (voltage)

Lp: primary side inductance

Lr: primary side leakage sense

Ls: Secondary inductance

Naux: Number of auxiliary winding turns

Q1: Power-on transistor

Q2: Lower transistor

Rcs: Inductive flow measurement resistance

T: Transformer

TL431: Voltage regulator

Tzvs_ENA: Turn on the enable signal again

up_on: Power-on transistor conduction control signal

Vaux: Auxiliary winding voltage

Vcs: current characteristic signal (voltage)

Vin: Input voltage

Vo: output voltage

ZVS_off: Turn off the control signal again

Claims (13)

A control circuit for an asymmetric half-bridge flyback converter power supply, the asymmetric half-bridge flyback converter power supply comprising an upper transistor, a lower transistor, and a transformer, the control circuit being configured to: after the upper transistor changes from an on state to an off state and before the upper transistor changes from an off state to an on state, based on an upper transistor control signal for controlling the on and off state of the upper transistor, Generate a first turn-on control signal for controlling the lower transistor to change from an off state to an on state for the first time; based on a demagnetization characteristic signal representing the demagnetization condition of the transformer, generate a first turn-off control signal for controlling the lower transistor to change from an on state to an off state for the first time; based on the demagnetization characteristic signal and an output feedback characteristic signal representing the output voltage of the asymmetric half-bridge flyback converter power supply, generate a first turn-off control signal for controlling the lower transistor to change from an on state to an off state for the first time The output feedback signal is used to generate a re-conduction control signal for controlling the lower transistor to change from the off state to the on state again; and based on the demagnetization characteristic signal, a re-off control signal is generated for controlling the lower transistor to change from the on state to the off state again; wherein the process of generating the re-conduction control signal includes: based on the demagnetization characteristic signal, generating a re-conduction enable signal for controlling whether to allow the lower transistor to change from the off state to the on state again; based on the output feedback signal, generating a mode/frequency control signal for controlling at least one of the working mode and working frequency of the asymmetric half-bridge flyback converter power supply; and based on the re-conduction enable signal and the mode/frequency control signal, generating the re-conduction control signal. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 1, wherein after a first predetermined time period starting from the moment when the upper transistor control signal controls the upper transistor to change from the on state to the off state, the first turn-on control signal controls the lower transistor to change from the off state to the on state. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 1, wherein the process of generating the re-conduction enable signal includes: generating a first sampling signal by sampling the demagnetization characteristic signal during the period when the upper transistor is in the on state and the lower transistor is in the off state; generating a second sampling signal by sampling the demagnetization characteristic signal during the period when the upper transistor is in the off state and the lower transistor is in the on state; and generating the re-conduction enable signal by performing an operation comparison on the first sampling signal and the second sampling signal. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 1, wherein the process of generating the shut-down control signal again includes: generating a third sampling signal by sampling the demagnetization characteristic signal, wherein the third sampling signal can reflect the voltage at the midpoint between the upper transistor and the lower transistor before the upper transistor changes from the off state to the on state or the voltage change amplitude at the midpoint between the upper transistor and the lower transistor before and after the upper transistor changes from the off state to the on state; generating a compensation control signal by integrating the difference between the third sampling signal and the reference signal; and generating the shut-down control signal again by comparing the compensation control signal with a predetermined ramp signal. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 4, wherein the reference signal is a set fixed voltage or is generated by sampling the demagnetization characteristic signal while the upper transistor is in the on state. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 1, wherein the process of generating the re-shutdown control signal includes: generating a fourth sampling signal by sampling the demagnetization characteristic signal during the period when the upper transistor is in the on state and the lower transistor is in the off state; generating a fifth sampling signal by sampling the demagnetization characteristic signal during the period when the upper transistor is in the off state and the lower transistor is in the on state; generating a duration-related signal related to the duration of the re-on state of the lower transistor by controlling the charging of a predetermined capacitor based on the fifth sampling signal and the re-shutdown control signal; and generating the re-shutdown control signal based on the fourth sampling signal and the duration-related signal. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 6, wherein the process of generating the duration-related signal includes: using a voltage-controlled current source to generate a charging current proportional to the fifth sampling signal; and using the re-conduction control signal to control the charging current proportional to the fifth sampling signal to charge the predetermined capacitor. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 7, wherein during the period in which the lower transistor is controlled by the re-conduction control signal to be in the on state again, a charging current proportional to the fifth sampling signal charges the predetermined capacitor. The control circuit for the asymmetric half-bridge flyback converter power supply as described in claim 1 is also configured to generate the upper transistor control signal based on the output feedback signal, the current characterization signal characterizing the resonant current on the primary side of the transformer, and the lower transistor control signal for controlling the on and off of the lower transistor. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 9, wherein the lower transistor control signal is generated based on the first turn-on control signal, the first turn-off control signal, the turn-on control signal again, and the turn-off control signal again, and the process of generating the upper transistor control signal includes: generating an upper transistor turn-off control signal based on the output feedback signal and the current characterization signal; generating an upper transistor turn-on control signal based on the lower transistor control signal; and generating the upper transistor control signal based on the upper transistor turn-off control signal and the upper transistor turn-on control signal. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 10, wherein the upper transistor shutdown control signal is generated by comparing the voltage division signal of the output feedback signal and the current characteristic signal. A control circuit for an asymmetric half-bridge flyback converter power supply as described in claim 10, wherein after a second predetermined time period starting from the moment when the lower transistor control signal controls the lower transistor to change from the on state to the off state, the upper transistor conduction control signal controls the upper transistor to change from the off state to the on state. An asymmetric half-bridge flyback converter power supply, comprising a control circuit for an asymmetric half-bridge flyback converter power supply as described in any one of claims 1 to 12.

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