TWI777412B - Resonant half-bridge flyback power converter and primary controller circuit and control method thereof - Google Patents

Abstract

A resonant half-bridge flyback power converter includes a power transformer and a resonant capacitor which are coupled in series between a half-bridge power stage and an output power, and a primary controller circuit configured to control a high side power switch and a low side power switch of the half-bridge power stage. The low side power switch includes a resonant switching pulse for resonant switching of the low side switch and a soft switching pulse for achieving ZVS of the high side switch. When the output power is lower than a delay threshold, the primary controller circuit determines a delay period between the resonant switching pulse and the soft switching to control both the high side power switch and the low side power switch to be OFF, wherein the delay period is reversely proportional to the output power.

Description

Resonant half-bridge flyback power supply and primary side control circuit and control method thereof

The invention relates to a flyback power supply circuit, in particular to a resonant half-bridge flyback power supply. The present invention also relates to a control circuit and a control method for a resonant half-bridge flyback power supply.

The prior art of US Patent "US5959850A, Asymmetric Duty Cycle Flyback Converter" discloses a half-bridge flyback power supply circuit with zero voltage switching (ZVS) to achieve higher power efficiency. However, the disadvantage of this prior art is that the power conversion efficiency is poor during light loads of the power converter due to only operating in continuous conduction mode or boundary conduction mode. The present invention provides a resonant half-bridge flyback power supply, which can be operated in discontinuous conduction mode (DCM), and at the same time can be controlled by a lower-bridge power switch to improve power conversion efficiency in heavy-load and light-load operations at the same time .

In one aspect, the present invention provides a resonant half-bridge flyback power supply for converting an input power supply into an output power supply, the resonant half-bridge flyback power supply comprising: a half-bridge power stage circuit, including an upper bridge power switch and a lower bridge power switch connected in series between the input power supply and a reference potential, wherein the upper bridge power switch and the lower bridge power switch are coupled to a phase node; a power transformer is coupled to the half between the bridge power stage circuit and the output power supply; a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; and a primary side control circuit for according to An upper bridge switching signal and a lower bridge switching signal are generated in relation to a feedback signal of the output power, so as to respectively control the upper bridge power switch and the lower bridge power switch, and switch a primary side winding of the power transformer, to convert the input power into the output power; wherein the primary side winding is magnetized when the upper bridge power switch is turned on, and after the upper bridge power switch is turned off, the primary side control circuit switches on the lower bridge A resonant switching pulse is generated in the signal to turn on the lower bridge power switch, and through the resonant capacitor and the primary side winding, the energy obtained during magnetic induction is transmitted to a secondary side winding of the power transformer in a resonance manner, so as to generating the output power; wherein when the output power is lower than a delay threshold, the primary side control circuit determines a delay period in the lower bridge switching signal according to the output power, and controls the upper Neither the bridge power switch nor the lower bridge power switch is turned on, wherein the delay period is inversely related to the output power.

In a preferred embodiment, when the delay period is longer than a light-load threshold period, neither the upper-bridge power switch nor the lower-bridge power switch is controlled to be turned off during the delay period after the light-load threshold period, The light load threshold period is greater than or equal to 0.

In a preferred embodiment, when the delay period is longer than the light load threshold period, after the delay period ends, the primary side control circuit further generates a flexible switching pulse in the lower bridge switching signal to turn on the lower The bridge power switch has a flexible period, so that the upper bridge power switch can achieve flexible switching when it is turned on next time.

In a preferred embodiment, the flexible switching corresponds to zero-voltage switching when the upper-bridge power switch is turned on next time.

In a preferred embodiment, the conduction period of the low-bridge power switch is related to the demagnetization period of the power transformer, and is greater than or equal to the demagnetization period of the power transformer.

In a preferred embodiment, the primary side control circuit maintains the upper bridge switching signal and the lower bridge switching signal at a low level for a period of upper bridge hysteresis immediately before and after the upper bridge switching signal is switched to a high level. Dead time and a lower bridge dead time, so that the upper bridge power switch and the lower bridge power switch respectively achieve flexible switching when they are turned on next time, wherein the upper bridge dead time and the lower bridge dead time Inside, the upper bridge power switch and the lower bridge power switch are both non-conductive.

In a preferred embodiment, the enabling of the lower bridge switching signal precedes the enabling of the upper bridge switching signal.

In a preferred embodiment, before the upper bridge power switch is turned on, the lower bridge power switch is controlled to be turned on to charge a bootstrap capacitor, wherein the bootstrap capacitor is used to provide power to the upper bridge switch driver , the upper bridge switch driver is used to drive the upper bridge power switch.

In a preferred embodiment, the primary side control circuit further determines the delay period according to a waveform characteristic of a quasi-resonant signal, and then determines the starting time of the resonant switching pulse of the lower bridge switching signal, wherein the quasi-resonant switching signal is A quasi-resonant period of the resonant signal is related to the inductance value of the primary side winding and the stray capacitance value of the half-bridge power stage circuit.

In a preferred embodiment, when the output power is lower than a burst threshold, a burst signal is generated, wherein when the burst signal is generated, the delay period further includes a burst period to extend the delay period.

In a preferred embodiment, the burst threshold is lower than the delay threshold.

In another aspect, the present invention also provides a primary side control circuit for controlling a resonant half-bridge flyback power supply to convert an input power into an output power, the resonant half-bridge flyback power supply comprising: a half-bridge power stage circuit, including an upper-bridge power switch and a lower-bridge power switch connected in series between the input power supply and a reference potential, wherein the upper-bridge power switch and the lower-bridge power switch are coupled to a phase node; a power transformer coupled between the half-bridge power stage circuit and the output power supply; and a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; the The primary side control circuit includes: a pulse modulation circuit for generating a modulation signal according to a feedback signal related to the output power; an upper bridge driving circuit for generating an upper bridge according to the modulation signal a switching signal to control the upper bridge power switch; and a timing control circuit, coupled to the pulse modulation circuit, for generating a lower bridge switching signal to control the lower bridge power switch to switch the power transformers one by one A secondary side winding to convert the input power into the output power; wherein the primary side winding is magnetically induced when the upper bridge power switch is turned on, and after the upper bridge power switch is turned off, the sequence control circuit is in the A resonant switching pulse is generated in the lower bridge switching signal to turn on the lower bridge power switch, and through the resonant capacitor and the primary side winding, the energy obtained during magnetic induction is transmitted to a secondary side of the power transformer in a resonance manner winding to generate the output power; wherein when the output power is lower than a delay threshold, the timing control circuit determines a delay period in the lower bridge switching signal according to the output power, and controls the Neither the upper-bridge power switch nor the lower-bridge power switch is turned on, wherein the delay period is inversely related to the output power.

In another aspect, the present invention also provides a control method for controlling a resonant half-bridge flyback power supply to convert an input power into an output power, the resonant half-bridge flyback power supply comprising: A half-bridge power stage circuit includes an upper-bridge power switch and a lower-bridge power switch connected in series between the input power supply and a reference potential, wherein the upper-bridge power switch and the lower-bridge power switch are coupled to a phase node; a power a transformer coupled between the half-bridge power stage circuit and the output power supply; and a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; the control method Including: generating a modulation signal according to a feedback signal related to the output power; generating an upper bridge switching signal and a lower bridge switching signal according to the modulation signal, so as to respectively control the upper bridge power switch and the lower bridge a power switch to switch a primary side winding of the power transformer to convert the input power into the output power; wherein the step of controlling the upper-bridge power switch and the lower-bridge power switch includes: turning the upper-bridge power switch After being turned off, a resonant switching pulse is generated in the lower bridge switching signal to turn on the lower bridge power switch, and the primary side winding is connected to the upper bridge power switch in a resonance manner through the resonant capacitor and the primary side winding. The energy obtained when conducting and magnetic induction is transmitted to a secondary winding of the power transformer to generate the output power; when the output power is lower than a delay threshold, according to the output power, in the lower bridge switching signal A delay period is determined, and during a part of the delay period, both the upper bridge power switch and the lower bridge power switch are controlled to be turned off, wherein the delay period is inversely related to the output power.

The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

The drawings in the present invention are schematic, mainly intended to represent the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

1A shows a schematic diagram of a preferred embodiment of a resonant half-bridge flyback power supply according to the present invention (resonant half-bridge flyback power supply 1001 ). The resonant half-bridge flyback power supply 1001 includes an upper-bridge power switch 30 and a lower-bridge power switch 40 forming a half-bridge power stage circuit 300 , wherein the upper-bridge power switch 30 and the lower-bridge power switch 40 are connected in series with the input power Vin and a reference between potentials. The power transformer 10 and the resonant capacitor 20 are coupled in series between the phase node HB of the half-bridge power stage circuit 300 and the output power source Po, wherein the upper-bridge power switch 30 and the lower-bridge power switch 40 are coupled to the phase node HB. The power transformer 10 includes a primary winding NP, a secondary winding NS and an auxiliary winding NA. The primary side winding NP and the secondary side winding NS have a turns ratio n. The secondary winding NS and the auxiliary winding NA have a turns ratio m. The primary side control circuit 100 generates the upper bridge switching signal SH and the lower bridge switching signal SL, and switches the power transformer 10 through the half-bridge power stage circuit 300 to generate the output power Po on the secondary side of the power transformer 10 . Specifically, the primary side winding NP is magnetized when the upper bridge power switch 30 is turned on, and after the upper bridge power switch 30 is turned off, the primary side control circuit 100 generates a resonant switching pulse in the lower bridge switching signal SL When PRES turns on the lower bridge power switch 40, the energy obtained during magnetic induction is transferred to the secondary winding NS of 10 in a resonance manner through the resonant capacitor 20 and the primary winding NP to generate the output power Po. The resistor 60 is used for detecting the primary side switch current IP of the power transformer 10 to generate the current detection signal VCS.

In one embodiment, the primary-side control circuit 100 generates the upper-bridge switching signal SH and the lower-bridge switching signal SL in response to the feedback signal VFB, and the feedback signal VFB is based on the output power Po of the resonant half-bridge flyback power supply 1001 . produced. Specifically, the secondary side control circuit 200 is coupled to the output power Po to generate the feedback signal VFB. In one embodiment, the feedback signal VFB is coupled to the primary side control circuit 100 through the optocoupler 90 . The secondary side control circuit 200 is also used for generating the driving signal SG for driving the synchronous rectification switch 70 during the demagnetization period TDS of the power transformer 10 . The winding NA generates the auxiliary winding signal VNA during switching of the power transformer 10 , and the resistors 51 and 52 further attenuate the auxiliary winding signal VNA to generate the auxiliary winding related signal VAUX connected to the primary side control circuit 100 .

1B shows a schematic diagram of a specific embodiment of the primary side control circuit 100 in the resonant half-bridge flyback power supply according to the present invention (the primary side control circuit 100 ). As shown in FIG. 1B , the primary-side control circuit 100 includes a pulse width modulation circuit 101 , an upper bridge driving circuit 102 and a timing control circuit 120 . In one embodiment, the timing control circuit 120 includes a first timing circuit 105, an SSW (soft switching) pulse generation circuit 106, dead time generation circuits 107, 107', a second timing circuit 108, a lower bridge control circuit 103, The delay signal circuit 109 , the third timing circuit 110 and the output level sensing circuit 104 .

The first timing circuit 105 is used for generating the ramp signal VC1 according to the discharge current ID related to the output power Po. The SSW pulse wave generating circuit 106 generates a signal S1 corresponding to the flexible switching pulse wave PSSW according to the ramp signal VC1. The dead time generating circuit 107 generates the signal S2 to provide the dead time between the switching of the upper bridge power switch 30 and the lower bridge power switch 40 . The pulse width modulation circuit 101 and the upper bridge driving circuit 102 are used for determining the pulse width of the upper bridge switching signal SH according to, for example, the feedback signal VFB and the current sensing signal VCS. The dead time generating circuit 107' generates the signal S4 to provide the dead time between the switching of the upper bridge power switch 30 and the lower bridge power switch 40. The second timing circuit 108 generates the ramp signal VC5 after the dead time generated by the signal S4. The lower bridge control circuit 103 determines the pulse width of the signal S5 (corresponding to the resonance switching pulse PRES) according to the ramp signal VC5, and is used for The lower bridge switching signal SL is generated by combining the signal S1 and the signal S5. The third timing circuit 110 is used for determining the time point of the trough of a quasi-resonant signal according to the auxiliary winding related signal VAUX. The delay signal circuit 109 integrates the ramp signal VC1, the time point of the trough and the signal S5 to generate a signal S6 related to the delay period TDLY. The output level sensing circuit 104 is used for determining the aforementioned discharge current ID according to the feedback signal VCOM (corresponding to the level of the output current Io).

FIG. 2 shows a waveform diagram corresponding to the embodiment shown in FIG. 1A of the present invention. When the high-side switching signal SH is enabled (eg, at a high level), the power transformer 10 is induced and generates an induced current IM, wherein the enabling period TW of the high-side switching signal SH corresponds to the conduction of the high-side power switch 30 period. When the upper bridge switching signal SH is disabled, the power transformer 10 is demagnetized, and the power transformer 10 generates the secondary-side switching current IS during the demagnetization period TDS. The enabling period TSL of the lower bridge switching signal SL is related to the demagnetizing period TDS of the power transformer 10 , wherein the enabling period TSL of the lower bridge switching signal SL corresponds to the conducting period of the lower bridge power switch 40 . The enabling period TSL of the lower bridge switching signal SL is equal to or longer than the demagnetizing period TDS of the power transformer 10 to prevent the power transformer 10 from operating in continuous conduction mode (CCM). During the demagnetization period TDS of the power transformer 10, the reflected voltage VX is generated and clamped in the resonant capacitor 20, where VX = nVO.

When the high-bridge switching signal SH is disabled (eg, turned to a low level), the low-bridge switching signal SL can then be enabled. When the lower bridge switching signal SL is disabled, the upper bridge switching signal SH can be enabled. There is a dead time between the upper-bridge switching signal SH and the lower-bridge switching signal SL, and the lengths of the dead times TRH and TRL are related to the resonance period, so that the upper-bridge power switch 30 and the lower-bridge power switch 40 are respectively turned on next time It can achieve soft switching (soft switching), or further achieve zero voltage switching (ZVS, zero voltage switching).

FIG. 3 shows a schematic diagram of waveforms according to an embodiment of the present invention. When the output power Po is lower than the delay threshold, the lower bridge switching signal SL includes a delay period TDLY. When the output power Po is lower than the delay threshold, as the output power Po decreases, the delay period TDLY increases accordingly, and the frequency of the high-bridge switching signal SH decreases. It should be noted that the aforementioned "when the output power Po is lower than the delay threshold", in one embodiment, may mean that the power level of the output power Po is lower than the delay threshold, or, in another embodiment, especially when the output When the voltage Vo is fixed, it may mean that the current level of the output power source Po is lower than the delay threshold.

As shown in Figure 3, when the output power Po is lower than the delay threshold, the lower bridge switching signal SL will be separated into the resonance switching pulse PRES and the flexible switching pulse PSSW, and between the resonance switching pulse PRES and the flexible switching pulse PSSW A delay period TDLY is generated between them. As shown in FIG. 3 , during the delay period TDLY, the lower bridge switching signal SL is at a low level (disabled), that is, the lower bridge power switch 40 is controlled to be non-conductive.

During the delay period TDLY, since the demagnetization of the power transformer 10 is completed, and the upper-bridge power switch 30 and the lower-bridge power switch 40 are both controlled to be non-conductive, the power transformer 10 will generate quasi-resonance with the stray capacitance, so that, for example, at the phase node A quasi-resonant waveform is observed on the voltage VHB or the auxiliary winding related signal VAUX. In one embodiment, the delay period TDLY is also determined according to the timing of the occurrence of a waveform characteristic (eg, a trough) of the quasi-resonant signal by the primary-side control circuit 100, so as to enable the lower bridge switching signal SL to realize flexible switching or zero-voltage switching. . The trough of the aforementioned quasi-resonant signal may correspond to, for example, any one of the troughs VV1 to VVN of the phase node voltage VHB in FIG. 3 , or the sequence of the corresponding troughs may be determined according to the level of the output power Po, where N is positive. Integer.

The lower bridge switching signal SL turns on the lower bridge power switch 40 at the valley of the quasi-resonant signal (eg at VV4 ), so as to realize the flexible switching or zero-voltage switching of the lower bridge power switch 40 , thereby reducing the switching of the lower bridge power switch 40 loss. The quasi-resonant period TQV of the quasi-resonant signal (such as the time length between any two valleys in VV1 to VVN) is related to the inductance value of the primary winding NP of the power transformer 10 and the stray capacitance of the half-bridge power stage circuit 300 value, wherein the stray capacitance is related to the parasitic capacitance of the upper bridge power switch 30 , the lower bridge power switch 40 and the power transformer 10 .

FIG. 4 shows a schematic diagram of a state operation waveform according to an embodiment of the present invention. The lower bridge switching signal SL is formed by the signal S1 and the signal S5. In one embodiment, the lower bridge switching signal SL is generated by the OR logic operation of the signal S1 and the signal S5, wherein the enable period of the signal S1 corresponds to TSLB. The high-bridge switching signal SH corresponds to the signal S3. In one embodiment, the pulse width of the signal S3 is related to the level of the feedback signal VFB and the current sensing signal VCS. The pulse width of the signal S2 determines the dead time TRH. The pulse width of the signal S4 determines the dead time TRL. The pulse width TS6 of the signal S6 determines the delay period TDLY, the detailed relationship thereof will be described in detail later, wherein the pulse width TS6 of the signal S6 includes a first period TS6A and a second period TV.

The signal S1 is enabled before the signal S3 is enabled, so the lower bridge switching signal SL is enabled before the upper bridge switching signal SH is enabled. As shown in FIG. 4 , before the upper power switch 30 is turned on, the lower power switch 40 is turned on to charge the bootstrap capacitor 277 that provides power to the upper switch driver 275 ( FIG. 7 , which will be described in detail later). ).

As shown in Figure 4, the signal S2 is enabled at the falling edge of the signal S1, then the signal S3 is enabled at the falling edge of the signal S2, the signal S4 is enabled at the falling edge of the signal S3, and the signal S5 is enabled at the falling edge of the signal S4. Falling edge is enabled.

The signal S6 is enabled at the rising edge of the signal S56, and the signal S56 is generated before the end of the signal S5. Specifically, when the signal S5 is enabled, the signal S56 will be generated after the period TSLA (that is, the ramp signal VC5 exceeds the threshold VT5A). ), therefore, there is an overlap period T5TH between the start of the signal S6 and the end of the signal S5.

The ramp signal VC1 is used to determine the switching period of the upper bridge switching signal SH and the lower bridge switching signal SL. The charging time of the ramp signal VC1 (the rise time shown in Figure 4) determines the pulse width of the signal S1. The discharge time (fall time as shown in FIG. 4 ) of the ramp signal VC1 determines the first period TS6A of the signal S6. According to the present invention, in an embodiment, the discharge time of the ramp signal VC1 is inversely related to the output power Po, in other words, When the output current Io is lower, the first period TS6A is longer. The second period TV of the signal S6 is related to the period of the quasi-resonant signal and the corresponding valley sequence (VV1 ˜VVN).

The ramp signal VC5 is used to determine the pulse width of the signal S5 and generate the signal S56. The enabling of the signal S5 starts the charging of the ramp signal VC5, that is, the ramp signal VC5 starts to rise from the rising edge of the signal S5. When the ramp signal VC5 is higher than the threshold VT5A, the signal S56 is enabled. When the ramp signal VC5 is higher than the threshold VT5B, the pulse wave of the signal S5 ends, wherein the level of the threshold VT5B is higher than the level of the threshold VT5A.

In one embodiment, since the discharge time of the ramp signal VC1 is inversely related to the output power Po, the output power Po (eg, the level of the output current Io) of the resonant half-bridge flyback power supply 1001 is relatively high, so that the When the discharge time of the ramp signal VC1 is shorter than the overlapping period T5TH (such as the embodiment of the falling ramp of several dashed lines in VC1 ), the pulse width TS6 of the signal S6 will be shorter than the overlapping period T5TH (such as the falling of several dashed lines in S6 ) edge), and signal S1 will overlap with signal S5. Therefore, the lower bridge switching signal SL will have only one pulse during the disable period of the upper bridge switching signal SH (as shown in FIG. 2 ). In one embodiment, when the discharge time of the ramp signal VC1 is shorter than the overlap period T5TH, the second period TV will not be counted, that is, TS6 is equal to TS6A.

On the other hand, if the output power Po of the resonant half-bridge flyback power supply 1001 is relatively low, so that the discharge time of the ramp signal VC1 is longer than the overlapping period T5TH (such as the embodiment of several solid lines falling ramps in VC1 ), then The lower bridge switching signal SL will be split into a resonant switching pulse PRES and a flexible switching pulse PSSW (FIG. 4), wherein the resonance switching pulse PRES and the flexible switching pulse PSSW correspond to the signal S1 and the signal S5, respectively.

In this embodiment, the delay period TDLY starts from the falling edge of the signal S5, and its time length is related to the period TS6A. In one embodiment, the delay period TDLY further includes a second period TV.

Since the pulse width TS6 of the signal S6 is the predecessor of the delay period TDLY, from a point of view, the pulse width TS6 of the signal S6 can also be regarded as another delay period, when the delay period TS6A is longer than the light load threshold period (corresponding to the light load threshold period) During the overlapping period T5TH), within the delay period TDLY, both the upper-bridge power switch 30 and the lower-bridge power switch 40 are turned off. It should be noted that, in this embodiment, the delay period TS6 is equal to the sum of the light load threshold period (T5TH) and the delay period TDLY. In one embodiment, the light load threshold period (T5TH) is greater than or equal to zero. In embodiments where the light load threshold period (T5TH) is equal to 0, the delay period TS6 overlaps the delay period TDLY. In addition, the delay period TDLY exists only when the delay period TS6A is longer than the light load threshold period (T5TH), that is, greater than 0.

In addition, from an angle, in one embodiment, the overlapping period T5TH determines the aforementioned light load threshold period.

Please refer to FIG. 1B at the same time, the following FIGS. 5 to 10 show schematic diagrams of more specific embodiments of the circuit blocks corresponding to the embodiment of FIG. 1B . The primary side control circuit 100 in FIG. 1B can be used to generate operations corresponding to the foregoing.

FIG. 5 shows a specific embodiment of the primary side control circuit of the present invention. Specifically, FIG. 5 shows a schematic diagram of a specific embodiment of the first timing circuit 105 and the SSW (flexible switching) pulse wave generating circuit 106 . Please refer to FIG. 5 , and compare FIGS. 1B and 4 , the first timing circuit 105 is used for generating the ramp signal VC1 , and the SSW pulse wave generating circuit 106 is used for generating the signal S1 corresponding to the flexible switching pulse wave PSSW. When the signal S6 is disabled, the charging current IC charges the capacitor 230 through the switch 210 to generate a rising slope of the ramp signal VC1. When the level of the ramp signal VC1 is higher than the threshold VT1A, the comparator 231 enables the signal S1. When the level of the signal VC1 is higher than the threshold VT1B, the comparator 232 resets the signal S1. The pulse width of the signal S1 is related to the requirement for the high-side power switch 30 to realize flexible switching or zero-voltage switching. Therefore, the capacitance values and thresholds VT1A and VT1B of the charging current IC and the capacitor 230 can be determined according to the above requirements.

When the signal S6 is enabled, the discharge current ID passes through the switch 220 to discharge the capacitor 230. In one embodiment, when the feedback signal VCOM is lower than the threshold VTH1 (as shown in FIG. 10 , corresponding to the above, the output power Po is low Due to the delay threshold, which will be described in detail later), the discharge current ID decreases as the output power Po decreases. The level of the feedback signal VCOM is related to the level of the feedback signal VFB. In one embodiment, the level of the feedback signal VCOM and the level of the feedback signal VFB are positively related to the output current Io of the output power supply Po. level. When the feedback signal VCOM is lower than the threshold VTH2 (as shown in FIG. 10 , corresponding to the foregoing, the output power Po is lower than the burst threshold, which will be described in detail later), the burst signal BST is generated. In one embodiment, the level of the threshold VTH2 is lower than the threshold VTH1, that is, the burst threshold is lower than the delay threshold. When the signal S6 is enabled, the burst signal BST will disable the switches 210, 220 and the charging and discharging of the capacitor 230. Therefore, when the burst signal BST is generated, the burst period is included in the delay period TDLY, and the burst The transmission period will extend the duration of the delay period TS6, and at the same time, the duration of the delay period TDLY will be extended.

FIG. 6 shows a schematic diagram of a specific embodiment of the dead time generating circuit in the primary-side control circuit of the present invention (the dead time generating circuit 107 ). The dead time generating circuit 107 in FIG. 6 corresponds to, for example, 107 or 107 in FIG. 1B . '. Please refer to FIG. 6 , and compare FIGS. 1B and 4 at the same time, the dead time generating circuit 107 is used for correspondingly generating the signal S2 or S4 with the pulse width of the dead time TRH or TRL according to the signal S1 or S2 , wherein the current source 245 The current and the capacitance value of the capacitor 250 determine the time constant of the dead time generation circuit 107. In one embodiment, the time constant of the dead time generation circuit 107 is related to the resonance caused by the inductance and stray capacitance of the power transformer 10. cycle.

FIG. 7 shows a specific embodiment of the primary-side control circuit of the present invention. Specifically, FIG. 7 shows a schematic diagram of a specific embodiment of the pulse width modulation circuit and the upper bridge driving circuit (the pulse width modulation circuit 101 and the above bridge drive circuit 102). Please refer to FIG. 7 , and compare FIGS. 1B and 4 , the pulse width modulation circuit 101 is used to generate the upper bridge switching signal SH, and the feedback signal VCOM is the level shift signal generated by the feedback signal VFB through the transistor 265 , that is, the feedback signal VCOM is positively related to the feedback signal VFB, and the difference between the two is approximately a fixed level difference. The level of the feedback signal VFB is proportional to the level of the output power Po of the resonant half-bridge flyback power supply 1001. As mentioned above, in one embodiment, the level of the feedback signal VFB is proportional to the level of the output power Po. The output current level is proportional to Io.

The signal S3 is enabled by the falling edge of the signal S2. After the signal S3 is enabled, the pulse generator 271 is used to determine the minimum on-time of the signal S3. The resistors 262, 263 generate the attenuated VCOM signal, the feedback signal VCOM'. When the current sensing signal VCS is higher than the feedback signal VCOM', the comparator 260 disables the signal S3.

In the high-bridge driving circuit 102 , the signal S3 generates the high-bridge switching signal SH through the high-bridge switch driver 275 . Please refer to FIG. 1A and FIG. 1B at the same time, when the power supply VDD is turned on when the lower bridge power switch 40 is turned on, the bootstrap capacitor 277 is charged through the bootstrap diode 279, and the upper bridge switch driver 275 is based on the bootstrap grounding point HGND. A bootstrap power supply is provided, wherein the bootstrap ground point HGND is coupled to the aforementioned phase node HB.

FIG. 8 shows a specific embodiment of the primary side control circuit of the present invention. Specifically, FIG. 8 shows a schematic diagram of a specific embodiment of the second timing circuit and the lower bridge control circuit (the second timing circuit 108 and the lower bridge control circuit 103 ). Please refer to FIG. 8 , and compare FIGS. 1B and 4 , the second timing circuit 108 is used for generating the ramp signal VC5 , and the lower bridge control circuit 103 is used for generating the signal S5 and the lower bridge switching signal SL.

In the second timing circuit 108, the falling edge of the signal S4 controls the switch 291 to be non-conductive through the logic circuits 281, 280 (flip-flops), and 292, so that the current source 293 charges the capacitor 290 to generate the rising slope of the ramp signal VC5, The signal S2 controls the switch 291 to be turned on through the logic circuits 282 , 280 and 292 to reset the capacitor 290 . In detail, the flip-flop 280 generates the signal SC5 according to the falling edge of the signal S4, the enabling of the signal S2 resets the signal SC5, and the enabling of the signal SC5 causes the capacitor 290 to start its charging cycle. The time constant determined by the current of the current source 293 and the capacitance of the capacitor 290 is related to the demagnetization period TDS of the power transformer 10 , in other words, this makes the conduction period of the lower power switch 40 related to the demagnetization period of the power transformer 10 . When the level of the ramp signal VC5 is higher than the threshold VT5A, the comparator 297 generates a signal S56. When the level of the ramp signal VC5 is higher than the threshold VT5B, the comparator 295 resets the signal S5. The level of the threshold VT5B is higher than the level of the threshold VT5A. As shown in FIG. 4 , the difference between the thresholds VT5B and VT5A and the rising slope of the ramp signal VC5 determine the pulse width T5TH of the signal S56 , which corresponds to the aforementioned light-load threshold period and the overlapping period of the signals S5 and S6 T5TH.

In the lower bridge control circuit 103 , the enabling of the signal SC5 enables the signal S5 through the flip-flop 285 , and the signal S5 and the signal S1 generate the lower bridge switching signal SL through the OR gate 286 and the lower bridge switch driver 288 .

FIG. 9 shows a specific embodiment of the primary side control circuit of the present invention. Specifically, FIG. 9 shows a schematic diagram of a specific embodiment of the delay signal circuit and the third timing circuit (the delay signal circuit 109 and the third timing circuit 110 ). Please refer to FIG. 9 , and compare FIGS. 1B and 4 , the delay signal circuit 109 is used for generating the delay signal S6 , and the third timing circuit 110 is used for generating the signal VlyN.

In the delay signal circuit 109, the signal S56 enables the signal S6 through the flip-flop 350. When the ramp signal VC1 is discharged below the threshold VT1A, the comparator 340 will generate the signal S6TV, and the signal S6TV is used to reset the signal S6 under the following conditions: (1) If the S6TV signal is generated when the S5 is enabled, then The S6TV signal will reset the signal S6 immediately. (2) If the S6TV signal is generated when the S5 is disabled, the signal S6 will not be reset until the S6TV signal and the VlyN signal are enabled at the same time. Or (3) the S6TV signal will start the timer 330 (see also the third timer circuit 110). If the valley of the quasi-resonant signal (VV1-VVN) cannot be detected, once the timer 330 expires, the timer 330 will enable the signal VlyN, and then reset the signal S6 under the condition as (2), in other words, the timer 330 It is for overdue timing. As shown in FIG. 9 , the circuit between the comparator 340 and the reset terminal of the flip-flop 350 is an embodiment of a logic circuit for realizing the above operation.

In the third timing circuit 110, when the waveform of the auxiliary winding signal VNA becomes negative during the period when the S6TV signal is enabled, the operational amplifier 310, the resistor 316 and the mirror transistors 311, 312, 315 are coupled to the auxiliary winding related The signal VAUX is used to generate the signal VNEG to indicate that the auxiliary winding signal VNA is negative. The flip-flop 320 is used to generate the signal VNEG according to the aforementioned method, and the signal S5 is used to reset the signal VNEG. When the auxiliary winding related signal VAUX is higher than a positive threshold (eg 0.1V) and the signal VNEG is enabled, the comparator 325 will generate a signal VlyN, where the signal VlyN indicates the Nth valley of the auxiliary winding signal VNA. It should be noted that, in the embodiment shown in FIG. 3 , the best time to turn on the lower bridge power switch 40 is to align with the peak of the auxiliary winding signal VNA (corresponding to the trough of VHB). In the third timing circuit 110, for example, but not limited to, an appropriate delay circuit is added to the signal path for generating the signal VNEG, so as to delay the time point when the signal VNEG is enabled, for example, by a half of the quasi-resonant period TQV, so that the The timing of turning on the low-bridge power switch 40 is aligned with the peak of the auxiliary winding signal VNA, so as to achieve a better effect.

In one embodiment, the third timing circuit 110 further includes a state circuit 360 for latching the comparison result of the comparator 325 .

FIG. 10 shows a specific embodiment of the primary-side control circuit of the present invention. Specifically, FIG. 10 shows a schematic diagram of a specific embodiment of the output level sensing circuit (the output level sensing circuit 104 ). Please refer to FIG. 10 , and compare FIGS. 1B , 4 and 5 , the output level sensing circuit 104 is used for generating the discharge current ID related to the level of the output power Po, and also for generating the burst signal BST. The current source 425 is used to determine the maximum value of the discharge current ID, and the current source 435 is used to determine the minimum value of the discharge current ID. When the feedback signal VCOM is lower than the threshold VTH1 (that is, corresponding to the aforementioned output power Po is lower than the delay threshold), the operational amplifiers 410, 420, the resistor 416 and the mirror transistors 411, 412, 415, 421, 422, 431, 432 The formed current control sub-circuit reduces the value of the discharge current ID as the feedback signal VCOM decreases, which reduces the falling slope of the ramp signal VC1, thereby prolonging the aforementioned delay period.

In addition, when the feedback signal VCOM is lower than the threshold VTH2 (that is, corresponding to the aforementioned output power Po is lower than the burst threshold), the comparator 430 generates the burst signal BST. In one embodiment, the comparator 430 can be configured to have a hysteresis voltage comparator.

The present invention has been described above with respect to the preferred embodiments, but the above-mentioned descriptions are only intended to make it easy for those skilled in the art to understand the content of the present invention, and are not intended to limit the scope of rights of the present invention. The described embodiments are not limited to be used alone, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace those in another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. According to the signal itself, when necessary, the signal is subjected to voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion, etc., and then processed or calculated according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed and described here. Accordingly, the scope of the present invention should cover the above and all other equivalent changes.

10: Power Transformer 100: Primary side control circuit 101: Pulse width modulation circuit 102: Upper bridge drive circuit 103: Lower bridge control circuit 104: Output level sensing circuit 105: The first timing circuit 106: SSW pulse generation circuit 107, 107’: Dead time generation circuit 108: Second timing circuit 109: Delay signal circuit 110: Third timing circuit 120: Sequence control circuit 1001: Resonant Half-Bridge Flyback Power Supply 20: Resonant capacitor 200: Secondary side control circuit 210, 220: switch 230: Capacitor 231, 232, 260: Comparator 245: Current source 250: Capacitor 262, 263: Resistors 265: Transistor 271: Pulse Generator 275: High-Side Switch Driver 277: Bootstrap capacitor 279: Bootstrap Diode 281, 282, 292: Logic circuits 291: switch 293: Current Source 290: Capacitor 280: Flip-flop 285: Flip-flop 286: or gate 288: Lower Bridge Switch Driver 297: Comparator 30: Upper bridge power switch 300: Half-bridge power stage circuit 310: Operational Amplifier 316: Resistor 311, 312, 315: Mirror transistors 320: Flip-flop 330: Timer 325, 340: Comparator 350: Flip-flop 40: Lower bridge power switch 410, 420: Operational Amplifiers 411, 412, 415, 421, 422, 431, 432: Mirrored transistors 430: Comparator 416: Resistor 51, 52, 60: Resistors 70: Synchronous rectification switch 90: Optocoupler BST: burst signal HB: Phase Node HGND: Bootstrap ground point ID: discharge current IM: Inductive current Io: output current IP: Primary side switch current IS: Secondary side switching current n, m: turns ratio NA: Auxiliary winding NP: Primary winding NS: Secondary winding Po: output power PRES: Resonant switching pulse PSSW: Flexible Switching Pulse S1, S2, S3, S4, S5, S6, S56, S6TV: Signal SG: drive signal SH: Upper bridge switching signal SL: Lower bridge switching signal TDLY: Delay period TDS: During demagnetization TQV: Quasi-resonant period TSL, TW: Enable period TRH, TRL: dead time TS6: Pulse width T5TH, TS6A, TSLA, TSLB, TV: Period VAUX: Auxiliary winding related signal VC1, VC5: Ramp signal VCS: Current detection signal VFB, VCOM, VCOM’: Feedback signal VHB: phase node voltage Vin: input power VlyN: Signal VNA: Auxiliary winding signal Vo: output voltage VT1A, VT1B, VT5A, VT5B, VTH1, VTH2: Threshold VV1~VVN: Valley

FIG. 1A shows a schematic diagram of an embodiment of a resonant half-bridge flyback power supply according to the present invention.

FIG. 1B shows a schematic diagram of a specific embodiment of a resonant half-bridge flyback power supply according to the present invention.

FIG. 2 shows a waveform diagram corresponding to the embodiment shown in FIG. 1A of the present invention.

FIG. 3 shows a schematic diagram of waveforms according to an embodiment of the present invention.

FIG. 4 shows a schematic diagram of a state operation waveform according to an embodiment of the present invention.

FIG. 5 shows a schematic diagram of a specific embodiment of the first timing circuit and the SSW (flexible switching) pulse wave generating circuit in the primary side control circuit of the present invention.

FIG. 6 shows a schematic diagram of a specific embodiment of the dead time generating circuit in the primary side control circuit of the present invention.

FIG. 7 shows a schematic diagram of a specific embodiment of the pulse width modulation circuit and the upper bridge driving circuit in the primary side control circuit of the present invention.

FIG. 8 shows a schematic diagram of a specific embodiment of the second timing circuit and the lower bridge control circuit in the primary side control circuit of the present invention.

FIG. 9 shows a schematic diagram of a specific embodiment of the delay signal circuit and the third timing circuit in the primary side control circuit of the present invention.

FIG. 10 shows a schematic diagram of a specific embodiment of the output level sensing circuit in the primary side control circuit of the present invention.

none

10: Power Transformer

100: Primary side control circuit

1001: Resonant Half-Bridge Flyback Power Supply

20: Resonant capacitor

200: Secondary side control circuit

30: Upper bridge power switch

300: Half-bridge power stage circuit

40: Lower bridge power switch

51, 52, 60: Resistors

70: Synchronous rectification switch

90: Optocoupler

HB: Phase Node

Io: output current

IP: Primary side switch current

IS: Secondary side switching current

n,m: turns ratio

NA: Auxiliary winding

NP: Primary winding

NS: Secondary winding

Po: output power

PRES: Resonant switching pulse

SG: drive signal

SH: Upper bridge switching signal

SL: Lower bridge switching signal

TDS: During demagnetization

VAUX: Auxiliary winding related signal

VCS: Current detection signal

VFB: Feedback signal

Vin: input power

VNA: Auxiliary winding signal

Vo: output voltage

Claims (30)

A resonant half-bridge flyback power supply is used to convert an input power into an output power, the resonant half-bridge flyback power supply comprises: a half-bridge power stage circuit, including a series connection between the input power and a reference potential an upper-bridge power switch and a lower-bridge power switch, wherein the upper-bridge power switch and the lower-bridge power switch are coupled to a phase node; a power transformer is coupled between the half-bridge power stage circuit and the output power supply ; a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power source; and a primary side control circuit for a feedback signal related to the output power source and generate an upper bridge switching signal and a lower bridge switching signal to control the upper bridge power switch and the lower bridge power switch respectively, and switch a primary side winding of the power transformer to convert the input power into the output power ; wherein the primary side winding is magnetically induced when the upper bridge power switch is turned on, and after the upper bridge power switch is turned off, the primary side control circuit generates a resonant switching pulse in the lower bridge switching signal and conducts The lower bridge power switch, through the resonant capacitor and the primary winding, transmits the energy obtained during induction to a secondary winding of the power transformer in a resonance manner to generate the output power; wherein when the output power When lower than a delay threshold, the primary side control circuit determines a delay period in the lower bridge switching signal according to the output power, and controls the upper bridge power switch and the lower bridge power switch during part of the delay period are not turned on, wherein the delay period is inversely related to the output power. The resonant half-bridge flyback power supply as claimed in claim 1, wherein when the delay period is longer than a light-load threshold period, the upper-bridge power switch and the None of the lower bridge power switches are turned on, wherein the light load threshold period is greater than or equal to 0. The resonant half-bridge flyback power supply of claim 2, wherein when the delay period is longer than the light load threshold period, after the delay period ends, the primary side control circuit further generates the lower bridge switching signal A flexible switching pulse wave is used to turn on the lower bridge power switch for a flexible period, so that the upper bridge power switch achieves flexible switching when the upper bridge power switch is turned on next time. The resonant half-bridge flyback power supply of claim 3, wherein the flexible switching corresponds to zero-voltage switching when the upper-bridge power switch is turned on next time. The resonant half-bridge flyback power supply according to claim 1, wherein the conduction period of the lower bridge power switch is related to the demagnetization period of the power transformer, and is greater than or equal to the demagnetization period of the power transformer. The resonant half-bridge flyback power supply of claim 1, wherein the primary-side control circuit maintains the upper-bridge switching signal and the lower-bridge switching respectively immediately before and after the upper-bridge switching signal is switched to a high level The signal is at a low level for a period of dead time of the upper bridge and a dead time of the lower bridge, so that the upper bridge power switch and the lower bridge power switch respectively achieve flexible switching when they are turned on next time. During the delay time and the idle delay time of the lower bridge, neither the upper bridge power switch nor the lower bridge power switch is turned on. The resonant half-bridge flyback power supply according to claim 1, wherein before the upper-bridge power switch is turned on, the lower-bridge power switch is controlled to be turned on to charge a bootstrap capacitor, wherein the bootstrap capacitor uses to provide power to an upper bridge switch driver, and the upper bridge switch driver is used for driving the upper bridge power switch. The resonant half-bridge flyback power supply of claim 1, wherein the primary-side control circuit further determines the delay period according to a waveform characteristic of a quasi-resonant signal, and then determines the resonant switching pulse of the lower bridge switching signal The initial time point of the wave, wherein a quasi-resonant period of the quasi-resonant signal is related to the inductance value of the primary side winding and the stray capacitance value of the half-bridge power stage circuit. The resonant half-bridge flyback power supply of claim 1, wherein when the output power is below a burst threshold, a burst signal is generated, wherein when the burst signal is generated, the delay period A burst period is further included to extend the delay period. The resonant half-bridge flyback power supply of claim 9, wherein the burst threshold is lower than the delay threshold. A primary side control circuit is used to control a resonant half-bridge flyback power supply to convert an input power supply into an output power supply, the resonant half-bridge flyback power supply comprises: a half-bridge power stage circuit, including a series of An upper-bridge power switch and a lower-bridge power switch between the input power supply and a reference potential, wherein the upper-bridge power switch and the lower-bridge power switch are coupled to a phase node; a power transformer is coupled to the half-bridge power switch between the stage circuit and the output power supply; and a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; the primary side control circuit includes: a pulse width modulation a circuit for generating a modulation signal according to a feedback signal related to the output power; an upper bridge driving circuit for generating an upper bridge switching signal according to the modulation signal to control the upper bridge power switch; and A timing control circuit, coupled to the pulse width modulation circuit, is used to generate a lower bridge switching signal to control the lower bridge power switch and switch a primary winding of the power transformer to convert the input power into the output power; The primary side winding is magnetically induced when the upper bridge power switch is turned on, and after the upper bridge power switch is turned off, the timing control circuit generates a resonant switching pulse in the lower bridge switching signal to turn on the lower bridge power switch. The bridge power switch, through the resonant capacitor and the primary winding, transmits the energy obtained during induction to a secondary winding of the power transformer in a resonance manner to generate the output power; wherein when the output power is lower than When a delay threshold is present, the timing control circuit determines a delay period in the lower bridge switching signal according to the output power, and controls both the upper bridge power switch and the lower bridge power switch to be non-conductive during part of the delay period, The delay period is inversely related to the output power. The primary-side control circuit of claim 11, wherein when the delay period is longer than a light-load threshold period, the upper-bridge power switch and the lower-bridge power switch are controlled during the delay period after the light-load threshold period None of the switches are turned on, wherein the light-load threshold period is greater than or equal to 0. The primary side control circuit of claim 12, wherein when the delay period is longer than the light load threshold period, after the delay period ends, the timing control circuit further generates a flexible switching pulse in the lower bridge switching signal The lower bridge power switch is turned on for a flexible period, so that the upper bridge power switch achieves flexible switching when it is turned on next time. The primary side control circuit of claim 13, wherein the flexible switching corresponds to zero-voltage switching when the upper bridge power switch is turned on next time. The primary-side control circuit of claim 11, wherein the conduction period of the lower bridge power switch is related to the demagnetization period of the power transformer, and is greater than or equal to the demagnetization period of the power transformer. The primary-side control circuit of claim 11, wherein the primary-side control circuit maintains the upper-bridge switching signal and the lower-bridge switching signal at a low level immediately before and after the upper-bridge switching signal is switched to a high level, respectively A section of upper bridge dead time and a section of lower bridge Dead time, so that the upper-bridge power switch and the lower-bridge power switch respectively achieve flexible switching when they are turned on next time, wherein within the upper-bridge dead time and the lower-bridge dead time, the upper-bridge power switch and the None of the lower bridge power switches are turned on. The primary-side control circuit of claim 11, wherein the timing control circuit controls the lower-bridge power switch to be turned on before the upper-bridge power switch is turned on, so as to charge a bootstrap capacitor of the upper-bridge driving circuit, The bootstrap capacitor is used for providing power to a high-side switch driver of the high-side driving circuit, and the high-side switch driver is used for driving the high-side power switch. The primary-side control circuit as claimed in claim 11, wherein the timing control circuit further determines the delay period according to a waveform characteristic of a quasi-resonant signal, and further determines the start time point of the resonant switching pulse of the lower bridge switching signal , wherein a quasi-resonant period of the quasi-resonant signal is related to the inductance value of the primary side winding and the stray capacitance value of the half-bridge power stage circuit. The primary-side control circuit of claim 11, wherein the timing control circuit generates a burst signal when the output power is lower than a burst threshold, wherein when the burst signal is generated, the delay period A burst period is further included to extend the delay period. The primary side control circuit of claim 19, wherein the burst threshold is lower than the delay threshold. A control method for controlling a resonant half-bridge flyback power supply to convert an input power supply into an output power supply, the resonant half-bridge flyback power supply comprising: a half-bridge power stage circuit, including a power supply connected in series with the input an upper bridge power switch and a lower bridge power switch between the power supply and a reference potential, wherein the upper bridge power switch and the lower bridge power switch are coupled to a phase node; a power transformer is coupled to the half-bridge power stage circuit and the output power supply; and a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; the control method includes: A modulation signal is generated according to a feedback signal related to the output power; according to the modulation signal, an upper-bridge switching signal and a lower-bridge switching signal are generated to respectively control the upper-bridge power switch and the lower-bridge power switch , and switch a primary side winding of the power transformer to convert the input power into the output power; wherein the step of controlling the upper-bridge power switch and the lower-bridge power switch includes: when the upper-bridge power switch is turned off After being turned on, a resonant switching pulse is generated in the lower bridge switching signal to turn on the lower bridge power switch, and through the resonant capacitor and the primary side winding, the primary side winding is turned on to the upper bridge power switch in a resonance manner to turn on the power switch. The energy obtained during induction is transferred to a secondary winding of the power transformer to generate the output power; when the output power is lower than a delay threshold, a segment is determined in the lower bridge switching signal according to the output power During a delay period, and during a part of the delay period, both the upper-bridge power switch and the lower-bridge power switch are controlled to be non-conductive, wherein the delay period is inversely related to the output power supply. The control method of claim 21, wherein when the delay period is longer than a light-load threshold period, both the upper-bridge power switch and the lower-bridge power switch are controlled during the delay period after the light-load threshold period Non-conducting, where the light load threshold period is greater than or equal to 0. The control method of claim 22, wherein when the delay period is longer than the light-load threshold period, after the delay period ends, the primary-side control circuit further generates a flexible switching pulse in the lower bridge switching signal to The lower bridge power switch is turned on for a flexible period, so that the upper bridge power switch achieves flexible switching when the upper bridge power switch is turned on next time. The control method of claim 23, wherein the flexible switching corresponds to zero-voltage switching when the upper-bridge power switch is turned on next time. The control method according to claim 21, wherein the conduction period of the lower bridge power switch is related to the demagnetization period of the power transformer, and is greater than or equal to the demagnetization period of the power transformer. The control method of claim 21, wherein the primary-side control circuit maintains the upper-bridge switching signal and the lower-bridge switching signal at a low-level segment immediately before and after the upper-bridge switching signal is switched to a high level. Bridge dead time and a lower bridge dead time, so that the upper bridge power switch and the lower bridge power switch respectively achieve flexible switching when they are turned on next time, wherein the upper bridge dead time and the lower bridge During the dead time, neither the upper bridge power switch nor the lower bridge power switch is turned on. The control method of claim 21, wherein before the upper bridge power switch is turned on, the lower bridge power switch is controlled to be turned on to charge a bootstrap capacitor, wherein the bootstrap capacitor is used to provide power to an upper A bridge switch driver, the upper bridge switch driver is used for driving the upper bridge power switch. The control method as claimed in claim 21, further comprising: determining the delay period according to a waveform characteristic of a quasi-resonant signal, and then determining the starting time point of the resonant switching pulse of the lower bridge switching signal, wherein the quasi-resonance A quasi-resonant period of the signal is related to the inductance value of the primary side winding and the stray capacitance value of the half-bridge power stage circuit. The control method of claim 21, wherein when the output power is lower than a burst threshold, the delay period further includes a burst period to extend the delay period. The control method of claim 29, wherein the burst threshold is lower than the delay threshold.

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