TWI842513B - Decoder for decoding data in a pam-2m format, decoder device using the decoder, and receiver using the decoder device - Google Patents

Abstract

A decoder includes a demultiplexer and P analog-to-digital converters, wherein P 2. The demultiplexer receives and demultiplexes a data signal to be decoded modulated by a pulse amplitude modulation technique in a ^2M format into P demultiplexed data signals, wherein M 2. The analog-to-digital converters receive the demultiplexed data signals respectively. One of the analog-to-digital converters with a resolution of M+1 bits performs analog-to-digital conversion on the received demultiplexed data signal to generate a first decoded signal including an M-bit wide data portion and a 1-bit wide error portion. The remaining analog-to-digital converters with a resolution of M bits each perform analog-to-digital conversion on the received demultiplexed data signal to generate a second decoded signal including an M-bit wide data portion.

Description

Decoder, decoding device and receiver for decoding PAM-2M data

The present invention relates to data decoding, and more particularly to a decoder, a decoding device and a receiver for decoding data modulated by a pulse amplitude modulation technique in a ^2M format.

The Serializer/Deserializer (SerDes) function is widely used in communication standards such as Ethernet, Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), and extra-short reach (XSR) applications such as package-to-package computing chips and optical communication chips. Importantly, the receiver used to convert serial input data to parallel output data has enhanced performance and reduced power consumption.

Therefore, an object of the present invention is to provide a decoder, a decoding device and a receiver for decoding data modulated by a pulse amplitude modulation technique in a ^2M format, wherein the receiver can have enhanced performance and reduced power consumption at the same time.

According to one aspect of the present invention, a decoder includes a demultiplexer and P analog-to-digital converters.

The demultiplexer receives a data signal to be decoded modulated by a pulse amplitude modulation technique in a ^2M format, and demultiplexes the data signal to be decoded into P demultiplexed data signals, wherein M 2 and P 2.

The analog-to-digital converters are connected to the demultiplexer and receive the demultiplexed data signals respectively.

The resolution of one of the analog-to-digital converters is M+1 bits, and the received demultiplexed data signal is converted from analog to digital to generate a first decoded signal. The first decoded signal includes an M-bit wide data portion and a 1-bit wide error portion.

Wherein, except for the analog-to-digital converter with a resolution of M+1 bits, each analog-to-digital converter has a resolution of M bits, and performs analog-to-digital conversion on the received demultiplexed data signal to generate a second decoded signal, which includes an M-bit wide data portion.

According to another aspect of the present invention, a decoding device includes N decoders.

Each decoder includes a first demultiplexer, a buffer, a second demultiplexer, and P analog-to-digital converters, wherein N 2 and P 2.

The first demultiplexers of the decoders cooperate with each other to receive a feed data signal modulated by a pulse amplitude modulation technique in a ^2M format, and demultiplex the feed data signal into N first demultiplexed data signals respectively from the first demultiplexers, wherein M 2.

For each decoder, the buffer of the decoder is connected to the first demultiplexer of the decoder to receive the first demultiplexed data signal from the first demultiplexer, and buffers the first demultiplexed data signal to generate a data signal to be decoded.

For each decoder, the second demultiplexer of the decoder is connected to the buffer of the decoder to receive the data signal to be decoded and demultiplex the data signal to be decoded into P second demultiplexed data signals.

For each decoder, each analog-to-digital converter of the decoder is connected to the second demultiplexer of the decoder to receive a corresponding second demultiplexed data signal among the second demultiplexed data signals.

For each decoder, one of the analog-to-digital converters of the decoder has a resolution of M+1 bits, and performs analog-to-digital conversion on the received second demultiplexed data signal to generate a first decoded signal, which includes an M-bit wide data portion and a 1-bit wide error portion.

For each decoder, the resolution of each analog-to-digital converter of the decoder except the analog-to-digital converter with a resolution of M+1 bits is M bits, and the received second demultiplexed data signal is analog-to-digital converted to generate a second decoded signal, which includes an M-bit wide data portion.

According to another aspect of the present invention, a receiver includes a channel compensator, a voltage regulator, a phase interpolator, a decoding device, and an adaptive controller, wherein the decoding device includes N decoders.

The channel compensator receives an input data signal modulated by a ^2M format pulse amplitude modulation technique and performs channel compensation on the input data signal to generate a feed data signal, wherein M 2 and a gain of the channel compensator is adjustable.

The voltage regulator generates an adjustable reference voltage.

The phase interpolator receives a clock input and performs phase interpolation on the clock input to generate N interpolated clock signals, wherein N 2, and each interpolated clock signal can vary corresponding to a phase shift of the clock signal.

Each decoder has a de-skewer, a first demultiplexer, a buffer, a second demultiplexer, and P analog-to-digital converters.

For each decoder, the de-skewer of the decoder is connected to the phase interpolator to receive a corresponding one of the interpolated clock signals and delay the interpolated clock signal to generate a de-skewed clock signal, wherein the de-skewed clock signal can be changed corresponding to the delay of the interpolated clock signal.

For each decoder, the first demultiplexer of the decoder is connected to the deskew device and the channel compensator to receive the deskewed clock signal.

Among them, the first demultiplexers of the decoders cooperate with each other to receive the feed data signal from the channel compensator. The first demultiplexers demultiplex the feed data signal according to the de-skewed clock signals of the corresponding de-skewers and output N first demultiplexed data signals.

For each decoder, the buffer of the decoder is connected to the first demultiplexer to receive the first demultiplexed data signal from the first demultiplexer and buffer the first demultiplexed data signal to generate a data signal to be decoded.

For each decoder, the second demultiplexer of the decoder is connected to the buffer to receive the data signal to be decoded and demultiplex the data signal to be decoded into P second demultiplexed data signals.

For each decoder, the analog-to-digital converters of the decoder are connected to the second demultiplexer and the voltage regulator, and correspondingly receive the second demultiplexed data signals from the second demultiplexer and the reference voltage of the voltage regulator, wherein P 2.

For each decoder, one of the analog-to-digital converters of the decoder has a resolution of M+1 bits, and performs analog-to-digital conversion on the received second demultiplexed data signal according to the reference voltage to generate a first decoded signal, wherein the first decoded signal includes an M-bit wide data portion and a 1-bit wide error portion.

For each decoder, the resolution of each analog-to-digital converter of the decoder except the analog-to-digital converter with a resolution of M+1 bits is M bits, and the received second demultiplexed data signal is analog-to-digital converted according to the reference voltage to generate a second decoded signal, which includes an M-bit wide data portion.

The adaptive controller is connected to the decoding device, the channel compensator, the voltage regulator, the phase interpolator, and the de-skewers of the decoding device, and receives a decoded output of a first decoded signal and a second decoded signal generated by the analog-to-digital converters of the decoding device, and generates a data portion of the decoded output based on the data portion of the first decoded signal and the second decoded signals. An output signal is generated, and the channel compensator, the voltage regulator, the phase interpolator, and the de-skewers of the decoders are adaptively calibrated to adjust the gain of the channel compensator, the magnitude of the reference voltage, the phase offset of each interpolated clock signal, and the delay of each de-skewed clock signal of an erroneous portion of the decoded output based on the erroneous portion of the first decoded signal.

The utility model discloses a method for performing phase interpolation on the clock input by the phase interpolator to generate the interpolated clock signals, and the de-skew device delays the interpolated clock signal to generate the de-skewed clock signal, the channel compensator performs channel compensation on the input data signal to generate the feed data signal, the first demultiplexers demultiplex the feed data signal according to the de-skewed clock signal and output the first demultiplexed data signals, the buffers buffer the demultiplexed first demultiplexed data signals to generate the waiting-to-decode data signal, and the second demultiplexers demultiplex the waiting-to-decode data signal. The signal is demultiplexed into the second demultiplexed data signals, the analog-to-digital converters perform analog-to-digital conversion on the second demultiplexed data signals according to the reference voltage generated by the voltage regulator to generate the first decoded signals and the second decoded signals, the adaptive controller generates the output signal according to the data portion of the decoded output of the data portion of the first decoded signals and the second decoded signals, and adaptively calibrates the channel compensator, the voltage regulator, the phase interpolator, and the de-skewers of the decoders to improve the performance of the receiver and reduce the power consumption of the receiver.

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

1 and 2 , an embodiment of a receiver of the present invention is used to convert serial input data into parallel output data, including a channel compensator 11, a voltage regulator 12, a multi-phase filter 13, a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter 14, a phase interpolator 15, a decoding device 16, and an adaptive controller 17.

The channel compensator 11 receives an input data signal modulated by a ^2M pulse amplitude modulation technique and performs channel compensation on the input data signal to generate a feed data signal modulated by a ^2M pulse amplitude modulation technique, wherein M 2 and a gain of the channel compensator 11 is adjustable. It is worth mentioning that in the present embodiment, the input data signal and the feed data signal are modulated by a pulse amplitude modulation technique of 4 format (ie, M=2), and the data rate is 112 Gbps (ie, 56 Gbaud).

In this embodiment, the channel compensator 11 includes an equalizer device 111 and a variable gain amplifier 112 (VGA). The equalizer device 111 has a continuous time linear equalizer 116 (CTLE), a low frequency equalizer 117 (Low Frequency Equalizer, referred to as LFEQ), the high frequency component of the input data signal is compensated by the continuous time linear equalizer 116, the intermediate frequency component and the low frequency component of the input data signal are compensated by the low frequency equalizer 117, and a result signal of the above compensation is adjusted by the adjustable gain amplifier 112 to adjust the pulse amplitude so as to generate the feed data signal, wherein the parameters of the continuous time linear equalizer 116 and the low frequency equalizer 117 can be adjusted to change the gain of the channel compensator 11.

The voltage regulator 12 generates a reference voltage with an adjustable amplitude.

The multi-phase filter 13 receives a differential input clock signal pair of a current mode logic level and divides the differential input clock signal pair into two differential first clock signal pairs belonging to the current mode logic level and 90 degrees out of phase. It is worth mentioning that in this embodiment, the differential input clock signal pair has a frequency of 14 GHz.

The current mode logic to complementary metal oxide semiconductor converter 14 is connected to the multi-phase filter 13 to receive the differential first clock signal pairs and convert the differential first clock signal pairs into two differential second clock signal pairs belonging to a complementary metal oxide semiconductor level.

The phase interpolator 15 and some components of the adaptive controller 17 cooperate to form a clock data recovery (CDR) circuit. The phase interpolator 15 is connected to the current mode logic to the complementary metal oxide semiconductor converter 14 to receive the differential second clock signal pairs that together constitute a clock input, and perform phase interpolation on the clock input to generate N interpolated clock signals, where N 2, and each interpolated clock signal can vary corresponding to the phase offset of the clock signal. It is worth mentioning that in this embodiment, four interpolated clock signals are generated (ie, N=4).

The decoding device 16 includes N decoders 160 (i.e., there are four decoders 160 in this embodiment). In this embodiment, each decoder 160 has a de-skew device 161, a ring counter 162, a 1/Q frequency divider 163, a first demultiplexer 164, a buffer 165, a second demultiplexer 166, P analog-to-digital converters 167, a phase alignment circuit 168, and a Q-to-1 demultiplexer 169, wherein P 2 and Q 2. It is worth mentioning that in this embodiment, a 1/2 frequency divider, four analog-to-digital converters 167, and a two-to-one demultiplexer (ie, P=4 and Q=2) are used.

For each decoder 160, the de-skew device 161 of the decoder 160 is connected to the phase interpolator 15 to receive a corresponding one of the interpolated clock signals and delay the interpolated clock signal to generate a de-skewed clock signal, wherein the de-skewed clock signal can be changed corresponding to the delay of the interpolated clock signal. The first demultiplexer 164 of the decoder 160 is connected to the de-skew device 161 and the channel compensator 11 to receive the de-skewed clock signal.

The first demultiplexers 164 of the decoders 160 cooperate with each other to receive the feed data signal from the channel compensator 11. The first demultiplexers 164 demultiplex the feed data signal into N first demultiplexed data signals (i.e., four first demultiplexed data signals in this embodiment) outputted by the first demultiplexers 164, respectively, according to the de-skewed clock signals generated by the corresponding de-skewers 161. In this embodiment, each first demultiplexer 164 has a data rate of 14 Gbps.

It should be particularly noted that, for each de-skewed clock signal, the deviation between the de-skewed clock signal and other de-skewed clock signals can be changed by adjusting the delay of the de-skewed clock signal.

In this embodiment, for each decoder 160, the first demultiplexer 164 of the decoder 160 has a sampling switch 1641, the sampling switch 1641 having a first end connected to the channel compensator 11 to receive the feed data signal, a second end outputting the corresponding first demultiplexed data signal, and a control end connected to the de-skew device 161 to receive the de-skewed clock signal. The sampling switch 1641 switches between conducting and non-conducting according to the de-skewed clock signal. When the sampling switch 1641 is conducting, the feed data signal is transmitted through the sampling switch 1641 as one of the first demultiplexed data signals.

For each decoder 160, the ring counter 162 of the decoder 160 is connected to the de-skew clock signal to receive the de-skew clock signal and generates a P-bit wide (i.e., 4-bit wide in this embodiment) count output according to the de-skew clock signal. A predetermined logical value (i.e., the logical value is 1 in this embodiment) cycles around the bits of the count output at a speed defined by the de-skew clock signal. The 1/Q divider 163 (i.e., the 1/2 divider 163 in this embodiment) is connected to the ring counter 162 to receive the counting output and generate a third clock signal with a frequency of 1/Q (i.e., 1/2 of the frequency of the counting output) according to the counting output.

For each decoder 160, the buffer 165 of the decoder 160 is connected to the second end of the sampling switch 1641 to receive and buffer the first demultiplexed data signal to generate a data signal to be decoded modulated by a pulse amplitude modulation technique in a ^2M format (i.e., 4 format in this embodiment). The second demultiplexer 166 is connected to the buffer 165 to receive the data signal to be decoded, and is connected to the ring counter 162 to receive the count output, and demultiplexes the data signal to be decoded into P second demultiplexed data signals (i.e., four second demultiplexed data signals in this embodiment) according to the count output. Each analog-to-digital converter 167 is connected to the second demultiplexer 166 and the voltage regulator 12, and correspondingly receives the second demultiplexed data signals from the second demultiplexer 166 and the reference voltage from the voltage regulator 12. The resolution of one of the analog-to-digital converters 167 is M+1 bits (i.e., 3 bits in this embodiment), and performs analog-to-digital conversion on the received second demultiplexed data signal according to the reference voltage to generate a non-return-to-zero (NRZ) signal. The first decoded signal in the NRZ (Non-Return-to-Zero) format is generated, the first decoded signal includes an M-bit wide (i.e., 2-bit wide in the present embodiment) data portion and a 1-bit wide error portion, the resolution of each analog-to-digital converter 167 except the analog-to-digital converter 167 with a resolution of M+1 bits is M bits, and the second demultiplexed data signal is digitally converted according to the reference voltage to generate a second decoded signal in a non-return-to-zero format, the second decoded signal includes an M-bit wide (i.e., 2-bit wide in the present embodiment) data portion, in the present embodiment, each second demultiplexed data signal has a data rate of 3.5 Gbps.

In this embodiment, for each decoder 160, the second demultiplexer 166 of the decoder 160 has P sampling switches 1661 (i.e., four sampling switches 1661 in this embodiment), each sampling switch 1661 having a first end connected to the buffer 165 to receive the data signal to be decoded, a second end outputting the corresponding second demultiplexed data signal, and a control end connected to the ring counter 162 to receive the corresponding bit of the count output. Each sampling switch 1661 is turned on when the corresponding bit of the count output is a predetermined logical value (i.e., the logical value is 1 in this embodiment), and is not turned on when it is not the logical value. For each sampling switch 1661, when the sampling switch 1661 is turned on, the feed data signal is transmitted through the sampling switch 1661 to serve as one of the second demultiplexed data signals. In addition, each analog-to-digital converter 167 is a successive approximation analog-to-digital converter (ADC).

For each decoder 160, the phase alignment circuit 168 of the decoder 160 is connected to the analog-to-digital converters 167 to receive the first decoded signal and the second decoded signals, and is connected to the ring counter 162 to receive the count output, and aligns the first decoded signal and the second decoded signals according to the count output to generate a phase signal including a The alignment signal of the data portion of 1 bit width (i.e., 8 bits width in the present embodiment) and the error portion of 1 bit width is derived from the first decoded signal and the data portion of the second decoded signals, and the error portion is derived from the error portion of the first decoded signal. The Q-to-1 demultiplexer 169 (i.e., 2-to-1 demultiplexer in the present embodiment) is connected to the phase alignment circuit 168 to receive the alignment signal, and is connected to the 1/Q divider (i.e., 1/2 divider in the present embodiment) to receive the third clock signal, and demultiplexes the alignment signal into a demultiplexed signal including a data portion and an error portion according to the third clock signal, the data portion of the demultiplexed signal being The alignment signal is a data portion of the first decoded signal and the second decoded signals, and the error portion of the demultiplexed signal is Q bit wide (i.e., 2 bits wide in the present embodiment) and is derived from the error portion of the first decoded signal, wherein the Q-to-1 demultiplexer 169 of the decoder 160 cooperates to generate the demultiplexed signal to jointly constitute a decoded output. In the present embodiment, for each decoder 160, the alignment signal has a data rate of 8 3.5 Gbps data portion and a data rate of 1 3.5 Gbps error fraction, and the demultiplexed signal has a data rate of 16 The data portion of the Gigabit Ethernet and a data rate of 2 The wrong part of Jibao.

The adaptive controller 17 is connected to the Q-to-1 demultiplexers 169 (i.e., 2-to-1 demultiplexers in the present embodiment) of the decoders 160 to receive the decoded outputs, and is connected to the equalizer device 111, the voltage regulator 12, the phase interpolator 15, and the de-skew device 161 of the decoders 160 to generate an output data signal based on the data portion of the decoded outputs of the first decoded signals and the data portion of the second decoded signals generated by the analog-to-digital converters 167 of the decoders 160. The adaptive controller 17 further performs adaptive calibration on the equalizer device 111, the voltage regulator 12, the phase interpolator 15, and the de-skew device 161 of the decoders 160 to adjust the gain of the channel compensator 11, the magnitude of the reference voltage, the phase offset of each interpolated clock signal, and the delay of each de-skewed clock signal of the erroneous portion of the decoded output based on the erroneous portion of the first decoded signal, so as to obtain an eye diagram of the feed data signal with the best quality, a correct swing of the feed data signal, and an optimal sampling position of the feed data signal. In this embodiment, the output data signal has 64 gigabyte data rate.

In summary, the receiver of the present invention has the following advantages.

1. The continuous time linear equalizer 116 is only used to compensate the high frequency component of the input data signal, so the receiver is suitable for working when the input data signal is transmitted through a low loss channel. In addition, the analog-to-digital converters 167 of the decoders 160 are all continuous approximation analog-to-digital converters, and the first demultiplexers 164 and the second demultiplexers 166 of the decoders 160 operate in a time-interleaved manner, which is beneficial to reducing the power consumption of the decoding device 16.

2. For each decoder 160, only the analog-to-digital converter 167 with a resolution of M+1 bits (i.e., 3 bits in the present embodiment) extracts 2 ^M (i.e., 4 in the present embodiment) data values corresponding to the data portion of the first decoded signal, which are used for adaptive phase calibration of the equalizer device 111 and the phase interpolator 15. This can enable the jitter tolerance of the clock data recovery circuit to reach an acceptable level, thereby improving the performance of the receiver and reducing the power consumption of the receiver.

3. The voltage regulator 12 generates the reference voltage for use by all analog-to-digital converters 167 of the decoders 160, which helps reduce the size and power consumption of the voltage regulator 12.

4. By connecting the buffer 165 of each decoder 160 to the first demultiplexer 164 and the second demultiplexers 166, the channel compensator 11 has a light load capacitance at the output and thus has a wide bandwidth.

Therefore, the purpose of the present invention can be achieved.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

11: Channel compensator 111: Equalizer device 112: Adjustable gain amplifier 116: Continuous time linear equalizer 117: Low frequency equalizer 12: Voltage regulator 13: Phase filter 14: Current mode logic to complementary metal oxide semiconductor converter 15: Phase interpolator 16: Decoder device 160: Decoder 161: Deskewer 162: Ring counter 163: 1/Q divider 164: First demultiplexer 1641: Sampling switch 165: Buffer 166: Second demultiplexer 1661: Sampling switch 167: Analog-to-digital converter 168: Phase alignment circuit 169: Q-select-1 demultiplexer 17: Adaptive controller

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG. 1 is a circuit block diagram illustrating an embodiment of a receiver of the present invention; and FIG. 2 is a block diagram illustrating a channel compensator of the embodiment.

11: Channel compensator

12: Voltage regulator

13: Phase filter

14: Current mode logic to complementary metal oxide semiconductor converter

15: Phase interpolator

16: Decoding device

160:Decoder

161: De-skewer

162: Ring counter

163:1/Q crossover

164: The first demultiplexer

1641: Sampling switch

165: Buffer

166: Second demultiplexer

1661: Sampling switch

167:Analog-to-digital converter

168: Phase alignment circuit

169:Q choose 1 demultiplexer

17: Adaptive controller

Claims (15)

A decoder comprises: a demultiplexer, receiving a data signal to be decoded modulated by a pulse amplitude modulation technique in a ^2M format, and demultiplexing the data signal to be decoded into P demultiplexed data signals, wherein M 2 and P 2; and P analog-to-digital converters connected to the demultiplexer and receiving the demultiplexed data signals respectively; wherein one of the analog-to-digital converters has a resolution of M+1 bits and performs analog-to-digital conversion on the received demultiplexed data signal to generate a first decoded signal, the first decoded signal includes an M-bit wide data portion and a 1-bit wide error portion; and wherein each analog-to-digital converter except the analog-to-digital converter with a resolution of M+1 bits has a resolution of M bits and performs analog-to-digital conversion on the received demultiplexed data signal to generate a second decoded signal, the second decoded signal includes an M-bit wide data portion. A decoder as described in claim 1, wherein the demultiplexer includes P sampling switches, each sampling switch having a first end for receiving the data signal to be decoded and a second end connected to one of the analog-to-digital converters and outputting a corresponding demultiplexed data signal. A decoder as described in claim 1, wherein each analog-to-digital converter is a continuous approximation analog-to-digital converter. A decoding device includes: N decoders, each decoder includes a first demultiplexer, a buffer, a second demultiplexer, and P analog-to-digital converters, wherein N 2 and P 2. The first demultiplexers of the decoders cooperate with each other to receive a feed data signal modulated by a pulse amplitude modulation technique in a ^2M format, and demultiplex the feed data signal into N first demultiplexed data signals respectively from the first demultiplexers, wherein M 2; for each decoder, the buffer of the decoder is connected to the first demultiplexer of the decoder to receive the first demultiplexed data signal from the first demultiplexer, and buffers the first demultiplexed data signal to generate a data signal to be decoded, the second demultiplexer of the decoder is connected to the buffer of the decoder to receive the data signal to be decoded, and demultiplexes the data signal to be decoded into P second demultiplexed data signals, each analog-to-digital converter of the decoder is connected to the second demultiplexer of the decoder to receive a corresponding second demultiplexed data signal among the second demultiplexed data signals, One of the analog-to-digital converters of the decoder has a resolution of M+1 bits, and performs analog-to-digital conversion on the received second demultiplexed data signal to generate a first decoded signal, the first decoded signal includes an M-bit wide data portion and a 1-bit wide error portion, and each analog-to-digital converter of the decoder except the analog-to-digital converter with a resolution of M+1 bits has a resolution of M bits, and performs analog-to-digital conversion on the received second demultiplexed data signal to generate a second decoded signal, the second decoded signal includes an M-bit wide data portion. A decoding device as described in claim 4, wherein the second demultiplexer of each decoder includes P sampling switches, each sampling switch having a first end connected to the buffer to receive the data signal to be decoded and a second end connected to one of the analog-to-digital converters and outputting a corresponding second demultiplexed data signal. A decoding device as described in claim 4, wherein each analog-to-digital converter is a continuous approximation analog-to-digital converter. A decoding device as described in claim 4, wherein the first demultiplexer of each decoder includes a sampling switch having a first end for receiving the feed data signal and a second end connected to the buffer and outputting a corresponding first demultiplexed data signal. The decoding device as described in claim 4, wherein each decoder further includes a phase alignment circuit connected to the analog-to-digital converters to receive the first decoded signal and the second decoded signals, and align the first decoded signal and the second decoded signals to generate a phase alignment circuit having a phase difference of bit wide data portion and a 1 bit wide error portion. The decoding device as claimed in claim 8, wherein each decoder further comprises a Q-select-1 demultiplexer connected to the phase alignment circuit to receive the alignment signal and demultiplex the alignment signal to obtain a signal including a The demultiplexed signal has a 1-bit wide data portion and a 1-Q bit wide error portion. A receiver includes: a channel compensator, receiving an input data signal modulated by a pulse amplitude modulation technique in a ^2M format, and performing channel compensation on the input data signal to generate a feed data signal, wherein M 2 and a gain of the channel compensator is adjustable; a voltage regulator, generating an adjustable reference voltage; a phase interpolator, receiving a clock input and performing phase interpolation on the clock input to generate N interpolated clock signals, wherein N 2, and each interpolated clock signal can be changed corresponding to the phase offset of the clock signal; a decoding device, including N decoders, each decoder having a de-skewer, connected to the phase interpolator, to receive a corresponding one of the interpolated clock signals, and delay the interpolated clock signal to generate a de-skewed clock signal, wherein the de-skewed clock signal can be changed corresponding to the delay of the interpolated clock signal, a first demultiplexer, connected to the de-skewer and the channel compensator, to receive the de-skewed clock signal, The first demultiplexers of the decoders cooperate with each other to receive the feed data signal from the channel compensator, and the first demultiplexers demultiplex the feed data signal according to the de-skew clock signals of the corresponding de-skewers and output N first demultiplexed data signals. Each decoder also has a buffer connected to the first demultiplexer to receive the first demultiplexed data signal from the first demultiplexer and buffer the first demultiplexed data signal to generate a data signal to be decoded. a second demultiplexer connected to the buffer to receive the data signal to be decoded and demultiplex the data signal to be decoded into P second demultiplexed data signals, and P analog-to-digital converters connected to the second demultiplexer and the voltage regulator and correspondingly receiving the second demultiplexed data signals from the second demultiplexer and the reference voltage of the voltage regulator, wherein P 2. One of the analog-to-digital converters has a resolution of M+1 bits and performs analog-to-digital conversion on the received second demultiplexed data signal according to the reference voltage to generate a first decoded signal. The first decoded signal includes an M-bit wide data portion and a 1-bit wide error portion, and the resolution of each analog-to-digital converter except the analog-to-digital converter with a resolution of M+1 bits is M bits, and the received second demultiplexed data signal is analog-to-digital converted according to the reference voltage to generate a second decoded signal, the second decoded signal includes an M-bit wide data portion; and an adaptive controller connected to the decoding device, the channel compensator, the voltage regulator, the phase interpolator, and the de-skew devices of the decoding device, and receiving a signal from the decoding device. The invention relates to a method for generating a decoded output of a first decoded signal and a second decoded signal generated by analog-to-digital converters, and generating an output signal according to a data portion of the decoded output derived from the data portion of the first decoded signal and the second decoded signals, and adaptively calibrating the channel compensator, the voltage regulator, the phase interpolator, and the de-skewers of the decoders to adjust the gain of the channel compensator, the size of the reference voltage, the phase offset of each interpolated clock signal, and the delay of each de-skewed clock signal of an erroneous portion of the decoded output derived from the erroneous portion of the first decoded signal. A receiver as described in claim 10, wherein the second demultiplexer of each decoder includes P sampling switches, each sampling switch having a first end connected to the buffer to receive the data signal to be decoded and a second end connected to one of the analog-to-digital converters and outputting a corresponding second demultiplexed data signal. A receiver as described in claim 10, wherein each analog-to-digital converter is a continuous approximation analog-to-digital converter. In the receiver as described in claim 10, the first demultiplexer of each decoder includes a sampling switch having a first end connected to the channel compensator to receive the feed data signal and a second end connected to the buffer and outputting a corresponding first demultiplexed data signal. A receiver as claimed in claim 10, wherein each decoder further comprises a phase alignment circuit connected to the analog-to-digital converters to receive the first decoded signal and the second decoded signals, and align the first decoded signal and the second decoded signals to generate a phase alignment circuit including a bit wide data portion and a 1 bit wide error portion. A receiver as claimed in claim 14, wherein each decoder further comprises a Q-select-1 demultiplexer connected to the phase alignment circuit and the adaptive controller to receive the alignment signal and demultiplex the alignment signal to obtain a signal including a bit-wide data portion and a Q-bit-wide error portion, where Q 2, and the demultiplexed signals respectively generated by the Q-to-1 demultiplexers of the decoders jointly construct the decoded output.

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