CN103347161B

CN103347161B - Parallel digital signal is converted to method and the device of serial TMDS signal

Info

Publication number: CN103347161B
Application number: CN201310256397.6A
Authority: CN
Inventors: 夏洪锋; 魏胜涛; 苏进; 陶成; 任殿升; 刘志明; 陈晓飞; 陈�峰
Original assignee: Long Xun Semiconductor (hefei) Ltd By Share Ltd
Current assignee: Long Xun Semiconductor (hefei) Ltd By Share Ltd
Priority date: 2013-06-25
Filing date: 2013-06-25
Publication date: 2016-05-25
Anticipated expiration: 2033-06-25
Also published as: CN103347161A

Abstract

The embodiment of the present invention provides a kind of method and device thereof that parallel digital signal is converted to serial TMDS signal, and described method comprises the even bit parallel signal and the odd bits parallel signal that utilize in the first clock difference sample-parallel data signal; Described even bit parallel signal is serialized as to even bit serial signal, described odd bits parallel signal is serialized as to odd bits serial signal, and a byte of described odd bits serial signal delay is obtained to first kind signal, the reference clock frequency division that wherein said the first clock is produced by phaselocked loop obtains; Described even bit serial signal and described first kind signal are rattled to process and obtain differential digital signal; Described differential digital signal is converted to serial TMDS signal. The method that parallel digital signal is converted to serial TMDS signal that the embodiment of the present invention provides, has realized employing Half Speed clock parallel digital signal has been converted to serial TMDS signal, has greatly promoted the speed of signal conversion.

Description

Method and device for converting parallel digital signals into serial TMDS signals

Technical Field

The invention belongs to the technical field of chip design, and particularly relates to a method and a device for converting a parallel digital signal into a serial TMDS signal.

Background

A high definition signal transmitter (HDMI) is a digital video/audio interface technology, which is a special digital interface suitable for image transmission and can transmit audio and video signals simultaneously. The HDMI is used to convert a parallel digital signal into a serial TMDS signal (transmission minimized differential signal) and transmit.

In the prior art, HDMI usually converts parallel digital signals into serial TMDS signals by using a full-speed parallel digital signal to serial TMDS signal, that is, a full-speed clock is used to convert parallel digital signals into serial TMDS signals. For example, for a parallel digital signal with a data rate of 340MBps, a full speed clock of 3.4GHz is required to convert the parallel digital signal to a serial TMDS signal. Under certain conditions of manufacturing process, the conversion mode using the full-speed clock is relatively slow.

With the continuous development of technology, a fast method for converting parallel digital signals into serial TMDS signals is needed.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method and an apparatus for converting a parallel digital signal into a serial TMDS signal with a fast conversion speed, so as to solve the problem in the prior art that the speed of converting a parallel digital signal into a serial TMDS signal by using a full-speed clock mode is very slow.

To achieve the above object, an embodiment of the present invention provides a method of converting a parallel digital signal into a serial TMDS signal, including:

sampling even-number parallel signals and odd-number parallel signals in the parallel digital signals respectively by using a first clock; serializing the even-bit parallel signals into even-bit serial signals, serializing the odd-bit parallel signals into odd-bit serial signals, and delaying the odd-bit serial signals by one byte to obtain first-class signals, wherein the first clock is obtained by frequency division of a reference clock generated by a phase-locked loop;

performing ping-pong processing on the even-numbered serial signals and the first-class signals to obtain differential digital signals;

converting the differential digital signal to a serial TMDS signal.

Preferably, the converting the differential digital signal into a serial TMDS signal includes:

performing pre-drive processing on the differential digital signal;

and performing driving processing on the differential digital signal to obtain the serial TMDS signal.

Preferably, while the even-bit serial signal and the first-type signal are subjected to ping-pong processing to obtain a differential digital signal, the method further includes:

delaying the even-numbered serial signals by one byte to obtain second-class signals, and delaying the first-class signals by one byte to obtain third-class signals;

and performing ping-pong processing on the second type of signal and the third type of signal to obtain a fourth type of signal.

delaying the even-numbered serial signals by two bytes to obtain fifth signals, and delaying the first signals by two bytes to obtain sixth signals;

and performing ping-pong processing on the fifth type of signal and the sixth type of signal to obtain a seventh type of signal.

Preferably, before sampling the even-bit parallel signal and the odd-bit parallel signal in the parallel digital signals respectively by using the first clock, the method further includes:

and performing first-in first-out processing on the parallel digital signals.

Preferably, the ping-pong processing the even-numbered serial signals and the first-class signals to obtain differential digital signals includes:

triggering the even-bit serial signals by adopting the rising edge of the reference clock, and triggering the first-class signals by adopting the falling edge of the reference clock;

outputting the even-bit serial signal aligned with a rising edge of the reference clock and the first type signal aligned with a falling edge of the reference clock;

and performing ping-pong processing on the even-numbered serial signals and the first-class signals to obtain the differential digital signals.

Accordingly, an embodiment of the present invention further provides an apparatus for converting a parallel digital signal into a serial TMDS signal, including:

a sampling serialization unit for respectively sampling the even-numbered parallel signals and the odd-numbered parallel signals in the parallel digital signals by using a first clock; serializing the even-bit parallel signals into even-bit serial signals, serializing the odd-bit parallel signals into odd-bit serial signals, and delaying the odd-bit serial signals by one byte to obtain first-class signals, wherein the first clock is obtained by frequency division of a reference clock generated by a phase-locked loop;

the first ping-pong processing unit is used for performing ping-pong processing on the even-numbered serial signals and the first-class signals to obtain differential digital signals;

and the conversion unit is used for converting the differential digital signal into a serial TMDS signal.

Preferably, the conversion unit includes:

the pre-driving processing unit is used for performing pre-driving processing on the differential digital signal;

and the driving processing unit is used for driving the differential digital signal to obtain the serial TMDS signal.

Preferably, the conversion unit includes a pre-driving circuit, a driving circuit, and a bias circuit; wherein,

the pre-driving circuit consists of four inverters;

the driving circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor, wherein the drain terminal of the first NMOS transistor and the drain terminal of the third NMOS transistor are connected with the output end of the conversion unit, the gate terminal of the first NMOS transistor is connected with the gate terminal of the third NMOS transistor, the source terminal of the first NMOS transistor is connected with the drain terminal of the second NMOS transistor and connected with a current source, the source terminal of the second NMOS transistor is grounded, the gate terminal of the second NMOS transistor is connected with the pre-driving circuit, the source terminal of the third NMOS transistor is connected with the drain terminal of the fourth NMOS transistor and connected with the current source, and the source terminal of the fourth NMOS transistor is grounded, and the gate terminal of the fourth NMOS transistor is grounded;

the biasing circuit comprises a fifth NMOS transistor and a sixth NMOS transistor, wherein the drain terminal of the fifth NMOS transistor is connected with the digital-to-analog converter in the conversion unit, the gate terminal of the fifth NMOS transistor is connected with the gate terminal of the third NMOS transistor, the source terminal of the fifth NMOS transistor is connected with the drain terminal of the sixth NMOS transistor, the drain terminal of the sixth NMOS transistor is connected with the gate terminal, the source terminal of the sixth NMOS transistor is grounded, and the gate terminal of the sixth NMOS transistor is connected with the power supply.

Preferably, the apparatus further comprises:

the first delay unit is used for delaying the even-numbered serial signals by one byte to obtain second-class signals;

the second delay unit is used for delaying the first type of signals by one byte to obtain third type of signals;

and the second ping-pong processing unit is used for performing ping-pong processing on the second type of signals and the third type of signals to obtain fourth type of signals.

Preferably, the apparatus further comprises:

the third delay unit is used for delaying the even-numbered serial signals by two bytes to obtain fifth signals;

the fourth delay unit is used for delaying the first type of signals by two bytes to obtain sixth type of signals;

and the third ping-pong processing unit is used for performing ping-pong processing on the fifth type signal and the sixth type signal to obtain a seventh type signal.

Preferably, the apparatus further comprises:

and the first-in first-out processing unit is used for performing first-in first-out processing on the parallel digital signals.

Preferably, the first ping-pong processing unit comprises:

the trigger unit is used for triggering the even-bit serial signals by adopting the rising edge of the reference clock and triggering the first-class signals by adopting the falling edge of the reference clock;

an output unit for outputting the even-bit serial signal aligned with a rising edge of the reference clock and the first type signal aligned with a falling edge of the reference clock;

and the fourth ping-pong processing unit is used for performing ping-pong processing on the even-numbered serial signals and the first-class signals to obtain the differential digital signals.

Preferably, the fourth ping-pong processing unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; wherein,

the source end of the first PMOS transistor is connected with a power supply, the drain end of the first PMOS transistor is connected with the source end of the second PMOS transistor, and the grid end of the first PMOS transistor is connected with the output unit;

the source end of the second PMOS transistor is connected with the source end of the first PMOS transistor, the drain end of the second PMOS transistor is connected with the drain end of the seventh NMOS transistor and connected with the output end of the fourth ping-pong processing unit, and the gate end of the second PMOS transistor is connected with the selection signal output by the output unit;

the drain end of the seventh NMOS transistor is connected with the drain end of the second PMOS transistor, the source end of the seventh NMOS transistor is connected with the drain end of the eighth NMOS transistor and is connected with the output end of the fourth ping-pong processing unit, and the gate end of the seventh NMOS transistor is connected with the reverse signal of the selection signal output by the output unit;

the drain end of the eighth NMOS transistor is connected with the source end of the seventh NMOS transistor, the source end of the eighth NMOS transistor is grounded, and the gate end of the eighth NMOS transistor is connected with the output unit;

the source end of the third PMOS transistor is connected with a power supply, the drain end of the third PMOS transistor is connected with the source end of the fourth PMOS transistor, and the grid end of the third PMOS transistor is connected with the output unit;

the source end of the fourth PMOS transistor is connected with the drain end of the third PMOS transistor, the drain end of the fourth PMOS transistor is connected with the drain end of the ninth NMOS transistor, the drain end of the ninth NMOS transistor is connected with the output end of the fourth ping-pong processing unit and is connected with the drain end of the second PMOS transistor, and the gate end of the ninth NMOS transistor is connected with the reverse signal of the selection signal output by the output unit;

the drain end of the ninth NMOS transistor is connected with the drain end of the fourth PMOS transistor, connected with the output end of the fourth ping-pong processing unit in parallel and connected with the drain end of the second PMOS transistor, the source end of the ninth NMOS transistor is connected with the drain end of the tenth NMOS transistor, and the gate end of the ninth NMOS transistor is connected with the selection signal output by the output unit;

and the drain end of the tenth NMOS transistor is connected with the source end of the ninth NMOS transistor, the drain end of the tenth NMOS transistor is grounded, and the gate end of the tenth NMOS transistor is connected with the output unit.

According to the method and the device for converting the parallel digital signals into the serial TMDS signals, the even-numbered parallel signals and the odd-numbered parallel signals in the parallel digital signals are respectively sampled according to the clock, the even-numbered parallel signals and the odd-numbered parallel signals are serialized to obtain the even-numbered serial signals and the odd-numbered serial signals, the odd-numbered serial signals are delayed by one byte to obtain the first type of signals, then the even-numbered serial signals and the first type of signals are subjected to ping-pong processing to finally obtain the serial TMDS signals, the parallel digital signals are converted into the serial TMDS signals by the half-speed clock, and the signal conversion speed is greatly improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a flow chart of a method of converting a parallel digital signal to a serial TMDS signal according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an apparatus for converting parallel digital signals into serial TMDS signals according to an embodiment of the present invention;

FIG. 3 is a block diagram of an apparatus for converting parallel digital signals to serial TMDS signals according to an embodiment of the present invention;

FIG. 4a is a schematic diagram of a structure employing only one-level pre-emphasis in an embodiment of the present invention, and FIG. 4b is a schematic diagram of a structure employing two-level pre-emphasis in an embodiment of the present invention;

FIG. 5 is a schematic diagram of the phase relationship between a reference clock generated by a phase locked loop and first and second clocks generated by a frequency divider;

FIG. 6 is a diagram illustrating the results of pre-emphasis processing of even-bit serial signals and first-type signals;

FIG. 7 is a schematic circuit diagram of a TMDS driving circuit in the prior art;

FIG. 8 is a schematic circuit diagram of a TMDS driver according to an embodiment of the invention;

FIG. 9a is a schematic diagram of a prior art equalizing data selector;

fig. 9b is a schematic circuit diagram of an equalization data selector according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the existing HDMI interface technology, a full-speed clock is usually used to convert a parallel digital signal into a serial TMDS signal. However, the speed of the conversion method using the full-speed clock is relatively slow under certain conditions of the manufacturing process. To solve this problem, embodiments of the present invention provide the following technical solutions.

An embodiment of the present invention provides a method for converting a parallel digital signal into a serial TMDS signal, where fig. 1 shows a flowchart of the method, and the method includes the following steps:

step S11: and respectively sampling the even-numbered parallel signals and the odd-numbered parallel signals in the parallel digital signals by using a first clock, wherein the first clock is obtained by frequency division of a reference clock generated by a phase-locked loop.

Before converting the parallel digital signal into the serial TMDS signal, the phase locked loop generates a reference clock, which is a half-speed clock (if the data rate is 3.4Gbps, the frequency of the full-speed clock is 3.4GHz, and the frequency of the reference clock is 1.7GHz, which is half of the full-speed clock), with a duty cycle of 1:1 (i.e., the ratio between high and low levels is 1: 1). The first clock is generated by frequency division on the basis of a reference clock using a frequency divider. In one specific example, the first clock is generated by dividing the frequency of the reference clock by a fifth frequency divider, the frequency of the first clock is one fifth of the frequency of the reference clock (e.g., 340 MHz), the duty cycle of the first clock is 1: 4.

in addition, the parallel digital signal carries a parallel clock, the first clock and the parallel clock have a certain phase relationship, and the phase relationship between the two clocks can be determined according to the specific application requirement, which is not limited herein.

In one specific example, the parallel digital signal is a 10-bit digital signal, the even-numbered parallel signal sampled with the first clock is a 5-bit digital signal, and the odd-numbered parallel signal sampled with the first clock is also a 5-bit digital signal.

The parallel digital signals are a series of binary signals composed of high and low levels, and the binary signals are composed of odd-bit parallel signals and even-bit parallel signals. The odd-bit parallel signal and the even-bit parallel signal in the binary signal have the same phase.

Step S12: the even-bit parallel signal is serialized into an even-bit serial signal, the odd-bit parallel signal is an odd-bit serial signal, and the odd-bit serial signal is delayed by one byte to obtain a first-class signal.

And serializing the even-bit parallel signals and the odd-bit parallel signals obtained by sampling to obtain corresponding even-bit serial signals and odd-bit serial signals.

The first type of signal can be obtained by delaying the odd-bit serial signal by one byte, i.e., by one half-speed clock. The first type of signal is the same as the odd-numbered serial signal, and the difference between the first type of signal and the odd-numbered serial signal is that the phase of the first type of signal is delayed by one byte from the phase of the even-numbered serial signal, that is, the phase of the first type of signal is delayed by one byte from the phase of the odd-numbered serial signal.

The use of a first-in-first-out circuit reduces the complexity of the design of a serializing circuit that serializes errors in sampling signals (including sampling even-bit parallel signals and sampling odd-bit parallel signals).

Step S13: and performing ping-pong processing on the even-bit serial signals and the first-class signals to obtain differential digital signals.

The process of performing ping-pong treatment is as follows: the rising edge of a reference clock generated by a phase-locked loop is adopted to trigger even-bit serial signals, meanwhile, the falling edge of the reference clock is adopted to trigger a first type of signals (namely, the high and low levels of the reference clock are adopted as selection signals), the even-bit serial signals aligned with the rising edge of the reference clock and the first type of signals aligned with the falling edge of the reference clock are output, and at the moment, the first type of signals are delayed by one byte compared with the even-bit differential signals (namely, half time difference exists between the even-bit serial signals and the first type of signals). And performing ping-pong processing on the even-numbered serial signals with half clock difference and the first class signals to obtain differential digital signals.

In other embodiments of the present invention, while step S13 is performed, one or both of the following steps a (including a1 and a 2) or B (including B1 and B2) may also be performed simultaneously:

step A1: delaying the even-bit serial signal by one byte to obtain a second-class signal, and delaying the first-class signal by one byte to obtain a third-class signal; the second type of signal is identical to the even-bit serial signal and differs therefrom only in that the phase of the second type of signal is delayed by one byte from the phase of the even-bit serial signal, and the third type of signal is identical to the first type of signal and differs therefrom only in that the phase of the third type of signal is delayed by one byte from the phase of the first type of signal.

Step A2: and performing ping-pong processing on the second type of signal and the third type of signal to obtain a fourth type of signal, wherein the fourth type of signal is the same type of signal as the differential digital signal, namely the fourth type of signal is also the differential digital signal. The specific implementation of step A2 is similar to step S13, and will not be described herein.

Step B1: delaying the even-bit serial signal by two bytes to obtain a fifth signal, and delaying the first signal by two bytes to obtain a sixth signal; the fifth type signal is identical to the even-bit serial signal and differs therefrom only in that the phase of the fifth type signal is delayed by two bytes from the phase of the even-bit serial signal, and the sixth type signal is identical to the first type signal and differs therefrom only in that the phase of the sixth type signal is delayed by two bytes from the phase of the first type signal.

Step B2: and performing ping-pong processing on the fifth type signal and the sixth type signal to obtain a seventh type signal, wherein the seventh type signal is the same type of signal as the differential digital signal, namely the seventh type signal is also the differential digital signal. The specific implementation of step B2 is similar to step S13, and will not be described herein.

The process of performing either or both of the above steps a1 or B1 is a pre-emphasis process. For the case of very long transmission lines, this pre-emphasis process can effectively implement TMDS driving.

Step S14: the differential digital signal is converted to a serial TMDS signal.

The process of converting the differential digital signal into the serial TMDS signal specifically includes a process of performing pre-drive processing and a process of performing drive processing on the differential digital signal.

If step S13 is executed while executing one or both of steps a (including a1 and a 2) or B (including B1 and B2), then step S14 is executed while executing the following steps:

converting the fourth type of signal to a serial TMDS signal and/or converting the seventh type of signal to a serial TMDS signal.

According to the method for converting the parallel digital signals into the serial TMDS signals, the even-numbered parallel signals and the odd-numbered parallel signals in the parallel digital signals are respectively sampled according to the clock, the even-numbered parallel signals and the odd-numbered parallel signals are serialized to obtain the even-numbered serial signals and the odd-numbered serial signals, the odd-numbered serial signals are delayed by one byte to obtain the first-class signals, then the even-numbered serial signals and the first-class signals are subjected to ping-pong processing to obtain the differential digital signals, and finally the differential digital signals are converted into the serial TMDS signals.

In a specific example, by adopting the method for converting the parallel digital signals into the serial TMDS signals, the parallel digital signals with the data rate of 340MBps can be converted into the serial TMDS signals without adopting a clock with 3.4GHz, and the parallel digital signals with the data rate of 340MBps can be converted into the serial TMDS signals only by adopting a clock with 1.7GHz, so that the signal conversion speed under the determined process is greatly improved.

Further, before performing step S11, the parallel digital signals may be first subjected to a first-in first-out process.

The FIFO processing may be performed by a FIFO circuit. In the specific implementation process, a parallel clock carried by the parallel digital signal is used as a write clock to write the parallel digital signal into the first-in first-out circuit; and then reading the parallel digital signals from the first-in first-out circuit by using a second clock generated by the frequency divider.

If the parallel digital signals are subjected to first-in first-out processing, the frequency divider divides the frequency on the basis of a reference clock generated by the phase-locked loop to obtain a first clock and a second clock, wherein the first clock has the same function as the first clock in the embodiment and is used for sampling even-numbered parallel signals and odd-numbered parallel signals in the parallel digital signals, the second clock is used for reading the parallel digital signals from the first-in first-out circuit, and the first clock and the second clock have a fixed phase relationship. In addition, the second clock and the parallel clock carried by the parallel digital signal have the same frequency, but the phase difference between the two is uncertain. In one specific example, the frequency of the first clock is 340MHz, and the duty cycle is 1: and 4, the frequency of the second clock is 340 MHz.

The parallel digital signals are subjected to first-in first-out processing, a read clock of a first-in first-out circuit and a first clock for sampling even-bit parallel signals and odd-bit parallel signals are generated by the same frequency divider, have absolute phase relation, are stable in time sequence relation and give more comprehensive allowance to the digital circuit; therefore, subsequent signal processing processes are unified to the same clock domain, and the stability of signal conversion is improved.

It should be noted that, the method for converting a parallel digital signal into a serial TMDS signal in the embodiment of the present invention may have various specific implementations, and the above embodiment is only exemplary and is only used for explaining the technical solution of the present invention, and the technical solution of the present invention is not limited. The technical scheme of the embodiment of the invention can also have other implementation modes, and is not described herein again.

Correspondingly, an embodiment of the present invention further provides an apparatus for converting a parallel digital signal into a serial TMDS signal, and fig. 2 shows a schematic structural diagram of the apparatus, where the apparatus includes the following structures:

a sampling serialization unit 201 for sampling the even-numbered parallel signal and the odd-numbered parallel signal in the parallel digital signal respectively by using a first clock; serializing the even-bit parallel signals into even-bit serial signals, serializing the odd-bit parallel signals into odd-bit serial signals, and delaying the odd-bit serial signals by one byte to obtain first-class signals, wherein the first clock is obtained by frequency division of a reference clock generated by a phase-locked loop.

In one specific example, the sampling serialization unit 201 is a sampling shift register. The sampling shift register comprises an even serializer, an odd serializer, a frequency divider and a trigger, wherein the even serializer is used for serializing even-bit parallel signals into even-bit serial signals, the odd serializer is used for serializing the odd-bit parallel signals into odd-bit serial signals, the frequency divider is used for generating a first clock and a second clock according to frequency division of a reference clock generated by a phase-locked loop, and the trigger is used for delaying the odd-bit serial signals by one byte to obtain a first-class signal.

The first ping-pong processing unit 202 is configured to perform ping-pong processing on the even-numbered serial signals and the first-class signals to obtain differential digital signals.

The first ping-pong processing unit 202 is a data ping-pong device. In a specific example, the data ping-pong device is composed of two single-ended to differential flip-flops and two balanced data selectors, the single-ended to differential flip-flops are used for triggering according to rising edges and falling edges of a reference clock generated by a phase-locked loop, for example, one single-ended to differential flip-flop is used for triggering even-bit serial signals according to the rising edges of the reference clock, and the other single-ended to differential flip-flop is used for triggering the first type of signals according to the falling edges of the reference clock. The equalization data selector uses the high and low levels of the half-speed reference clock as selection signals, and performs ping-pong processing on even-bit serial signals and first-class signals to obtain differential digital signals.

A conversion unit 203 for converting the differential digital signal into a serial TMDS signal.

Specifically, the conversion unit 203 may include (not shown in the figure):

In one embodiment, the conversion unit 203 includes a pre-driver circuit, a driver circuit, and a bias circuit; wherein, the pre-drive circuit consists of four inverters; the driving circuit comprises four NMOS transistors, wherein a drain terminal of a first NMOS transistor and a drain terminal of a third NMOS transistor are connected with an output interface (the output interface is used for outputting signals after driving processing), a gate terminal of the first NMOS transistor is connected with a gate terminal of the third NMOS transistor, a source terminal of the first NMOS transistor is connected with a drain terminal of a second NMOS transistor and connected with a power supply, a source terminal of the second NMOS transistor is grounded, the gate terminal of the second NMOS transistor is connected with one output terminal of the pre-driving circuit, a source terminal of the third NMOS transistor is connected with a drain terminal of a fourth NMOS transistor and connected with the power supply, and a source terminal of the fourth NMOS transistor is grounded, and a gate terminal of the fourth NMOS transistor is connected with the other output terminal of the driving circuit; the biasing circuit comprises two NMOS transistors, wherein the drain terminal of a fifth NMOS transistor is connected with a digital-to-analog converter in the conversion unit 203, the grid terminal of the fifth NMOS transistor is connected with the grid terminal of the third NMOS transistor, the source terminal of the fifth NMOS transistor is connected with the drain terminal of a sixth NMOS transistor, the drain terminal of the sixth NMOS transistor is connected with the grid terminal, the source terminal of the sixth NMOS transistor is grounded, and the grid terminal of the sixth NMOS transistor is connected with a power supply.

In addition, the apparatus for converting a parallel digital signal into a serial TMDS signal according to the embodiment of the present invention may further include the following structure (not shown in the figure):

In one embodiment, the first ping-pong processing unit comprises:

The fourth ping-pong processing unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor; the source end of the first PMOS transistor is connected with a power supply, the drain end of the first PMOS transistor is connected with the source end of the second PMOS transistor, and the grid end of the first PMOS transistor is connected with the output unit; the source end of the second PMOS transistor is connected with the source end of the first PMOS transistor, the drain end of the second PMOS transistor is connected with the drain end of the seventh NMOS transistor and connected with the output end of the fourth ping-pong processing unit, and the gate end of the second PMOS transistor is connected with the selection signal output by the output unit; the drain end of the seventh NMOS transistor is connected with the drain end of the second PMOS transistor, the source end of the seventh NMOS transistor is connected with the drain end of the eighth NMOS transistor and is connected with the output end of the fourth ping-pong processing unit, and the gate end of the seventh NMOS transistor is connected with the reverse signal of the selection signal output by the output unit; the drain end of the eighth NMOS transistor is connected with the source end of the seventh NMOS transistor, the source end of the eighth NMOS transistor is grounded, and the gate end of the eighth NMOS transistor is connected with the output unit; the source end of the third PMOS transistor is connected with a power supply, the drain end of the third PMOS transistor is connected with the source end of the fourth PMOS transistor, and the grid end of the third PMOS transistor is connected with the output unit; the source end of the fourth PMOS transistor is connected with the drain end of the third PMOS transistor, the drain end of the fourth PMOS transistor is connected with the drain end of the ninth NMOS transistor, the drain end of the ninth NMOS transistor is connected with the output end of the fourth ping-pong processing unit and is connected with the drain end of the second PMOS transistor, and the gate end of the ninth NMOS transistor is connected with the reverse signal of the selection signal output by the output unit; the drain end of the ninth NMOS transistor is connected with the drain end of the fourth PMOS transistor, connected with the output end of the fourth ping-pong processing unit in parallel and connected with the drain end of the second PMOS transistor, the source end of the ninth NMOS transistor is connected with the drain end of the tenth NMOS transistor, and the gate end of the ninth NMOS transistor is connected with the selection signal output by the output unit; and the drain end of the tenth NMOS transistor is connected with the source end of the ninth NMOS transistor, the drain end of the tenth NMOS transistor is grounded, and the gate end of the tenth NMOS transistor is connected with the output unit.

In addition, the apparatus for converting a parallel digital signal into a serial TMDS signal according to an embodiment of the present invention further includes a phase-locked loop (not shown in the figure). The phase-locked loop is used for generating a signal with a duty ratio of 1:1, which is a half-speed clock (e.g., a clock having a frequency of 1.7 GHz) in order to achieve a data rate of 3.4 Gbps. On the basis of a reference clock generated by a phase-locked loop, a frequency divider divides the reference clock to generate two clocks having a fixed phase relationship: a first clock and a second clock. The first clock has the same function as the first clock in the above-mentioned embodiment, and is used for sampling the even-numbered parallel signal and the odd-numbered parallel signal in the parallel digital signals, and the second clock is used for reading the parallel digital signals from the first-in first-out circuit, and the phase relationship between the first clock and the second clock may be determined according to actual requirements, and is not limited herein.

To describe the structure and function of the apparatus for converting a parallel digital signal into a serial TMDS signal according to an embodiment of the present invention in more detail, the structure and function of the apparatus will be described in detail with reference to a specific embodiment. However, the following description is only one example of an apparatus for converting a parallel digital signal into a serial TMDS signal according to an embodiment of the present invention, and the following description is only for explaining technical aspects of the embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an apparatus for converting a parallel digital signal into a serial TMDS signal according to an embodiment of the present invention, the apparatus comprising the following structures:

the device specifically includes: a phase locked loop 301, a first in first out circuit 302, a sampling shift register 303, a first data ping-pong device 304, a second data ping-pong device 305, a third data ping-pong device 306, a one-byte delay 307, a two-byte delay 308, and TMDS drivers 309, 310, and 311. The sampling shift register 302 comprises a five-frequency divider 3031, an even serializer 3032, an odd serializer 3033 and a delayer 3034; the first data ping-pong device 304 includes single-ended to differential flip-flops 3041 and 3042, balanced data selectors 3043 and 3044; the second data ping-pong device 305 includes single-ended to differential flip-flops 3051 and 3052, equalizing data selectors 3053 and 3054; the third data ping-pong 306 includes single ended to differential flip-flops 3061 and 3062, equalization data selectors 3063 and 3064. In addition, the driving ratio of the second data ping-pong device 305 is smaller than that of the first data ping-pong device 304 and larger than that of the third data ping-pong device 306. When the distance over which the signal needs to be transmitted is short or the signal attenuation is light, only the first data ping-pong device 304 (as shown in fig. 4 a) may be used; if the distance over which the signal needs to be transmitted is long or the signal attenuation is severe, a first data ping-pong device 304 and a second data ping-pong device 305 (as shown in fig. 4 b) can be adopted; if the signal needs to be transmitted over a long distance and the high frequency attenuation is severe, the first data ping-pong device 304, the second data ping-pong device 305 and the third data ping-pong device 306 (shown in fig. 3) can be used simultaneously. The TMDS drivers 309, 310, and 311 have the same structure but different sizes, with the largest driver 309 and the smallest driver 311, and the driver 310 being between the drivers 309 and 311, all three being programmable to control the output current. In addition, the apparatus for converting a parallel digital signal into a serial TMDS signal in this embodiment may further include an external transmission line 312 and a termination impedance 313 of a downstream chip to finally obtain a serial TMDS signal satisfying a predetermined requirement.

The phase locked loop 301 generates a reference clock, which is a half-speed clock having a duty ratio of 1:1, and a ratio between a high level and a low level of the reference clock is 1:1 in order to finally achieve a data rate of 3.4 Gbps.

The divider 3031 generates a first clock for sampling the even-numbered bit parallel signal and the odd-numbered bit parallel signal of the parallel digital signals from the fifo 302, a second clock for reading the parallel digital signals from the fifo 302, and the first clock and the second clock have a fixed phase relationship. The phase relationship between the reference clock generated by the phase locked loop 301 and the first and second clocks generated by the divider 3031 is shown with reference to fig. 5.

Then, the reference clock writes the even-numbered digital signal and the first type of signal into the data ping-pong 304, the data ping-pong 304 performs data ping-pong processing on the even-numbered digital signal and the first type of signal, and finally the reference clock outputs the differential digital signal obtained after the ping-pong processing from the data ping-pong 304 to the TMDS driver 309, so as to finally realize the serial TMDS signal.

In addition, the even-numbered digital signals and the first column signals may also be pre-emphasized using a one-byte delay 307 and/or a two-byte delay 308 before outputting the even-numbered digital signals and the first type signals to the TMDS driver 309. For example, an even-bit digital signal is delayed by one byte and an odd-bit digital signal delayed by one byte is delayed by one byte; and/or delaying the even-bit digital signal by two bytes and delaying the odd-bit digital signal by one byte later by two bytes. Fig. 6 shows the result after pre-emphasis processing of the even-bit serial signal and the first type of signal: the uppermost curve (a) is one-stage pre-emphasis, and the middle curve (b) and the lower curve (c) correspond to the settings of the positive phase and the negative phase of the two-stage pre-emphasis, respectively, where the one-stage pre-emphasis refers to delaying the even-bit serial signal and the first-type signal by only one byte and employing the drivers 309 and 310, and the two-stage pre-emphasis refers to delaying the even-bit serial signal and the first-type signal by two bytes and employing the drivers 309, 310, and 311 at the same time. The curve (a) of the first-stage pre-emphasis is in positive phase, the curve (b) of the second-stage pre-emphasis is in negative phase, and the curve (c) of the second-stage pre-emphasis is in positive phase and negative phase, and is adjusted according to different output transmission lines. Namely, curve (a) is a waveform obtained by using only the driving circuit and employing one-stage pre-emphasis, curve (b) is a waveform obtained by using the driving circuit and employing two-stage pre-emphasis and the 2 nd-stage pre-emphasis is a positive phase, curve (c) is a waveform obtained by using the driving circuit and employing two-stage pre-emphasis and the 2 nd-stage pre-emphasis is an inverted phase, wherein a dotted line in curve (b) and curve (c) is a waveform when pre-emphasis is not employed, and a solid line is a waveform when one-stage or two-stage pre-emphasis is employed.

There are various driving methods in the embodiments of the present invention, and fig. 7 shows a circuit structure diagram of a driving circuit commonly used in the prior art, where a, b, and c are a level shifter, a pre-driving circuit, and a driving circuit, respectively. The driving method using this structure has many disadvantages. For example, the conversion speed is limited by adopting a level shifter to convert a parallel digital signal into a differential signal of a level usable by a lower-stage circuit, the pre-driving circuit needs to adjust the output amplitude and common-mode level according to the requirements of the driving circuit, static current exists, and the power consumption is large.

In order to further increase the signal conversion speed and reduce the power consumption, an embodiment of the present invention further provides a driver with a specific structure, and fig. 8 shows a circuit structure diagram of the driver, where the driver includes a pre-driver circuit, a driver circuit, and a bias circuit. Wherein the pre-driver circuit consists of four inverters (shown in the left dashed box a). The driving circuit comprises four NMOS transistors M1, M2, M3 and M4, wherein a drain terminal of a first NMOS transistor M1 and a drain terminal of a third NMOS transistor M3 are connected with an output interface, a gate terminal of the first NMOS transistor M1 is connected with a gate terminal of the third NMOS transistor M3, a source terminal of the first NMOS transistor M1 is connected with a drain terminal of a second NMOS transistor M2 and connected with a power supply in parallel, a source terminal of the second NMOS transistor M2 is connected with the ground, a gate terminal of the second NMOS transistor M2 is connected with an output terminal of the pre-driving circuit, a source terminal of the third NMOS transistor M3 is connected with a drain terminal of the fourth NMOS transistor M4 and connected with the power supply in parallel, and a source terminal of the fourth NMOS transistor M4 is connected with the ground, and a gate terminal of the other output terminal. The bias circuit comprises two NMOS transistors M5 and M6, a drain terminal of a fifth NMOS transistor M5 is connected with the digital-to-analog converter, a gate terminal of the fifth NMOS transistor M3526 is connected with a gate terminal of the third NMOS transistor M3, a source terminal of the fifth NMOS transistor M3526 is connected with a drain terminal of the sixth NMOS transistor M6, a drain terminal of the sixth NMOS transistor M6 is connected with a gate terminal of the sixth NMOS transistor M6, a source terminal of the sixth NMOS transistor M6 is connected with the ground, and. The power supply connected to the source terminal of the first NMOS transistor M1 and the drain terminal of the second NMOS transistor M2 is a small current source, and the power supply connected to the source terminal of the third NMOS transistor M3 and the drain terminal of the fourth NMOS transistor M4 is also a small current source, and the two small current sources are used to ensure that the first NMOS transistor M1 and the third NMOS transistor are not completely turned off, so as to reduce the time for turning on the driver.

In the circuit structure of the driver, the upper first NMOS transistor M1 and the third NMOS transistor M3 are respectively used for isolating the lower second NMOS transistor M2 and the lower fourth NMOS transistor M4, and generate appropriate current corresponding to the bias circuit formed by the fifth NMOS transistor M5 and the sixth NMOS transistor M6, and the size of the bias circuit can be controlled by a digital-to-analog converter, so that the magnitude of the output amplitude can be precisely controlled in a programmable manner. In addition, the first NMOS transistor M1 and the third NMOS transistor M3 may adopt a NMOS33 transistor, the second NMOS transistor M2 and the fourth NMOS transistor M4 may adopt a NMOS18 transistor, wherein the NMOS33 is a MOS transistor with a voltage of 3.3V, the NMOS18 transistor may be a transistor with a voltage of 1.8V or a transistor with a voltage of 1.2V or lower, and the NMOS18 functions as a switch. The TMDS driver does not need to be provided with a special pre-driving circuit, the function of the traditional pre-driving circuit can be realized only by using a common inverter, and the NMOS18 is much smaller than the NMOS33 as a switch, so that the inverter of the pre-driving circuit does not need to be large, and the power consumption of the driver is much smaller compared with the power consumption of the driver.

Compared with the driver in the prior art, the driver circuit shown in fig. 8 has a simple structure and relatively low power consumption.

In this particular embodiment, the equalization data selector comprises (as shown in fig. 9 a): a first PMOS transistor M7, a second PMOS transistor M8, a seventh NMOS transistor M9, an eighth NMOS transistor M10, a third PMOS transistor M11, a fourth PMOS transistor M12, a ninth NMOS transistor M13, and a tenth NMOS transistor M14; wherein,

the source end of the first PMOS transistor M7 is connected with a power supply, the drain end is connected with the source end of the second PMOS transistor M8, and the grid end is connected with the single-end-to-differential trigger; a second PMOS transistor M8, the source terminal of which is connected to the drain terminal of the first PMOS transistor M7, the drain terminal of which is connected to the drain terminal of the seventh NMOS transistor M9 and is connected to the output terminal of the balanced data selector, and the gate terminal of which is connected to the selection signal of the single-terminal-to-differential flip-flop; the drain terminal of the seventh NMOS transistor M9 is connected to the drain terminal of the second PMOS transistor M8 and connected to the output terminal of the equalizing data selector, the source terminal is connected to the drain terminal of the eighth NMOS transistor M10, and the gate terminal is connected to SN; the drain terminal of the eighth NMOS transistor M10 is connected to the source terminal of the seventh NMOS transistor M9, the source terminal is grounded, and the gate terminal is connected to the single-end-to-differential flip-flop; the source end of the third PMOS transistor M11 is connected with the power supply, the drain end is connected with the source end of the fourth PMOS transistor M12, and the grid end is connected with the single-end-to-differential trigger; the source end of the fourth PMOS transistor M12 is connected to the drain end of the third PMOS transistor M11, the drain end is connected to the drain end of the ninth NMOS transistor M13, and the drain end is connected to the output end of the balanced data selector and the drain end of the second PMOS transistor M8, and the gate end is connected to the inverted signal of the selection signal of the single-end-to-differential flip-flop; a drain terminal of the ninth NMOS transistor M13 is connected to a drain terminal of the fourth PMOS transistor M12 and to a drain terminal of the second PMOS transistor M8, a source terminal is connected to a drain terminal of the tenth NMOS transistor M14, and a gate terminal is connected to a selection signal of the single-terminal-to-differential flip-flop; the drain terminal of the tenth NMOS transistor M14 is connected to the source terminal of the ninth NMOS transistor M13, the drain terminal is grounded, and the gate terminal is connected to the single-terminal-to-differential flip-flop.

In other embodiments, the equalization data selector may also adopt a structure as shown in fig. 9b, and of course, may also adopt other structures to implement, which are not described herein again.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method of converting a parallel digital signal to a serial TMDS signal, comprising:

converting the differential digital signal to a serial TMDS signal;

wherein, when the even-numbered serial signals and the first-class signals are subjected to ping-pong processing to obtain differential digital signals, the method further comprises:

performing ping-pong processing on the second type of signal and the third type of signal to obtain a fourth type of signal

2. The method of claim 1, wherein converting the differential digital signal to a serial TMDS signal comprises:

performing pre-drive processing on the differential digital signal;

3. The method of claim 1, wherein before sampling the even-bit parallel signal and the odd-bit parallel signal of the parallel digital signals respectively with the first clock, the method further comprises:

and performing first-in first-out processing on the parallel digital signals.

4. The method of claim 1, wherein ping-pong processing the even-bit serial signal and the first type of signal to obtain a differential digital signal comprises:

5. An apparatus for converting a parallel digital signal to a serial TMDS signal, comprising:

the second ping-pong processing unit is used for performing ping-pong processing on the second type of signals and the third type of signals to obtain fourth type of signals;

the third ping-pong processing unit is used for performing ping-pong processing on the fifth type signal and the sixth type signal to obtain a seventh type signal;

6. The apparatus of claim 5, wherein the conversion unit comprises:

7. The apparatus of claim 5, wherein the conversion unit comprises a pre-driver circuit, a driver circuit, and a bias circuit; wherein,

the pre-driving circuit consists of four inverters;

the driving circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor, wherein the drain terminal of the first NMOS transistor and the drain terminal of the third NMOS transistor are connected with the output end of the conversion unit, the gate terminal of the first NMOS transistor is connected with the gate terminal of the third NMOS transistor, the source terminal of the first NMOS transistor is connected with the drain terminal of the second NMOS transistor and connected with a power supply in parallel, the source terminal of the second NMOS transistor is grounded, the gate terminal of the second NMOS transistor is connected with the pre-driving circuit, the source terminal of the third NMOS transistor is connected with the drain terminal of the fourth NMOS transistor and connected with the power supply in parallel, and the source terminal of the fourth NMOS transistor is grounded, and the gate terminal of the fourth NMOS transistor is grounded;

8. The apparatus of claim 5, further comprising:

9. The apparatus of claim 5, wherein the first ping-pong processing unit comprises:

10. The apparatus of claim 9, wherein the fourth ping-pong processing unit comprises first, second, third and fourth PMOS transistors and seventh, eighth, ninth and tenth NMOS transistors; wherein,