TWI842381B - Light-emitting diode display system - Google Patents

Abstract

A light-emitting diode (LED) display system is disclosed. The LED display system includes: a plurality of LED driving circuits, wherein each LED driving circuit is respectively coupled and drives a plurality of LEDs to emit light; a first wire, for transmitting a data signal to the plurality of LED driving circuits in a serial connecting or multi-drop way; and a second wire, for transmitting a latch enabling signal embedded with a first clock signal to the plurality of LED driving circuits in the multi-drop way.

Description

LED Display System

The present invention relates to a light emitting diode, and in particular to a light emitting diode display system.

As shown in FIG1 , a conventional LED display system 1 includes LED driver circuits IC1 to IC10, a series line WS, and common lines WP1 to WP2. Each LED driver circuit IC1 to IC10 is coupled to a plurality of LEDs. The series line WS sequentially transmits a data signal SDI_0 to the LED driver circuits IC1 to IC10 in series. The common line WP1 transmits an external clock signal DCLK to the LED driver circuits IC1 to IC10 in parallel. The common line WP2 transmits a latch enable signal LE to the LED driver circuits IC1 to IC10 in parallel. The LED driver circuits IC1~IC10 respectively generate a plurality of pulse width modulation signals PWMs to drive the plurality of LEDs coupled thereto to emit light. Please refer to FIG2 for the timing diagram of the latch enable signal LE, the data signal SDI_0 and the external clock signal DCLK in FIG1.

However, the conventional LED display system 1 needs to include at least one series wire WS and two common wires WP1-WP2 to operate normally, that is, the number of wires cannot be reduced, resulting in the area and cost cannot be reduced, and needs to be improved.

Therefore, the present invention proposes a light-emitting diode display system to effectively solve the above problems encountered by the prior art.

A preferred specific embodiment of the present invention is a light-emitting diode display system. In this embodiment, the light-emitting diode display system includes a plurality of light-emitting diode driving circuits, a first connection and a second connection. Each light-emitting diode driving circuit is respectively coupled to and drives a plurality of light-emitting diodes to emit light. The first connection transmits a data signal to the plurality of light-emitting diode driving circuits in series or in parallel. The second connection transmits a latch enable signal embedded with a first clock signal to the plurality of light-emitting diode driving circuits in parallel.

In one embodiment, each LED driving circuit includes a clock data recovery circuit. The clock data recovery circuit is coupled to the second line to receive a latch enable signal embedded with the first clock signal and output the first clock signal and the latch enable signal respectively.

In one embodiment, each LED driving circuit further includes a phase-locked loop. The phase-locked loop is coupled to the clock data recovery circuit to generate a second clock signal according to the first clock signal.

In one embodiment, the first clock signal is an external clock signal and the second clock signal is an internal clock signal with adjustable frequency.

In one embodiment, each LED driving circuit generates a pulse width modulation signal according to the second clock signal and drives the plurality of LEDs to emit light according to the pulse width modulation signal.

In one embodiment, each LED driving circuit includes a clock data recovery circuit. The clock data recovery circuit is coupled to the second line and is used to receive a latch enable signal embedded with a first clock signal and output the first clock signal.

In one embodiment, each LED driving circuit further includes a phase-locked loop. The phase-locked loop is coupled to the clock data recovery circuit to generate a second clock signal according to the first clock signal.

In one embodiment, the first clock signal is an external clock signal and the second clock signal is an internal clock signal with adjustable frequency.

In one embodiment, each LED driving circuit generates a pulse width modulation signal according to the second clock signal and drives the plurality of LEDs to emit light according to the pulse width modulation signal.

In one embodiment, the lock enable signal embedded with the first clock signal further includes a plurality of instructions.

In one embodiment, the first clock signal includes a plurality of pulses, and the plurality of pulses and the plurality of commands are interlaced and appear at different times.

Compared with the prior art, the LED display system of the present invention embeds an external clock signal into a lock enable signal and transmits it to each LED driver circuit in parallel. The phase-locked loop in each LED driver circuit then generates an internal clock signal with an adjustable frequency according to the external clock signal and generates a corresponding pulse width modulation signal to drive the LED to emit light. Therefore, multiple effects such as adjusting the LED brightness, reducing the number of wiring, and reducing the area and cost can be achieved at the same time.

A preferred embodiment of the present invention is a light emitting diode (LED) display system. In this embodiment, the LED display system only needs a first wire (serial wire or common wire) for transmitting a data signal and a second wire (common wire) for transmitting a latch enable signal embedded with an external clock signal, thereby achieving the specific effect of reducing the number of wires while being able to adjust the LED brightness.

Please refer to FIG. 3 , which shows a schematic diagram of the LED display system in this embodiment. As shown in FIG. 3 , the LED display system 3 includes LED driver circuits IC1 to IC10, a series wire (first wire) WS, and a common wire (second wire) WP. Each LED driver circuit IC1 to IC10 is coupled to a plurality of LEDs LEDs. The series wire WS sequentially transmits the data signal SDI_0 to the LED driver circuits IC1 to IC10 in a series manner. The common wire WP transmits the latch enable signal LE embedded with the external clock signal DCLK to the LED driver circuits IC1 to IC10 in a parallel manner. Each of the light-emitting diode driving circuits IC1~IC10 generates a plurality of pulse width modulation signals PWMs to drive the plurality of light-emitting diodes LEDs coupled thereto to emit light.

It should be noted that, although the LED display system 3 in FIG. 3 includes a single row of LED driver circuits IC1 to IC10, in practice, the LED display system may also include a plurality of rows of LED driver circuits, as shown in the following embodiment.

As shown in FIG4 , the LED display system 4 includes LED driver circuits IC1 to IC20, series wiring (first wiring) WS1 to WS2 and common wiring (second wiring) WP1 to WP2. Among them, the LED driver circuits IC1 to IC10 are the first row of LED driver circuits and the LED driver circuits IC11 to IC20 are the second row of LED driver circuits.

The serial line WS1 sequentially transmits the data signal SDI_0 to the first row of LED driver circuits IC1~IC10 in serial connection. The common line WP1 sequentially transmits the latch enable signal LE embedded with the external clock signal DCLK to the first row of LED driver circuits IC1~IC10 in parallel connection. Similarly, the serial line WS2 sequentially transmits the data signal SDI_1 to the second row of LED driver circuits IC11~IC20 in serial connection. The common line WP2 sequentially transmits the latch enable signal LE embedded with the external clock signal DCLK to the second row of LED driver circuits IC11~IC20 in parallel connection. Each of the light-emitting diode driving circuits IC1~IC20 generates a plurality of pulse width modulation signals PWMs to drive the plurality of light-emitting diodes LEDs coupled thereto to emit light.

Please refer to FIG. 5 , which shows a schematic diagram of a light-emitting diode display system in another preferred specific embodiment of the present invention. As shown in FIG. 5 , the light-emitting diode display system 5 includes light-emitting diode driver circuits IC1 to IC10, a common wiring (first wiring) WP1, and a common wiring (second wiring) WP2. Each light-emitting diode driver circuit IC1 to IC10 is respectively coupled to a plurality of light-emitting diode LEDs. The common wiring WP1 transmits a latch enable signal LE embedded with an external clock signal DCLK to the light-emitting diode driver circuits IC1 to IC10 in a parallel manner. The common wiring WP2 transmits a data signal SDI_0 to the light-emitting diode driver circuits IC1 to IC10 in a parallel manner. Each of the light-emitting diode driving circuits IC1~IC10 generates a plurality of pulse width modulation signals PWMs to drive the plurality of light-emitting diodes LEDs coupled thereto to emit light.

Please refer to FIG6, which shows the timing diagram of the latch enable signal LE and the data signal SDI_0 embedded with the external clock signal DCLK. As shown in FIG6, the data signal SDI_0 sequentially transmitted to the LED driver circuits IC1~IC10 by the serial line WS in a serial manner may include red data R0~R15, green data G0~G15 and blue data B0~B15 in time sequence, but is not limited thereto.

The latch enable signal LE embedded with the external clock signal DCLK and transmitted to the light-emitting diode driving circuit IC1~IC10 by the common line WP in parallel may include pulse P1, instruction CMD1, pulse P2, instruction CMD2, pulse P3, instruction CMD3, pulse P4 and instruction CMD4 in time sequence, wherein the external clock signal DCLK includes pulses P1~P4, and the pulses P1~P4 and instructions CMD1~CMD4 appear at different times staggered with each other, but not limited to this.

In fact, there is no specific restriction on the duration of the pulse P1, instruction CMD1, pulse P2, instruction CMD2, pulse P3, instruction CMD3, pulse P4 and instruction CMD4 included in the lock enable signal LE, and they can be adjusted according to actual needs.

Please refer to FIG. 7, which shows a schematic diagram of an embodiment of the LED driving circuit IC1. As shown in FIG. 5, the LED driving circuit IC1 includes a clock data recovery circuit CDR, a phase-locked loop PLL and a pulse width modulation signal generating circuit PG. The clock data recovery circuit CDR is coupled between the common line WP and the pulse width modulation signal generating circuit PG. The phase-locked loop PLL is coupled between the clock data recovery circuit CDR and the pulse width modulation signal generating circuit PG. The pulse width modulation signal generating circuit PG is respectively coupled to the series line WS, the clock data recovery circuit CDR, the phase-locked loop PLL and a plurality of light-emitting diodes LEDs.

The data signal SDI_0 transmitted to the LED driver circuit IC1 by the serial line WS is directly transmitted to the pulse width modulation signal generation circuit PG. The clock data recovery circuit CDR receives the latch enable signal LE embedded with the external clock signal DCLK from the common line WP and outputs the latch enable signal LE and the external clock signal DCLK respectively. The phase-locked loop PLL receives the external clock signal DCLK from the clock data recovery circuit CDR and generates an internal clock signal GCLK with an adjustable frequency to the pulse width modulation signal generation circuit PG accordingly. In this embodiment, the phase-locked loop PLL generates a higher frequency internal clock signal GCLK according to a lower frequency external clock signal DCLK, but the present invention is not limited thereto.

The pulse width modulation signal generating circuit PG receives the data signal SDI_0, the latch enable signal LE, the external clock signal DCLK and the internal clock signal GCLK with adjustable frequency respectively and outputs a plurality of pulse width modulation signals PWMs to the plurality of light emitting diodes LEDs respectively to drive the plurality of light emitting diodes LEDs to emit light.

In practice, the pulse width modulation signal generating circuit PG generates the plurality of pulse width modulation signals PWMs according to the internal clock signal GCLK with adjustable frequency, so as to correspondingly adjust the luminous brightness of the plurality of light emitting diodes LEDs, but the present invention is not limited thereto.

Please refer to FIG8 , which shows a schematic diagram of another embodiment of the LED driver circuit IC1. As shown in FIG8 , the LED driver circuit IC1 includes a clock data recovery circuit CDR, a phase-locked loop PLL, and a pulse width modulation signal generating circuit PG. The clock data recovery circuit CDR is coupled between the common line WP and the pulse width modulation signal generating circuit PG. The phase-locked loop PLL is coupled between the clock data recovery circuit CDR and the pulse width modulation signal generating circuit PG. The pulse width modulation signal generating circuit PG is respectively coupled to the series line WS, the common line WP, the clock data recovery circuit CDR, the phase-locked loop PLL, and a plurality of light-emitting diodes LEDs.

The data signal SDI_0 transmitted from the serial line WS to the LED driver circuit IC1 is directly transmitted to the pulse width modulation signal generating circuit PG. The latch enable signal LE embedded with the external clock signal DCLK transmitted from the common line WP to the LED driver circuit IC1 is directly transmitted to the pulse width modulation signal generating circuit PG. The clock data recovery circuit CDR receives the latch enable signal LE embedded with the external clock signal DCLK from the common line WP and analyzes the external clock signal DCLK and then outputs the external clock signal DCLK. The phase-locked loop PLL receives the external clock signal DCLK from the clock data recovery circuit CDR and generates an internal clock signal GCLK with adjustable frequency to the pulse width modulation signal generation circuit PG. In this embodiment, the phase-locked loop PLL generates a higher frequency internal clock signal GCLK according to the lower frequency external clock signal DCLK, but is not limited thereto.

The pulse width modulation signal generating circuit PG receives the data signal SDI_0, the latch enable signal LE embedded with the external clock signal DCLK, the external clock signal DCLK and the internal clock signal GCLK with adjustable frequency respectively, and outputs a plurality of pulse width modulation signals PWMs to the plurality of light-emitting diodes LEDs respectively to drive the plurality of light-emitting diodes LEDs to emit light respectively.

In practice, the pulse width modulation signal generating circuit PG generates the plurality of pulse width modulation signals PWMs according to the internal clock signal GCLK with adjustable frequency, so as to correspondingly adjust the luminous brightness of the plurality of light emitting diodes LEDs, but the present invention is not limited thereto.

Compared with the prior art, the LED display system of the present invention embeds an external clock signal into a latch enable signal and transmits it to each LED driver circuit in parallel. The phase-locked loop in each LED driver circuit then generates an internal clock signal with an adjustable frequency according to the external clock signal and generates a corresponding pulse width modulation signal to drive the LED to emit light. Therefore, multiple effects such as adjusting the LED brightness, reducing the number of wiring, and reducing the area and cost can be achieved at the same time.

1, 3, 4, 5…LED display system IC1~IC20…LED driver circuit WP, WP1, WP2…Common wiring WS, WS1, WS2…Serial wiring LE…Lock enable signal DCLK…External clock signal SDI_0, SDI_1…Data signal LEDs…Multiple LEDs PWMs…Multiple pulse width modulation signals R0~R15…Red data G0~G15…Green data B0~B15…Blue data P1~P4…Pulse CMD1~CMD4…Command CDR…Clock data recovery circuit PLL…Phase-locked loop PG…Pulse width modulation signal generation circuit GCLK…Internal clock signal with adjustable frequency

FIG. 1 is a schematic diagram of a conventional LED display system.

FIG. 2 shows the timing diagrams of the latch enable signal, the data signal, and the external clock signal in FIG. 1 , respectively.

FIG. 3 is a schematic diagram of a light-emitting diode display system in a preferred embodiment of the present invention.

FIG. 4 is a schematic diagram showing a light emitting diode display system including a plurality of rows of LED driving circuits.

FIG. 5 is a schematic diagram of a light-emitting diode display system in another preferred embodiment of the present invention.

FIG. 6 shows the timing diagram of the latch enable signal and the data signal respectively with the external clock signal embedded therein.

FIG. 7 and FIG. 8 are schematic diagrams showing different embodiments of the LED driving circuit.

3…LED display system IC1~IC10…LED driver circuit WP…Common wiring WS…Serial wiring LE…Latch enable signal DCLK…External clock signal SDI_0…Data signal LEDs…Multiple LEDs PWMs…Multiple pulse width modulation signals

Claims (10)

A light-emitting diode display system includes: a plurality of light-emitting diode driving circuits, each of which is respectively coupled to and drives a plurality of light-emitting diodes to emit light; a first connection, which transmits a data signal to the plurality of light-emitting diode driving circuits in series or parallel; and a second connection, which transmits a latch enable signal embedded with a first clock signal to the plurality of light-emitting diode driving circuits in parallel; wherein each light-emitting diode driving circuit includes: a clock data recovery circuit, coupled to the second connection, for receiving the latch enable signal embedded with the first clock signal and outputting the first clock signal. The LED display system as described in claim 1, wherein the clock data recovery circuit also outputs the latch enable signal. The LED display system as described in claim 2, wherein each LED driving circuit further includes: a phase-locked loop coupled to the clock data recovery circuit to generate a second clock signal according to the first clock signal. A light-emitting diode display system as described in claim 3, wherein the first clock signal is an external clock signal and the second clock signal is an internal clock signal with adjustable frequency. A light-emitting diode display system as described in claim 3, wherein each light-emitting diode driving circuit generates a pulse width modulation signal according to the second clock signal and drives the plurality of light-emitting diodes to emit light according to the pulse width modulation signal. The LED display system as described in claim 1, wherein each LED driving circuit further includes: a phase-locked loop coupled to the clock data recovery circuit to generate a second clock signal according to the first clock signal. A light-emitting diode display system as described in claim 6, wherein the first clock signal is an external clock signal and the second clock signal is an internal clock signal with adjustable frequency. A light-emitting diode display system as described in claim 6, wherein each light-emitting diode driving circuit generates a pulse width modulation signal according to the second clock signal and drives the plurality of light-emitting diodes to emit light according to the pulse width modulation signal. The LED display system as described in claim 1, wherein the lock enable signal embedded with the first clock signal also includes a plurality of instructions. The LED display system as described in claim 9, wherein the first clock signal includes a plurality of pulses and the plurality of pulses and the plurality of instructions are interlaced and appear at different times.

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