JP2007533168A - Parallel pulse code modulation system and method - Google Patents

Abstract

The present invention provides a parallel pulse code modulation system that allows independent control of multiple groups of one or more electronic devices. The system includes a memory unit configured to be able to write and read control data to receive control data from an external source. The system further includes a multiplexer connected to the memory unit for receiving control data from the memory unit and organizing the control data into a serial data stream including data groups. A shift register connected to the multiplexer receives the serial data stream from the multiplexer and converts each data group to a parallel data stream output. Each parallel data stream output refers to a specific group of control parameters consisting of one or more electronic devices. A latch connected to a plurality of groups of shift registers and one or more electronic devices receives a respective parallel data stream output, and a specific parallel data stream output to a specific group of one or more electronic devices To send. This provides independent control over a plurality of groups of one or more electronic devices. The logic sequencer incorporated in the system controls its operation and timing by providing sequence and timing signals to the memory unit, multiplexer, shift register and latch.

Description

  The present invention particularly relates to an apparatus and a method for controlling a plurality of light-emitting elements individually or as a group of several elements.

  Recent developments in the development of semiconductor light-emitting diodes (LEDs) and organic light-emitting diodes (OLEDs) have made these solid elements suitable for use in general lighting devices such as, for example, architectural, entertainment and road lighting. . As such, these elements have become increasingly competitive with light sources such as incandescent lamps, fluorescent lamps and powerful discharge lamps.

  The advantage of LEDs is that turn-on and turn-off times are typically less than 100 nanoseconds. Therefore, the average illumination intensity of the LED is such that the time-averaged illumination intensity is linearly proportional to the PWM duty ratio illustrated in FIG. 1 as three types: 25%, 50% and 100%. It can be controlled by performing pulse width modulation (PWM) of the LED drive current using a current power supply. This technique is disclosed in U.S. Pat. No. 4,090,189, and a study of monochromatic LEDs is described in “Optoelectronics Applications Manual” 1977 Gage, S .; , M.M. Modapp, D.M. Evans and H.C. By Sorenson, New York, NY, McGraw-HillBookCompany.

  W. Howell's web document “A Brief History of LED Lighting”, Middelsex, UK: Artistic License Inc. , 2002, J. J. Laidman has developed a product using a PWM-based controller for multiple single color LEDs for a company called SoundChamber. A PWM based control method and apparatus using a plurality of similar single color LEDs was subsequently disclosed in US Pat. No. 4,845,481. According to these inventions, an essentially infinite variety of colors can be obtained by optically mixing single colors of different illumination intensities.

  Today, PWM provides a linear control range of 1000 to 1 (1000: 1) or higher without the negative effects of power loss of current limiting resistors, uneven illumination intensity of LED arrays and appreciable color shifts. Therefore, it is typically the preferred method for controlling the illumination intensity of LEDs (Zukauskas, A., MS Schur and R. Caska, 2002, Introduction to Sold-State Lighting. New York, NY: Wiley-Interscience, page 136). The PWM signal used for control is preferably generated by a microcontroller and associated peripherals.

  However, there are some implementation difficulties in realizing the PWM control signal in hardware. For example, most microcontrollers provide 1 to 4 PWM channels on-chip, which must control the illumination intensity for each color. For example, it is suitable for a light source device using a combination of three-color or four-color LEDs such as red, green, blue, and possibly amber. However, in some applications, more PWM channels may be required to control each LED or group of LEDs.

  One application that requires this type of control is a lighting device in which individual LEDs are directly visible. In the current LED manufacturing process, individual manufactured LEDs vary in illumination intensity over a wide range even with the same constant value of driving current. LED manufacturers are addressing this problem by aligning similar performance characteristics of LEDs, including “binning” or illumination intensity. However, within a bin that is considered to have the same performance, the illumination intensity typically varies by 30% (eg, Lumileds Lighting, 2002, Application Brif AB22-Luxeon Product Binning and Labeling, San Jose). , CA; Lumileds Lighting, LLC). In applications where visibility is important, the luminaire manufacturer will require the selection of LEDs of uniform intensity within a single segment. Alternatively, the lighting device manufacturer can use PWM technology to control the intensity of each LED independently, in which case one independent PWM channel is used for each LED or group of LEDs. In order to be necessary.

  Another application is cove lighting in a building where a row of closely spaced LEDs illuminates a wall near the ceiling. The length of such a row can be several meters to tens of meters. Although these LEDs control the illumination intensity individually or in groups, it is economically advantageous to minimize the number of interprocessor communication hardware associated with the microcontroller.

  Yet another application that requires control of individual LEDs or groups of LEDs is such that a plurality of single color LEDs are arranged in a straight line or geometric pattern, and the illumination intensity and / or color pattern varies. This is a case where each LED or LED group dynamically changes the illumination intensity. Such applications may include an amusement lighting system referred to as “marque writing” or “chase lighting”.

  Individual PWM control integrated circuits (ICs) are commercially available for such applications up to 48 independent channels communicating with the microcontroller. Examples of these IC, LE71D1048PWM controller (Logic Device Technology, 2003, LE71D1048-48Output LED Driver / 10 Bit PWM Controller (Product data sheet)), and SL70D0948PWM controller (System Logic Semiconductor SL70D0948-48Output LED Driver / 9BitPWMController, (Product data sheet)). In addition, a custom PWM controller can be configured using, for example, a programmable integrated circuit (FPGA) or an application specific integrated circuit (ASIC) when manufactured in large quantities.

  However, these devices have two common problems. First, it becomes a physically large device with a maximum of 128 pins, and it is difficult to wire the PWM signal to the LED driver other than solving with an expensive multilayer printed circuit board, for example. And secondly, the device generally has limited heat spreading capability, which requires an additional PWM channel-like circuit driver when positioning the LED away from the PWM controller. It may be.

  As an example, the PWM control signal can be configured by firmware using a general-purpose microcontroller. However, in order to avoid visible flicker being included in the illumination by the LED, the PWM signal frequency should usually be at least 100 Hz, preferably higher. As such, the requirement is to provide one or more channels on a microcontroller (usually with a 20 MHz clock CPU) without having to provide a special hardware timer for each channel. Is unrealistic.

  Therefore, there is a clearly identifiable need for a simple hardware circuit that can generate multiple control signals without requiring an expensive multilayer circuit board to direct control signals to the LED driver.

  In the field of voice and data communication, a well known alternative to PWM is pulse code modulation (PCM). This technology was originally developed in voice telephone technology and is disclosed in US Pat. No. 2,272,070. In its original form, an analog signal is periodically sampled and represented by a digital code. However, unlike PWM, there is no linear relationship between the on-time average of the digital signal and the analog input signal. As a result, it would seem that there is no apparent advantage to using conventional PCM technology for LED drive current.

  However, there is one derivative of PCM that appears to be competitive with PWM for LED control. The web document “Application Note 011: An Overview of the Electronic Drive Techniques for the Intensive for Intensity Control and Hour in the Slow and the Color of the Sour.” Proposals have been made of what is referred to as “angle modulation” or BAM. He said that this technology essentially “drives the LED by a pulse train, which is a binary word that defines the required intensity value”, where “the bit of each pulse train is defined by what that bit means. An example of a comparison between a PWM signal and a BAM signal specifying 16 discrete signal levels is shown in FIG.

  Howell, by means of the following example, states that BAM is the most efficient in using the resources of the microcontroller: “A microprocessor that generates a 100 Hz PWM signal with 8 bit stages has an output of 39 micron. It is necessary to process every second, and a total of 256 processes are required for each output cycle, and in comparison, in the case of a 100 Hz BAM signal having an 8-bit stage, the output is changed from the start of the cycle. It only needs to be processed 8 times, ie, 5000 μsec, 2500 μsec, 1250 μsec, 625 μsec, 312 μsec, 156 μsec, 78 μsec, 36 μsec, ”he argues that this means an 800% reduction in required processing power compared to PWM. is doing.

  As described above, BAM uses a microcontroller that does not have a PWM channel by hardware, for example, performs other tasks in addition to controlling the LED driver, and sends and receives signals to and from the host controller. This is effective when using a microcontroller. However, this does not address the problem of independently controlling a plurality of LEDs with a single microcontroller. Although it is true that the application of firmware BAM requires much less processing power than using equivalent PWM, the microcontroller still has a minimum period of 39 μs in the Howell example. It must respond to the hardware timer. Assuming the use of a typical microcontroller with an instruction period of 200 nanoseconds (using a 20 MHz clock), control becomes difficult when the number of independent BAM channels is about 20 or more.

  Furthermore, considering the Howell example, the LED driver for most lighting applications requires 10-bit resolution at 200 Hz to avoid visible flicker when the LED emission intensity is lowered. The example seems somewhat optimistic. As a result of this typical requirement, the minimum BAM pulse width is reduced to 5 μs and the number of BAM channels is reduced to 4 for the same 20 MHz clock (in this case, the microprocessor reduces its most processing time). It is assumed that it will be spent on handling hardware timer interrupts and controlling BAM output signals.)

  For example, if the microcontroller can independently control 128 LED drivers independently, the number of physical control signal lines from the microcontroller corresponds to one or two 8-bit digital output ports. Or it is desirable to limit to 16. Therefore, there is a clear need for an apparatus and method that can control a large number of LEDs or groups of LEDs so that the number of physical connections between the microcontroller as a signal source and the LED driver is small.

  This background information presents known information that the applicant believes is optimal for the present invention. None of the above information is intended to give approval to constitute prior art for the present invention.

  One object of the present invention is to provide a system and method for parallel pulse code modulation. In one aspect of the present invention, a parallel pulse code modulation system is provided that can independently control multiple groups of one or more electronic devices, comprising: A memory unit that receives control data from an external source and writes or reads the input control data. A multiplexer connected to the memory unit for receiving control data from the memory unit and preparing the control data into a serial data string of a data group. A shift register connected to a multiplexer, receiving a serial data stream from the multiplexer, and converting each data group into a respective parallel data stream output representing a control parameter corresponding to one or more electronic device groups. One is connected to the shift register and one or more electronic devices, receives the parallel data stream output, and outputs the parallel data stream to one or more specific devices to which each parallel data corresponds. A latch for independently controlling one or more groups of electronic devices. A logic sequencer for supplying sequence commands and timing signals to the memory unit, multiplexer, shift register and latch.

  In another aspect of the present invention, there is provided a control method comprising the following steps capable of independently controlling a plurality of groups of one or a plurality of electronic devices. The control unit receives control data from an external source and writes the control data to the memory unit. The control data is read from the memory unit and transmitted to the multiplexer. The control data received by the multiplexer is organized into a serial data stream composed of data groups. Each data group is converted into a group of parallel data stream outputs, each parallel data stream output representing a control parameter for a particular group of one or more electronic devices. By doing so, it is possible to independently control a plurality of groups of one or a plurality of electronic devices.

Detailed Description of the Invention
The definition term "light emitting device" emits electromagnetic radiation in the visible light region when a potential difference is applied or current flows, for example, semiconductors, organic light emitting diodes (LEDs) and other similar ones as you can see Means any device, and any drive electronics required to control its excitation may be included. As one with ordinary knowledge in this field can easily understand, a single light-emitting element can be used in the infrared or ultraviolet region instead of emitting in the visible light region of electromagnetic radiation. It can be replaced by any other element that emits electromagnetic radiation in any spectral region.

The term “word” is used to mean a set of bits of a plurality of binary codes representing a digital signal.
The term “random access memory” or “RAM” is intended to mean any circuit that makes up a collection of cells and a memory unit that is ancillary circuitry necessary to move information in and out of the cells. Used as a replaceable term. These memory cells can access any desired cell in any random location in the memory unit to transfer information in and out. Those of ordinary skill in the art will appreciate that any type of memory unit can replace a single RAM block.

  The term “first-in-first-out memory” or “FIFO” refers to the oldest program, such as the data written to memory first being read first, then the data written next. It is used as a mutually interchangeable term to mean any circuit that constitutes a memory unit that can initially process work requests. The FIFO consists of a plurality of RAM blocks and a read / write address generator for identifying each word in the RAM that is written to and read from the RAM. It will be appreciated by those skilled in the art that other aspects of the FIFO are possible. For example, a microcontroller with internal or external RAM, or a programmable gate array (FPGA) can also be programmed to emulate a hardware FIFO.

  The terms “multiplexer” or “MUX” are used interchangeably as meaning any circuit that prepares the received data into a serial bit sequence that is arranged in a particular order. The MUX includes a switch for selecting a specific bit of input data and outputting it in a specific order, and a sequence address generator for specifying which part of the data bit is selected at a certain time.

The term “shift register” is used to mean any circuit that can accept serial data input, shift the data, and output it as one or more parallel data streams.
The term “latch” is used to mean any circuit that can hold input data until it is commanded to input and hold other data and provide it as an output.

  Unless otherwise defined, all scientific and technical terms used herein have the same meaning as commonly understood by those with ordinary knowledge in the art to which this invention belongs. Is done.

  A highly schematic drawing of the present invention is shown in FIG. The parallel pulse coat modulation system 100 of the present invention reduces the number of connection lines between a signal source and a light emitting element, and uses a control signal from the signal source to emit a light emitting element such as a semiconductor or an organic light emitting diode (LED). It is possible to control one or a plurality of groups independently. In this way, control of one or a plurality of light emitting element groups is possible without requiring a multilayer printed circuit board.

  In one aspect of the invention, the parallel pulse code modulation system 100 receives N words of binary data from an external source 10 such as a microcontroller, host computer or digital communication system. Here, N is the number of light emitting element groups 200 to be controlled. Each of the N words consists of M-bit binary data, and each M-bit data represents a desired emission intensity of a specific light emitting element or element group.

  FIG. 4 illustrates one aspect of the present invention, where N words from an external signal source control N LED driver channels. N words, each of which is binary data representing the light intensity of a specific LED or group of LEDs each driven to a specific LED driver channel, are stored in one first-in first-out memory (FIFO) 12. Entered.

  In this embodiment, the FIFO memory 12 comprises at least two blocks of dual port random access memory (RAM) 14, each capable of storing N M-bit words. A sequential write address generator 16 and a sequential read address generator 18 specify a word to be written to and read from the RAM 14, respectively. As each word of data is input to the FIFO 12 from the external data source 10 via the data line 34, the write line 36 is pulsed by the external data source. This action causes the word data to be written to the currently addressed RAM location, and the write address generator 16 increments the address in increments (to specify the RAM location for the next word data to be written. Modulo) Increase to 2N.

  The contents of the RAM 14 can be read asynchronously even when the RAM is being written. When the read line is toggled by the logic sequencer 20, the read address generator 18 is incremented by a unit increment (Modulo) N, specifying the next RAM location, and the word data stored at that location becomes the data line 40. Is output.

  During operation, N words of data are repeatedly input to the FIFO 12 at a rate of P times per second, where P can be set to 100 to 300, for example, so that flicker is not perceived smoothly. Provides light intensity adjustment of the light emitting device. Each repetition of inputting N words repeatedly is hereinafter referred to as “one cycle”.

  As described above, the FIFO 12 can receive 2N words of M-bit data at any time and store them in the dual port RAM 14. Therefore, reading of data stored in the RAM 14 is delayed by one cycle with respect to data written by the external data source 10. In this way, the data of the current cycle can be read asynchronously with the data being written for the next cycle. That is, for example, in each even cycle, the contents of RAM locations 1 through N can be read while the contents of locations N + 1 through 2N are being written, and vice versa in odd cycles. it can. In addition, the logic sequencer 20 toggles the control line 42 to determine which of the first block and the second block of the RAM 14 is accessed. The FIFO 12 therefore also plays the additional role of buffering data input from the external data source 10. In addition, the excitation of the read line 38 repeatedly performed by the logic sequencer 20 enables the contents of the dual port RAM to be read many times in the order in which data is input.

  The output of the FIFO 12 is connected to the input of an M: 1 digital multiplexer (MUX) 22 that prepares the word data read from the FIFO 12 into a serial bit stream. The MUX 22 includes a sequential address generator 24 and an M circuit (M-way) switch 26. The logic sequencer 20 is connected to the address generator 24 via a control line 44. Toggling the control line 44 by the logic sequencer 20 reduces the address generator 24 by a modulo M. According to the address designated by the address generator 24 for the M circuit (M-way) switch 26, the first to Mth bit values of the input word are output from the MUX 22.

  The output of the MUX 22 is connected to the input of the N-bit serial-parallel shift register 28 by the data line 46, and basically holds the Mth bit of each word when inputted from the MUX 22. A shift register shifts the words and outputs each word in parallel format. It is also possible to use a plurality of shift registers having a capacity of N bits as a whole as in the following mode. A logic sequencer 20 is connected to the shift register 28 via a read line 38 to provide a clock signal that provides a pulse for shifting the bits of each word in the register.

  The N digital outputs of the shift register 28 are connected via data lines 48 to the N inputs of an N-bit latch 30 that holds the data received from the shift register until the next set of data is received. ing. The logic sequencer 20 is connected to the latch 30 via the control line 44 and provides a pulse signal so that the latch 30 can receive each bit via the data line 48. N outputs of the latch 30 are connected to N LED drivers 32 via a data line 50, and a driver to which one LED or a group of LEDs is connected is driven to a non-excited state.

The logic sequence and timing logic sequencer 20 basically defines the order and time in which the operations defined in accordance with the present invention are performed. It constitutes one programmable timer that can be synchronized with the external data source 10 via the control line 52. This control line is pulsed at the beginning of each cycle. The external data source 10 then sequentially outputs N words to the FIFO 12 at a rate of P times per second under the condition that all N words are output before the start of the next cycle. . This condition defines an upper limit imposed on the number of words that can be included in each cycle, but this value also depends on the clock speed used by the system.

  At the start of each cycle (after the first N words have been written to the FIFO 12 by the first cycle), the logic sequencer 20 is used to sequentially transfer the N words from the FIFO 12 to the MUX 22. Repeatedly pulses the readout line 38. In one embodiment in which bit angle modulation (BAM) of the present invention is performed, the address generator 24 selects the bit representing the largest unit in each word. The Mth bit of each word is output to the shift register 28. Control line 42 is set to access the appropriate block of RAM 14, for example to access block 1 in the second cycle. When the readout line 38 is pulsed, the readout line also pulses the clock to the shift register 28 and the bits in the register are shifted sequentially. One shift register 28 stores the first bit of each N words to be output, and the logic sequencer 20 pulses the control line 44 and sets each bit via the data line 48. Allows latch 30 to receive. These bits are output to the LED driver 32 via the data line 50. The toggle operation on the control line 44 simultaneously increments the MUX address generator 24 to select the bit representing the next largest unit. Therefore, for example, if bit M is the bit representing the largest unit, and the bit representing the largest unit after bit M is bit M-1, in all words, bit M further includes M- 1, M-2, etc. will follow.

  In this aspect of the invention where BAM is performed, the logic sequencer 20 timing is programmed so that the pulse excitation of the control line 44 is delayed by 1 / (2P), considering the bit representing the largest unit. Is done. In this way, the bit representing the largest unit is basically extended for this period. During this stretching time, the logic sequencer 20 repeatedly pulses the read line 38 and sequentially transfers N words from the FIFO 12 to the MUX. When this extending time elapses, the logic sequencer 20 pulses the control line 44 again, and each bit is latched and output to the LED driver 32.

This process is repeated M times, and the timer extension time is halved each time, so each bit is extended by a ratio that defines the required intensity value. Thus, in the BAM, the timing of the logic sequencer 20 is programmed to be extended only during [Formula: (1 / (2 ⁱ * P)) = 2 times i multiplied by 1]. Here, “i” means the size of a unit represented by a certain bit. For example, “i” being 1 means a bit representing the largest unit in a word, and “i” being 2 means a bit representing the second largest unit. is there. For the bits representing the second largest unit, the delay is equal to 1 / (4P). In this way, N words received from the external data source 10 are converted into a BAM bitstream for transfer to the respective LED driver.

  If the last bit of each word in the shift register 28 is selected to complete the transfer to the latch 30 and further to the LED driver 32, the first cycle is complete. The control line 42 is then toggled to select another block of RAM 14, consisting of N words for the next cycle, in order to prepare the entire process described above to run in the next cycle. The

  FIG. 5 is a schematic diagram of the process flow of the above aspect of the invention. The value of “x” is a value that defines the extended time of each control bit. In the case of BAM, the value is equal to 2 to the power of i, but in the case of PCM, “x” can be a constant. .

Further, the above-described process is expressed as follows by pseudo code as an example.
DO FOREVER
Read N words data into FIFO12
Set MUX 22 bit select address to M
FOR i = 1 to M
FOR j = 1 to N
Output data [j] from FIFO12 to MUX22
Pulse shift register28 clock
ENDFOR
Pulse latch 30
Decrement MUX22 bit select address
Delay 1 / (x ^* P) seconds
ENDFOR
Toggle RAM14 block select
ENDDO

  As described above, in one embodiment of the present invention, the LED channel is driven using BAM and the timing and sequence are controlled. However, the present invention is for controlling one or a plurality of light emitting element groups. Can be used to convert any binary word into a parallel output stream and extend each bit of data if necessary.

In one embodiment of the present invention, as shown in FIG. 6, a plurality of shift registers 54 and latches 56 are provided corresponding to the respective LED drivers 58, and the total capacity thereof is N bits. can do. In this configuration, each shift register, latch, and corresponding LED driver are serially connected to the data connection 62 as a daisy chain, as an independent module 60 having a common shift register clock signal 64 and a common latch enable signal 66. Can be installed.

  One advantage of the present invention is that the shift register and associated latch may be physically separate from the FIFO 12, MUX 22, and logic sequencer 20. On the other hand, a PWM controller requires N separate connections for each LED driver channel, whereas the present invention provides a shift register between each shift register and its associated latch. Only three connections are required: the data input line 46, the read line 38 from the logic sequencer, and the latch enable signal 44 from the logic sequencer. The present invention thus avoids the need for expensive multilayer circuit boards that are typically required in the case of PWM based controllers.

  Another advantage of the present invention is that a logic sub-unit including a FIFO, MUX, shift register, latch and logic sequencer can be combined with a low gate, as opposed to a discrete IC, a less expensive FPGA, or a more expensive microcontroller, for example. It can be built using count specific application ICs (ASICs).

  A further advantage of the present invention is that the logic subunits can be operated at higher switching speeds and cycle times than can be achieved with commercially available microcontrollers due to low circuit complexity. Therefore, by using an example of the present invention, hundreds of LED driver channels can be controlled independently.

  In the above description, it is explained that the present invention can be used for excitation of a light emitting element. However, if the person has ordinary knowledge in this field, the present invention can connect the source and the electronic device itself. It will be readily appreciated that it provides a means by which multiple electronic devices using pulses can be excited / de-excited while reducing the number of pulses.

  It will be apparent that the embodiments of the present invention described above can be modified in various ways. Such variations are not to be understood as departing from the spirit and scope of the invention, and all such variations apparent to those of ordinary skill in the art are intended to be covered by the claims herein. It is intended to be included in

It is a figure which shows the example of a 25%, 50%, and 100% duty ratio of a pulse width modulation signal. It is an example of the signal which enables the production | generation of 16 types of output signals by each of a pulse width modulation signal and a bit angle modulation signal. FIG. 3 is a highly conceptual representation of one embodiment of the present invention. It is a block diagram of 1 aspect of this invention. FIG. 3 is a process flow diagram of one embodiment of the present invention. It is a block diagram of another aspect of this invention.

Claims (22)

A parallel pulse code modulation system that allows multiple groups of one or more electronic devices to be controlled independently, including:
a) a memory unit that receives control data from an external source, the memory unit being capable of writing and reading control data;
b) a multiplexer connected to the memory unit for receiving control data from the memory unit and organizing the control data into a serial data stream including data groups;
c) connected to the multiplexer, receives the serial data stream from the multiplexer and converts each data group into a respective parallel data stream output, which means control parameters for a particular group of one or more electronic devices Shift register;
d) A latch connected to a plurality of groups of shift registers and one or more electronic devices, each receiving a parallel data stream output and corresponding to a corresponding group of one or more electronic devices. Said latch for independently controlling a plurality of groups of one or more electronic devices by sending a particular parallel data stream output; and e) for memory units, multiplexers, shift registers and latches Logic sequencer for supplying sequence commands and timing signals.   The control data includes a plurality of binary words, each of the plurality of binary words including a plurality of binary data bits defining a desired level of operation of a particular group of one or more electronic devices. The parallel pulse code modulation system described.   The parallel pulse code modulation system of claim 2, wherein the electronic device is a light emitting element and the desired operating level represents a desired illumination level.   The parallel pulse code modulation system according to claim 1, wherein the memory unit is a first-in first-out memory.   The parallel pulse code modulation system according to claim 1, wherein the memory unit is a dual-port random access memory capable of simultaneously reading and writing.   The parallel pulse code modulation system of claim 2, wherein the multiplexer organizes the plurality of binary words into a serial data stream based on the significance of the binary data bits within each binary word.   The parallel pulse code modulation system of claim 6, wherein the binary words are organized into a serial data stream based on the decreasing significance of the binary data bits in each binary word.   Each parallel data stream output includes a plurality of binary data bits, and when sending a particular parallel data stream output to a corresponding group of one or more electronic devices, the transmission of each successive binary bit The parallel pulse code modulation system according to claim 1, wherein a predetermined time delay is provided therebetween.   The default length of time is reduced sequentially after sending each binary bit in the parallel data stream output, and the default output is reset to send the next parallel data stream output. The parallel pulse code modulation system according to claim 8.   9. The parallel pulse code modulation system of claim 8, wherein the binary data bits have an assigned significance and the predetermined length of time is based on the significance of the particular binary data bits.   The parallel pulse code modulation system of claim 10, wherein a predetermined length of time is divided by two after transmitting each binary data bit in a particular parallel data stream output.   A shift register is connected in a daisy chain format with a plurality of additional shift registers, each shift register is connected to a corresponding latch, and each latch is a corresponding plurality of one or more electronic devices. The parallel pulse code modulation system according to claim 1, wherein the parallel pulse code modulation system is connected to the group and serial data stream output by the multiplexer is sequentially transmitted to each shift register. A method that allows a plurality of groups of one or more electronic devices to be independently controlled by a method that includes the following steps.
a) receiving control data by the memory unit from an external source and writing the control data to the memory unit;
b) reading the control data from the memory unit and sending the control data to the multiplexer;
c) Organizing the control data into a serial data stream containing data groups by a multiplexer;
d) converting each data group into a plurality of parallel data stream outputs, each representing a control parameter for a particular group of one or more electronic devices;
e) Send each parallel data stream output to a corresponding group of one or more electronic devices.   14. The control data includes a plurality of binary words, each of the binary words including a plurality of binary data bits defining a desired level of operation for a particular group of one or more electronic devices. the method of.   The method of claim 14, wherein the electronic device is a light emitting element, and the desired operating level is intended to mean a desired emission level.   The method of claim 13, wherein writing control data to the memory unit and reading control data from the memory unit are performed simultaneously.   15. The method of claim 14, wherein organizing control data includes organizing a plurality of binary words into a serial data stream based on the significance of binary data bits in each binary word.   The method of claim 17, wherein the binary words are organized into a serial data stream based on the decreasing significance of the binary data bits in each binary word.   14. Each parallel bitstream output includes a plurality of binary data bits, and the step of transmitting each parallel data stream output includes a predetermined length of time delay between transmission of each binary data bit. The method described in 1.   The predetermined length of time is progressively reduced after each binary bit in the parallel data stream output is transmitted, and the default output is reset to transmit the next parallel data stream output. 20. The method of claim 19, wherein   20. The method of claim 19, wherein the binary data bits have an assigned significance and the predetermined length of time is based on the significance of the particular binary data bits.   21. The method of claim 20, wherein after transmitting each binary data bit in a particular parallel data stream output, a predetermined length of time is divided by two.

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