TWI842087B - Word line driving circuit, word line driver, and storage device - Google Patents

Abstract

The disclosed embodiment relates to a word line driver circuit, a word line driver, and a storage device. The word line driver circuit includes: at least two sub-word line drivers connected to a main word line and a sub-word line, the main word line provides an enable signal; the sub-word line driver includes a holding transistor, the first end and the second end of the holding transistor are connected to different sub-word lines, and the holding transistor receives a second driving signal; the sub-word line driver is configured to respond to the first driving signal. The invention relates to a circuit for controlling a word line driving circuit, wherein the first driving signal and the enable signal are provided to the selected sub-word line; the first driving signal, the enable signal and the second driving signal are responded to, and the holding transistor is turned on; the holding transistor includes a first transistor and a second transistor, and the sub-word line connected to the first end and the second end of the first transistor corresponds to the same main word line, and the main word line connected to the first end and the second end of the second transistor corresponds to a different main word line. The disclosed embodiment is conducive to reducing the layout area of the word line driving circuit.

Description

Word line driving circuit, word line driver, and storage device

The disclosed embodiments relate to the field of semiconductor technology, and in particular to word line driver circuits, word line drivers, and storage devices.

Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memory can be incorporated on the chip, which helps increase product capacity. In dynamic random access memory (DRAM), data needs to be written/read to/from memory cells using word lines and bit lines, and operates based on the voltage applied to the word lines.

As DRAM capacity increases, the number of memory cells connected to one word line increases, and the distance between word lines decreases, speed delay problems may occur. In order to improve the delay of word line voltage, one word line can be divided into multiple sub-word lines and each sub-word line can be driven by using a sub word-line driver (SWD), wherein the sub-word-line driver can be set in the word line driving circuit.

However, the layout area of the current word line driver circuit is relatively large, resulting in a low integration of the memory. In view of this, the present invention proposes the following technical solution to solve the above problem.

The disclosed embodiment provides a word line driver circuit, a word line driver, and a storage device, which at least helps to reduce the layout area of the word line driver circuit.

According to an embodiment of the present disclosure, a word line driver circuit is provided, comprising: at least two sub-word line drivers, each sub-word line driver is connected to a main word line and a sub-word line, the main word line is used to provide an enable signal; the sub-word line driver comprises a holding transistor, the first end and the second end of the holding transistor are respectively connected to different sub-word lines, and the gate of the holding transistor receives a second driving signal; the sub-word line driver is configured to respond to the first driving signal and the enable signal. signal, providing a first driving signal to the selected sub-word line; in response to the first driving signal, the enable signal and the second driving signal, turning on the first end and the second end of the holding transistor; wherein the holding transistor includes a first transistor and a second transistor, the two sub-word lines connected to the first end and the second end of the first transistor correspond to the same main word line respectively, and the two sub-word lines connected to the first end and the second end of the second transistor correspond to different main word lines respectively.

In some embodiments, the selected sub-word line is a sub-word line connected to the first end or the second end of the retention transistor

In some embodiments, the holding transistor includes an NMOS transistor.

In some embodiments, the sub-word line driver includes: a pull-up transistor, a gate connected to the main word line, a source receiving a first driving signal, a drain connected to the sub-word line and a first end or a second end of a holding transistor; a pull-down transistor, a gate connected to the main word line, a drain connected to the drain of the pull-up transistor, and a source receiving a third driving signal.

In some embodiments, the pull-up transistor includes a PMOS transistor; the pull-down transistor includes an NMOS transistor.

Correspondingly, the disclosed embodiment further provides a word line driver, comprising: a PMOS region, comprising a plurality of first active regions extending along a first direction, the first active region comprising a first channel region and a first source region and a first drain region respectively located at two opposite sides of the first channel region; an NMOS region, arranged along a second direction with the PMOS region, comprising a plurality of second active regions extending along the first direction, the second active region comprising a second channel region and a second source region and a second drain region respectively located at two opposite sides of the second channel region, the second active region further comprising a third channel region and a third source region and a third drain region respectively located at two opposite sides of the third channel region; a first gate, each of the first gates extending along the second direction and covering the plurality of first channel regions and the plurality of second channel regions, the first gate being connected to the main word line electrode. The first gate, the first source region and the first drain region constitute a pull-up transistor, the first gate, the second source region and the second drain region constitute a pull-down transistor, and the pull-down transistor includes a first transistor and a second transistor; a plurality of second gates, each second gate covers a corresponding third channel region, and the second gate, the third source region and the third drain region constitute a holding transistor; wherein the first drain region of a pull-up transistor is electrically connected to the first drain region of a pull-down transistor and is electrically connected to the corresponding sub-word line; the third drain region and the third source region of the same first transistor are respectively electrically connected to the second drain regions of two pull-down transistors sharing the same first gate; the third drain region and the third source region of the same second transistor are respectively electrically connected to the second drain regions of two pull-down transistors corresponding to different first gates.

In some embodiments, the NMOS region includes: a first NMOS region and a second NMOS region, respectively located on opposite sides of the PMOS region; wherein the first transistor is located in the first NMOS region; the second transistor is located in the second NMOS region; a portion of the pull-down transistors are located in the first NMOS region, and the remaining portion of the pull-down transistors are located in the second NMOS region.

In some embodiments, each first gate includes: at least two extension portions arranged at intervals along the first direction, extending along the second direction and covering a plurality of first channel regions and a plurality of second channel regions; and a connecting portion connecting between two adjacent extension portions along the first direction.

In some embodiments, the connecting portion covers the area between adjacent first active regions and also covers the area between the first active region and the second active region.

In some embodiments, along the first direction, the distance between adjacent extensions of the first NMOS region is greater than the distance between adjacent extensions of some PMOS regions, and the second gate corresponding to the first transistor is located between the adjacent extensions.

In some embodiments, the third drain region of the first transistor is shared with the second drain region of a pull-down transistor located in the first NMOS region; the third source region of the first transistor is shared with the second drain region of another pull-down transistor located in the first NMOS region.

In some embodiments, along the first direction, the distance between adjacent extensions of the second NMOS region is smaller than the distance between adjacent extensions of some PMOS regions, and the second gate corresponding to the second transistor is located outside the region surrounded by the two extensions.

In some embodiments, the third drain region of the second transistor is shared with the second drain region of a pull-down transistor located in the second NMOS region; the third source region of the second transistor is shared with the second drain region of another pull-down transistor located in the second NMOS region.

In some embodiments, the PMOS region includes: a first PMOS region and a second PMOS region arranged along the second direction, the second PMOS region is located between the first PMOS region and the first NMOS region; two extensions of the same first gate cover the same first active region of the first PMOS region, and the two extensions also cover two first active regions of the second PMOS region arranged along the first direction; wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is smaller than the distance between adjacent extensions of the second PMOS region.

In some embodiments, the pull-up transistors corresponding to the first PMOS region share a first source region, and the shared first source region receives a first driving signal.

In some embodiments, each first gate covers 4×N first channel regions and 4×N second channel regions, and the pull-up transistor and the pull-down transistor formed by each first gate are electrically connected to 2×N holding transistors; wherein N is a positive integer greater than or equal to 1.

In some embodiments, the plurality of first active regions include: at least two first active regions disposed near the NMOS region, the two first active regions are spaced apart along the first direction and have a spacer region, wherein the second gate and the spacer region are disposed opposite to each other along the second direction.

Correspondingly, the disclosed embodiment also provides a storage device, including: a storage cell array, including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driving circuit provided by any of the above items; or, a word line driver provided by any of the above items.

In some embodiments, it also includes: a signal generating circuit configured to output a first drive signal and a second drive signal, and the positive edge moment of the second drive signal has a preset time delay compared to the negative edge moment of the first drive signal.

In some embodiments, the signal generating circuit includes: a decoder configured to output a first driving signal; a PMOS transistor, a gate receiving the first driving signal, one receiving the original driving signal, and the other connected to an inverter, the inverter outputting a second driving signal, wherein the edge timing of the original driving signal is consistent with the edge timing of the first driving signal.

The technical solution provided by the disclosed embodiment has the following advantages: The technical solution of the word line driving circuit provided by the disclosed embodiment includes at least two sub-word line drivers, each of which is connected to a main word line and a sub-word line, so that the sub-word line driver can drive the sub-word line based on the enable signal received by the main word line. The sub-word line driver includes a holding transistor, and the first end and the second end of the holding transistor are respectively connected to different sub-word lines, that is, the two sub-word lines share the same holding transistor, so that it can be achieved that while driving a sub-word line connected to one end of the holding transistor, another sub-word line connected to the other end of the holding transistor is in an unselected state. The first transistor is set to control two sub-word lines corresponding to the same main word line, and the second transistor controls two sub-word lines corresponding to two different main word lines, that is, the connection between the transistor and different sub-word lines can be flexibly set to reduce the area occupied by the word line driving circuit while keeping the performance of the word line driving circuit unchanged, thereby reducing the layout area of the word line driving circuit.

1: Keep the transistor

11: District 1

110: First active area

12: Second District

120: Second active area

100: Sub-word line driver

101: Pull-up transistor

102: Pull-down transistor

103: first transistor

104: Second transistor

13: The first source area

130: First gate

131:Connection part

132: Extension Department

14: First Drainage Area

140: Second gate

15: Second channel area

150:Decoder

151:PMOS transistor

152: Inverter

16: Second source area

17: Second Drainage Area

18: The third source area

20: PMOS area

21: First NMOS area

22: Second NMOS area

23: First PMOS area

24: Second PMOS area

One or more embodiments are illustrated by the corresponding figures in the accompanying drawings. These exemplary descriptions do not constitute limitations on the embodiments. Unless otherwise stated, the figures in the accompanying drawings do not constitute proportion restrictions. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For ordinary technical personnel with limited skills, other accompanying drawings can be obtained based on these accompanying drawings without creative labor.

FIG. 1 is a circuit diagram of a word line driver circuit; FIG. 2 is a sub-word line system architecture diagram; FIG. 3 is a circuit diagram of a word line driver circuit provided by the present disclosure; FIG. 4 is a timing diagram of each signal in a word line driver circuit provided by the present disclosure; FIG. 5 is a schematic diagram of a layout structure of a word line driver provided by the present disclosure; FIG. 6 is a schematic diagram of a layout structure of another word line driver provided by the present disclosure; FIG. 7 is a schematic diagram of a layout structure of yet another word line driver provided by the present disclosure; FIG. 8 is a schematic diagram of a layout structure of yet another word line driver provided by the present disclosure; FIG. 9 is a circuit diagram of a signal generation in a storage device provided by the present disclosure.

As can be seen from the background technology, the current word line driver circuit has a large layout area. Analysis has found that one of the reasons for the large layout area of the current word line driver circuit is that, referring to Figure 1 and Figure 2, the current word line driver circuit includes at least one sub-word line driver, which is connected to a main word line MBLb and a sub-word line WL; the sub-word line driver also includes a holding transistor 1, the first end of the holding transistor 1 is connected to the sub-word line WL, and the other end is coupled to the low potential VKK. The sub-word line driver receives an enable signal and a drive signal PXID, and provides the drive signal PXID to the sub-word line WL, thereby driving the sub-word line WL; when the sub-word line WL does not need to be selected, the first end and the second end of the holding transistor 1 can be turned on in response to the enable signal, the drive signal PXID, and the drive signal PXIB, so that the first end of the holding transistor 1 is coupled to the low potential VKK, and the sub-word line WL connected to the first end of the holding transistor 1 is also pulled down to the low potential VKK, so that the sub-word line WL is turned off. In other words, one holding transistor 1 is only used to control one sub-word line, so that the sub-word line remains unselected. Referring to Figure 2, it can be seen that when there are two main word lines in the word line driver circuit, respectively marked as MWLb1 and MWLb2, and each main word line corresponds to two sub-word line drivers SWD, each holding transistor is electrically connected to a sub-word line (the multiple sub-word lines are marked as WL0 to WL15 in the figure), so that the sub-word line drivers respond to the corresponding drive signals PXIB and PXID, respectively, to control the closing of the sub-word lines, which will occupy more space in the word line driver circuit layout.

The disclosed embodiment provides a word line driver circuit, a word line driver, and a storage device. The word line driver circuit includes at least two word line drivers, and each word line driver is connected to a main word line and a sub-word line. The first end and the second end of the retention transistor in the sub-word line driver are respectively connected to the two sub-word lines, that is, the two sub-word lines share the same retention transistor. When the sub-word line connected to one end of the retention transistor is driven, the retention transistor can make the sub-word line connected to the other end of the retention transistor in an unselected state. The first transistor is set to control two sub-word lines corresponding to the same main word line, and the second transistor is set to control two sub-word lines corresponding to two different main word lines, thereby reducing the area occupied by the word line driving circuit and the layout area of the word line driving circuit while keeping the performance of the word line driving circuit unchanged.

The following will be combined with the attached figures to explain in detail the various embodiments of this disclosure. However, ordinary technicians in this field can understand that in the various embodiments of this disclosure, many technical details are proposed to enable readers to better understand this disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by this disclosure can also be implemented.

Figure 3 is a circuit diagram of a word line driving circuit provided in the disclosed embodiment.

Referring to FIG. 3 , 4×N sub-wordline drivers 100 are provided. Each sub-wordline driver 100 is connected to a main wordline and a sub-wordline. The main wordline is used to provide an enable signal. The 4×N sub-wordline drivers 100 include 2×N retention transistors. The first end and the second end of the retention transistor are respectively connected to different sub-wordlines. The gate of the retention transistor receives the second drive signal PXIB. The sub-wordline driver 100 is configured to provide the first drive signal PXID to the selected sub-wordline in response to the first drive signal PXID and the enable signal. ID; in response to the first drive signal PXID, the enable signal and the second drive signal PXIB, the first end and the second end of the holding transistor are turned on; wherein the 2×N holding transistors include at least one first transistor 103 and at least one second transistor 104, the two sub-word lines connected to the first end and the second end of the first transistor 103 correspond to the same main word line, and the two sub-word lines connected to the first end and the second end of the second transistor 104 correspond to different main word lines; N is a positive integer greater than or equal to 1.

The first end and the second end of the holding transistor are respectively connected to two different sub-word lines, that is, the two sub-word lines share the same holding transistor. When the word line driver responds to the first driving signal PXID and the enable signal, the first driving signal PXID is provided to the selected sub-word line. In some embodiments, the selected sub-word line is the sub-word line connected to the first end or the second end of the holding transistor, so that the sub-word line connected to the first end or the second end of the holding transistor is selected, and the other sub-word line connected to the holding transistor is not selected; when the word line driver responds to the first driving signal PXID, the enable signal and the second driving signal PXIB, the first end and the second end of the holding transistor are turned on, so that the potential of the selected sub-word line is pulled to be consistent with the potential of the unselected sub-word line, so as to close the selected word line. That is, when the sub-word line connected to one end of the holding transistor is driven, the holding transistor can make the sub-word line connected to the other end of the holding transistor in an unselected state, thereby reducing the area occupied by the word line driving circuit and the layout area of the word line driving circuit while maintaining the performance of the word line driving circuit unchanged.

Referring to FIG. 3, the same main word line is connected to at least two sub-word line drivers 100, and the same main word line corresponds to at least two sub-word lines; the two sub-word lines connected to the first end and the second end of the first transistor 103 correspond to the same main word line. The two sub-word lines connected to the first end and the second end of the second transistor 104 correspond to different main word lines. In other words, the enable signal provided by the same main word line can be used to drive multiple corresponding sub-word lines.

In some embodiments, the number of main word lines is 2, one main word line can be connected to 8 sub-word line drivers 100, and one main word line corresponds to 8 sub-word lines, that is, two main word lines can be used to control 16 sub-word lines. Since the two sub-word lines share the same retention transistor, the number of retention transistors is only 8. Among them, the number of first transistors 103 is 4, and the number of second transistors 104 is 4. Specifically, the word line driver circuit can be divided into a first area 11 and a second area 12. In the first area 11, the number of first transistors 103 is 4, and the first end and the second end of each first transistor 103 are respectively connected to two sub-word lines corresponding to the same main word line. In the second region 12, the first end and the second end of each second transistor 104 are respectively connected to two sub-word lines corresponding to different main word lines, wherein the main word line MWL1 corresponds to the sub-word line WL1, and the main word line MWL2 corresponds to the sub-word line WL2. That is, in the first region 11, each main word line corresponds to a different first transistor 103, and in the second region 12, two main word lines can share the same second transistor 104. When there are two main word lines, a total of 16 sub-word lines can be driven, and the number of holding transistors is only 8. Compared with one main word line corresponding to 8 holding transistors, the area occupied by the sub-word line driver 100 is greatly reduced, thereby greatly reducing the layout area of the word line driving circuit.

It is understandable that in other embodiments, the number of first transistors 103 in the first region 11 may be 2, and the number of second transistors 104 in the second region 12 may be 6. The disclosed embodiment does not limit the number of first transistors 103 in the first region 11 and the number of second transistors 104 in the second region 12, and only needs to satisfy that the first end and the second end of each holding transistor are connected to different sub-word lines respectively.

It can be understood that no matter how many sub-word line drivers 100 are connected to a main word line, and no matter whether a main word line shares 4 retention transistors or two main word lines share 8 retention transistors, in a word line driver circuit, only one sub-word line can be driven at the same time, and the remaining sub-word lines are all in an unselected state.

The sub-wordline driver 100 can activate or pre-charge the selected sub-wordline in response to the enable signal provided by the main wordline and the first drive signal PXID and the second drive signal PXIB input to the sub-wordline driver 100. The enable signal, the first drive signal PXID and the second drive signal PXIB can be provided by an external circuit. In some embodiments, the first drive signal PXID can be a high voltage level, and the sub-wordline driver 100 can drive the sub-wordline with a high voltage. Correspondingly, when a high voltage level is used to drive the sub-wordline, a low voltage level can be used to turn off the sub-wordline.

Referring to FIG. 3, since a sub-word line driver 100 is connected to a sub-word line, and a retention transistor is connected to two different sub-word lines respectively. Therefore, in the word line driving circuit, the number of sub-word line drivers 100 is twice the number of retention transistors, that is, the two sub-word lines connected to a retention transistor are also connected to two sub-word line drivers 100 respectively.

It is worth noting that in the word line driving circuit, when one of the word line drivers drives the sub-word line connected to it, the sub-word lines connected to the remaining sub-word line drivers 100 are all in an unselected state, that is, in the word line driving circuit, only one sub-word line can be selected at the same time. It can be seen that when the sub-word line connected to one of the first terminal or the second terminal of the holding transistor is selected, the sub-word line connected to the other of the first terminal or the second terminal of the holding transistor is in an unselected state. Thus, when the first and second ends of the holding transistor are turned on, the potential of the sub-word line connected to the first end of the holding transistor will be pulled to the same level as the potential of the sub-word line connected to the second end of the holding transistor, thereby lowering the potential of the selected sub-word line to the same level as the potential of the unselected sub-word line, so that the selected sub-word line is in a closed state.

In some embodiments, the holding transistor includes an NMOS transistor. The second driving signal PXIB can be a high-level signal. The holding transistor is turned on in response to the high-level signal, thereby turning on the first end and the second end of the holding transistor. When the first end and the second end are turned on, the potentials of the two sub-word lines connected to the first end and the second end are consistent. Specifically, when the sub-word line connected to the first end of the holding transistor is selected, the sub-word line connected to the second end of the holding transistor is in an unselected state. If the sub-word line is driven in response to the high voltage level, the node of the first end of the holding transistor is at a high voltage level, and the node of the second end is at a low voltage level. When the first and second ends of the holding transistor are turned on, the potential of the node at the first end of the holding transistor is pulled down to the same potential as the node at the second end, that is, the node at the first end of the holding transistor has a negative voltage level, which is equivalent to pre-charging the sub-word line connected to the first end of the holding transistor with a negative voltage, ensuring that the sub-word line connected to the first end of the transistor is turned off.

It is not difficult to find that in the disclosed embodiment, since the first end and the second end of the holding transistor are respectively connected to two sub-word lines, when the first end and the second end of the holding transistor are turned on, the potential of the node at the first end is consistent with the potential of the node at the second end, that is, the voltage of the selected word line is consistent with the voltage of the unselected word line, thereby ensuring that the selected word line can be turned off.

In some embodiments, the sub-word line driver 100 includes: a pull-up transistor 101, a gate connected to the main word line, a source receiving a first driving signal PXID, a drain connected to the sub-word line and a first end or a second end of a holding transistor; a pull-down transistor 102, a gate connected to the main word line, a drain connected to the drain of the pull-up transistor 101, and a source receiving a third driving signal VKK. The pull-up transistor 101 pulls up the sub-word line to the level of the first drive signal PXID in response to the enable signal and the first drive signal PXID, and the sub-word line is driven in response to the first drive signal PXID; the pull-down transistor 102 pulls down the sub-word line to the level of the third drive signal VKK in response to the enable signal, and the sub-word line is closed in response to the third drive signal VKK. In some embodiments, the first drive signal PXID can be a high level, and the third drive signal VKK can be a low level, for example, the voltage of the third drive signal VKK can be 0 or less than 0.

Specifically, when the sub-word line driver 100 drives the sub-word line, the gate of the pull-up transistor 101 turns on the pull-up transistor 101 in response to the enable signal, and the first drive signal PXID is transmitted from the source to the drain of the pull-up transistor 101. Since the drain of the pull-up transistor 101 is connected to the sub-word line, the first drive signal PXID is transmitted from the drain of the pull-up transistor 101 to the sub-word line, so that the potential of the sub-word line is pulled up to the potential of the first drive signal PXID.

When the sub-word line driver 100 turns off the sub-word line, the gate of the pull-down transistor 102 turns on the pull-down transistor 102 in response to the enable signal, and the third drive signal VKK is transmitted from the source of the pull-down transistor 102 to the drain, and the drain of the pull-down transistor 102 is connected to the drain of the pull-up transistor 101, and the drain of the pull-up transistor 101 is connected to the sub-word line, so that the third drive signal VKK is transmitted from the drain of the pull-down transistor 102 to the sub-word line, so that the potential of the sub-word line is pulled down to the third drive signal VKK.

It is worth noting that, since the enable signal or the third drive signal VKK may be unstable, or since the word line drive circuit may be interfered by external noise, the potential of the sub-word line may not be less than 0. Therefore, relying solely on the third drive signal VKK may not be able to completely shut down the sub-word line. In the disclosed embodiment, since the first and second ends of the holding transistor are connected to two different sub-word lines, when the first and second ends of the holding transistor are turned on, the voltage of the selected word line will be pulled down to the same voltage as the unselected word line. That is, the holding transistor can couple the voltage of the selected word line to the negative voltage level, thereby shutting it down. Therefore, no matter how the level of the enable signal or the third drive signal VKK changes, the unselected word lines can maintain a stable voltage value.

In some embodiments, the pull-up transistor 101 includes a PMOS transistor; the pull-down transistor 102 includes an NMOS transistor. That is, the pull-up transistor 101 is turned on in response to a low-level signal, and the pull-down transistor 102 is turned on in response to a high-level signal, so that the pull-up transistor 101 and the pull-down transistor 102 can achieve mutual non-interference and control the driving and closing of the sub-word line respectively.

Specifically, when the pull-up transistor 101 is a PMOS transistor and the pull-down transistor 102 is an NMOS transistor, the working principle of the word line driver circuit is as follows: the two sub-word line drivers 100 are respectively recorded as: the first sub-word line driver and the first sub-word line driver, and the sub-word line connected to the first end of the holding transistor is recorded as the first sub-word line WL1, and the sub-word line connected to the second end of the holding transistor is recorded as the second sub-word line WL2. Among them, the first sub-word line WL1 is connected to the first sub-word line driver, and the second sub-word line WL2 is connected to the first sub-word line driver.

The first sub-word line driver drives the first sub-word line WL1, and at this time, the second sub-word line WL2 is in an unselected state.

The first sub-word line driver drives the first sub-word line WL1 in response to the low-level enable signal, the high-level first drive signal PXID and the low-level second drive signal PXIB. Specifically, the pull-up transistor 101 is turned on in response to the low-level enable signal, and the high-level first drive signal PXID is transmitted from the source of the pull-up transistor 101 to the drain of the pull-up transistor 101. At the same time, the holding transistor is turned off in response to the low-level second drive signal PXIB, so that the level of the first sub-word line WL1 is pulled up to the first drive signal PXID, with a high level, and thus driven.

The first sub-word line driver turns off the first sub-word line WL1 in response to the enable signal with a high level, the first drive signal PXID with a low level, and the second drive signal PXIB with a high level. The pull-down transistor 102 is turned on in response to the enable signal with a high level, and the pull-up transistor 101 is turned off in response to the enable signal with a low level. The third drive signal VKK is transmitted from the source of the pull-down transistor 102 to the drain of the pull-down transistor 102, so that the potential of the first sub-word line WL1 is pulled down to the third drive signal VKK, which has a low level. At the same time, the transistor is kept turned on in response to the second driving signal PXIB at a high level, so that the level of the first sub-word line WL1 is consistent with the level of the second sub-word line WL2. Since the second sub-word line WL2 is in an unselected state, it can be ensured that the first sub-word line WL1 is turned off and thus becomes an unselected state.

The principle of the first sub-word line driver driving the second sub-word line WL2 and closing the sub-word line is the same as that of the first sub-word line driver, and will not be repeated below. It is worth noting that since the first sub-word line driver and the first sub-word line driver correspond to the same holding transistor, when the selected second sub-word line WL2 needs to be closed, the first end and the second end of the holding transistor can be turned on to pull the potential of the second sub-word line WL2 down to the potential of the first sub-word line WL1, so that the second sub-word line WL2 is closed. In other words, a holding transistor can be set to connect two different sub-word lines to achieve control of the closing of the two sub-word lines.

In the first region 11, the first sub-word line driver and the first sub-word line driver are connected to the same main word line. At this time, when the main word line inputs an enable signal, the gate of the pull-up transistor 101 of the first sub-word line driver and the gate of the pull-up transistor 101 of the first sub-word line driver will simultaneously receive the enable signal from the main word line. Considering that only one sub-word line can be driven, the first drive signal PXID received by the source of the pull-up transistor 101 of the first sub-word line driver and the first drive signal PXID received by the source of the pull-up transistor 101 of the first sub-word line driver can be set to be different in level to prevent the two sub-word lines from being turned on at the same time.

In the first region 11, in some embodiments, the first sub-word line driver and the second sub-word line driver are respectively connected to different main word lines, for example, the first word line driver is connected to the first main word line, and the second word line driver is connected to the second main word line, so that the first word line driver and the second word line driver can respectively respond to the enable signal from the first main word line and the enable signal from the second main word line to drive the connected sub-word lines.

Refer to Figure 4, which is a timing diagram of various signals in a word line driving circuit provided by the disclosed embodiment.

When driving the sub-word line WL, in response to the enable signal provided by the main word line MWL, the potential of the first drive signal PXID is first pulled high. When the potential of the first drive signal PXID is pulled high, the potential of the second drive signal PXIB is pulled low, and then the potential of the enable signal is pulled low, thereby driving the sub-word line.

When the sub-word line is closed, the potential of the first drive signal PXID is first pulled low. After the potential of the first drive signal PXID is pulled low for a period of time, the potential of the second drive signal PXIB is pulled high, that is, the time when the potential of the second drive signal PXIB is pulled high is later than the time when the potential of the first drive signal PXID is pulled low. When the second drive signal PXIB is at a high level, the transistor is kept in a closed state. In this way, the time for keeping the transistor in a closed state can be longer, which can slow down the aging speed of the transistor.

In the technical solution of the word line driving circuit provided by the above disclosed embodiment, the first end and the second end of the holding transistor in the sub-word line driver 100 are respectively connected to the two sub-word lines, that is, the two sub-word lines share the same holding transistor. When the sub-word line connected to one end of the holding transistor is driven, the holding transistor can make the sub-word line connected to the other end of the holding transistor in an unselected state, and the first transistor 103 is set to control the two sub-word lines corresponding to the same main word line, and the second transistor 104 controls the two sub-word lines corresponding to two different main word lines, that is, the connection between the holding transistor and different sub-word lines can be flexibly set, so as to reduce the area occupied by the word line driving circuit and the layout area of the word line driving circuit while keeping the performance of the word line driving circuit unchanged.

Correspondingly, the disclosed embodiment also provides a word line driver, which can be used to form the word line driver circuit provided in the previous embodiment. The word line driver provided in the disclosed embodiment will be described in detail below.

Referring to FIG. 5 , the word line driver includes: a PMOS region 20 including a plurality of first active regions 110 extending along a first direction X, the first active region 110 including a first channel region and a first source region 13 and a first drain region 14 located at opposite sides of the first channel region; an NMOS region arranged along a second direction Y with the PMOS region 20, including a plurality of second active regions 120 extending along the first direction X, the second active region 120 including a second channel region 15 and second source regions 16 and second drain regions 17 respectively located at opposite sides of the second channel region 15, the second active region 120 further includes a third channel region and a third source region 18 and a third drain region respectively located at opposite sides of the third channel region; first gates 130, each of the first gates 130 extending along the second direction Y and covering a plurality of first channel regions and a plurality of second channel regions 15, the first gates 130 being electrically connected to the main word line, the first gates 130, the first source regions 130, and the third drain regions 17 respectively located at opposite sides of the third channel region; The first drain region 14 constitutes a pull-up transistor 101, the first gate 130, the second source region 16 and the second drain region 17 constitute a pull-down transistor 102, and the holding transistor includes a first transistor 103 and a second transistor 104; a plurality of second gates 140, each second gate 140 covers a corresponding third channel region, and the second gate 140, the third source region 18 and the third drain region constitute a holding transistor; wherein the first drain of a pull-up transistor 101 The third drain region 14 is electrically connected to the first drain region 14 of a pull-down transistor 102 and is electrically connected to the corresponding sub-word line; the third drain region and the third source region 18 of the same first transistor 103 are electrically connected to the second drain region 17 of two pull-down transistors 102 that share the same first gate 130; the third drain region and the third source region 18 of the same second transistor 104 are electrically connected to the second drain regions 17 of two pull-down transistors 102 that correspond to different first gates 130.

Specifically, the third drain region of the same first transistor 103 is electrically connected to the second drain region 17 of a pull-down transistor 102, the third source region 18 is electrically connected to the second drain region 17 of another pull-down transistor 102, and the two pull-down transistors 102 electrically connected to the same first transistor share a first gate 130; the third drain region of the same second transistor 104 is electrically connected to the second drain region 17 of a pull-down transistor 102, the third source region 18 is electrically connected to the second drain region 17 of another pull-down transistor 102, and the two pull-down transistors 102 electrically connected to the same second transistor 104 correspond to two first gates 130.

The PMOS region 20 is used to form a PMOS transistor. The pull-up transistor 101 is located in the PMOS region 20, that is, the pull-up transistor 101 is a PMOS transistor. The NMOS region is used to form an NMOS transistor. The pull-down transistor 102 is located in the NMOS region, so that the pull-down transistor 102 is an NMOS transistor. The first drain region 14 is used to form the drain of the pull-up transistor 101, and the second drain region 17 is used to form the drain of the pull-down transistor 102. The first drain region 14 of the pull-up transistor 101 is electrically connected to the second drain region 17 of the pull-down transistor 102, and the first drain region 14 and the second drain region 17 are also electrically connected to a sub-word line respectively. In this way, the driving signal for driving the sub-word line can be transmitted from the source of the pull-up transistor 101 to the drain of the pull-up transistor 101, and input to the sub-word line to control the sub-word line driving; the driving signal for closing the sub-word line can be transmitted from the source of the pull-down transistor 102 to the drain of the pull-down transistor 102, and input to the sub-word line to control the sub-word line to be closed. Furthermore, since the pull-up transistor 101 and the pull-down transistor 102 are different types of transistors, when the pull-up transistor 101 is turned on, the pull-down transistor 102 is turned off, so that the pull-up transistor 101 can be used to drive the sub-word line; and when the pull-down transistor 102 is turned on, the pull-up transistor 101 is turned off, so that the pull-down transistor 102 can be used to drive the sub-word line. That is, the pull-up transistor 101 and the pull-down transistor 102 can be used to drive and turn off the sub-word line respectively.

It can be understood that a pull-up transistor 101 and a pull-down transistor 102 can be used to form a sub-word line driver 100 for driving and closing a sub-word line. Since the pull-up transistor 101 and the pull-down transistor 102 are different types of transistors, the pull-up transistor 101 is located in the PMOS region 20, and the pull-down transistor 102 is located in the NMOS region, therefore, in some embodiments, a metal layer may also be included, and the metal layer is used to electrically connect the first drain region 14 of the pull-up transistor 101 and the second drain region 17 of the pull-down transistor 102.

Referring to FIG. 5 , in some embodiments, when the number of the first gates 130 is 2, the number of the first drain regions 14 is 16, and the number of the second drain regions 17 is 16, the first drain regions 14 in the PMOS region 20 are marked as (1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12), (13), (14), (15), and (16); the second drain regions 17 in the NMOS region are marked as (1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12), (13), (14), (15), and (16). When a metal layer is used to electrically connect the first drain region 14 and the second drain region 17, the metal layer can be set to connect the first drain region 14 and the second drain region 17 with the same label. For example, the metal layer can electrically connect the first drain region 14 marked as (1) in the PMOS region 20 and the second drain region 17 marked as (1) in the NMOS region. In this way, after the multiple metal layers are connected to the first drain region 14 and the second drain region 17, the extension direction of the multiple metal layers is consistent, that is, they extend along the second direction Y, which is conducive to simplifying the complexity of the layout. In other embodiments, a metal layer may be provided to connect the first drain region 14 and the second drain region 17 with different labels. For example, the metal layer may electrically connect the first drain region 14 labeled (1) in the PMOS region 20 and the second drain region 17 labeled (2) in the NMOS region. It is only necessary for the metal layer to connect one first drain region 14 to one second drain region 17 in correspondence.

Specifically, in some embodiments, the metal layer and the first draw region 14 and the second draw region 17 can be electrically connected via a conductive plug.

The first gate 130 can serve as a main word line and also as a gate of a plurality of pull-up transistors 101 and a pull-down transistor 102, so that the plurality of pull-up transistors 101 and a pull-down transistor 102 can drive a plurality of sub-word lines in response to an enable signal provided by the first gate 130.

The third drain region is used as the drain of the holding transistor, and the third source region 18 is used as the source of the holding transistor. The third source region 18 and the third drain region of the same holding transistor are electrically connected to the second drain regions 17 of two different pull-down transistors 102, respectively, that is, the source and drain of the same holding transistor are respectively connected to the drains of two different pull-down transistors 102. Since the drains of the two different pull-down transistors 102 are also connected to two different sub-word lines, the source and drain of the same holding transistor are also electrically connected to the two different sub-word lines, respectively, so that one holding transistor can play the role of maintaining the voltage of the two different sub-word lines stable. This is because, at the same time, the word line driver can only drive one sub-word line. For example, if the number of sub-word lines is 2, when one of the sub-word lines connected to the holding transistor is selected, the other sub-word line is in an unselected state. When the selected sub-word line needs to be turned off, the source and drain of the holding transistor are turned on, so that the potential of the selected sub-word line is pulled to the same level as the unselected sub-word line, thereby ensuring that the selected sub-word line can be completely turned off.

Compared with a holding transistor used to control a sub-word line, in the disclosed embodiment, a holding transistor is provided with a source and a drain electrically connected to two sub-word lines respectively, so as to be used to control the two sub-word lines, thereby greatly reducing the number of holding transistors in the word line driver, thereby reducing the layout area of the word line driver.

The holding transistor includes a first transistor 103 and a second transistor 104, wherein the two pull-down transistors 102 electrically connected to the first transistor 103 share a first gate 130. That is, the two pull-down transistors 102 electrically connected to the first transistor 103 correspond to the same main word line, so that the first transistor 103 controls two sub-word lines corresponding to the same main word line. The two pull-down transistors 102 electrically connected to the same second transistor 104 correspond to two first gates 130, respectively, that is, the two pull-down transistors 102 electrically connected to the second transistor 104 correspond to two different main word lines, so that the second transistor 104 can control two different main word lines.

In some embodiments, the NMOS region includes: a first NMOS region 21 and a second NMOS region 22, which are respectively located at opposite sides of the PMOS region 20; wherein the first transistor 103 is located in the first NMOS region 21; the second transistor 104 is located in the second NMOS region 22; a portion of the pull-down transistors 102 are located in the first NMOS region 21, and the remaining portion of the pull-down transistors 102 are located in the second NMOS region 22. Since the two pull-down transistors 102 electrically connected to the first transistor 103 share the first gate 130, and the two pull-down transistors 102 electrically connected to the same second transistor 104 correspond to the two first gates 130, respectively, the connection method between the first transistor 103 and the first gate 130 is different from the connection method between the second transistor 104 and the first gate 130. Therefore, the first transistor 103 is arranged in the first NMOS region 21, and the second transistor is arranged in the second NMOS region 22, which is conducive to forming the first transistor 103 and the second transistor 104 respectively, simplifying the complexity of the layout design. In addition, the pull-down transistor 102 electrically connected to the first transistor 103 is arranged in the first NMOS region 21, and the pull-down transistor 102 electrically connected to the second transistor 104 is arranged in the second NMOS region 22. In this way, when the pull-down transistor 102 is electrically connected to the first transistor 103 and the second transistor 104 respectively, it is conducive to shortening the wiring length of the metal layer, thereby reducing the signal delay in the metal layer.

In some embodiments, each first gate 130 includes: at least two extensions arranged at intervals along the first direction X, extending along the second direction Y and covering a plurality of first channel regions and a plurality of second channel regions 15; and a connecting portion 131 connected to the extensions arranged adjacently along the first direction X. The two extensions cover the plurality of first channel regions and the second channel regions 15, so that one first gate 130 is electrically connected to the plurality of first channel regions and the plurality of second channel regions 15, and is used to control the conduction of the plurality of pull-up transistors 101 and the pull-up transistor 101, so that the pull-up transistor 101 and the pull-up transistor 101 can be used to drive and close the sub-word line, respectively. The connecting portion 131 connects the adjacently arranged extension portions in the first direction X, so that the two spaced extension portions are electrically connected to form a main word line for controlling the conduction of multiple pull-up transistors 101 and the second pull-down transistor.

In some embodiments, the material of the first gate 130 may include at least one of polysilicon or metal.

In some embodiments, the connecting portion 131 covers the area between the adjacent first active regions 110, and also covers the area between the first active region 110 and the second active region 120. Compared with the connecting portion 131 only covering the area between the first active region 110 and the second active region 120, the connecting portion 131 is provided to cover the area between the first active region 110 and the second active region 120 at the same time, so that the volume of the connecting portion 131 is increased, thereby reducing the resistance of the connecting portion 131, which is beneficial to reducing the signal delay, thereby improving the performance of the word line driver.

Specifically, in some embodiments, when there are multiple first active regions 110, the connecting portion 131 may cover the region between each adjacent first active region 110, or may only cover the region between one of the adjacent first active regions 110.

In other embodiments, the connection portion 131 may also only cover the area between the first active region 110 and the second active region 120, so that the process complexity can be reduced and the material for forming the connection portion 131 can be saved.

Referring to FIG. 5 , in some embodiments, along the first direction X, the distance between adjacent extensions of the first NMOS region 21 is greater than the distance between adjacent extensions of a portion of the PMOS region 20, and the second gate 140 corresponding to the first transistor 103 is located between the adjacent extensions. In other words, the distance between adjacent extensions of a portion of the PMOS region 20 is smaller, which reduces the area occupied by the second gate 140, thereby facilitating a reduction in the layout area of the wordline driver. The extensions on both sides of the second gate 140 can serve as gates of two different pull-up transistors 101, and the third drain region of the first transistor 103 and the third source region 18 of the first transistor 103 are electrically connected to the second drain regions 17 of two different pull-down transistors 102. Therefore, when the second gate 140 is located between the two extensions, it is beneficial to form an electrical connection between the first transistor 103 and the second drain regions 17 of the different pull-down transistors 102 on both sides, and the extensions on both sides of the second gate 140 belong to the first gate 130, so that the first transistor 103 is electrically connected to the two pull-down transistors 102 corresponding to the same first gate 130, thereby improving the rationality of the layout.

The extensions on both sides of the second gate 140 belong to the same first gate 130, that is, the same main word line is connected to the two sub-word line drivers 100, and the two sub-word line drivers 100 share the same retention transistor, that is, one main word line corresponds to only one retention transistor. Specifically, the corresponding circuit diagrams can refer to FIG. 3 and FIG. 4. The same main word line is connected to at least two sub-word line drivers 100, and the same main word line corresponds to at least two sub-word lines. In the first region 11, the two sub-word lines connected to the first end and the second end of the first transistor 103 correspond to the same main word line. When the number of sub-wordline drivers 100 in the first region 11 is 8, one main wordline can be connected to 4 sub-wordline drivers 100, one main wordline corresponds to 4 sub-wordlines, and two sub-wordlines share one sub-wordline driver 100, that is, one main wordline corresponds to only 2 retention transistors. When there are two main wordlines, each main wordline corresponds to a different first transistor 103, and a total of 8 sub-wordlines in the first region 11 can be driven, and the number of first transistors 103 is only 8, thereby greatly reducing the layout area of the wordline driver.

Specifically, when the second gate 140 is located between two adjacent extensions, the principle of the word line driver driving the sub-word line and closing the sub-word line can be: take the first gate 130 as the gate of two pull-up transistors 101 and the gate of two pull-down transistors 102 as an example, wherein the two pull-up transistors 101 are respectively recorded as the first pull-up transistor and the second pull-up transistor, and the pull-down transistor 102 are respectively recorded as the first pull-down transistor and the second pull-down transistor, wherein the first pull-down transistor is electrically connected to the source of the holding transistor, and the second pull-down transistor is electrically connected to the drain of the holding transistor.

The principle of driving the sub-word line connected to the first pull-up transistor is as follows: the first gate 130 inputs an enable signal, the gates of the first pull-up transistor and the second pull-up transistor are turned on in response to the enable signal, the first transistor 103 is turned off in response to the low-level second drive signal PXIB, the source of the first pull-up transistor inputs a high-level first drive signal PXID, and the source of the second pull-up transistor inputs a low-level first drive signal PXID, so that the sub-word line connected to the first pull-up transistor has a high level and is driven, and the sub-word line connected to the second pull-up transistor has a low level and is closed.

The principle of closing the sub-word line connected to the first pull-up transistor is as follows: the first gate 130 inputs an enable signal, the gates of the first pull-down transistor and the second pull-down transistor are turned on in response to the enable signal, the first transistor 103 is turned on in response to the high-level second drive signal PXIB, the source of the first pull-down transistor inputs a low-level third drive signal VKK, so that the sub-word line connected to the drain of the first pull-down transistor has a low level, and since the source and drain of the first transistor 103 are respectively connected to different pull-down transistors 102, the level of the sub-word line connected to the first pull-down transistor is pulled down to the level of the sub-word line connected to the second pull-down transistor, so that the sub-word line connected to the first pull-down transistor is closed.

The process of driving the sub-word line connected to the second pull-down transistor and closing the sub-word line connected to the second pull-down transistor is the same as the above process and will not be repeated here.

In some embodiments, the third drain region of the first transistor 103 is shared with the second drain region 17 of a pull-down transistor 102 located in the first NMOS region 21; the third source region 18 of the first transistor 103 is shared with the second drain region 17 of another pull-down transistor 102 located in the first NMOS region 21.

In the first NMOS region 21, the second gate 140 covers the surface of the third channel region so that the formed second gate 140 is electrically connected to the third channel region, and the second gate 140 serves as the gate of the holding transistor, and the third drain region and the third source region 18 on both sides of the third channel region serve as the drain and source of the first transistor 103. The two extensions on both sides of the second gate 140 serve as the gates of two different pull-down transistors 102, respectively, for providing the third driving signal VKK. Among them, the third drain region can serve as the drain of one of the pull-down transistors 102, and the third source region 18 can serve as the drain of the other pull-down transistor 102. The second source region 16 of the two pull-down transistors 102 is located on the side of the extension away from the third gate, and is used as the source of the pull-down transistor 102. In some embodiments, the second source region 16 can also be used as the source of the pull-down transistor 102 corresponding to another first gate 130. In other words, the second drain region 17 of the same pull-down transistor 102 is shared with the third drain region of the holding transistor, and the second source region 16 is shared with the second source region 16 of the pull-down transistor 102 corresponding to another first gate 130. In this way, the occupied area of the second active region 120 can be greatly reduced, thereby improving the integration of the word line driver.

In some embodiments, along the first direction X, the distance between adjacent extensions of the second NMOS region 22 is smaller than the distance between adjacent extensions of some PMOS regions 20, and the second gate 140 corresponding to the second transistor 104 is located outside the area surrounded by the two extensions. In this way, when there are multiple first gates 130 arranged at intervals, the distance between the extensions of different first gates 130 in the second NMOS region 22 is larger, providing more space for forming the second gate 140.

In the second NMOS region 22, the extensions on both sides of the second gate 140 are used as gates of two different pull-up transistors 101, and the extensions on both sides of the second gate 140 belong to different first gates 130, so that the formed second transistors 104 correspond to different main word lines.

The corresponding circuit diagram can be referred to FIG. 3. In the second region 12, two sub-wordline drivers 100 connected to different main wordlines share the same second transistor 104. When the same main wordline is connected to four different sub-wordline drivers 100, one main wordline corresponds to four second transistors 104. Since the two main wordlines share the same second transistor 104, the two main wordlines share four second transistors 104. In other words, the two main wordlines can drive a total of eight sub-wordlines in the second region 12, and the number of holding transistors is still only four, thereby reducing the number of holding transistors in the sub-wordline driver 100, thereby reducing the layout area of the wordline driving circuit. When the sub-word line driver 100 connected to two different main word lines drives the connected sub-word lines, it can respectively respond to the enable signals from different main word lines and drive the connected sub-word lines respectively.

There are 16 sub-wordline drivers 100 in the first area 11 and the second area 12, and each main wordline corresponds to 8 sub-wordline drivers 100, and each sub-wordline driver 100 corresponds to one sub-wordline. In the first area 11 and the second area 12, the total number of retention transistors is 8, that is, the number of retention transistors is only half of the number of sub-wordline drivers 100. It can be understood that no matter how many retention transistors there are in the first area 11 and the second area 12, it is only necessary to satisfy that one retention transistor corresponds to two sub-wordlines, so that the number of retention transistors is only half of the number of sub-wordline drivers 100.

In some embodiments, the third drain region of the second transistor 104 is shared with the second drain region 17 of a pull-down transistor 102 located in the second NMOS region 22; the third source region 18 of the second transistor 104 is shared with the second drain region 17 of another pull-down transistor 102 located in the second NMOS region 22.

The two extensions located on both sides of the second gate 140 belong to different first gates 130 respectively, and are used to form different pull-down transistors 102, that is, the second transistor 104 is electrically connected to the pull-down transistors 102 corresponding to two different first gates 130. The third drain region located on one side of the third channel region can be used as the drain of a pull-down transistor 102 corresponding to a first gate 130, and the third source region 18 located on the other side of the third channel region can be used as the drain of a pull-down transistor 102 corresponding to another first gate 130. Among them, the second source region 16 of the pull-down transistor 102 corresponding to the two different first gates 130 is located on the side of the extension away from the second gate 140. In some embodiments, two adjacent pull-down transistors 102 corresponding to the same first gate 130 can also share the second source region 16, thereby reducing the occupied area of the second active region 120, thereby reducing the layout area of the word line driver.

In some embodiments, each first gate 130 covers 4×N first channel regions and 4×N second channel regions 15, and the pull-up transistor 101 and the pull-down transistor 102 formed by each first gate 130 are electrically connected to 2×N holding transistors; wherein N is a positive integer greater than or equal to 1. In other words, the number of the first channel regions and the number of the second channel regions 15 remain equal, so that the number of the pull-up transistors 101 is the same as the number of the pull-down transistors 102, and each pull-up transistor 101 and the pull-down transistor 102 constitute a sub-word line driver 100. The number of holding transistors is half of the number of pull-up transistors 101 or pull-down transistors 102, so that two sub-word line drivers 100 can share one holding transistor, which is beneficial to reduce the number of holding transistors in the word line driver, thereby reducing the layout area of the word line driver.

Specifically, referring to FIG. 5 and FIG. 3, in some embodiments, N is 2, and there are 2 extensions, wherein one extension covers 4 first channel regions, and one extension also covers 4 second channel regions 15. Based on this, the number of pull-up transistors 101 is 8, and the number of pull-down transistors 102 is 8, constituting 8 sub-wordline drivers 100, each sub-wordline driver 100 corresponds to one sub-wordline, and the number of holding transistors is 4, that is, one holding transistor is used to control 2 sub-wordlines, thereby making one main wordline formed by the first gate 130 used to control 8 sub-wordlines. When the number of first gates 130 is 2, two main wordlines are used to control 8 sub-wordlines.

In other embodiments, referring to FIG. 6 , N can be 4, and there are 4 extensions, wherein one extension covers 4 first channel regions, and one extension also covers 4 second channel regions 15. Based on this, the number of pull-up transistors 101 is 16, and the number of pull-down transistors 102 is 16, constituting 16 sub-word line drivers 100, each sub-word line driver 100 corresponds to one sub-word line, and the number of holding transistors is 8, that is, one holding transistor is used to control 2 sub-word lines, thereby making one main word line formed by the first gate 130 used to control 16 sub-word lines. When the number of the first gate 130 is 2, two main word lines are used to control 32 sub-word lines.

In some other embodiments, N can be 3, the number of extensions is 3, the number of pull-up transistors 101 is 12, the number of pull-down transistors 102 is 12, and 12 sub-word line drivers 100 are formed. Each sub-word line driver 100 corresponds to one sub-word line. The number of holding transistors is 6, that is, one holding transistor is used to control two sub-word lines, so that one main word line formed by the first gate 130 is used to control 12 sub-word lines. When the number of first gates 130 is 2, two main word lines are used to control 24 sub-word lines.

In some embodiments, the PMOS region 20 includes: a first PMOS region 23 and a second PMOS region 24 arranged along the second direction Y, the second PMOS region 24 is located between the first PMOS region 23 and the first NMOS region 21; two extensions of the same first gate 130 cover the same first active region 110 of the first PMOS region 23, and the two extensions also cover two first active regions 110 of the second PMOS region 24 arranged along the first direction X; wherein, along the first direction X, the distance between adjacent extensions of the first PMOS region 23 is smaller than the distance between adjacent extensions of the second PMOS region 24.

The two extensions of the same first gate 130 cover the same first active region 110 of the first PMOS region 23, so that the two extensions of the formed first gate 130 are electrically connected to the same first active region 110 of the first PMOS region 23, thereby forming two pull-up transistors 101. The two extensions respectively cover the two first active regions 110 of the second PMOS region 24 arranged along the first direction X, so that the two extensions are electrically connected to the two first active regions 110, respectively, to form two pull-up transistors 101. Since the two extensions of the first gate 130 are located on the same active region, the distance between the adjacent extensions of the first PMOS region 23 is smaller, so that the area occupied by the first gate 130 can be reduced, thereby reducing the layout area.

In some embodiments, the pull-up transistor 101 corresponding to the first PMOS region 23 shares the first source region 13, and the shared first source region 13 receives the first driving signal PXID.

In the first active region 110 of the first PMOS region 23, each extension covers a first channel region, and the first source region 13 is located between the two first extensions and is used to input the first drive signal PXID. The first drain region 14 is located on the side of the channel region away from the first extension and is used to form a pull-up transistor 101. Among them, the number of first source regions 13 located between the two first extensions can be 1, and the number of first drain regions 14 can be 2, that is, the two pull-up transistors 101 share the same first source region 13, which is beneficial to improve the integration of the formed word line driver and further reduce the layout area.

In the first active region 110 of the second PMOS region 24, each extension covers a first channel region, and the first source region 13 and the first drain region 14 are located on both sides of the first channel region. The first drain region 14 can be located between the two extensions, and the first source region 13 is located on the side of the extension far from the first channel region. In this way, in the second PMOS region 24, the two pull-up transistors 101 do not share the first source region 13, which can prevent the first driving signal PXID input to the source of the pull-up transistor 101 from being damaged due to the excessive number of pull-up transistors 101 sharing the same source, thereby causing the problem of being unable to drive the corresponding sub-word line. In some embodiments, the first source region 13 in the second PMOS region 24 can be used as the source of the pull-up transistor 101 corresponding to another first gate 130. Thus, when there are multiple first gates 130, the size of the overall active region can be smaller, thereby making the layout area smaller.

Referring to FIG. 6 , in some embodiments, a connecting portion 131 is provided between two extensions of the same first gate 130 . The connecting portion 131 is used to electrically connect the two extensions. The connecting portion 131 is located between the first PMOS region 23 and the second PMOS region 24 and between the first NMOS region 21 and the first PMOS region 23 . The length of the connecting portion 131 is equal to the distance between the two extensions.

Referring to FIG. 7 , in some other embodiments, the length of the connecting portion 131 between the first NMOS region 21 and the first PMOS region 23 may be greater than the length between two adjacent extension portions. Thus, the length of the connecting portion 131 is longer, thereby increasing the volume of the first gate 130 and reducing the resistance of the first gate 130, thereby improving the transmission rate of the electrical signal.

In addition, the first gate 130 further includes: an extension portion 132, the extension portion 132 extends in the first direction X, and the extension portion 132 is connected to the extension portion. Referring to FIG. 7, the number of the extension portions 132 can be 2, and the two extension portions 132 are located between the two adjacent first active regions 110 in the second PMOS region 24, and are also located between the two adjacent extension portions. The two extension portions 132 are arranged opposite to each other and are not connected. The provision of the extension portion 132 can further increase the volume of the first gate 130, which is conducive to further reducing the resistance of the first gate 130, and when the enable signal is transmitted through the first gate 130, the delay can be reduced.

Referring to FIG. 8 , in some other embodiments, an extension portion 132 may be provided between two adjacent first active regions 110 in the first PMOS region 23, and an extension portion 132 may be provided between the second PMOS region 24 and the second NMOS region 22, so that the space can be fully utilized, the volume of the first gate 130 is larger, and the resistance of the first gate 130 is reduced. Considering that the distance between the two adjacent extension portions 132 in the first PMOS region 23 is smaller than the distance between the two adjacent extension portions 132 in the second PMOS region 24, the two extension portions 132 in the first PMOS region 23 may be provided outside the region surrounded by the two adjacent extension portions, so that the two extension portions 132 are separated.

In addition, referring to FIG. 6, FIG. 7 and FIG. 8, the region between the first PMOS region 23 and the first NMOS region 21, the region between the first PMOS region 23 and the second PMOS region 24, the region between the adjacent first active regions 110 in the first PMOS region 23, and the region between the adjacent first active regions 110 in the second PMOS region 24 can be used to form an isolation structure. The existence of the isolation structure may cause a hot-electron-induced punchthrough (HEIP) effect, thereby forming a breakdown current between the two active regions. Therefore, referring to FIG. 6 , a connection portion 131 is provided in the region between the first PMOS region 23 and the first NMOS region 21, and a connection portion 131 is provided between the first PMOS region 23 and the second PMOS region 24, which not only allows the two extensions to be electrically connected, but also prevents the breakdown effect caused by the isolation structure. Similarly, referring to FIG. 7 , an extension portion 132 is provided between adjacent first active regions 110 in the second PMOS region 24, which prevents the breakdown effect between adjacent PMOS transistors formed in the second PMOS region 24. Referring to FIG. 8 , an extension portion 132 is also provided between adjacent first active regions 110 in the first PMOS region 23, and an extension portion 132 is provided between the second PMOS region 24 and the second NMOS region 22, which can further prevent the breakdown effect between adjacent PMOS transistors formed in the first PMOS region 23.

It is understandable that when two active regions with different doping types are adjacent to each other, a breakdown effect will occur. Specifically, when the circuit formed by the two active regions with different doping types is an analog circuit, the potentials may be different from each other. When the difference in potential between the two active regions is large enough, the depletion region of the active region will expand outward, thereby forming a breakdown current between the two active regions and generating electrical interference. Based on this, in some embodiments, the plurality of first active regions 110 include: at least two first active regions 110 disposed near the NMOS region, the two first active regions 110 are arranged at intervals along the first direction X and have an interval region, wherein the second gate 140 and the interval region are disposed opposite to each other along the second direction Y. That is, the extension direction of the second gate 140 is the same as the extension direction of the spacer, and the second gate 140 is located on the extension line of the spacer. The second gate 140 is used to cover the third channel region, that is, the third channel region is directly opposite to the spacer. The spacer is used to form an isolation structure between two first active regions 110 arranged at intervals. Therefore, the second gate 140 is arranged directly opposite to the isolation structure, so that the third channel region of the second source region 16 and the first channel region of the first source region 13 are not adjacent, which is conducive to improving the breakdown effect.

In the word line driver provided by the above embodiment, the third source region 18 and the third drain region of the same holding transistor are electrically connected to the second drain regions 17 of two different pull-down transistors 102, that is, the source and drain of the same holding transistor are respectively connected to the drains of two different pull-down transistors 102, and the first transistor 103 is set to control the two sub-word lines corresponding to the same main word line, and the second transistor 104 controls the two sub-word lines corresponding to two different main word lines. Compared with one holding transistor used to control one sub-word line, the number of holding transistors in the word line driver can be greatly reduced, thereby reducing the layout area of the word line driver.

Correspondingly, the disclosed embodiment also provides a storage device, including: a storage cell array, including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driving circuit provided by any of the above items; or a word line driver provided by any of the above items. In some embodiments, the storage cell may be a DRAM storage cell.

In some embodiments, the present invention further comprises: a signal generating circuit configured to output a first drive signal PXID and a second drive signal PXIB, and the positive edge timing of the second drive signal PXIB is delayed by a preset time length compared to the negative edge timing of the first drive signal PXID. Specifically, referring to FIG. 4, when the sub-word line is closed, the potential of the first drive signal PXID is first pulled low, and after the potential of the first drive signal PXID is pulled low for a period of time, the potential of the second drive signal PXIB is pulled high, that is, the time when the potential of the second drive signal PXIB is pulled high is later than the time when the potential of the first drive signal PXID is pulled low. When the second drive signal PXIB is at a high level, the transistor is kept in the off state. This can keep the transistor in the off state for a longer time and slow down the aging speed of the transistor.

Referring to FIG. 9 , in some embodiments, the signal generating circuit includes: a decoder 150 configured to output a first driving signal PXID; a PMOS transistor 151, a gate receiving the first driving signal PXID, one end receiving the original driving signal, and the other end connected to an inverter 152, the inverter 152 outputs a second driving signal PXIB, wherein the edge timing of the original driving signal is consistent with the edge timing of the first driving signal PXID. In other words, the original driving signal is consistent with the first driving signal PXID, and the source of the PMOS transistor 151 receives the original driving signal, and the drain is connected to the inverter 152. Thus, when the PMOS transistor 151 is turned on, the original driving signal is transmitted from the source of the PMOS transistor 151 to the drain of the PMOS transistor 151, and then after passing through the inverter 152, the output second driving signal PXIB is opposite to the potential of the original driving signal, that is, opposite to the potential of the first driving signal PXID.

Specifically, in some embodiments, taking the example of closing the sub-word line when the first driving signal PXID is at a low level, when the sub-word line needs to be closed, the principle of the signal generating circuit generating the first driving signal PXID and the second driving signal PXIB is as follows: The decoder 150 outputs the low-level first driving signal PXID, and the gate of the PMOS transistor 151 responds to the low-level first driving signal PXID. The driving signal PXID is turned on; the source of the PMOS transistor 151 receives the low-level original driving signal, and the original driving signal is transmitted to the drain through the source of the PMOS transistor 151, and then outputs the high-level second driving signal PXIB after passing through the inverter 152, keeping the transistor turned on based on the high-level second driving signal PXIB, thereby closing the sub-word line. Since the original drive signal needs to be inverted by the inverter 152 to form the second drive signal PXIB, and then transmitted to the gate of the holding transistor, that is, the inverter 152 plays a buffering role, the positive edge moment of the second drive signal PXIB has a preset time delay compared to the negative edge moment of the first drive signal PXID.

Ordinary technicians in this field can understand that the above-mentioned implementation methods are specific embodiments of the present disclosure, and in actual application, various changes can be made to them in form and details without deviating from the spirit and scope of the present disclosure. Any technician in this field can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the scope defined by the patent scope.

11: First region 12: Second region 100: Sub-word line driver 101: Pull-up transistor 102: Pull-down transistor 103: First transistor 104: Second transistor

Claims (10)

A word line driver circuit includes: 4×N sub-word line drivers, each of which is connected to a main word line and a sub-word line, and the main word line is used to provide an enable signal; the 4×N sub-word line drivers include 2×N holding transistors, the first end and the second end of the holding transistor are respectively connected to different sub-word lines, and the gate of the holding transistor receives a second driving signal; the sub-word line driver is configured to provide the first driving signal to the selected sub-word line in response to the first driving signal and the enable signal. signal; in response to the first drive signal, the enable signal and the second drive signal, the first end and the second end of the holding transistor are turned on; wherein the 2×N holding transistors include at least one first transistor and at least one second transistor, the two sub-word lines connected to the first end and the second end of the first transistor correspond to the same main word line, and the two sub-word lines connected to the first end and the second end of the second transistor correspond to different main word lines; N is a positive integer greater than or equal to 1. The word line driving circuit as described in claim 1, wherein the selected sub-word line is the sub-word line connected to the first end or the second end of the holding transistor; the sub-word line driver comprises: a pull-up transistor, a gate connected to the main word line, a source receiving the first driving signal, and a drain connected to the sub-word line and the first end or the second end of the holding transistor; a pull-down transistor, a gate connected to the main word line, a drain connected to the drain of the pull-up transistor, and a source receiving a third driving signal. A word line driver comprises: a PMOS region, comprising a plurality of first active regions extending along a first direction, the first active region comprising a first channel region and a first source region and a first drain region respectively located on opposite sides of the first channel region; an NMOS region, arranged along a second direction with the PMOS region, comprising a plurality of second active regions extending along the first direction, the second active region comprising a second channel region and a second source region and a second drain region respectively located on opposite sides of the second channel region, the second active region further comprising a third channel region and a third source region and a third drain region respectively located on opposite sides of the third channel region; a first gate, each of the first gates extending along the second direction and covering a plurality of the first channel regions and a plurality of the second channel regions, the first gate being electrically connected to a main word line, the first gate, the first source region and the first drain region ... A pull-up transistor is formed by a drain region, the first gate, the second source region and the second drain region form a pull-down transistor, and the holding transistor includes a first transistor and a second transistor; a plurality of second gates, each of the second gates covers a corresponding third channel region, the second gate, the third source region and the third drain region form the holding transistor; wherein the first drain region of the pull-up transistor is electrically connected to the first drain region of the pull-down transistor and is electrically connected to the corresponding sub-word line; the third drain region and the third source region of the same first transistor are electrically connected to the second drain regions of the two pull-down transistors sharing the same first gate; the third drain region and the third source region of the same second transistor are electrically connected to the second drain regions of the two pull-down transistors corresponding to different first gates. A word line driver as described in claim 3, wherein the NMOS region includes: a first NMOS region and a second NMOS region, respectively located on opposite sides of the PMOS region; wherein the first transistor is located in the first NMOS region; the second transistor is located in the second NMOS region; a portion of the pull-down transistors are located in the first NMOS region, and the remaining portion of the pull-down transistors are located in the second NMOS region. As described in claim 4, each of the first gates includes: at least two extensions arranged at intervals along the first direction, extending along the second direction and covering a plurality of the first channel regions and a plurality of the second channel regions; and a connecting portion connecting between two adjacent extensions along the first direction. A word line driver as described in claim 5, wherein the connecting portion covers the region between the adjacent first active regions, and also covers the region between the first active region and the second active region; along the first direction, the distance between the adjacent extensions of the first NMOS region is greater than the distance between the adjacent extensions of some of the PMOS regions, and the second gate corresponding to the first transistor is located between the adjacent extensions; along the first direction, the distance between the adjacent extensions of the second NMOS region is less than the distance between the adjacent extensions of some of the PMOS regions, and the second gate corresponding to the second transistor is located outside the region surrounded by the two extensions. A word line driver as described in claim 6, wherein the PMOS region includes: a first PMOS region and a second PMOS region arranged along the second direction, the second PMOS region being located between the first PMOS region and the first NMOS region; the two extensions of the same first gate cover the same first active region of the first PMOS region, and the two extensions also respectively cover two first active regions of the second PMOS region arranged along the first direction; wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is smaller than the distance between adjacent extensions of the second PMOS region. The word line driver as described in claim 3, wherein each of the first gates covers 4×N first channel regions and 4×N second channel regions, and the pull-up transistor and the pull-down transistor formed by each of the first gates are electrically connected to 2×N holding transistors; wherein N is a positive integer greater than or equal to 1; the plurality of first active regions include: at least two first active regions disposed close to the NMOS region, the two first active regions are spaced apart along the first direction and have a spacer region, wherein the second gate and the spacer region are disposed opposite to each other along the second direction. A storage device, comprising: a storage cell array, including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driver circuit as described in claim 1 or 2, or a word line driver as described in any one of claims 6-8. The storage device as described in claim 9, further comprising: a signal generating circuit configured to output a first drive signal and a second drive signal, and the positive edge timing of the second drive signal has a preset time delay compared to the negative edge timing of the first drive signal; the signal generating circuit comprises: a decoder configured to output the first drive signal; a PMOS transistor, a gate receiving the first drive signal, one of a source and a drain receiving the original drive signal, and the other connected to an inverter, the inverter outputting the second drive signal, wherein the edge timing of the original drive signal is consistent with the edge timing of the first drive signal.

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