GB2332967A

GB2332967A - SRAM having a single bit line and a reference voltage generator

Info

Publication number: GB2332967A
Application number: GB9828837A
Authority: GB
Inventors: Jin Hyeok Choi
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1997-12-30
Filing date: 1998-12-30
Publication date: 1999-07-07
Anticipated expiration: 2018-12-30
Also published as: JPH11328969A; GB2332967B; GB9828837D0; KR19990057810A; KR100275106B1

Abstract

In a static RAM having an access transistor 41, coupling input /output data from single bit line BL to a latch circuit 42-45 for storing data, a word line WL for applying a voltage to a gate of the access transistor 41, a sense amplifier (SA21- SA28, Fig 4) for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line BL, and a voltage generator for providing the reference voltage to the sense amplifier, a voltage on the word line WL is increased for a write operation. A further aspect relates to an SRAM including memory cells having an access transistor 41 and a latch circuit 42-45, word lines for applying voltages to a gate of the access transistor, dummy cells (200, Fig 4), a sense amplifier (SA21-SA28) coupled to a global bit line (GBL) for sensing the difference between a reference voltage, provided by one of the dummy cells through a dummy bit line (DBL), and a voltage on the global bit line (GBL) and a switch (101) for selectively coupling the global bit line to one of the local bit lines BL.

Description

.SRKM DEVICE HAVING A TINGLE BIT LINE AND R REFERENCE VOLTAGE GENERATOR Field of the Invention The present invent on relates to SRAM memory devices; and, more particularly, tolSPSM memory devices to reduce the chip size by providing a siwple cell structure.

Description of the Prior Art First, referring to Fig. 1, the conventional SRAM cell includes two access transistors 305 and 306, two drive transibtors 303 and 304 and two MOS transistors 301 and 302. The PMOS transistors 301 is coupled to the drive transistors 303 in order to form a first inverter and the PMOS transistors 302 is coupled to the drive transistors 304 in order to form a second inverter. As a result, the SANK cell in Fig. 1 may be have a latch circuit between nodes A and B as shown in Fig. 2. Accordingly, the latch circuit stores data and the stored data is transferred to a bit lines (hereinafter, referred to as BL) and a bit bar lines (hereinafter, referred to as /BL) in response to a word line signal which control the access transistors O5 and 306. The SRAS cell, as shown in Fig.

1, necessarily comprises the BL and the /BL. The SRAM cell has a latch structure in which two inverters engage with their input and output terminals and it is #available to read and write data by controlling the access transistor provided at each of nodes A and B. For example, if 'high' data: is stored at node A which is coupled to the BL and 'low' data at node B, this cell has data '1' in it and; otherwise, this cel data 'O' in it.

At a read operation, if the voltage of word line goes up, the access transistors 305 and 306 are turned on and transfer the voltage at node A and node B to the BL and the /BL, respectively.

At this time, the voltage difference between the BL and the /BL is delivered to a sense ampiifier through data bus line illustrated in the cell array of Fig. 3. The sense amplifier senses and amplifies the voltage difference so that data '1' is read out if the voltage on the BL is higher than that on the /BL and; otherwise, data O' is read out.

At a write operaticn, in the case where data ult is written in the cell, the voltage Vdd is applied to the BL and OV is applied to the /BL. Nodes A. and B are in high and low voltage levels, respectively. Accordingly, the drive transistor 304 of which gate is connected to node A is turned on so that thee voltage level at .node B is becoming less and the drive transistor 303 of'w'hitdh gate is connected to node B is turned off so that thee voltage level at node A is becoming much adore. In the case of '0', only the voltages on the BL and the /BL are reverse, the result of which is the same as the foregoing.

Next, the reason the SRAM cell must be composed of a pair of bit line (BL and /BL) will be explained as below.

First, at the read operation, the voltage difference between two bit lines is used or sensing data stored in the SRAM cell.

That is, the SRAM cell compares voltages on the BL and /BL within the same cell, thereby providing the reliability even for a littie change of voltage.

Second, at the read operation, there may be an environment in which the voltages at the nodes corresponding to '0' out of data stored in SRAM cell is increased. In this case, if the voltages at the nodes are too much increased, a node having a low voltage level can be changed to another node having a high voltage level by a week noise. If another line such a bit bar line /BL maintains higher voltage level, such an erroneous inversion may be prevented during the read operation.

Third, at the write operation, in the case where data stored in SRAD should be inverted to be recognized as different value, the bit line paiT is needed. That is, when the SRAM cell in which '0' is stored must have data '1', each voltage at node A and B in Fig.

2 must be changed at the same time so as to invert such data.

Accordingly, two input termanals corresponding to the BL and the /EL are required, respectively.

Due to such reasons, it has been thought that there are naturally both the BL and the /BL in the SRAM cell. Fig. 3 is a circuit diagram illustrating a cell array of the SRAM device having such bit line pairs.

As stated above, since the conventional SRAM device are in need of the bit line pius (BL and /BL) in column arrays C1 to CN, data bus line pairs corresponding to such bit line pairs are also required. In particular, a plurality of the data bus line pairs DB1 to DE8 and /DD1 to /DBS are required to reduce the increase of the parasite capacitance so that the desired chip area becomes larger.

Zn Fig. 3, the reference numerals 10, 20, 30 and 40 denote a cell, a column decoder, an input driver and a transfer gate, respectively .

However, with the increase of the integration of the SRAM device a simple cell which occupies the smaller chip area will be required in order to improve the integration of SRAM. Too many cells connected to a bit line bring about the increase of the parasite capacitance and the delay in the output of data; on the contrary, a static RAM device having a few cells, which are connected to the bt line, generally cause circuits to be complicated and the c;zip size to be larger.

These problems may happen even in word lines as well as bit lines, but the problem caused in the word line has been settled by use of a hierarchical. stricture. The large the capacity-of chip grows, the more necessary such a hierarchical structure becomes, but it is difficult for the hierarchical structure to be introduced even in bit line because there is a problem in that the manufacturingcost may be raised due to additional layers required for the hierarchical structure of the bit line.

Summary of the Invention It is, therefore, an object of the present invention to provide a static RAM memory device capable of decreasing chip area by diminishing the number of wire and the size of memory cell and by providing the reliable read and write using a single bit line, Another object of t.' present entlon is to provide a static .RAM memory device capable of implementing a hierarchical structure if bit lines.

In accordance with an aspect of the present invention, there is provided b static RAM memory device comprising: an access transistor; a latch circuit storing data, being coupled to the access transistor; a word line applying voltage to a gate of the access transistor; a single bit line transferring data between the latch circuit and an input/output means, wherein the access transistor is coupled between the single bit line and the latch circuit; a sense amplifier for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line; a voltage generating means for providing the reference voltage for the sense amplifier; and a voltage increasing means for increasing a voltage on the word line at a write operation In accordance with a further aspect of the present invention, there is provided a static RAM memory device comprising: an access transistor; a latch circuit storing data, being coupled to the access transistor; a word line applying voltage to a gate of the access transistor; a sinle bit line transferring data between the latch circuit and an input/output means, wherein the access transistor is coupled between the single bit line and the latch circuit, a sense amplifier for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line; a voltage generating means for providing the reference voltage for the sense amplifiers a voltage increasing means for. increasing a voltage on the word line at a write operation; and a voltage generating means for providing the latch circuit with a first voltage a read operation and a second voltage at the write operation.

In accordance wits another aspect of tfle present invention, there is provided a static EAM memory device comprising: a) a first inverter including: 2-1) a first PMOS transistor hating a source coupled to a first power supply a-2) a first NMOS having- a drain coupled to a drain of the first PMOS transistor, a source coupled to a second power supply, and a gate coupled to a gate of the first PMOS transistor; ) a second inverter including; b-l) a second PMOS transistor having a source coupled to the first power supply, and b-2) a second;NMOS having a drain coupled to the gate of. the first PMOS transistor and a drain of the second PMOS transistor, a source coupled to the second power supply and a gate coupled to the gate of the second PMOS trcasistor, and the drain of the first PMOS, transistor: c) a third NMOS transistor having a first terminal coupled to the drain of the first PMOS transistor and the gate of the second PMOS transistor, a second terminal coupled to a single bit line, and a gate coupled to a word line; d) a sense amplifier for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line; and e) a voltage generating means for providing the reference voltage for the sense amplifier.

In accordance with a still another aspect of the present invention, there is provided a static RAM memory device comprising: a plurality of memory cells including one access transistor and a latch circuit which is coupled to the access transistor in order to store cell data; a plurality of word lines for applying a voltage to a gate of the access transistor; a plurality of dummy cells; a sense amplifier coupled to a global bit line and a dummy bit line for sensing and amplifying a voltage difference between a reference voltage and a voltage on the global bit line, wherein the reference voltage is provided by one of the dummy cells through the dummy bit line; a plurality of local bit lines coupled to the memory cells through the access transistor, wherein the global bit line is selectively coupled to one of the plurality of local bit lines; and a switching means for selectively coupling the global bit line to one of the plurality.

Brief Description of the Drawings The above and other and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram illustrating a conventional SRAM cell having a bit line pair; Fig. 2 is a circuit diagram illustrating read and write operations of memory cell in Fig. 1; Fig, 3 is a circuit diagram illustrating a cell array in the SRAM device having bit line pairs, Fig. 4 is a circuit diagram illustrates, a cell array of a static RAM device having a single bit line in accordance with the present invention; Fig. 5 i a circuit diagram illustrating a static RAM unit cell having a single bit line in accordance with the present invention; Fig. 6 is a graph showing a signal transmission characteristic of a CMOS inverter; Fig 7a is a graph showing a voltage characteristic at a read operation of the SRAM device in Fig. 4; Fig. 7b is a graph showing a voltage characteristic at a write operation of the SRAM device' in Fig. 4; Fig. 8 is a view ilustrating a hierarchical structure of the SRAM device in Fig. 4; Fig. 9a is a block diagram illustrating a hierarchical structure of the conventional SRAM device having the bit line pair of Fig. 3; Fig. 9b is a block diagram illustrating a hierarchical structure of the SRAM device in accordance with the present invention; and Fig. 9c is a view illustrating transfer gates in implementing the hierarchical structure of Fig. 9b.

Detailed Descrition of the Preferred Embodiments Hereinafter, the ir.vention will be described in detail by the following preferred embodiment referring to the accompanying drawings.

First of all, the present invention can be implemented by providing a new voltage source generating preference voltage which may be substituted for a voltage on a bit bar line.

The first reason nor the necessity of bit bar line will be overcome as follows: the necessity for toltage-comparison required at a read operation is r-smoved by using a reference voltage from a dummy cell in which data '1' is always stored so that the voltage level from the dunny cell is compared with the voltage on E single bit line in SRAM cell during data sensing operation.

Fig. 4 illustrates a cell array of a static RAM device having such dummy cells. As shcwn in Fig. 4, the SRAM device according tb the present invention includes 'a plurality of cell blocks SC1 to SCN having a plurality of cells and further includes a dummy cell block SD. For example, if the device has 128 cell blocks, the dummy cell block SD may have 128 dummy cells. That is, each of the cell block SC1 to SCN corresponds to one dummy cell. Each of the cell block SC1 to SCN includes a global bit line GBL which is selectively coupled to a plurality of single bit lines BX through a transfer gate (BTG) 101. Furthermore, each of single bit lines fiL is connected to a plurality of memory cells 100. Likewise, the dummy cell block SD includes a dummy global bit line DG3L which are selectively coupled to a plurality of dummy single bit lines DBL through transfer gates (TG) 201 and each of dummy single bit lines DEL is connected to a plurality of dummy cells 200. As shown in Fig. 4, since a bit bar line is not needed, petal lines used as bit bar lines can be used for the hierarchical structure with the increase of the integration of device.

Also, the single bit line according to the present invention contributes to the reduction of the number of data bus lines DE21 to DB28. That is, since the SRPIM device according to the present invention uses the single bit lines BL, a data bus line to be connected to the single bit line BL is formed by a single metal line without a pair structure.

For example, in the case where a first cell block SC1 is selected through the transfer gate 140 in response to an output from a :olumn decoder 21 at the read operation and one memory cell is selected through the transfer gate 101, a specific dummy cell is selected at the same tire. Information stored in the memory cell is output to the data bus line DB21 via the transfer gate 101, the global bit line and the transfer gate 140 and information stored in the selected dummy cell is output to a dummy data bus line DDB which is couple to the dummy global bit line DGBL.

Accordingly, sense amplifiers SA21 to SA28 senses and amplifies voltage difference between the data bus line DB21 and the dusmy data bus line DDB. Further, the dummy data bus line DDB may be not connected to the column decoder 21 because the data from e dummy cell must be read out as a reference voltage whenever a memory cell is selected in the cell block. In order to use the dummy cell data as a reference voltage, each dummy cell must store data 'l'.

The present invention shows a method for differentiating the cell ratio at the read and write operations in order to settle the above second and third reasons why a bit bar line must be provided and another method for changing Vdd voltage permitted to cell at the write operation. Furthermore, it.is possible to simultaneously employ the above two method, Fig. 5 is a circuit diagram illustrating a static RAM unit cell having a single bit line in accordance with the present invention. As shown in Fig. 5, the SRAM cell according to the present invention includes two MOS transistors 42 and 43, two drive transistors 44 and 45 and only one access transistor 41.

Accordingly, in comparison with Fig. 1, there is seen more simple structure in which an access transistor and a bit bar line are removed. Also, as stated above, the dummy cell in Fig. 4 always output data '1'. The sense amplifier which is below the cell array, as different from the conventional SRAM to sense the voltage difference between the bit line and the bit bar line, senses '0' and '1' by comparing the voltage from the dummy cell with that from the memory cell coupled to the single bit line. Owing to such a method, the necessity of the bit bar line required to sense the stored data can be removed.

In the SRAM device according to the present invention, the. following method is used for preventing cell data '0' at the read operation from being inverted to data '1' and, otherwise, for effectively inverting the cell data at the write operation. That is, as different from the prior method .wherein the word line bootstrap is used at both read and write operations and a word line voltage is never changed at both read and write operations, the present invention can affectively settle the above problems by using word line bootstrap not at the read operation but at the write operation.

In Fig. 2, if the state of an inverter C is inverted during the read operation, cell data may be damaged. Fig. 6 shows a characteristic of signal transmission of the inverter C in Fig. 2, As shown in Fig. 6, if an input voltage goes up a specific voltage to invert the inverter C, this means a low-to-high logic transition is achieved. The chara=teristic of signal transmission can be changed into A or B in Fig. 6 by changing the size of PMOS and NMOS transistor of the inverter C.

The value, which is obtained by dividing the current drivability of the drive transistor 303 in Fig. 1 by the current drivability of the access transistor 305, is Cell Rate (hereinafter, referred to as "CR"). If the CR is small, the voltage at node A in Fig. 2 is increased at the read operation, and if the voltage is higher than that in which the characteristic of signal transmission in Fig. 6 is inverted, there is a probability of data inversion. This is not such a good thing because the above probability means that, at the same time as the data 'O' is read out from the cell storing data 101, the stored value ('0') of the cell is inverted to '1'. If an operation voltage is 3V, the voltage at which the characteristic of signal transmission is inverted is 1.2V and CR is 2, the voltage at the read operation represents a value of Vdd/(CR+l) of .or. That is, data stored in the cell is inverted at 1.2 V, but, in this case, it is apparent that the voltage is increased only to 1.OV at the read operation.

Accordingly, the stable read operation can be obtained by controlling CR from the beginning of cell design.

On the contrary, at the write operation, the voltage applied to a gate of the access transistor is increased through the word line bootstrap method, in which CR becomes smaller because the dritability of the access transistor is increased.

If the value is set to '1', the voltage at node A is 1.5 at write operation and previously stored data '0' is inverted into data w because the inversion voltage to change the characteristic of signal transmission is 1.2V. In the case of data '0, since the drivability of the access transistor is higher than that of the PMCS transistor 301, there is no problem in writing data roX, By using a differen word line voltage at the write operation, the read and write operations are executed through the variation of the CR. However, it is difficult to design such a cell because the CR to satisfy a specific condition should be designed. For example, if the CR is designed to be changed from 2 to 1, the inversion voltage to change the characteristic of signal transmission should be designed to be changed from l.OV to 1.5V. Actually, it is not sufficient to comply with the variations of the operating voltage and the processing conditions by applying the word line voltage variation to the write operation.

Accordingly, in order to provide the same effect as the word line voltage variation, the present invention decrease a power supply voltage Vdd applied to the cell at the write operation.

In other words, the read operation is carried out by maintaining the power supply voltage Vdd (about 3v) at the read operation and the write operation is curried out in a low voltage (about 2V) less than the power supply vcltage Vdd. By decreasing the power supply voltage Vdd at the write operation, the drivability of the drive transistors becomes lower with the low cell ratio (CR). Therefore, the data inversion may be easily achieved by lowering a voltage level required to invert cell data.

Further, if the word line bootstrap and the low Vdd power supply are used at the write operation, relatively stable read and write operations may be achieved. Based on such a stable operation, a processing margin in manufacturing elements, such as transistors, may be easily obtained as well as an architecture design margin.

That is, even if the CR is varied within a few tens of percentage due to the variation of the processing conditions and the operation voltage is varied within a predetermined range, the present invention may secure stable read and write operations.

Referring to Fig. ?a showing a voltage characteristic at the read operation, a cell cel which has selected a word lone wll stores data '0' and another cell ce2 which has selected a word line w12 stores data '1'. The data stored in each cell are output via a data bus line db. As shorn in Fig. 7a; the cell supply voltage vcel and the word line voltage are set to approximately 3V at the read operation.

On the other hand, referring to Fig. 7b showing a voltage characteristic at the write operation, the word line voltage is increased from 3V to 4V through a typical bootstrap circuit and the cell supply voltage vcel is decreased. As shown in Fig. 7b, data 'O' stored in a cell cel is dramatically inverted into data '1' and also data '1' stored in a cel2 is dramatically inverted into data lOr.

Furthermore, the present invention having a single bit line may easily implement a hierarchical structure. Fig. 8 is a view illustrating a hierarchical structure in accordance with the present invention. In Xig. e, a metal line A is connected to a plurality of memory elements having a large parasite capacitance, which corresponds to a conventional SRAM cell array having the bit line pair of Fig. 3. however, as shown in Fig. 4, by using the single bit line in the SRAM cell array, the bit bar line can be used as a global bit line which corresponds to a metal line B in Fig. a.

Fig. 9a shows a hierarchical structure of the conventional SRAM device having the bit line pair of Fig. 3. Fig. 9b shows a hierarchical structure of the SRAM device in accordance with the present inventlon. For example, a column having 512 cells, as shown in Fig. 9a, can be divided into 4 columns each of which has 128 cells, as shown in Fig. 9b. 128 cells are connected to the single bit line according to the present invention and the single bit lines are connected to a global bit line through transfer gates BTG.

Fig. 9c is a view illustrating the transfer gates BTG in implementing the hierarchical structure of Fig, 9b. The transfer gates BTG includes switching transistors in response to a control signal which is generated by column addresses. Accordingly, the hierarchical structure according to the present invention may be easily implemented in the cell array by adding transfer gates connecting a plurality of single bit line to the global bit line.

As apparent from the above, the present invention has effects on the integration of the SRAM cell by removing the bit bar line and one access transistor and by implementing the hierarchical structure in the cell array.

While the present invention has been disclosed with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

What is claimed is:

1. A static RAM memory device comprising: an access transistor, a latch circuit s-oring data, being coupled to the access transistor; a word line applying voltage to a gate of the access transistor; a single bit line transferring data between the latch circuit and an input/output means, wherein the access transistor is coupled between the single bit line and the latch circuit; a sense amplifier for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line; a voltage generating means for providing the reference voltage for the sense amplifier; and a voltage increasing means for increasing a voltage on the word line at a write operation.

2. The static RAM memory as recited in claim 1, wherein the reference voltage is prcvided by a dummy cell.

3. The static RAM memory as recited in claim 2, wherein the latch circuit comprises two inverters which are cross-coupled and wherein each inverter comprises a PMOS transistor and an NMOS transistor.

4. The static RAM memory as recited in claim 3, wherein drivability of the access transistor is higher than that of the latch circuit.

5. The static RAM memory as recited in claim 3, wherein a cell ratio between the access transistor and the NMOS transistor of the latch circuit is selected in order that a signal transmission characteristic is not inverted at a read operation.

6. The static RAM memory as recited in claim 3, wherein a cell ratio at a read operation is different form that at the write operation.

7. The static RAM memory as recited in claim 6, wherein the cell ratio at the read operation is higher than that at the write operation.

8. A static RAN memory device comprising: an access transistor; a latch circuit storing data, being coupled to the access transistor; a word line applying voltage to a gate of the access transistor; a single bit line transferring data between the latch circuit and an input/output means, wherein the access transistor is coupled between the single bit line and the latch circuit; a sense amplifier for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line; a voltage generating means for providing the reference voltage for the sense amplifier; a voltage increasing means for increasing a voltage on the word line at a write operation; and a voltage generating means for providing the latch circuit with a first voltage a read operation and a second voltage at the write operation.

9. The static RAN memory as recited in claim 8, wherein the reference voltage is provided by a dummy cell.

10. The static RAM memory as recited in claim 9, wherein the second voltage is lower than the first voltage.

11. The static RAM nemory as recited in claim 10, wherein the latch circuit comprises two inverters which are cross-coupled and wherein each inverter comprises a PMOS transistor and an NMOS transistor.

12. The static RiM memory as recited in claim 11, wherein drivability of the access transistor is higher than that of the latch circuit.

13. The static Wr memory as recited ih claim 11, wherein a cell ratio between the access transistor and the NMOS transistor of the latch circuit is selected in order that a signal transmission characteristic is not inverted at a read operation.

14. The static RAM memory as recited in claim 11, wherein a cell ratio at a read operation is different form that at the write operation.

15. The static RAM memory as recited in claim 14, wherein the cell ratio at the read operation.is higher than that at the write operation.

16. A static RAM mamory device comprising: a) a first inverter including: a-l) a first ?MOS transistor having a source coupled to a first power supply; a-2) a first NMOS having a drain coupled to a drain of the first PMOS transistor, a source coupled to a second power supply, and a gate coupled to a gate of the first PMOS transistor; b) a second inverter including: b-l) a second PMOS transistor having a source coupled to the first power supply; and b-2) a second NMOS having a drain coupled to the gate of the first PMOS transistor and a drain of the second PMOS transistor, a source coupled to the second power supply and a gate coupled to the gate of tIe second PMOS transistor, and the drain of the first PMOS transistor; c) a third NMOS transistor having a first terminal coupled to the drain of the first -MOS transistor and the gate of the second PMOS transistor, a second terminal coupled to a single bit line, and gate coupled to a word line; d) a sense amplifier for sensing and amplifying a voltage difference between a reference voltage and a voltage on the single bit line; and e) a voltage generating means for providing the reference voltage for the sense amplifier.

17. The static RAM memory as recited in claim 16, wherein the reference voltage is prcvided by a dummy cell.

18. The static RAN nemory as recited in claim 17, wherein the static RAM memory further comprises a voltage generating means for providing the first power supply with a first voltage at a reid operation and a second voltage at the write operation, wherein the first voltage is different from the second voltage.

19. The static MM memory as recited in claim 18, wherein the second voltage is lower than the first voltage.

20. The static RAM memory as recited in claim 16, wherein drivability of the third NMOS transistor is higher than that of the first PMOS transistor.

21. The static RAS memory as recited in claim 16, wherein a cell ratio between the third NMOS transistor and the first NMOS transistor is selected in order that a signal transmission characteristic of the first and second inverters is not inverted at a read operation.

22. The static RAM memory as recited in claim 17, wherein a cell ratio at a read operation is different form that at the write operation.

23. The static RAH memory as recited in claim 17, wherein the sense amplifier is coupled to a dumpy bit line of a cell block hating the plurality of dummy cells, each of which stores data '1'.

24. The static RAM memory as recited in claim 22, wherein the cell ratio at the read operation is higher than that at the write operation.

25. A static RAM memory device comprising: a plurality of menory cells including one access transistor an a latch circuit which is coupled to the access transistor in order to store cell dat; a plurality of word lines for applying a voltage to a gate of the access transistor; a plurality of dumpy cells; a sense amplifier coupled to a global bit line and a dummy bit line for sensing and amplifying a voltage difference between a reference voltage and a voltage on the global bit line, wherein the reference voltage is provided by one of the dummy cells through the dummy bit line; a plurality of local bit lines coupled to the memory cells through the access transistor, wherein the global bit line is selectively coupled to one of the plurality of local bit lines; and a switching means for selectively coupling the global bit line to one of the plurality.

26. The static RAM memory as recited in claim 25, wherein the static RAM memory further comprises a voltage generating means for providing the first power supply with a first voltage at a read operation and a second voltage at a write operation, wherein the first voltage is different from the second voltage.

27. The static RAM memory as recited in claim 25, wherein the global bit line is opposite to the local bit lines and the memory cells are between the global bit line and the local bit lines.

28. The static RAM memory as recited in claim 25, wherein the reference voltage is provided by one of dummy cells, each of which stores data "1"

29. A static RAM memory as substantially hereinbefore described with reference to any of figures 4 to 8, 9b and 9c.