TWI837342B - Manufacturing method of structure and intermediate structure - Google Patents

Abstract

The manufacturing method of the structure includes: preparing a processing object, wherein the processing object includes: an etching object including an etched surface including a conductive group III nitride, and an etched region is arranged on the etched surface; a conductive member is arranged to contact at least a part of the surface of the conductive region of the etching object electrically connected to the etched region; and a mask is formed on the etched surface and includes a non-conductive material; And a step of etching the III-nitride constituting the etched area by irradiating light to the etched surface through the etching solution while the object to be treated is immersed in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidant that receives electrons, and while the etched area and the conductive component are in contact with the etching solution; and defining the edge of the etched area to include the edge of the mask instead of the edge of the conductive component.

Description

Method for manufacturing structure and intermediate structure

The present invention relates to a manufacturing method of a structure and an intermediate structure.

Group III nitrides such as gallium nitride (GaN) are used as materials for manufacturing semiconductor devices such as light-emitting elements and transistors.

Photoelectrochemical (PEC) etching has been proposed as an etching technique for forming various structures on group III nitrides such as GaN (see, for example, non-patent document 1). PEC etching is a wet etching technique that causes less damage than general dry etching. In addition, it is superior to special dry etching techniques that cause less damage, such as neutral particle beam etching (see, for example, non-patent document 2) and atomic layer etching (see, for example, non-patent document 3), in terms of simplicity of equipment. [Prior art document] [Non-patent document]

[Non-patent document 1] J. Murata et al., "Photo-electrochemical etching of free-standing GaN wafer surfaces grown by hydride vapor phase epitaxy", Electrochimica Acta, 171(2015)89-95 [Non-patent document 2] S. Samukawa, Japanese Journal of Applied Physics (JJAP), 45(2006)2395. [Non-patent document 3] T. Faraz, ECS Journal of Solid State Science and Technology, 4, N5023(2015).

[Problem to be solved by the invention] One object of the present invention is to provide a technology for performing PEC etching of group III nitrides well. [Means for solving the problem]

According to one aspect of the present invention, a method for manufacturing a structure is provided, comprising: a step of preparing a processing object, wherein the processing object comprises: an etching object, comprising an etched surface comprising a conductive group III nitride and an etched region disposed on the etched surface; a conductive component, arranged to contact at least a portion of a surface of a conductive region of the etched object electrically connected to the etched region; and a mask, formed on the etched surface and comprising a non-conductive material; and immersing the object to be processed in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidant that receives electrons, and irradiating the etched surface with light through the etching solution while the etched area and the conductive component are in contact with the etching solution, thereby etching the group III nitride constituting the etched area; and defining the edge of the etched area to include the edge of the mask instead of the edge of the conductive component.

According to another aspect of the present invention, an intermediate structure is provided, comprising: An etching object, comprising an etched surface including a conductive III-nitride, and an etched region is arranged on the etched surface; A conductive component is arranged to contact at least a portion of the surface of the conductive region of the etching object electrically connected to the etched region; and A mask is formed on the etched surface and comprises a non-conductive material; and The etched region and the conductive component are immersed in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidant for receiving electrons in a contacting state; The edge of the etched region is defined to include not the edge of the conductive component but the edge of the mask. [Effect of invention]

A technique is provided for making PEC etching of Group III nitrides perform well.

<First embodiment> A method for manufacturing a structure according to the first embodiment of the present invention is described. The manufacturing method includes an etching step (hereinafter referred to as a PEC etching step) using photoelectrochemical (PEC) etching on an etching object 10 (hereinafter referred to as a wafer 10) as a material of the structure. Hereinafter, PEC etching is also referred to as etching.

The wafer 10 includes a substrate 11 and a group III nitride layer 12 (hereinafter also referred to as an epitaxial layer 12) formed on the substrate 11 (see FIG. 1 (a)). The upper surface of the epitaxial layer 12 constitutes an etched surface 20 to be etched. The etched surface 20 includes a conductive group III nitride. An etched region 21 to be etched is arranged on the etched surface 20.

The object to be processed by PEC etching, that is, the object immersed in (contacting) the etching liquid 201, is called the processing object 100. The processing object 100 can be regarded as a structure (intermediate structure) in the intermediate stage for obtaining the final structure. The processing object 100 includes at least a wafer 10, and further includes a mask 50 and the like as a component required for the PEC etching process. The mask 50 is formed on the etched surface 20 of the wafer 10 with a pattern of an opening of the etched area 21. That is, the mask 50 is arranged at a position to define the etched area 21.

Before explaining the details of the method for manufacturing a structure according to the present embodiment, first, an experiment conducted for preliminary research (hereinafter also referred to as a preliminary experiment) is explained. In the preliminary experiment, it is studied how the progress state of PEC etching changes by changing the structure and configuration of the processing object 100. The details of the PEC etching step (refer to (c) of FIG. 1 ) and the details of the mechanism of PEC etching (refer to (1) to (7)) are described later.

10 is a schematic cross-sectional view showing a processing object 100 in a preliminary experiment. In the preliminary experiment, PEC etching is performed in a state where the processing object 100 is immersed in an etching liquid 201 contained in a container 210.

As the etching liquid 201, an acidic liquid prepared by mixing a 0.1 M phosphoric acid (H ₃ PO ₄ ) aqueous solution and a 0.05 M K ₂ S ₂ O ₈ aqueous solution at a ratio of 1:1 is used. Ultraviolet (UV) light 221 is irradiated on the etched surface 20 through the etching liquid 201. The irradiation wavelength of the UV light 221 is set to 260 nm, and the irradiation intensity (I) is set to 4 mW/cm ² . The distance L (d _electrolyte ) from the etched surface 20 to the upper surface 202 of the etching liquid 201 is set to 5 mm. The mask 50 is formed of silicon oxide (SiO ₂ ) which is a non-conductive material.

FIG. 10 (a) to FIG. 10 (d) respectively show the conditions of the first preliminary experiment to the fourth preliminary experiment. In the first preliminary experiment, the second preliminary experiment and the fourth preliminary experiment, an n-type conductive gallium nitride (GaN) substrate was used as the substrate 11 of the wafer 10. In the third preliminary experiment, a semi-insulating sapphire substrate was used as the substrate 11 of the wafer 10. Here, the so-called "conductivity" refers to, for example, a state where the specific resistance is less than 10 ⁵ Ωcm, and the so-called "semi-insulation" refers to, for example, a state where the specific resistance is greater than 10 ⁵ Ωcm. In the first preliminary experiment to the fourth preliminary experiment, an n-type conductive GaN layer was grown on the substrate 11 as the epitaxial layer 12.

In the etched surface 20, which is the upper surface of the epitaxial layer 12, an etched region 21 is defined as a portion exposed to the etching liquid 201. As described later, the etched region 21 is considered to function as an anode of PEC etching.

The portion of the surface of the conductive region of the object 100 that is electrically connected to the etched region 21 and that is exposed to the etching liquid 201 is considered to be able to function as a cathode of PEC etching as described later. Hereinafter, the region that can function as a cathode of PEC etching is referred to as a cathode region 40. The cathode region 40 is indicated by a bold line in FIG10. In addition, the cathode region 40 is also indicated by a bold line in FIG1 (a) and FIG9 described later.

Refer to FIG. 10 (a). In the first preliminary experiment, the object 100 is placed on the support member (spacer) 240 in a state where the bottom surface of the conductive GaN substrate 11 is exposed to the etching liquid 201. In the first preliminary experiment, the side surfaces of the substrate 11 and the epitaxial layer 12 and the bottom surface of the substrate 11 constitute the cathode region 40.

Refer to FIG. 10( b ). In the second preliminary experiment, the object 100 was placed on the bottom surface of the container 210 in a state where the bottom surface of the conductive GaN substrate 11 was not exposed to the etching solution 201 . In the second preliminary experiment, the side surfaces of the substrate 11 and the epitaxial layer 12 constituted the cathode region 40 .

Refer to (c) of Figure 10 . In the third preliminary experiment, the object 100 is placed on the bottom surface of the container 210 as in the second preliminary experiment. In the third preliminary experiment, since a semi-insulating sapphire substrate 11 is used, even if the surface of the substrate 11 is exposed to the etching liquid 201, it does not become the cathode region 40, and only the side surface of the epitaxial layer 12 constitutes the cathode region 40.

Refer to (d) of Figure 10. In the fourth preliminary experiment, the processing object 100 is arranged on the bottom surface of the container 210 as in the second preliminary experiment. The processing object 100 of the fourth preliminary experiment includes not only the wafer 10 and the mask 50, but also the anti-etching coating 60. The anti-etching coating 60 is formed in a manner covering the side surfaces of the wafer 10, i.e., the substrate 11 and the side surfaces of the epitaxial layer 12, and the bottom surface of the wafer 10, i.e., the bottom surface of the substrate 11. In addition, if an alkaline etching solution 201 is used, the anti-etching coating 60 is peeled off, so in this preliminary experiment, an acidic etching solution 201 is used.

In the fourth preliminary experiment, the conductive GaN substrate 11 was used as in the first and second preliminary experiments, but the side surfaces of the substrate 11 and the epitaxial layer 12 and the bottom surface of the substrate 11 were not exposed to the etching liquid 201 in order to form the anti-etching coating 60. Therefore, in the fourth preliminary experiment, the cathode region 40 did not exist.

In the first preliminary experiment, the second preliminary experiment, and the fourth preliminary experiment, a GaN substrate 11 of 6 mm square and 0.4 mm thick was used, and a GaN layer (n-GaN) having an n-type impurity concentration of 1×10 ¹⁶ /cm ³ and a thickness of 10 μm was formed on the GaN substrate 11 as the epitaxial layer 12. The areas of the cathode region 40 in the first preliminary experiment, the second preliminary experiment, and the fourth preliminary experiment were 0.456 cm ² , 0.096 cm ² , and 0 cm ² , respectively. In addition, here, the epitaxial layer 12 is very thin compared to the GaN substrate 11, so the area of the cathode region 40 formed by the side surface of the epitaxial layer 12 is approximately 0. In the third preliminary experiment, a sapphire substrate 11 of 6 mm square and 0.4 mm thick was used, and a GaN layer (un-GaN) with a thickness of 3 μm and no impurities added and a GaN layer (n-GaN) with a thickness of 2 μm and an n-type impurity concentration of 1.2×10 ¹⁶ /cm ³ were stacked on the sapphire substrate 11 to form an epitaxial layer 12 (same structure as shown in FIG. 1 (b) described later). The area of the cathode region 40 in the third preliminary experiment was 0.00048 cm ² (the area of the side surface of the n-GaN as the conductive part in the epitaxial layer 12).

Sulfate radicals (SO ₄ ^{- *} radicals) can be generated by irradiating the etched surface 20 with UV light 221 through the etchant 201. It is estimated that the SO ₄ ^{- *} radicals exist in the etchant 201, spreading to a certain extent from the etched surface 20 to the bottom. It is believed that the region where the SO ₄ ^{- *} radicals exist in the cathode region 40 (region that can function as a cathode in PEC etching) becomes a region that effectively functions as a cathode (actual effective cathode region).

In the first preliminary experiment and the second preliminary experiment, the side surface of the epitaxial layer 12 and the side surface of the substrate 11 are considered to be the actual effective cathode region. In addition, in the third preliminary experiment, the side surface of the epitaxial layer 12 is considered to be the actual effective cathode region. However, in the first preliminary experiment, it is inferred that the SO ₄ ^{- *} radicals do not reach the vicinity of the center of the bottom surface of the substrate 11, but exist in the peripheral portion of the bottom surface of the substrate 11. That is, in the first preliminary experiment, it is inferred that the actual effective cathode region in the bottom surface of the substrate 11 is the peripheral portion of the bottom surface of the substrate 11. If based on the results shown in the following FIG. 11, in the first preliminary experiment, the peripheral portion of the bottom surface of the substrate 11 with a width of about 0.4 mm is considered to be the actual effective cathode region. The area of the actually effective cathode region in the first preliminary experiment was estimated to be 0.192 cm ² . The areas of the actually effective cathode regions in the second to fourth preliminary experiments were 0.096 cm ² , 0.00048 cm ² , and 0 cm ² , respectively, which were equal to the area of the cathode region 40 .

FIG11 is a graph showing the results of PEC etching in the preliminary experiments. The horizontal axis represents the area of the effective cathode area, and the vertical axis represents the etching rate. The results of the first preliminary experiment are represented as "with spacer", the results of the second preliminary experiment are represented as "without spacer", the results of the third preliminary experiment are represented as "on SAP", and the results of the fourth preliminary experiment are represented as "side & back resist coat".

According to this result, the larger the area of the effective cathode region, the higher the etching rate. In addition, it is considered that in order to make the PEC etching of the etched area 21 as the anode proceed well, it is better to expand the area of the effective cathode region to improve the electrical balance, so it is better to expand the cathode region 40, which is the area that can function as a cathode.

In the first and second preliminary experiments, by using the conductive substrate 11, the cathode region 40 can be expanded and set using the side or bottom surface of the substrate 11, so it is easy to increase the etching rate. In contrast, in the third preliminary experiment, by using the semi-insulating substrate 11, the cathode region 40 includes only a narrow region of the side surface of the epitaxial layer 12, so it is difficult to increase the etching rate. As can be seen from FIG. 11, in the third preliminary experiment, etching is basically not performed, similar to the fourth preliminary experiment in which the cathode region 40 does not exist.

Furthermore, even when a semi-insulating substrate 11 is used, when the mask 50 includes a conductive material, the surface of the mask 50 also functions as the cathode region 40. This is because the mask 50 is electrically connected to the etched region 21. In this case, the etching rate can be increased compared to the case where the mask 50 includes a non-conductive material.

As a material for manufacturing semiconductor devices using group III nitrides, there is a case where a wafer 10 having an epitaxial layer 12 formed on a semi-insulating substrate 11 such as a sapphire substrate, a silicon carbide (SiC) substrate, or a semi-insulating GaN substrate is used. In this case, a mask 50 is formed using a non-conductive material such as an anti-etching agent or silicon oxide.

The results of the third preliminary experiment show that it is difficult to perform PEC etching well when a semi-insulating substrate 11 is used and a non-conductive material is used to form the mask 50. The inventor of the present application has proposed a technique that enables PEC etching to be performed well even in such a situation.

The following is a detailed description of the method for manufacturing a structure according to the first embodiment. FIG1(a) is a schematic cross-sectional view showing an example of a processing object 100 according to the first embodiment. First, as shown in FIG1(a), the processing object 100 is prepared. The processing object 100 of this embodiment includes not only a wafer 10 and a mask 50, but also a cathode pad (conductive member) 30.

In this embodiment, as the substrate 11, a semi-insulating substrate such as a sapphire substrate, a SiC substrate, a (semi-insulating) GaN substrate, etc. can be used. The mask 50 is formed of a non-conductive material such as an anti-etching agent, silicon oxide, etc. The shape, width, and depth of the etched area 21 can be appropriately selected as needed. The mask 50 is arranged at a position to define the etched area 21 (the edge of the etched area 21 includes the edge of the mask 50).

The cathode pad 30 is a conductive member containing a conductive material. The cathode pad 30 is provided to contact at least a portion of the surface of the conductive region of the wafer 10 electrically connected to the etched region 21. The cathode pad 30 illustrated in FIG. 1(a) is preferably arranged in a state of contact with the mask 50 (in a state where the etched surface 20 is not exposed in the gap between the mask 50 and the cathode pad 30) in a region on the etched surface 20 that is enclosed by the mask 50 when viewed from above. The cathode pad 30 is not arranged at a position that defines the etched region 21.

The cathode pad 30 "is not arranged at the position defining the etched area 21", which means that at least a part of the cathode pad 30 is "not arranged at the position defining the etched area 21", that is, the cathode pad 30 includes a part that does not function as a mask for defining the etched area 21 (the etched area 21 is not defined only by the cathode pad 30 as a mask, and the edge of the etched area 21 is not defined only by the edge of the cathode pad 30). In addition, the configuration of the cathode pad 30 can be appropriately adjusted as needed. For example, the cathode pad 30 may be arranged in an area that is not included in the mask 50 when viewed from above. The edge of the cathode pad 30 may include a portion included in the edge of the defined etched region 21, or may include a portion not included in the edge of the defined etched region 21.

The material of the cathode pad 30 is preferably a material having a low Schottky barrier height to the etched surface 20 and having resistance to the etching solution 201 (alkaline or acid). Specifically, a metal such as titanium (Ti) is preferably used. In addition to Ti, for example, Ti/Au in which gold (Au) is layered on Ti, nickel (Ni), platinum (Pt), a single layer of Au, etc. can also be used.

When the object 100 is immersed in the etching liquid 201, the upper surface of the cathode pad 30 is exposed to the etching liquid 201. Therefore, the upper surface of the cathode pad 30 functions as the cathode region 40. As described above, in this embodiment, not only the side surface of the epitaxial layer 12 but also the upper surface of the cathode pad 30 constitutes the cathode region 40.

In this embodiment, the cathode region 40 is expanded by providing the cathode pad 30, compared with the case where the cathode pad 30 is not provided. Thereby, PEC etching can be performed more favorably than the case where the cathode pad 30 is not provided.

The cathode pad 30 of this embodiment can utilize the upper surface of the cathode pad 30 as the cathode region 40, so it is easy to expand the cathode region 40. In addition, by arranging the cathode pad 30 on the etched surface 20, the _SO4- ^* radicals generated by irradiating the etched surface 20 with UV light 221 can be more reliably present near the upper surface of the cathode pad 30. Thus, the upper surface of the cathode pad 30 can be easily utilized as ^an effective cathode region.

FIG1(b) is a schematic cross-sectional view showing an example of the structure of a wafer 10 (an example used in the experimental examples described later). The substrate 11 is a sapphire substrate. The epitaxial layer 12 is composed of a GaN layer (un-GaN) with no dopant added and a thickness of 3 μm and a GaN layer (n-GaN) with n-type dopant added and a carrier concentration (net donor concentration) of 1.2×10 ¹⁶ /cm ³ and a thickness of 2 μm.

1( c ) is a schematic cross-sectional view of a PEC etching apparatus 200 showing a PEC etching step. The PEC etching apparatus 200 includes a container 210 storing an etching liquid 201 , and a light source 220 emitting ultraviolet (UV) light 221 .

In the PEC etching step, the object 100 is immersed in the etching liquid 201, and the etched area 21 and the cathode pad 30 are in contact with the etching liquid 201. The etched surface 20 is irradiated with UV light 221 through the etching liquid 201, so that the III-nitride constituting the etched area 21 is etched. The details of the etching liquid 201, the UV light 221 and the PEC etching mechanism are described later.

In addition, the manufacturing method of the structure may also include steps such as electrode formation and protective film formation as other steps as needed.

Next, a method for forming the cathode pad 30 will be described by way of example. Fig. 2 is a schematic cross-sectional view showing a first example of the method for forming the cathode pad 30. In the first example, the cathode pad 30 is formed before forming the mask 50. The material of the mask 50 can be, for example, an anti-etching agent.

First, as shown in FIG. 2 (a), a cathode pad 30 is formed on the etched surface 20 of the wafer 10 using a lift-off method, for example, using Ti. Next, as shown in FIG. 2 (b), an anti-etching film 51 is formed on the entire surface of the etched surface 20 so as to cover the cathode pad 30. Next, as shown in FIG. 2 (c), a mask 50 is formed by patterning the anti-etching film 51. The mask 50 has an opening that exposes the etched area 21 and an opening that exposes the upper surface of the cathode pad 30.

3 is a schematic cross-sectional view showing a second example of a method for forming the cathode pad 30. In the second example, the cathode pad 30 is formed after the mask 50 is formed. The material of the mask 50 can be exemplified by silicon oxide.

First, as shown in FIG3(a), a silicon oxide film is formed on the entire surface of the etched surface 20 of the wafer 10, and then the silicon oxide film is patterned by photolithography and etching to form a mask 50. The mask 50 has an opening for exposing the etched area 21 and has an opening in the area where the cathode pad 30 is to be formed.

Next, as shown in Fig. 3(b), a resist pattern 70 for peeling is formed so as to cover the etched area 21 and expose the area where the cathode pad 30 is to be formed. Then, a Ti film 31 is formed on the entire surface of the etched surface 20, for example.

Next, as shown in FIG. 3( c ), by stripping, that is, by removing unnecessary portions of the Ti film 31 together with the anti-etching pattern 70 , the cathode pad 30 is formed (remaining) in the region where the cathode pad 30 is to be formed.

For example, when the mask 50 is formed using silicon oxide, hydrofluoric acid is preferably used for etching when forming the mask 50. Therefore, if the mask 50 is formed after the cathode pad 30 is formed, there is a risk of etching to the cathode pad 30. As in the second example, by forming the cathode pad 30 after the mask 50 is formed, unnecessary etching of the cathode pad 30 as described above can be avoided.

Next, the etching solution 201, UV light 221, and the mechanism of PEC etching are described in detail. An example of the group III nitride to be etched is GaN.

The etching solution 201 is an alkaline or acidic etching solution 201 containing oxygen for generating oxides of group III elements contained in group III nitrides constituting the etched region 21, and further containing an oxidant that accepts electrons. The oxidant can be exemplified by peroxodisulfate ions (S ₂ O ₈ ^2- ).

A first example of the etching solution 201 is an etching solution that is alkaline at the start of etching and is formed by mixing a potassium hydroxide (KOH) aqueous solution and a potassium peroxodisulfate (K ₂ S ₂ O ₈ ) aqueous solution. Such an etching solution 201 is prepared, for example, by mixing a 0.01 M KOH aqueous solution and a 0.05 M K ₂ S ₂ O ₈ aqueous solution at a ratio of 1:1. The concentration of the KOH aqueous solution, the concentration of the K ₂ S ₂ O ₈ aqueous solution, and the mixing ratio of these aqueous solutions can be appropriately adjusted as needed. In addition, the etching solution 201 mixed with the KOH aqueous solution and the K ₂ S ₂ O ₈ aqueous solution can also be acidic at the start of etching by, for example, reducing the concentration of the KOH aqueous solution.

The PEC etching mechanism when the etching solution 201 of the first example is used is described. By irradiating the etched surface 20 with UV light 221 having a wavelength of less than 365 nm, holes and electrons are generated in pairs in the GaN constituting the etched area 21. The generated holes decompose GaN into Ga ³⁺ and N ₂ (Chemical 1), and further, Ga ³⁺ is oxidized by hydroxide ions ( ^OH- ) to generate _gallium oxide ( _Ga2O3 ) (Chemical 2). Then, the generated _Ga2O3 dissolves in alkali or acid. In this way, _PEC etching of GaN is performed. In addition, the generated holes react with water, and the water is decomposed to generate oxygen (Chemical 3). [Chemical 1] [Chemistry 2] [Chemistry 3]

In addition, K ₂ S ₂ O ₈ is dissolved in water to generate peroxodisulfate ions (S ₂ O ₈ ^2- ) (Chemical 4), and sulfate ion radicals (SO ₄ ^{- *} radicals) are generated by irradiating S ₂ O ₈ ^2- with UV light 221 (Chemical 5). Electrons generated as pairs with holes react with water together with SO ₄ ^{- *} radicals, and water is decomposed to generate hydrogen (Chemical 6). As described above, in the PEC etching of the present embodiment, by using SO ₄ ^{- *} radicals, electrons generated as pairs with holes in GaN can be consumed, so that PEC etching can be performed well. In addition, as shown in (Chemical 6), as PEC etching proceeds, sulfate ions (SO ₄ ^2- ) increase, thereby increasing the acidity of the etching solution 201 (decreasing the pH value). [Chemistry 4] [Chemistry 5] [Chemistry 6]

As a second example of the etching solution 201, an etching solution that is acidic at the start of etching and is formed by mixing a phosphoric acid (H ₃ PO ₄ ) aqueous solution and a potassium peroxodisulfate (K ₂ S ₂ O ₈ ) aqueous solution can be cited. Such an etching solution 201 is prepared, for example, by mixing a 0.01 M H ₃ PO ₄ aqueous solution and a 0.05 M K ₂ S ₂ O ₈ aqueous solution in a ratio of 1:1. The concentration of the H ₃ PO ₄ aqueous solution, the concentration of the K ₂ S ₂ O ₈ aqueous solution, and the mixing ratio of these aqueous solutions can be appropriately adjusted as needed. Both the H ₃ PO ₄ aqueous solution and the K ₂ S ₂ O ₈ aqueous solution are acidic, so the etching solution 201 mixed with the H ₃ PO ₄ aqueous solution and the K ₂ S ₂ O ₈ aqueous solution is acidic at any mixing ratio. From the viewpoint of easily using an anti-etching mask as the mask 50, it is preferable that the etching solution 201 is acidic.

It is speculated that the PEC etching mechanism in the case of using the etching solution 201 of the second example replaces (Chemical 1) to (Chemical 3) described for the case of using the etching solution 201 of the first example with (Chemical 7). That is, GaN, holes generated by irradiation with UV light 221, and water react to generate _Ga2O3 , hydrogen _ions (H ⁺ ), and _N2 (Chemical 7). And, the generated _Ga2O3 dissolves in acid. In this way, _PEC etching of GaN is performed. In addition, the mechanism in which the electrons generated as pairs with ^holes are consumed by _S2O82- as shown in ( _Chemical 4) to (Chemical 6) is the same as the case of using the etching solution 201 of the first example. [Chemical 7]

As understood from (Chemical 1) and (Chemical 2) or (Chemical 7), the etched region 21 in the PEC etching of GaN is considered to function as an anode that consumes holes. In addition, as understood from (Chemical 6), the portion of the surface of the conductive region of the object 100 that is electrically connected to the etched region 21 and exposed to the etching solution 201 is considered to function as a cathode that consumes (releases) electrons.

As shown in (Chemical 5), the method of generating SO ₄ ^{- *} radicals from S ₂ O ₈ ^2- can use at least one of irradiation with UV light 221 and heating. When irradiation with UV light 221 is used, in order to increase light absorption caused by S ₂ O ₈ ^2- and efficiently generate SO ₄ ^{- *} radicals, it is preferable to set the wavelength of UV light 221 to be greater than 200 nm and less than 310 nm. That is, from the perspective of efficiently performing the following operation, that is, generating holes in the III-nitride in the wafer 10 by irradiation with UV light 221 and generating SO ₄ ^{- *} radicals from S ₂ O ₈ ^2- in the etching solution 201, it is preferable to set the wavelength of UV light 221 to be greater than 200 nm and less than 310 nm. When SO ₄ ^{− *} radicals are generated from S ₂ O ₈ ²⁻ by heating, the wavelength of the UV light 221 may be set to (365 nm or less and) 310 nm or more.

When SO ₄ ^{- *} radicals are generated from S ₂ O ₈ ^2- by irradiation with UV light 221, the distance L from the etched surface 20 of the wafer 10 to the upper surface 202 of the etchant 201 is preferably set to be, for example, not less than 5 mm and not more than 100 mm. If the distance L is too short, for example, less than 5 mm, there is a possibility that the amount of SO ₄ ^{- *} radicals generated in the etchant 201 above the wafer 10 becomes unstable due to the change of the distance L. In addition, if the distance L is too long, for example, more than 100 mm, a large amount of SO ₄ ^{- *} radicals that are not helpful for PEC etching and are unnecessary are generated in the etchant 201 above the wafer 10, thereby reducing the utilization efficiency of the etchant 201.

In addition, PEC etching can also be performed on group III nitrides other than GaN as exemplified. The group III element contained in the group III nitride is at least one of aluminum (Al), gallium (Ga) and indium (In). The idea of PEC etching of the Al component or the In component in the group III nitride is the same as the idea described for the Ga component with reference to (Chemical 1) and (Chemical 2), or (Chemical 7). That is, holes are generated by irradiation with UV light 221, thereby generating Al oxide or In oxide, and PEC etching can be performed by dissolving these oxides in alkali or acid. The wavelength (below 365 nm) of the UV light 221 can be appropriately changed according to the composition of the group III nitride to be etched. Taking GaN PEC etching as a benchmark, when Al is contained, a shorter wavelength UV light can be used, and when In is contained, a longer wavelength UV light can also be used.

Next, an experimental example of PEC etching of the first embodiment is described. In this experimental example, a mask 50 and a cathode pad 30 are formed on the etched surface 20 of a 6 mm square wafer 10 including a multilayer structure as described with reference to FIG. 1( b ), and it is studied how the progress of PEC etching changes by changing the area of the cathode pad 30 .

The etching liquid 201 is a mixture of 0.01 M KOH aqueous solution and 0.05 M K ₂ S ₂ O ₈ aqueous solution at a ratio of 1:1. UV light 221 is irradiated on the etched surface 20 through the etching liquid 201. The irradiation wavelength of the UV light 221 is set to 260 nm, and the irradiation intensity (I) is set to 4 mW/cm ^2. The distance L (d _electrolyte ) from the etched surface 20 to the upper surface 202 of the etching liquid 201 is set to 5 mm.

FIG4 is a photograph showing the patterns of the mask 50 and the cathode pad 30 formed on the first to fifth processed objects (hereinafter also referred to as the first to fifth samples) of this experimental example. In the first to fifth samples, the mask 50 including the opening area of the same shape is formed by using silicon oxide (SiO ₂ ). In FIG4 , the formation area of the mask 50 is shown as a dark area.

In FIG4 , the bright area indicates the opening area of the mask 50, that is, the etched area 21. However, in the bright area of FIG4 , the portion indicated as "Ti" indicates the cathode pad 30 formed of Ti. In the order of the first sample to the fifth sample, the area of the portion indicated as "Ti", that is, the area of the cathode pad 30 is enlarged. In FIG4 , the numerical value shown in the upper part indicates the ratio of the area of the upper surface of the cathode pad 30 to the total area (36 mm ² ) of the etched surface 20 of 6 mm square (hereinafter also referred to as the cathode ratio). The cathode ratios of the first to fifth samples were 0.0056 (0.6%), 0.011 (1.1%), 0.022 (2.2%), 0.044 (4.4%), and 0.078 (7.8%), respectively.

FIG4(f) is a photograph showing a pattern of a mask 50 of a sixth processing object (hereinafter also referred to as the sixth sample). The sixth sample uses Ti to form a mask 50 including an opening area of the same shape as the first to fifth samples. In addition, the cathode pad 30 is not formed in the sixth sample. Since the sixth sample does not include the cathode pad 30, but the mask 50 itself is formed of Ti and functions as the cathode area 40, it corresponds to a situation where the area of the cathode pad 30 is expanded to the limit in the mask 50 including an opening area of the same shape as the first to fifth samples. The sixth sample corresponds to 0.504 (50.4%) in terms of the cathode ratio.

FIG5 (a) and FIG5 (b) are graphs showing the results of this experimental example. FIG5 (a) shows the dependence of the etching depth of the first to sixth samples on the etching time. FIG5 (b) shows the dependence of the etching rate of the first to sixth samples on the cathode area (the value obtained by converting the cathode ratio into the area). The etching rate is the average value in the etching time of 120 minutes.

5(a) and 5(b) show that the etching depth per unit time, that is, the etching rate, can be increased by forming the cathode pad 30. Also, it can be seen that the etching rate can be increased by increasing the cathode ratio (enlarging the cathode area).

The standard for the preferred width of the cathode pad 30 can be, for example, as follows: The cathode ratio, i.e., the ratio of the cathode area (the area of the cathode pad 30 in contact with the etching liquid 201) to the overall area of the etched surface 20 is preferably set to 1% or more, more preferably 2% or more, particularly preferably 4% or more, and most preferably 8% or more.

The standard for the preferred width of the cathode pad 30 is, for example, as follows: The cathode area (the area where the cathode pad 30 contacts the etching solution 201) is preferably larger than the area of the cathode region 40 when the cathode pad 30 is not provided, that is, the entire area of the side surface (conductive portion) of the epitaxial layer 12.

<Second embodiment> Next, a method for manufacturing a structure according to the second embodiment is described. In the second embodiment, the structure 150 manufactured can be exemplified by a high electron mobility transistor (HEMT).

Fig. 6(a) is a schematic cross-sectional view illustrating a structure 150 (hereinafter also referred to as HEMT 150) according to the second embodiment. Fig. 6(b) is a schematic cross-sectional view illustrating a wafer 10 used as a material of the HEMT 150.

The substrate 11 may be, for example, a semi-insulating SiC substrate. The epitaxial layer 12 may be, for example, a layered structure of a nucleation layer 12a including aluminum nitride (AlN), a channel layer 12b including GaN and having a thickness of 1.2 μm, a barrier layer 12c including aluminum gallium nitride (AlGaN) and having a thickness of 24 nm, and a cap layer 12d including GaN and having a thickness of 5 nm. In the layered portion of the channel layer 12b and the barrier layer 12c, a two-dimensional electron gas (2DEG) is generated to become a channel of the HEMT 150.

A source electrode 151, a gate electrode 152, and a drain electrode 153 of the HEMT 150 are formed on the upper surface of the cap layer 12d. A protective film 154 is formed to have openings on the upper surfaces of the source electrode 151, the gate electrode 152, and the drain electrode 153.

The HEMT 150 includes a device isolation trench 160 for isolating adjacent devices. The device isolation trench 160 is provided so that its bottom surface is disposed at a position deeper than the upper surface of the channel layer 12 b , that is, between adjacent devices, 2DEG is separated by the device isolation trench 160 .

In this embodiment, the shape of the element separation groove 160 of the HEMT 150 formed by PEC etching is exemplified. FIG7 (a) is a schematic cross-sectional view of the processing object 100 when PEC etching is performed to form the element separation groove 160. FIG7 (b) is a schematic top view of the processing object 100. FIG7 (c) is a schematic cross-sectional view of the PEC etching device 200 showing the PEC etching step.

The processing object 100 of this example has a structure in which a mask 50 for PEC etching is formed as a component at a stage where a source electrode 151 and a drain electrode 153 are formed on a wafer 10. The source electrode 151 and the drain electrode 153 are used as a cathode pad 30. The cathode pad 30 (source electrode 151 and drain electrode 153) is formed of, for example, Ti/Al/Au in which aluminum (Al) is layered on Ti and Au is layered on Al.

The mask 50 is formed on the upper surface of the cap layer 12d, i.e., the etched surface 20, and includes an opening for exposing the etched area 21 and an opening for exposing the upper surface of the cathode pad 30 (source electrode 151 and drain electrode 153). The etched area 21 is a region where the device isolation groove 160 is to be formed, and is arranged in a grid pattern, for example, so as to surround each HEMT device in a plan view.

The mask 50 is formed of, for example, an anti-etching agent. The etching solution 201 is preferably an acidic etching solution (from the etching start point). By etching the III-nitride constituting the etched area 21 to a position deeper than the upper surface of the channel layer 12b, a recessed portion used as the device separation groove 160 is formed. After the recessed portion (device separation groove 160) is formed, the mask 50 is removed, the gate electrode 152 is formed, and the protective film 154 is formed. In this way, the HEMT 150 is manufactured.

According to the second embodiment, even when the wafer 10 including the semi-insulating substrate 11 such as a SiC substrate is used and the mask 50 including a non-conductive material such as an anti-etchant is used, the device isolation trench 160 of the HEMT 150 can be easily formed by PEC etching.

<Third embodiment> Next, a method for manufacturing a structure according to the third embodiment is described. In the third embodiment, a configuration of the cathode pad 30 which is preferred for improving the controllability of the shape of the recess formed by PEC etching is described.

As described in the first and second embodiments, by providing the cathode pad 30 , PEC etching can be performed well even when the mask 50 made of a non-conductive material (hereinafter also referred to as the non-conductive mask 50 ) is used.

From the perspective of promoting the progress of PEC etching, a portion of the edge of the mask defining the etched area 21 may also include the edge of the cathode pad 30. However, as described below, according to the knowledge obtained by the inventors of the present application, from the perspective of improving the controllability of the shape of the recessed portion formed by PEC etching, it is preferred that the entire portion of the edge of the mask defining the etched area 21 does not include the edge of the cathode pad 30, but includes the edge of the non-conductive mask 50.

Such a structure is obtained, for example, by disposing the cathode pad 30 on the inner side of the non-conductive mask 50 (the side opposite to the etched area 21) when viewed from above, that is, by disposing the cathode pad 30 in a manner that the entire periphery of the cathode pad 30 is surrounded by the non-conductive mask 50 (for example, refer to FIG. 7 (b)).

12( a ) and 12 ( b ) are schematic cross-sectional views and plan views illustrating a configuration in which the cathode pad 30 is configured such that the edge 35 of the cathode pad 30 becomes the edge 85 of the mask 80 defining the etched area 21 (views showing a portion where the edge 85 of the mask 80 includes the edge 35 of the cathode pad 30 ).

By utilizing the cathode pad 30, the progress of PEC etching is promoted, so that the recess 22 can be formed in the etched area 21. Ideally, the edge of the recess 22 is formed at a position along the edge 85 of the mask 80, that is, the edge 35 of the cathode pad 30 (the edge 23a of the recess 22 in the ideal case is indicated by a dotted line). However, it can be seen that, by this form of PEC etching, the edge 23 of the recess 22 is actually formed in a position separated from the edge 35 of the cathode pad 30 to the outside (the etched area 21 side) in a disordered shape with an irregular distance from the edge 35. It is speculated that the reason is that since the cathode pad 30 is conductive, a depletion layer is formed on the etched surface 20 near the cathode pad 30 .

Fig. 13 (a) and Fig. 13 (b) are schematic cross-sectional views and top views showing a configuration in which the non-conductive mask 50 and the cathode pad 30 are arranged in such a manner that the edge 55 of the non-conductive mask 50 becomes the edge 85 of the mask 80 that defines the etched area 21. In this example, the cathode pad 30 is arranged on the inner side of the non-conductive mask 50 (the side opposite to the etched area 21).

The (shortest) distance between the edge 85 of the mask 80, that is, the edge 55 of the non-conductive mask 50 and the edge 35 of the cathode pad 30 (hereinafter referred to as the offset distance) is set to D _OFF . The inventors of the present application have found that by extending the offset distance D _OFF to a certain extent, the influence of the depletion layer caused by the cathode pad 30 can be suppressed, and the edge 23 of the recess 22 can be formed at a position along the edge 85 of the mask 80 (the edge 55 of the non-conductive mask 50). The offset distance D _OFF is preferably set to 5 μm or more, and more preferably set to 10 μm or more. The upper limit of the offset distance D _OFF is not particularly limited.

As described above, by forming the edge 85 of the mask 80 defining the etched area 21 by the edge 55 of the non-conductive mask 50, the controllability of the shape of the edge 23 of the recess 22 formed by PEC etching can be improved.

In addition, in the configuration shown in FIG. 7 (b), the cathode pad 30 is arranged inside the edge of the closed shape of the non-conductive mask 50 defining the etched area 21, but it is also possible to arrange the cathode pad 30 outside the edge as needed (depending on the device structure to be manufactured, etc.) (for example, refer to FIG. 15 (a) described later). In this form, it is easier to ensure that the offset distance D _OFF from the edge of the non-conductive mask 50 defining the etched area 21 to the cathode pad 30 is long.

The results of the experimental example of the third embodiment are described below. FIG. 14 is a photograph showing the results of PEC etching using a Ti mask. In the quadrangular region shown in the photograph, the bright regions on the upper and right sides represent the Ti mask. The slightly darker region on the outer side (lower side or left side) of the Ti mask represents the etched region 21 defined by the Ti mask. In the etched region 21, an edge 23 with a disordered shape of the formed recess 22 is observed.

FIG15(a) is a photograph showing a processing object 100 formed with a non-conductive mask 50 and a cathode pad 30. The cathode pad 30 is shown as a bright area, and the non-conductive mask 50 is shown as an area darker than the cathode pad _30. The etched area is demarcated by the non-conductive mask 50 and is shown as a (linear) area darker than the non-conductive mask 50. The experimental conditions in the experimental example described with reference to FIG15 are the same as the experimental conditions ( _irradiation wavelength, irradiation intensity and distance L) in the first embodiment described with reference to FIG4, except that a _K2S2O8 aqueous solution is used as an etching solution. The non-conductive mask 50 is formed of _SiO2 , and the cathode pad 30 is formed of Ti.

FIG. 15( b) and FIG. 15( c) are enlarged photographs of a portion of the area shown in the circle on the upper right of FIG. 15( a). In the circle, a quadrangular annular etched area 21 is demarcated by a non-conductive mask 50. FIG. 15( b) and FIG. 15( c) show the upper right corner of the etched area 21. FIG. 15( b) is a photograph before PEC etching, and FIG. 15( c) is a photograph after PEC etching. As shown in FIG. 15( b), the width of the portion of the etched area 21 extending in the left-right direction of the paper is 76 μm, and the width of the portion of the etched area 21 extending in the upper-lower direction of the paper is 45 μm.

The edge of the mask defining the etched area 21 does not include the edge of the cathode pad 30, but includes the edge of the non-conductive mask 50. That is, the cathode pad 30 is not arranged at the position defining the etched area 21. In addition, the edge of the non-conductive mask 50 defining the etched area 21 is sufficiently (more than 5μm or more than 10μm) separated from the cathode pad 30 (refer to FIG. 15 (a)).

Comparing FIG. 15(b) with FIG. 15(c), it can be seen that in this experimental example, the recess 22 is formed in a shape substantially consistent with the opening shape of the non-conductive mask 50, and the edge 23 of the recess 22 can be formed along the edge of the non-conductive mask 50. As described above, by making the edge defining the etched area 21 not include the edge of the cathode pad 30 but include the edge of the non-conductive mask 50, PEC etching can be performed to improve the controllability of the shape of the recess 22.

<Other implementation methods>

The above has specifically described the implementation method of the present invention. However, the present invention is not limited to the above implementation method, and various changes, improvements, combinations, etc. can be made within the scope of its main purpose.

For example, the shape, size, configuration, number, etc. of the cathode pad 30 can be adjusted as needed.

FIG8 (a) and FIG8 (b) are schematic top views of the processing object 100 showing an example in which the cathode pad 30 is arranged along the outer periphery of the wafer 10. The edge of the wafer 10 is indicated by a thick line.

Generally, there are many cases where no device is formed on the outer periphery of the wafer 10. Therefore, by using the outer periphery of the wafer 10 to arrange the cathode pad 30, it is easy to use the wide area inside the wafer 10 for forming devices. In addition, by arranging the cathode pad 30 along the outer periphery of the wafer 10, it is easy to form the cathode pad 30 long, that is, to form the cathode pad 30 wide.

FIG8 (a) shows an example in which a cathode pad 30 is arranged along the periphery of the wafer 10 and on the inner side of the wafer 10 when viewed from above. FIG8 (b) shows an example in which a cathode pad 30 is arranged along the periphery of the wafer 10 in a manner extending to the outer side of the wafer 10 when viewed from above (protruding in an eave-like manner). As in the example shown in FIG8 (b), by arranging the cathode pad 30 to the outer side of the wafer 10, the area in contact with the etching liquid 201 can be expanded, so that the cathode region 40 can be set to be wider. This structure is formed, for example, by bonding (or contacting) the cathode pad 30 prepared as a separate body to the wafer 10.

In the first and second embodiments, the substrate 11 of the wafer 10 is semi-insulating, but the substrate 11 may be conductive. That is, when the substrate 11 is conductive, the cathode pad 30 may be provided. When the substrate 11 is conductive, the cathode pad 30 may be arranged at any position on the surface of the substrate 11.

FIG9 is a schematic cross-sectional view conceptually illustrating a configuration in which a cathode pad 30 is provided on a wafer 10 including a conductive substrate 11. When the substrate 11 is conductive, the cathode pad 30 can be arranged not only on the upper surface of the wafer 10 (i.e., on the etched surface 20), but also on the side surface (of the substrate 11) of the wafer 10, and on the bottom surface (of the substrate 11) of the wafer 10. In addition, in this case, since only the substrate 11 is conductive, it is also possible to consider a configuration in which the substrate 11 itself without the epitaxial layer 12 is used as the wafer 10, and the cathode pad 30 is arranged on the upper surface (of the substrate 11) of the wafer 10. Where to arrange the cathode pad 30 on the surface of the conductive substrate 11 can be appropriately selected as needed.

As the etching liquid 201, for example _, the etching liquid 201 which is acidic at the start of etching may be a _K2S2O8 aqueous solution. In this case, the concentration of _{the K2S2O8 aqueous} solution may be set to _0.025M , for example.

In the above description, the form of supplying S ₂ O ₈ ^2- from potassium peroxodisulfate (K ₂ S ₂ O ₈ ) is exemplified, but S ₂ O ₈ ^2- may also be supplied from, for example, sodium peroxodisulfate (Na ₂ S ₂ O ₈ ), ammonium peroxodisulfate (ammonium persulfate, (NH ₄ ) ₂ S ₂ O ₈ ), or the like.

During PEC etching, the etching liquid 201 may be stationary or flow (move). When the etching liquid 201 is flowed, the same etching liquid 201 may be circulated (the etching liquid 201 is not replaced), or a new etching liquid 201 may be continuously supplied (the etching liquid 201 is replaced).

<Preferred form of the present invention> Below, the preferred form of the present invention is supplemented.

(Note 1) A method for manufacturing a structure, comprising: Preparing a treatment object, the treatment object comprising: an etching object, comprising an etched surface comprising a conductive group III nitride, and an etched region disposed on the etched surface; and a conductive component, arranged to contact at least a portion of the surface of the conductive region of the etched object electrically connected to the etched region; and By immersing the treatment object in a In an alkaline or acidic etching solution of an oxidant that receives electrons, and in a state where the etched area and the conductive component are in contact with the etching solution, ultraviolet light is irradiated to the etched surface through the etching solution, thereby etching the group III nitride constituting the etched area; and the edge of the etched area is defined not only to include the edge of the conductive component (the conductive component is not arranged at a position to define the etched area).

(Note 2) The manufacturing method of the structure as described in Note 1, wherein the processing object includes a mask, the mask is formed on the etched surface and contains a non-conductive material; and the edge of the etched area is defined including the edge of the mask (the mask is arranged at a position that defines the etched area).

(Note 3) The method for manufacturing a structure as described in Note 2, wherein the mask contains an anti-etching agent, and the etching solution is acidic.

(Note 4) A method for manufacturing a structure as described in any one of Notes 1 to 3, wherein the etching solution is acidic.

(Note 5) A method for manufacturing a structure as described in any one of Notes 1 to 4, wherein the Group III nitride is etched while the upper surface of the portion of the conductive component disposed on the etched surface is in contact with the etching liquid.

(Note 6) A method for manufacturing a structure as described in any one of Notes 1 to 5, wherein the etching object is used as a material for a high electron mobility transistor, and the conductive component is used as an electrode of the high electron mobility transistor.

(Supplementary Note 7) The method for manufacturing a structure as described in Supplementary Note 6, wherein the recess formed by etching the etched area is used as a device separation groove of the high electron mobility transistor.

(Note 8) A method for manufacturing a structure as described in any one of Notes 1 to 7, wherein the conductive member is arranged along the periphery of the etching object when viewed from above.

(Note 9) A method for manufacturing a structure as described in any one of Notes 1 to 8, wherein the conductive member is arranged so as to extend to the outside of the etching object when viewed from above.

(Note 10) A method for manufacturing a structure as described in any one of Notes 1 to 9, wherein the etching object includes a semi-insulating substrate.

(Supplementary Note 11) The method for manufacturing a structure as described in Supplementary Note 10, wherein the conductive component is provided on a group III nitride layer formed on the semi-insulating substrate.

(Note 12) The method for manufacturing a structure as described in Note 11, wherein the area of the conductive component in contact with the etching solution is preferably 1% or more, more preferably 2% or more, particularly preferably 4% or more, and particularly preferably 8% or more relative to the entire area of the upper surface of the group III nitride layer, i.e., the etched surface.

(Note 13) The method for manufacturing a structure as described in Note 11 or Note 12, wherein the area of the conductive member in contact with the etching solution is larger than the entire area of the side surface of the group III nitride layer.

(Note 14) A method for manufacturing a structure as described in any one of Notes 1 to 9, wherein the etching object includes a conductive substrate.

(Supplementary Note 15) The method for manufacturing a structure as described in Supplementary Note 14, wherein the conductive component is arranged on the surface of the group III nitride layer formed on the conductive substrate.

(Note 16) A method for manufacturing a structure as described in Note 14 or Note 15, wherein the conductive component is arranged on the surface of the conductive substrate.

(Note 17) An intermediate structure, comprising: An etching object, comprising an etched surface comprising a conductive group III nitride, and an etched region arranged on the etched surface; and A conductive component, arranged to contact at least a portion of the surface of the conductive region of the etching object electrically connected to the etched region; and The etched region and the conductive component are immersed in an alkaline or acidic etching solution containing an electron-receiving oxidant in a contacting state, and The edge of the etched region is not limited to the edge of the conductive component (the conductive component is not arranged at the position of the etched region).

(Note 18) The intermediate structure as described in Note 17, wherein it includes a mask, the mask is formed on the etched surface and contains a non-conductive material; and the edge of the etched area is formed by including the edge of the mask (the mask is arranged at a position to define the etched area).

(Note 19) The intermediate structure as described in Note 17 or Note 18, wherein the mask contains an anti-corrosion agent.

(Note 20) The intermediate structure as described in any one of Notes 17 to 19, wherein the etching object is used as a material of a high electron mobility transistor, and the conductive component is used as an electrode of the high electron mobility transistor.

(Note 21) The intermediate structure as described in any one of Notes 17 to 20, wherein the conductive member is arranged along the periphery of the etching object when viewed from above.

(Note 22) The intermediate structure as described in Note 21, wherein the conductive member is arranged so as to extend to the outside of the etching object when viewed from above.

(Note 23) The intermediate structure as described in any one of Notes 17 to 22, wherein the etching object includes a semi-insulating substrate.

(Note 24) The intermediate structure as described in any one of Notes 17 to 22, wherein the etching object includes a conductive substrate.

(Note 25) The intermediate structure as described in Note 24, wherein the conductive component is arranged on the surface of the conductive substrate.

(Note 26) The intermediate structure as described in any one of Notes 17 to 25, wherein the etched surface is irradiated with ultraviolet light through the etching liquid.

(Note 27) A method for processing a group III nitride crystal, wherein the crystal containing the group III nitride is immersed in an etching liquid and then electrochemically etched, the method comprising: a step of defining an etched area and an area other than the etched area on the surface of the group III nitride; and a step of etching the group III nitride by irradiating the surface with ultraviolet light through the etching liquid; and a conductive member that functions as a cathode that releases electrons in the etching liquid is connected (contacted) to a portion of the area other than the etched area.

(Note 28) The method for manufacturing a structure as described in Note 2, wherein the edge of the etched area does not include the edge of the conductive component but includes the edge of the mask.

(Note 29) The method for manufacturing a structure as described in Note 28, wherein the distance between the edge of the mask and the edge of the conductive component is preferably 5 μm or more, more preferably 10 μm or more.

(Note 30) A method for manufacturing a structure as described in Note 28 or Note 29, wherein the conductive member is arranged in such a manner that the entire periphery of the conductive member is surrounded by the mask when viewed from above.

(Note 31) The intermediate structure as described in Note 18, wherein the edge defining the etched area does not include the edge of the conductive member but includes the edge of the mask.

(Note 32) In the intermediate structure as described in Note 31, the distance between the edge of the mask and the edge of the conductive component is preferably 5 μm or more, and more preferably 10 μm or more.

(Note 33) The intermediate structure as described in Note 31 or Note 32, wherein the conductive member is arranged in such a manner that the entire periphery of the conductive member is surrounded by the mask when viewed from above.

10: Etching object (wafer) 11: Substrate (conductive GaN substrate) (semi-insulating sapphire substrate) 12: Epitaxial layer (III-nitride layer) 12a: Nucleation layer 12b: Channel layer 12c: Barrier layer 12d: Cap layer 20: Etched surface 21: Etched area 22: Recess 23, 23a, 35, 55, 85: Edge 30: Cathode pad (conductive member) 31: Ti film 40: Cathode area 50: Mask (non-conductive mask) 80: Mask 51: Anti-etching film 60: Anti-etching coating 70: Anti-etching pattern 100: Processing object 150: Structure (HEMT) 151: source electrode 152: gate electrode 153: drain electrode 154: protective film 160: element separation groove 200: PEC etching device 201: etching liquid 202: upper surface of etching liquid 210: container 220: light source 221: UV light 240: support member (spacer) D _OFF : offset distance L: distance

FIG. 1 (a) is a schematic cross-sectional view showing an example of a processing object based on the first embodiment of the present invention, FIG. 1 (b) is a schematic cross-sectional view showing an example of an etching object based on the first embodiment, and FIG. 1 (c) is a schematic view showing a PEC etching device showing an example of a PEC etching step based on the first embodiment. FIG. 2 is a schematic cross-sectional view showing a first example of a cathode pad forming method. FIG. 3 is a schematic cross-sectional view showing a second example of a cathode pad forming method. FIG. 4 is a photograph showing the first to sixth processing objects of an experimental example related to PEC etching of the first embodiment. FIG. 5 is a graph showing the results of PEC etching in the experimental example. FIG6 (a) is a schematic cross-sectional view illustrating a structure according to the second embodiment, and FIG6 (b) is a schematic cross-sectional view showing an example of an etching object according to the second embodiment. FIG7 (a) and FIG7 (b) are respectively a schematic cross-sectional view and a schematic top view illustrating an object to be processed according to the second embodiment, and FIG7 (c) is a schematic view of a PEC etching apparatus illustrating a PEC etching step according to the second embodiment. FIG8 is a schematic top view of an object to be processed showing an example in which a cathode pad is arranged along the periphery of the object to be processed. FIG9 is a schematic cross-sectional view conceptually illustrating a form in which a cathode pad is provided for an etching object including a conductive substrate. FIG10 is a schematic cross-sectional view showing an object to be processed in a preliminary experiment. FIG. 11 is a graph showing the results of PEC etching in a preliminary experiment. FIG. 12 is a schematic cross-sectional view and a top view showing a cathode pad configured in such a manner that the edge of the cathode pad becomes the edge of the mask defining the etched area. FIG. 13 is a schematic cross-sectional view and a top view showing a non-conductive mask and a cathode pad configured in such a manner that the edge of the non-conductive mask becomes the edge of the mask defining the etched area. FIG. 14 is a photograph showing the results of PEC etching using a Ti mask. FIG. 15( a ) is a photograph showing a treatment object on which a non-conductive mask and a cathode pad are formed, and FIG. 15( b ) and FIG. 15( c ) are enlarged photographs of a portion of the region indicated by the circle in the upper right corner of FIG. 15( a ).

10: Etching object (wafer)

11: Substrate (conductive GaN substrate) (semi-insulating sapphire substrate)

12: Epitaxial layer (III-nitride layer)

20: Etched surface

21: Etched area

30: Cathode pad (conductive component)

40:Cathode region

50: Mask (non-conductive mask)

100: Processing object

200:PEC etching device

201: Etching fluid

202: Upper surface of etching liquid

210:Container

220: Light source

221: UV light

L: Distance

Claims (23)

A method for manufacturing a structure, comprising: Preparing a treatment object, the treatment object comprising: an etching object, comprising an etched surface comprising a conductive group III nitride, and an etched region disposed on the etched surface; a conductive component, arranged to contact at least a portion of the surface of the conductive region of the etched object electrically connected to the etched region; and a mask, formed on the etched surface and comprising a non-conductive material; and The object to be processed is immersed in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidant that receives electrons, and the etched area and the conductive component are in contact with the etching solution, and the etched surface is irradiated with light through the etching solution, thereby etching the group III nitride constituting the etched area; and the edge of the etched area is defined to include an edge of the mask instead of an edge of the conductive component. The method for manufacturing a structure as described in claim 1, wherein the distance between the edge of the mask defining the etched area and the edge of the conductive member is greater than 5 μm. A method for manufacturing a structure as described in claim 1 or claim 2, wherein in the step of etching the group III nitride constituting the etched area, the etching is performed in a manner such that the edge of a recess formed by the etching is formed along a position defining an edge of the etched area. A method for manufacturing a structure as described in claim 1 or claim 2, wherein the mask contains an anti-etching agent and the etching solution is acidic. A method for manufacturing a structure as described in claim 1 or claim 2, wherein the group III nitride is etched while the upper surface of the portion of the conductive component disposed on the etched surface is in contact with the etching liquid. A method for manufacturing a structure as described in claim 1 or claim 2, wherein the etching object is used as a material for a high electron mobility transistor, and the conductive component is used as an electrode of the high electron mobility transistor. A method for manufacturing a structure as described in claim 6, wherein the recess formed by etching the etched area is used as an element separation groove of the high electron mobility transistor. The method for manufacturing a structure as described in claim 1 or claim 2, wherein the conductive member is arranged along the periphery of the etching object when viewed from above. A method for manufacturing a structure as described in claim 1 or claim 2, wherein the etching object includes a semi-insulating substrate. A method for manufacturing a structure as described in claim 9, wherein the conductive member is disposed on a Group III nitride layer formed on the semi-insulating substrate. A method for manufacturing a structure as described in claim 10, wherein the area of the conductive component in contact with the etching solution is greater than 1% relative to the entire area of the upper surface of the group III nitride layer, i.e., the etched surface. A method for manufacturing a structure as described in claim 1 or claim 2, wherein the etching object includes a conductive substrate. A method for manufacturing a structure as described in claim 12, wherein the conductive member is arranged on the surface of the conductive substrate. An intermediate structure includes: An etching object including an etched surface containing a conductive group III nitride, and an etched area is arranged on the etched surface; A conductive component is arranged to contact at least a portion of the surface of the conductive area of the etching object electrically connected to the etched area; and A mask is formed on the etched surface and contains a non-conductive material; and The etched area and the conductive component are immersed in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidant for receiving electrons in a contacting state; The edge of the etched area is defined to include the edge of the mask instead of the edge of the conductive component. The intermediate structure as described in claim 14, wherein the distance between the edge of the mask defining the etched area and the edge of the conductive component is greater than 5 μm. An intermediate structure as described in claim 14 or claim 15, wherein the mask includes an anti-corrosion agent. An intermediate structure as described in claim 14 or claim 15, wherein the etching object is used as a material of a high electron mobility transistor, and the conductive component is used as an electrode of the high electron mobility transistor. An intermediate structure as described in claim 14 or claim 15, wherein the conductive member is arranged along the periphery of the etching object when viewed from above. An intermediate structure as described in claim 14 or claim 15, wherein the etching object includes a semi-insulating substrate. An intermediate structure as described in claim 14 or claim 15, wherein the etching object includes a conductive substrate. An intermediate structure as described in claim 20, wherein the conductive member is disposed on a surface of the conductive substrate. A method for manufacturing a structure, comprising: Preparing a treatment object, the treatment object comprising: an etching object, comprising an etched surface containing a conductive group III nitride, and an etched region arranged on the etched surface; and a conductive component, arranged to contact at least a portion of the surface of the conductive region of the etched object electrically connected to the etched region; and By immersing the treatment object in a conductive material containing an electron receiving In an alkaline or acidic etching solution containing an oxidant of an etchant, and in a state where the etched area and the conductive component are in contact with the etching solution, light is irradiated to the etched surface through the etching solution, thereby etching the group III nitride constituting the etched area; and the edge of the etched area is not limited to the edge of the conductive component, and the conductive component is arranged along the periphery of the etched object when viewed from above. An intermediate structure includes: An etching object including an etched surface containing a conductive group III nitride, and an etched area is arranged on the etched surface; and A conductive component is arranged to contact at least a portion of the surface of the conductive area of the etching object that is electrically connected to the etched area; and The etched area and the conductive component are immersed in an alkaline or acidic etching solution containing an oxidant that accepts electrons in a state of contact; The edge of the etched area is not limited to the edge of the conductive component, and the conductive component is arranged along the periphery of the etching object when viewed from above.