TWI836307B - 半導體結構 - Google Patents

半導體結構 Download PDF

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TWI836307B
TWI836307B TW110147706A TW110147706A TWI836307B TW I836307 B TWI836307 B TW I836307B TW 110147706 A TW110147706 A TW 110147706A TW 110147706 A TW110147706 A TW 110147706A TW I836307 B TWI836307 B TW I836307B
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Taiwan
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layer
semiconductor structure
ball pad
diameter
ball
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TW110147706A
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TW202238868A (zh
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顏江霖
郭哲宏
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聯發科技股份有限公司
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種半導體結構包括具有主動表面的半導體裸晶、覆蓋半導體裸晶的主動表面的鈍化層以及設置在鈍化層上方的後鈍化互連(PPI)層。PPI層包括具有第一直徑的球墊。聚合物層覆蓋球墊的周邊。凸塊下金屬(UBM)層設置在球墊上。UBM層的第二直徑大於球墊的第一直徑。焊球被安裝在UBM層上。

Description

半導體結構
本發明實施例通常涉及半導體封裝領域，以及更具體地，本發明涉及半導體封裝，其具有用於半導體封裝(特別地，基於RDL的封裝)的新穎球墊(ball pad)設計。
半導體領域的進步引發了信號完整性(signal integrity，SI)和電源完整性(power integrity，PI)方面的一系列問題和挑戰。封裝的互連是信號和電力傳輸的不連續點，容易受到串擾、寄生耦合、阻抗不匹配、同步開關噪聲(simultaneous switching noise，SSN)和電磁干擾(electromagnetic interference，EMI)等多種因素的影響。
阻抗控制是高速電路和系統設計中的一個重要問題。阻抗匹配對射頻(RF)和微波電路設計提出了挑戰，因為誤差的窗口隨著頻率的增加而減小。由於誤碼率的影響及脈衝失真、反射和EMI的潛在影響，高速數位電路需要非常穩定的被控阻抗。
以下發明內容僅是說明性的，而無意於以任何方式進行限制。即，提供以下概述來介紹本文描述的新穎和非顯而易見的技術的概念，重點，益處和優點。選擇的實施方式在下面的詳細描述中進一步描述。因此，以下發明內容既不旨在標識所要求保護的主題的必要特徵，也不旨在用於確定所要求保護的主題的範圍。
本發明的目的之一在於提供一種新型球墊設計的半導體結構，其能 夠改善阻抗控制。
第一方面，本發明提供了一種半導體結構，包括：半導體裸晶，具有主動表面；鈍化層，覆蓋該半導體裸晶的該主動表面；鈍化後互連(PPI)層，位於該鈍化層的上方，其中，該PPI層包括球墊，該球墊具有第一直徑；聚合物層，覆蓋該球墊的周邊；凸塊下金屬(UBM)層，被設置在該球墊上，其中，該UBM層具有第二直徑，該第一直徑小於該第二直徑；以及，焊球，被安裝在該UBM層上。
在一些實施例中，該鈍化層包括氮化矽(silicon nitride)。
在一些實施例中，該聚合物層包括環氧樹脂、聚醯亞胺、苯並環丁烯(BCB)或聚苯並噁唑(PBO)。
在一些實施例中，該聚合物層中形成有開口，以暴露該球墊的至少一部分。
在一些實施例中，該UBM層被設置在該開口內且與該球墊直接接觸。
在一些實施例中，該UBM層包括黏著層、阻擋層及潤濕層。
在一些實施例中，該焊球為無鉛球。
在一些實施例中，該無鉛球具有包括銅、銀、錫或其組合的成分。
在一些實施例中，該第一直徑介於100~200微米之間。
在一些實施例中，該第一直徑約為124微米。
在一些實施例中，該第二直徑約為200微米。
在一些實施例中，該焊球具有約220微米的第三直徑，以及，焊球間距為0.35毫米。
在一些實施例中，該PPI層包括不連續的偽金屬環，其被設置為在距該球墊的周邊一定距離處環繞該球墊。
在一些實施例中，該不連續的偽金屬環與該球墊共面。
在一些實施例中，該PPI層包括被設置在該球墊周邊的偽金屬，其中，該偽金屬是連續的或不連續的。
在一些實施例中，該PPI層包括圍繞該球墊且連接到電源電壓或接地電壓的連續的金屬環。
在一些實施例中，該半導體結構還包括：模塑料，圍繞該半導體裸晶。
第二方面，本發明提供了一種半導體結構，包括：半導體裸晶，具有主動表面；鈍化層，覆蓋該半導體裸晶的該主動表面；模塑料，圍繞該半導體裸晶；以及，重佈線層(RDL)結構，位於該鈍化層和該模塑料的上方，其中，該RDL結構包括鈍化後互連(PPI)層，該PPI層包括球墊、覆蓋該球墊周邊的聚合物層、位於該球墊上的凸塊下金屬(UBM)層和被安裝在該UBM層上的焊球，其中，該球墊具有第一直徑，該UBM層具有第二直徑，該第一直徑小於該第二直徑。
在一些實施例中，該RDL結構的厚度小於10微米。
在一些實施例中，該鈍化層包括氮化矽。
在一些實施例中，該聚合物層包括環氧樹脂、聚醯亞胺、苯並環丁烯(BCB)或聚苯並噁唑(PBO)。
在一些實施例中，該聚合物層中形成有開口，以暴露該球墊的至少一部分。
在一些實施例中，該UBM層被設置在該開口內且與該球墊直接接觸。
在一些實施例中，該第一直徑介於100~200微米之間。
在一些實施例中，該第一直徑約為124微米。
在一些實施例中，該第二直徑約為200微米。
在一些實施例中，該焊球具有約220微米的第三直徑，以及，焊球間 距為0.35毫米。
在一些實施例中，該PPI層包括不連續的偽金屬環，其被設置為在距該球墊的周邊一定距離處環繞該球墊。
在一些實施例中，該不連續的偽金屬環與該球墊共面。
在一些實施例中，該PPI層包括被設置在該球墊周邊的偽金屬，其中，該偽金屬是連續的或不連續的。
在一些實施例中，該PPI層包括圍繞該球墊且連接到電源電壓或接地電壓的連續的金屬環。
本發明內容是通過示例的方式提供的，並非旨在限定本發明。在下面的詳細描述中描述其它實施例和優點。本發明由申請專利範圍限定。
1:半導體封裝
20:上部封裝
230:連接元件
10:下部封裝
152:穿模通孔
100a:半導體裸晶100的主動表面
100b:半導體裸晶100的後表面
320:載體基板
152:穿模通孔
150:模塑料
102:I/O焊盤
112:互連部件
120:RDL結構
GP:接地層
122:球墊
123:偽金屬
140a:開口
130:焊球
140:凸塊下金屬(UBM)層
PM0:聚合物層
110:鈍化層
100:半導體裸晶
105:裸晶附著膜
PPI-1,PPI-2,PPI-3,PPI-4:鈍化後互連(PPI)層
PM1,PM2,PM3,PM4,PM5,PM:保護層
附圖(其中，相同的數位表示相同的組件)示出了本發明實施例。包括的附圖用以提供對本公開實施例的進一步理解，以及，附圖被併入並構成本公開實施例的一部分。附圖示出了本公開實施例的實施方式，並且與說明書一起用於解釋本公開實施例的原理。可以理解的是，附圖不一定按比例繪製，因為可以示出一些部件與實際實施中的尺寸不成比例以清楚地說明本公開實施例的概念。
第1圖是根據本發明一實施例示出的半導體封裝的示意截面圖。
第2圖是示出在第1圖中半導體封裝1的焊球側上的球墊122的佈局的一部分的示意截面圖。
第3圖是沿第2圖中I-I’線的半導體封裝的局部剖視圖。
在下面的詳細描述中，為了說明的目的，闡述了許多具體細節，以便所屬技 術領域中具有通常知識者能夠更透徹地理解本發明實施例。然而，顯而易見的是，可以在沒有這些具體細節的情況下實施一個或複數個實施例，不同的實施例或不同實施例中披露的不同特徵可根據需求相結合，而並不應當僅限於附圖所列舉的實施例。
以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及申請專利範圍當中使用了某些詞彙來指稱特定的組件。所屬技術領域中具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同樣的組件。本說明書及申請專利範圍並不以名稱的差異來作為區別組件的方式，而係以組件在功能上的差異來作為區別的基準。本發明的範圍應當參考后附的申請專利範圍來確定。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於…”的意思。此外，術語“耦接”意指間接或直接的電氣連接。因此，若文中描述一個裝置耦接至另一裝置，則代表該裝置可直接電氣連接於該另一裝置，或者透過其它裝置或連接手段間接地電氣連接至該另一裝置。文中所用術語“基本”或“大致”係指在可接受的範圍內，所屬技術領域中具有通常知識者能夠解決所要解決的技術問題，基本達到所要達到的技術效果。舉例而言，“大致等於”係指在不影響結果正確性時，所屬技術領域中具有通常知識者能夠接受的與“完全等於”有一定誤差的方式。
應當理解的是，當稱呼一個元件(element)或層(layer)在另一個元件或層之上(on)、連接到另一個元件或層(connected to)或耦接到另一個元件或層(coupled to)時，它可以直接在、連接或耦接到該另一個元件或層也可能在兩者中間存在其它元件或層。相反，當稱呼元件或層直接/物理位於另一個 元件或層之上(on)、直接連接到另一個元件或層(connected to)或耦接到另一個元件或層(coupled to)時，則不存在中間的元件或層。相同的數值始終指代相同的元件。如本文所用，術語“和/或”包括一個或多個相關聯的所列項目的一個或多個的所有組合。
本發明涉及一種具有能夠改善信號阻抗控制的新型球墊設計的半導體結構，其適用於各種封裝領域，如倒裝芯片組裝(flip-chip assembly)、晶圓級芯片規模封裝(wafer-level chip scale package，WLCSP)、扇出型WLCSP封裝、三維集成電路(three-dimensional integrated circuit，3D-IC)堆棧(stack)和/或任何其它先進的封裝技術領域等。針對I/O電觸點，扇出型WLCSP結構能夠提供更大間距的凸點/凸塊(bump)。
具有高功率電流的高速和/或射頻芯片封裝通常需要較小的封裝電阻或電感(resistance or inductance，R/L)。基於RDL(re-distribution layer，重佈線層)的封裝由於其介電質(dielectric)厚度(1~10μm)比通常為20~100μm厚的其它封裝基板更薄，因此已成為新的封裝候選項。基於RDL的封裝的RDL結構的厚度更薄，這意味著它可以提供更短的電源/接地(power/ground，P/G)路徑，從而減少R/L。
由於焊球具有更大的橫截面積(cross-section area)，其會伴隨著更大的寄生電容，因此，芯片封裝的阻抗下降(impedance drop)通常在其焊球側(ball side)更大。然而，由於RDL結構的介電質層相對較薄，因此，基於RDL的封裝的阻抗下降在該焊球側甚至更糟。為了減輕基於RDL的封裝增加的阻抗下降，可以在第n個RDL層(如TTI層)的球墊下方的第(n-1)個RDL層處採用特殊的槽孔(void)設計。可以理解地，在位於次外層的TTI層中特意打槽孔(例如，槽孔也可稱為空洞/空槽/空洞等，其未填充任何形式的材質)，以減輕基於RDL的封裝增加的阻抗下降。然而，為了實現這種特殊的槽孔設計，需要更昂貴的 四層RDL或中介層基板(interposer substrate)，這會浪費封裝的佈線資源。此外，特殊的槽孔設計降低了RDL電路佈線的靈活性。本發明提出的方案能夠解決這些問題。
請參考第1圖。第1圖是根據本發明一實施例示出的示例性半導體封裝的示意截面圖。例如，如第1圖所示，半導體封裝1可以是層疊封裝(package-on-package，PoP)，在第1圖的示例中，其示出了包括上部封裝20和下部封裝10。應當理解的是，第1圖中的PoP封裝僅用於說明目的，所公開的球墊(ball pad)設計可應用於其它的封裝類型(如基於RDL的封裝)。半導體封裝1包括半導體裸晶(semiconductor die)100，其被模塑料(molding compound)150圍繞。根據本發明一實施例，例如，模塑料150可以包括環氧樹脂(epoxy resin)。根據本發明一實施例，半導體裸晶100的主動表面(active surface)100a被覆蓋有保護層(protective layer)PM。用於進一步連接的互連部件(Interconnect features)112，如微凸塊(micro-bumps)或導電跡線/走線(conductive traces)，被形成在保護層PM中。模塑料150的下表面(lower surface)可與保護層PM的下表面齊平(flush)。
根據本發明的一實施例，重佈線層(RDL)結構120被形成在模塑料150的下表面(lower surface)和保護層PM的下表面上。根據本發明的一實施例，RDL結構120可以包括多個PPI(post-passivation interconnect，鈍化後互連)層和多個聚合物層(polymer layer)。例如，圖中示出四個PPI層和五個聚合物層。根據本發明的一實施例，多個球墊(ball pad)122被形成在最外層(outermost)的PPI層(例如，本示例的第四PPI層)中。多個焊球(solder ball)130分別形成在多個球墊122上。根據本發明的一實施例，RDL結構120的厚度可小於10微米(micrometer)。根據本發明的一實施例，RDL結構120的厚度可為1~10微米。
根據本發明一實施例，例如，可在模塑料150中形成多個穿模通孔 (through mold via)152。載體基板(carrier substrate)320被提供在半導體裸晶100的背面(rear surface，即與主動表面相對的另一表面)100b上。載體基板320具有互連或跡線，其利用穿模通孔152將上部封裝(upper package)20的連接元件230與下面(underlying)的RDL結構120進行電連接。裸晶附著膜(die attach film)105被設置在半導體裸晶100的背面100b和載體基板320之間。根據本發明的另一實施例，載體基板320可以被替換為重佈線層(RDL)結構，在這種情況下，上部的RDL結構320可以被設置在半導體裸晶100的背面100b上，類似地，該上部的RDL結構320具有互連或跡線，其利用穿模通孔152將上部封裝20的連接元件230和下面的RDL結構120電連接。裸晶附著膜105被設置在半導體裸晶100的背面100b和上部的RDL結構320之間。
請參考第2圖和第3圖。第2圖是示出第1圖中半導體封裝1的焊球側上的球墊122的佈局的一部分的示意圖。第3圖是沿第2圖中的I-I’線的半導體封裝的局部剖視圖，其中，相同的層、區域或元件由相同的數值編號或標籤表示。
如第3圖所示，多個輸入/輸出(input/output，I/O)焊盤/焊墊(pad)102被提供在/位於半導體裸晶100的主動表面100a上。例如，I/O焊盤102可以是鋁焊盤，但本發明並不限於此。在一些實施例中，例如，I/O焊盤102可以是導電材料，包括但不限於銅(copper，Cu)、鎢(tungsten，W)、金(gold，Au)、銀(silver，Ag)、鋁(aluminum，Al)、鉛(lead，Pb)、錫(tin，Sn)及其合金。鈍化層110覆蓋基板100的主動表面以及每一個輸入/輸出接墊102的周邊(perimeter)。根據本發明一實施例，在鈍化層110中形成有開口(opening)110a，以暴露每一個輸入/輸出焊墊102的中心表面區域(central surface region)。根據本發明一實施例，鈍化層110可以包括氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)等。
根據本發明的一個實施例，例如，可以在鈍化層110上形成有保護層 (protective layer)PM和聚合物層(polymer layer)PM0。例如，保護層PM可以由氮化矽、氧化矽或其它絕緣材料構成。保護層PM可以通過掩膜沉積工藝、沉積蝕刻工藝等形成。根據本發明一實施例，開口OP被形成在保護層PM和聚合物層PM0中，以暴露每個I/O焊盤102的中心表面區域。
在本發明的一實施例中，重佈線層結構120被設置在聚合物層PM0上。RDL結構120電連接至I/O墊102。例如，RDL結構120可包括四個PPI層PPI-1~PPI-4和五個聚合物層PM1~PM5。應當理解的是，PPI層和聚合物層的數量僅用於說明目的，而不用於限制本發明，本發明對此數量不做任何限制。例如，在一些實施例中，取決於設計要求，RDL結構120可以僅包括三個PPI層或可以包括四個以上的PPI層。
根據本發明一實施例，例如，PPI層PPI-1~PPI-4中的每一個可以包括銅(Cu)層。根據本發明一實施例，例如，PPI層PPI-1~PPI-4中的每一個還可以包括位於銅層下方的鈦(Ti)層。根據本發明一實施例，例如，聚合物層PM1~PM5可以包括環氧樹脂(epoxy)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene，BCB)或聚苯並噁唑(polybenzoxazole，PBO)，但本發明並不限於此。例如，聚合物層PM1~PM5可以是聚醯亞胺層。
根據本發明一實施例，對於如第3圖所示的四層RDL結構來說，信號走線(signal trace)，如數位/類比信號走線，可通常設置在第一PPI層PPI-1和第二PPI層PPI-2中，以及，接地層(ground plane)GP可設置在第三PPI層PPI-3中，其中，球墊122被設置在最外層的PPI層(如第四PPI層PPI-4)中。再例如，對於三層RDL結構來說，諸如數位/類比信號走線等的信號走線可設置在第一PPI層中，以及，接地層可設置在第二PPI層中，其中，球墊122被設置在最外層的PPI層(如第三PPI層PPI-3)中。在最外層的PPI層中至少形成有球墊122。開口140a被形成在第五聚合物層PM5中，以暴露球墊122的中心區域。根據本發明一實施 例，凸塊下金屬(under-bump-metallurgy，UBM)層140被設置在開口140a內且與球墊122直接接觸(direct contact)，即UBM層140與球墊122物理接觸。
根據本發明一實施例，焊球130(諸如無鉛球)被形成在UBM層140上。例如，無鉛球可具有包括銅、銀、錫或其組合的成分，但本發明並不限於此。為了形成焊球130，例如，可將無鉛焊料塗佈到UBM層140上。再例如，可通常將無鉛焊料在240-260攝氏度下回流1到3分鐘，使得無鉛焊料回流以形成焊球130並與UBM層140連接。在一些實施例中，可通過使用電鍍工藝(electroplating process)或球安裝工藝(ball mounting process)來形成焊球130。
UBM層140可以包括黏著層(adhesion layer)、阻擋層(barrier layer)和潤濕層(wetting layer)，但本發明並不限於此。UBM層140可以包括鈦、氮化鈦、鈦鉭、氮化鈦鉭、鎢、鈦鎢、鎳、金、鉻、銅、銅合金或其任意組合，但本發明並不限於此示例。凡是可用於UBM的任何合適的材料或材料層均應包括在本發明的保護範圍內。
第2圖示出了焊球130、UBM層140和下面的球墊(underlying ball pad)122的投影圓形區域的同心佈局的透視圖。應當理解到的是，焊球和球墊的佈局不是按比例繪製的。如第3圖所示，例如，球間距(ball pitch，焊球與焊球之間的間距)P可以是0.35毫米(millimeter，mm)，以及，焊球130的直徑d3可大約為220微米。根據本發明一實施例，UBM層140的環形(circular-shaped)區域的直徑d2可約為200微米。在本發明的一實施例中，球墊122的直徑d1可約為100~200微米，例如，124微米(um)。應當說明的是，在本發明中，直徑d1小於直徑d2和d3這兩者是技術特徵之一。本發明通過減小球墊122的尺寸(如將球墊122的直徑d1設置為小於直徑d2和d3)，球墊122的電容性將是小的，從而可以獲得更高的阻抗，例如，其阻抗可以比原來的設計提高大約20歐姆，因此，基於減小尺寸的球墊設計，無需特殊的槽孔設計就能夠實現很好的阻抗控制。例如， 在RDL結構具有4層PPI層的示例中，不需要專門在次外層的PPI層(如第三PPI層)中打槽孔做阻抗補償，因為本發明透過減小/縮小最外層的PPI層(如第四PPI層)中的球墊尺寸或直徑就能夠達到阻抗補償的目的。而且，由於本發明無需專門在次外層的PPI層中挖槽孔做阻抗補償，從而，在RDL結構層數相同的情形中將具有更多的一個PPI層可用來佈線，或者，可以減少層數/RDL結構的厚度。
根據本發明一實施例，在距離球墊122(例如，球墊122位於第四PPI層PPI-4中)的周邊一定距離(如預設距離)處提供有偽金屬(dummy metal)123，以增加對結構應力的支撐。在本發明實施例中，偽金屬123不會用來傳遞訊號，而是為增加結構的應力專門設置的。在一些實施例中，偽金屬123可以是連續的或者不連續的，其可以在球墊122周邊任意散佈/佈置，本發明對此不做任何限制。在一些實施例中，偽金屬123設置在焊球130正下方且在俯視圖中與焊球130至少部分重疊。例如，連續或不連續的偽金屬123可以被佈置為環繞該球墊122，如形成圍繞球墊122整圈的環、3/4圓、半圓，或其它形狀等，本發明對此不做任何限制。作為舉例，如圖2及圖3所示，不連續的矩形的偽金屬123在球墊122周邊佈置，且偽金屬123設置在焊球130正下方且在俯視圖中與焊球130至少部分重疊。如第3圖所示，不連續的偽金屬123(例如，偽金屬環)與球墊122共面(coplanar)。不連續的偽金屬123有助於釋放通常集中在PPI層邊緣周圍的聚合物層上的高應力，從而防止裂紋的缺陷。根據本發明的另一實施例，偽金屬123可以被替換為是圍繞球墊122且連接到電源電壓或接地電壓的連續的金屬環。在一示例中，該連接到電源電壓或接地電壓的連續的金屬環與球墊122共面。在一實施例中，該連續的金屬環與球墊122周邊的電源金屬線/層或接地金屬線/層是一體形成的。本發明實施例提供的位於球墊122周邊的偽金屬或耦接到電源電壓/接地電壓的連續金屬環能夠用來做結構應力上的支撐。
使用本發明是有利的，因為通過縮小(shrinking)球墊122的直徑d1， 可以改進基於RDL的封裝的阻抗控制。根據實驗結果，在基於RDL的封裝的焊球側的阻抗可以從67歐姆增加到87歐姆。因此，可以提高基於RDL的封裝的信號完整性。此外，由於省去了球墊下方的槽孔電路設計(void circuit design)，因此增加了RDL結構的佈線靈活性，且降低了封裝成本。
在申請專利範圍中使用諸如“第一”，“第二”，“第三”等序數術語來修改申請專利要素，其本身並不表示一個申請專利要素相對於另一個申請專利要素的任何優先權、優先級或順序，或執行方法動作的時間順序，但僅用作標記，以使用序數詞來區分具有相同名稱的一個申請專利要素與具有相同名稱的另一個元素要素。
雖然已經對本發明實施例及其優點進行了詳細說明，但應當理解的係，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更，例如，可以通過結合不同實施例的若干部分來得出新的實施例。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。所屬技術領域中具有通常知識者皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
320:載體基板
152:穿模通孔
150:模塑料
102:I/O焊盤
112:互連部件
120:RDL結構
GP:接地層
122:球墊
123:偽金屬
140a:開口
130:焊球
140:凸塊下金屬(UBM)層
PM0:聚合物層
110:鈍化層
100:半導體裸晶
105:裸晶附著膜
PPI-1,PPI-2,PPI-3,PPI-4:鈍化後互連(PPI)層
PM1,PM2,PM3,PM4,PM5,PM:保護層

Claims (25)

  1. 一種半導體結構，包括：半導體裸晶，具有主動表面；鈍化層，覆蓋該半導體裸晶的該主動表面；鈍化後互連(PPI)層，位於該鈍化層的上方，其中，該PPI層包括球墊，該球墊具有第一直徑；聚合物層，覆蓋該球墊的周邊；凸塊下金屬(UBM)層，被設置在該球墊上，其中，該UBM層具有第二直徑，位於該鈍化層上方的該鈍化後互連(PPI)層中的該球墊的該第一直徑小於該第二直徑，以增大阻抗；以及，焊球，被安裝在該UBM層上；其中，該PPI層包括被設置在該球墊周邊的偽金屬，該偽金屬是連續的或不連續的，該偽金屬設置在該焊球正下方且在俯視圖中與該焊球至少部分重疊。
  2. 如請求項1之半導體結構，其中，該鈍化層包括氮化矽(silicon nitride)；和/或，該聚合物層包括環氧樹脂、聚醯亞胺、苯並環丁烯(BCB)或聚苯並噁唑(PBO)。
  3. 如請求項1之半導體結構，其中，該聚合物層中形成有開口，以暴露該球墊的至少一部分。
  4. 如請求項3之半導體結構，其中，該UBM層被設置在該開口內且與該球墊直接接觸。
  5. 如請求項1之半導體結構，其中，該UBM層包括黏著層、阻擋層及潤濕層。
  6. 如請求項1之半導體結構，其中，該焊球為無鉛球。
  7. 如請求項6之半導體結構，其中，該無鉛球具有包括銅、銀、 錫或其組合的成分。
  8. 如請求項1之半導體結構，其中，該第一直徑介於100~200微米之間。
  9. 如請求項1之半導體結構，其中，該第一直徑約為124微米；和/或，該第二直徑約為200微米。
  10. 如請求項1之半導體結構，其中，該焊球具有約220微米的第三直徑，以及，焊球間距為0.35毫米。
  11. 如請求項1之半導體結構，其中，該偽金屬包括不連續的偽金屬環，其被設置為環繞該球墊。
  12. 如請求項11之半導體結構，其中，該不連續的偽金屬環與該球墊共面。
  13. 如請求項1之半導體結構，其中，該偽金屬包括圍繞該球墊且連接到電源電壓或接地電壓的連續的金屬環。
  14. 如請求項1之半導體結構，其中，該半導體結構還包括：模塑料，圍繞該半導體裸晶。
  15. 一種半導體結構，包括：半導體裸晶，具有主動表面；鈍化層，覆蓋該半導體裸晶的該主動表面；模塑料，圍繞該半導體裸晶；以及，重佈線層(RDL)結構，位於該鈍化層和該模塑料的上方，其中，該RDL結構包括鈍化後互連(PPI)層，該PPI層包括球墊、覆蓋該球墊周邊的聚合物層、位於該球墊上的凸塊下金屬(UBM)層和被安裝在該UBM層上的焊球，其中，該球墊具有第一直徑，該UBM層具有第二直徑，位於該鈍化層上方的該鈍化後 互連(PPI)層中的該球墊的該第一直徑小於該第二直徑，以增大阻抗；其中，該PPI層包括被設置在該球墊周邊的偽金屬，該偽金屬是連續的或不連續的，該偽金屬設置在該焊球正下方且在俯視圖中與該焊球至少部分重疊。
  16. 如請求項15之半導體結構，其中，該RDL結構的厚度小於10微米。
  17. 如請求項15之半導體結構，其中，該鈍化層包括氮化矽；和/或，該聚合物層包括環氧樹脂、聚醯亞胺、苯並環丁烯(BCB)或聚苯並噁唑(PBO)。
  18. 如請求項15之半導體結構，其中，該聚合物層中形成有開口，以暴露該球墊的至少一部分。
  19. 如請求項18之半導體結構，其中，該UBM層被設置在該開口內且與該球墊直接接觸。
  20. 如請求項15之半導體結構，其中，該第一直徑介於100~200微米之間。
  21. 如請求項15之半導體結構，其中，該第一直徑約為124微米；和/或，該第二直徑約為200微米。
  22. 如請求項15之半導體結構，其中，該焊球具有約220微米的第三直徑，以及，焊球間距為0.35毫米。
  23. 如請求項15之半導體結構，其中，該偽金屬包括不連續的偽金屬環，其被設置為環繞該球墊。
  24. 如請求項23之半導體結構，其中，該不連續的偽金屬環與該球墊共面。
  25. 如請求項15之半導體結構，其中，該偽金屬包括圍繞該球墊 且連接到電源電壓或接地電壓的連續的金屬環。
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