TWI835200B - Quick response switching power converter and conversion control circuit thereof - Google Patents

Abstract

A conversion control circuit is configured to control a power stage circuit according to a first feedback signal and a second feedback signal, wherein the conversion control circuit includes an error amplifier circuit, a ramp signal generation circuit, a pulse width modulation circuit, and a quick response control circuit. The quick response control circuit is configured to perform a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal exceeds the reference threshold, adjusting the slope of a ramp signal to accelerate the increase or decrease of the duty of a PWM signal, thereby accelerating the transient response of a quick response switching converter.

Description

Fast response switching power converter and its conversion control circuit

The present invention relates to a switching power converter, in particular to a fast response switching power converter. The present invention also relates to a conversion control circuit suitable for a fast response switching power converter.

Under ideal conditions, switching power converters in the prior art maintain a stable output power regardless of changes in the load to which they are coupled. However, in actual situations, the power supply is bound to be affected by the transient response of the load, causing the output power to change. Please refer to Figure 1, which is a waveform diagram of a load transient response in the prior art. As shown in Figure 1, when the load current ILoad changes sharply, the output voltage VOUT generated by the power supply will respond. When the load current ILoad rises sharply, the output voltage VOUT will undershoot. and restores stability (as shown in the dotted box Sq1); when the value of the load current ILoad drops sharply, the output voltage VOUT will first overshoot, then undershoot and return to stability (as shown in the dotted box Sq2).

In view of this, the present invention aims at the shortcomings of the above-mentioned prior art and proposes a fast response switching power converter and its conversion control circuit to mitigate the negative impact caused by the load transient response and thereby improve the output generated by the power supply. Power supply stability.

The present invention provides a conversion control circuit, suitable for a fast response switching power converter, for controlling a power stage circuit based on a first feedback signal and a second feedback signal. The conversion control circuit includes: a An error amplification circuit is used to amplify the difference between the first feedback signal and a reference signal to generate an error amplification signal; a slope signal generation circuit is used to generate a slope signal; a pulse width modulation circuit, for comparing the error amplification signal and the ramp signal to generate a pulse width modulation signal, wherein the pulse width modulation signal is used to control the power stage circuit and thereby adjust an output voltage to a preset target level; and a A quick response control circuit is used to perform a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal When the reference threshold is exceeded, the slope of the ramp signal is adjusted to accelerate the increase or decrease of the duty cycle of the pulse width modulation signal, thereby accelerating the transient response of the fast response switching power converter; wherein, the first The feedback signal and the second feedback signal are positively related to the output voltage; when the second feedback signal exceeds the reference threshold, it indicates that the output voltage exceeds an output threshold.

In some embodiments, the quick response control function further includes: when the second feedback signal exceeds the reference threshold, adjusting the slope of the ramp signal according to the number of times the quick response control signal is enabled to adaptively accelerate the improvement or Accelerate and reduce the duty cycle of the pulse width modulation signal, thereby accelerating the transient response of the fast response switching power converter.

In some embodiments, the ramp signal generating circuit includes a ramp current source, a capacitor and at least one control switch. The at least one control switch is used to control the ramp current source to integrate the capacitor according to a clock signal, thereby generating the Ramp signal; the fast response control circuit includes at least one adjustment current source circuit, wherein the adjustment current source circuit is used to generate an adjustment current source circuit. When the fast response control signal is enabled, the fast response control circuit is used to superimpose the adjustment current and the current of the ramp current source to integrate the capacitor, thereby adjusting the slope of the ramp signal to accelerate the increase or Accelerate and reduce the duty cycle of the pulse width modulation signal, thereby accelerating the transient response of the fast response switching power converter.

In some embodiments, the at least one reference threshold includes a first reference threshold and/or a second reference threshold, and the output threshold includes a first output threshold and/or a second output threshold; wherein, when the second When the feedback signal is higher than the first reference threshold, the fast response control circuit controls the adjustment current to increase the absolute value of the slope of the ramp signal, thereby accelerating the reduction of the duty cycle of the pulse width modulation signal, wherein the second A feedback signal higher than the first reference threshold indicates that the output voltage is higher than the first output threshold, wherein the first output threshold is higher than the preset target level; when the second feedback signal is lower than the second reference When the threshold is reached, the fast response control circuit controls the adjustment current to reduce the absolute value of the slope of the ramp signal, thereby accelerating the increase in the duty cycle of the pulse width modulation signal, wherein the second feedback signal is lower than the second reference The threshold indicates that the voltage value of the output power supply is lower than the second output threshold, wherein the second output threshold is lower than the preset target level.

In some embodiments, the above-mentioned fast response control function further includes: adjusting the slope of the slope signal with an n-th adjustment amount when the fast response control signal is enabled for the nth time; and when the fast response control signal is enabled for the nth time, When enabled for +1 time, adjust the slope of the slope signal with an n+1th adjustment amount; where n is a positive integer, and the absolute value of the nth adjustment amount is greater than or equal to the n+1th adjustment The absolute value of a quantity.

In some embodiments, the above-mentioned quick response control function further includes: resetting the number of times the quick response control signal is enabled during a timeout period after the mth time the quick response control signal is enabled, where m is A positive integer.

In some embodiments, the above-mentioned quick response control function further includes: performing at least once the absolute value of the n-th adjustment amount being greater than the absolute value of the n+1-th adjustment amount.

In some embodiments, the first feedback signal is the second feedback signal.

In some embodiments, the ramp signal further includes an inductor current-related signal, and the inductor current-related signal is related to a current of an inductor, a conduction current of at least one power switch, or an output current of an output power supply.

In some embodiments, the above-mentioned fast response control function further includes at least one of the following: when the second feedback signal exceeds a third reference threshold, stopping controlling the power stage circuit; clamping the error amplification signal so that it does not exceed a preset clamp value; and/or when the second feedback signal exceeds a fourth reference threshold, adjust the frequency of the clock signal.

The present invention also provides a fast response switching power converter, including: a power stage circuit, including at least one power switch, the at least one power switch is used to switch one end of an inductor and/or the other end of the inductor. Convert an input power supply to generate an output power supply; the above-mentioned conversion control circuit is used to control the at least one power switch according to the first feedback signal and the second feedback signal related to the output voltage of the output power supply. ; And a feedback circuit for generating the first feedback signal and the second feedback signal according to the output voltage.

The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and achieved effects of the present invention.

10: Fast response switching power converter

100:Conversion control circuit

110: Error amplifier circuit

120:Ramp signal

130: Pulse width modulation circuit

131: Comparator

132: Logic circuit

140: Fast response control circuit

141A: Comparator

141B: Comparator

142: Adjustment circuit

143A: Adjust current source circuit

143B: Adjust current source circuit

200:Power stage circuit

210:Drive circuit

300:Feedback circuit

300A: Feedback circuit

300B: Feedback circuit

301: Voltage dividing circuit

302: Voltage dividing circuit

400: Clock signal adjustment circuit

AS1-AS4: Adjustment signal

Cout: output capacitor

Cr: capacitor

CLK: clock signal

CNT: Enabled times

CS1-CS2: comparison signal

duty1,duty2: duty cycle

G1-G2: control signal

Ir: current of ramp current source

Isp: adjust current

IL: inductor current

ILoad: load current

IS1: first current source

IS2: Second current source

ISr: ramp current source

k: magnification

L:Inductor

LD: external load

MS: relay signal

RST: reset signal

S1: first switch

S2: Second switch

S100-S400: Steps

S210-S240: Steps

S221-S228: Steps

Spwm: pulse width modulation signal

Spwm’: initial pulse width modulation signal

SpwmL: pulse width modulation signal

Sq1-Sq7: dashed box

Sr: control switch

t1-t9: time point

tto: timeout time

TOP: timeout period

Q1-Q2: Power switch

Rfb1-Rfb6: resistor

Vclamp: preset clamp value

Vea: error amplification signal

Vfb1: first feedback signal

Vfb2: second feedback signal

Vramp, Vramp2, Vramp3: ramp signal

Vramp1: initial ramp signal

Vref: reference signal

Vthr1: first reference threshold

Vthr2: second reference threshold

Vthr3: third reference threshold

Vthr4: fourth reference threshold

Vtho1: first output threshold

Vtho2: second output threshold

VIN: input voltage

VOUT: output voltage

W1, W4, W6: dashed waveform

W2,W5,W7: solid line waveform

W3: dotted line waveform

Figure 1 is a waveform diagram of a load transient response in the prior art.

FIG. 2 is a module block diagram of a fast response switching power converter according to an embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of an error amplification circuit in an embodiment of the present invention.

FIG. 4 is a schematic circuit diagram of a ramp signal generating circuit in an embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a pulse width modulation circuit in an embodiment of the present invention.

FIG. 6A is a circuit schematic diagram of a fast response control circuit in one embodiment of the present invention.

FIG. 6B is a schematic circuit diagram of an adjustment circuit in an embodiment of the present invention.

FIG. 7 is a voltage waveform diagram of a ramp signal and a pulse width modulation signal in an embodiment of the present invention.

FIG. 8A is a schematic circuit diagram of a feedback circuit in an embodiment of the present invention.

FIG. 8B is a schematic circuit diagram of a feedback circuit in another embodiment of the present invention.

FIG. 9A is an operation flow chart of a fast response switching power converter according to an embodiment of the present invention.

FIG. 9B is an operation flow chart of the conversion control circuit in one embodiment of the present invention.

FIG. 9C is a flow chart of a fast response control circuit performing a fast response control function in one embodiment of the present invention.

FIG. 10 is a signal waveform diagram of a fast response switching power converter in one embodiment of the present invention.

Figure 11A is a current waveform diagram (1) of the adjusted current in some embodiments of the present invention.

Figure 11B is a current waveform diagram (2) of the adjusted current in some embodiments of the present invention.

Figure 11C is a current waveform diagram (3) of the adjusted current in some embodiments of the present invention.

FIG. 12 is a schematic circuit diagram of a ramp signal generating circuit in another embodiment of the present invention.

FIG. 13 is a voltage waveform diagram of a ramp signal and a pulse width modulation signal in another embodiment of the present invention.

FIG. 14A is a signal waveform diagram of a fast response control circuit in one embodiment of the present invention.

FIG. 14B is a signal waveform diagram of a fast response control circuit in another embodiment of the present invention.

FIG. 15 is a schematic circuit diagram of a clock signal adjustment circuit in an embodiment of the present invention.

16A to 16J are circuit schematic diagrams of power stage circuits in some embodiments of the present invention.

Figure 17 is a signal simulation waveform diagram of a fast response switching power converter in one embodiment of the present invention.

The diagrams in the present invention are schematic and are mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale. For the sake of clear explanation, many practical details will be explained in the following description, but this is not intended to limit the patentable scope of the present invention.

Please refer to FIG. 2 , which is a module block diagram of a fast response switching power converter 10 in one embodiment of the present invention. As shown in FIG. 2 , the fast response switching power converter 10 includes a conversion control circuit 100 , a power stage circuit 200 and a feedback circuit 300 . The conversion control circuit 100 is used to control the power stage according to a first feedback signal Vfb1 and a second feedback signal Vfb2 Circuit 200. The power stage circuit 200 is used to switch one end of the inductor L and/or the other end of the inductor L to convert an input power supply, and then generate an output power supply to an external load LD, where the input power supply includes an input voltage VIN and an input current. , the output power supply includes the output voltage VOUT and the output current. The feedback circuit 300 is used to generate the first feedback signal Vfb1 and the second feedback signal Vfb2 according to the output voltage VOUT. The structure and function of each of the conversion control circuit 100, the power stage circuit 200 and the feedback circuit 300 will be explained in detail below, and the arrangement of each other will be described.

In some embodiments, the conversion control circuit 100 includes an error amplification circuit 110, a ramp signal generation circuit 120, a pulse width modulation circuit 130 and a fast response control circuit 140, wherein the error amplification circuit 110 is coupled to the pulse width modulation circuit. The variable circuit 130 and the feedback circuit 300 are provided. The slope signal generating circuit 120 is coupled to the pulse width modulation circuit 130 and the fast response control circuit 140 . The structures and functions of the error amplification circuit 110, the ramp signal generation circuit 120, the pulse width modulation circuit 130 and the fast response control circuit 140 will be explained in detail below, as well as how they are arranged.

Please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of the error amplification circuit 110 in one embodiment of the present invention. The error amplification circuit 110 is used to amplify the difference between the first feedback signal Vfb1 and a reference signal Vref. An error amplified signal Vea. As shown in FIG. 3 , in some embodiments, the error amplifier circuit 110 is an error amplifier, wherein the non-inverting input terminal of the error amplifier is used to receive the reference signal Vref, and the inverse input terminal of the error amplifier is used to receive the reference signal Vref. The phase input terminal is used to receive the first feedback signal Vfb1, and the output terminal of the error amplifier is used to output the error amplification signal Vea. The structure and function of the error amplifier are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

In some embodiments, the error amplification circuit 110 generates an error amplification signal Vea based on the difference between the first feedback signal Vfb1 and the reference signal Vref, which is positively related to the output voltage VOUT, to control the power stage circuit 200, and then Feedback adjusts the output voltage VOUT. by this time The feedback control method makes the level of the first feedback signal Vfb1 adjust to the level of the reference signal Vref in the steady state, that is, the output voltage VOUT is adjusted to the preset target level. In some embodiments, the first feedback signal Vfb1 has excellent stability, making it less susceptible to changes in the output signal caused by noise. Under ideal conditions, the level of the first feedback signal Vfb1 is maintained at the level of the reference signal Vref and will not be changed by noise or load.

Please refer to FIG. 4 , which is a schematic circuit diagram of a ramp signal generating circuit 120 in an embodiment of the present invention, where the ramp signal generating circuit 120 is used to generate a ramp signal Vramp. As shown in FIG. 4 , in some embodiments, the ramp signal generation circuit 120 includes a ramp current source ISr, a capacitor Cr and at least one control switch Sr, where the control switch Sr is used to control the ramp current according to a reset signal RST. The current Ir provided by the source ISr is superimposed with the adjustment current Isp and then integrated on the capacitor Cr, thereby generating a ramp signal Vramp. When the reset signal RST is in a low potential state (for example, 0), the control switch Sr is not turned on, so that the current Ir of the ramp current source ISr and the adjustment current Isp are superimposed and integrated on the capacitor Cr, thereby increasing the value of the ramp signal Vramp. Gradually rises to a certain value; when the reset signal RST is in a high potential state (for example, 1), the control switch Sr is turned on so that the ramp current source ISr stops integrating the capacitor Cr and discharges the capacitor Cr, thereby causing the ramp signal Vramp value drops to 0 volts.

Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a pulse width modulation circuit 130 in one embodiment of the present invention. The pulse width modulation circuit 130 is used to amplify the signal Vea, the ramp signal Vramp and a clock signal according to the error. CLK generates a pulse width modulation signal Spwm. The pulse width modulation signal Spwm is used to control the power stage circuit 200 to adjust the output voltage VOUT to a preset target level. As shown in FIG. 5 , in some embodiments, the pulse width modulation circuit 130 includes a comparator 131 and a logic circuit 132 . The comparator 131 is used to compare the error amplification signal Vea and the ramp signal Vramp to generate a relay signal MS. The logic circuit 132 is used to generate a reset according to the relay signal MS and the clock signal CLK. signal RST and pulse width modulation signal Spwm. The structure and function of the comparator 131 are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

Please refer to FIG. 6A. FIG. 6A is a circuit schematic diagram of the fast response control circuit 140 in one embodiment of the present invention. The fast response control circuit 140 is used to perform a fast response control function (hereinafter referred to as Fast response), thereby generating a fast response control signal to accelerate the transient response of the fast response switching power converter 10. As shown in Figure 6A, in some embodiments, the fast response control circuit 140 includes complex comparators 141A, 141B, an adjustment circuit 142 and complex adjustment current source circuits 143A, 143B, wherein the adjustment current source circuit 143A includes a first current The source IS1 and a first switch S1, the adjusted current source circuit 143B includes a second current source IS2 and a second switch S2. The structures and functions of the comparators 141A and 141B, the adjustment circuit 142 and the adjustment current source circuits 143A and 143B will be explained in detail below, as well as how they are arranged.

In some embodiments, the comparators 141A and 141B are used to determine whether the absolute value of the second feedback signal Vfb2 exceeds at least a reference threshold, wherein the comparator 141A is used to determine whether the value of the second feedback signal Vfb2 is greater than a first Referring to the threshold Vthr1, the comparator 141B is used to determine whether the value of the second feedback signal Vfb2 is less than a second reference threshold Vthr2. As shown in FIG. 6A, in this embodiment, the inverting input terminal of the comparator 141A is used to receive the first reference threshold Vthr1, and the non-inverting input terminal of the comparator 141B is used to receive the second reference threshold Vthr2. The comparator 141A The non-inverting input terminal of the comparator 141B and the inverting input terminal of the comparator 141B are used to receive the second feedback signal Vfb2. The output terminal of the comparator 141A is used to output a comparison signal CS1. The output terminal of the comparator 141B is used to output a comparison signal. Signal CS2. In this embodiment, the fast response control signal includes comparison signal CS1 and comparison signal CS2. The structure and function of the comparators 141A and 141B are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

In some embodiments, when the value of the second feedback signal Vfb2 is greater than the first reference threshold Vthr1, the comparator 141A outputs a comparison signal CS1 in a high potential state (for example, 1); when the value of the second feedback signal Vfb2 When it is less than the second reference threshold Vthr2, the comparator 141B outputs a comparison signal CS2 in a high potential state (for example, 1). On the other hand, when the value of the second feedback signal Vfb2 is less than the first reference threshold Vthr1, the comparator 141A outputs the comparison signal CS1 in the low potential state (for example, 0); when the value of the second feedback signal Vfb2 is greater than When the second reference threshold Vthr2 is used, the comparator 141B outputs a comparison signal CS2 in a low potential state (for example, 0).

In some embodiments, the first reference threshold Vthr1 and the second reference threshold Vthr2 are generated according to a preset reference threshold, where the preset reference threshold is, for example, the level of the reference signal Vref, the value of the first reference threshold Vthr1 For example, the value of the second reference threshold Vthr2 is the preset reference threshold plus an offset threshold, and the value of the second reference threshold Vthr2 is, for example, the preset reference threshold minus the offset threshold. In some embodiments, when the preset reference threshold is 0, there is a positive or negative relationship between the first reference threshold Vthr1 and the second reference threshold Vthr2, where the first reference threshold Vthr1 is a positive number and the second reference threshold Vthr2 is a negative number, and the absolute value of the first reference threshold Vthr1 is equal to the absolute value of the second reference threshold Vthr2.

As shown in FIG. 6A, in some embodiments, when the value of the second feedback signal Vfb2 is greater than the first reference threshold Vthr1, the comparator 141A outputs a comparison signal CS1 in a high potential state (for example, 1) as a quick response. Control signal, when the comparison signal CS1 is in the high potential state, the adjustment circuit 142 generates the adjustment signal AS2 in the high potential state, so that the first switch S1 is in the on state, and the current generated by the first current source IS1 is used as the adjustment current. Isp flows into the ramp signal generating circuit 120 in the opposite direction to the adjustment current Isp shown in FIG. 6A (that is, the adjustment current Isp is a negative current at this time). After superimposing with the current Ir, the total current charging the capacitor Cr increases. and make the slope The slope of the signal Vramp increases, thereby accelerating the reduction of the duty cycle of the pulse width modulation signal Spwm, and mitigating the overshoot of the output voltage VOUT.

When the value of the second feedback signal Vfb2 is less than the first reference threshold Vthr1, the comparison signal CS1 is in a low potential state; and when the value of the second feedback signal Vfb2 is also less than the second reference threshold Vthr2, the comparison signal CS2 is in a high potential state. As a quick response control signal, the adjustment circuit 142 generates an adjustment signal AS2 in a low potential state and an adjustment signal AS3 in a high potential state, so that the first switch S1 is in a non-conductive state and the second switch S2 is in a conductive state, and the second switch S2 is in a conductive state. The current generated by the current source IS2 serves as the adjustment current Isp, flows out of the slope signal generating circuit 120 in the same direction as the adjustment current Isp shown in FIG. 6A (that is, the adjustment current Isp is a positive current at this time), and is superimposed with the current Ir. , the total current charging the capacitor Cr decreases, which reduces the slope of the ramp signal Vramp, thereby accelerating the increase in the duty cycle of the pulse width modulation signal Spwm, and easing the undershoot of the output voltage VOUT.

When the value of the second feedback signal Vfb2 is less than the first reference threshold Vthr1, and when the value of the second feedback signal Vfb2 is greater than the second reference threshold Vthr2, both the comparison signal CS1 and the comparison signal CS2 are in a low potential state, and the adjustment circuit 142 The adjustment signals AS2 and AS3 in the low-potential state are generated, causing the first switch S1 and the second switch S2 to be in a non-conducting state, indicating that the output voltage VOUT does not exceed the output threshold, and there is no need to accelerate the adjustment of the output according to the fast response control signal. voltage VOUT.

In other words, in some embodiments, the adjustment signals AS2 and AS3 are used to control the conduction states of the first switch S1 and the second switch S2 respectively. In some embodiments, when the comparison signal CS1 is in the high-potential state and the comparison signal CS2 is in the low-potential state, the comparison signal CS1 is used as a fast response control signal to cause the adjustment circuit 142 to adjust the high-potential state. The signal AS2 and the low-potential state adjustment signal AS3 cause the first switch S1 to be in a conductive state and the second switch to be turned on. Switch S2 is in a non-conducting state; when the comparison signal CS1 is in the low potential state and the comparison signal CS2 is in the high potential state, the comparison signal CS2 is used as a quick response control signal to cause the adjustment circuit 142 to generate a low potential state. The adjustment signal AS2 and the adjustment signal AS3 in the high potential state cause the first switch S1 to be in a non-conductive state and the second switch S2 to be in a conductive state; when the comparison signal CS1 and the comparison signal CS2 are both in the low potential state, the adjustment circuit 142 The adjustment signals AS2 and AS3 in a low potential state are generated, so that both the first switch S1 and the second switch S2 are in a non-conducting state, indicating that the quick response control signal does not adjust the slope of the ramp signal Vramp. In some embodiments, the adjustment circuit 142 can further adjust the signals AS1 and AS4 according to the comparison signal CS1 and the comparison signal CS2 to respectively adjust the current value of the first current source IS1 and the second current source IS2.

In some embodiments, the adjustment current source circuits 143A and 143B are used to generate an adjustment current Isp according to the adjustment signals AS1, AS2, AS3 and AS4, and thereby adjust the slope of the ramp signal Vramp, where the first current source IS1 and the second current source IS2 is used to adjust the value of the current Isp. The first switch S1 and the second switch S2 are used to control the conduction state of the first current source IS1 and the second current source IS2 respectively. When the first switch S1 is in the on state, the first current source IS1 will reduce the value of the adjustment current Isp; when the second switch S2 is in the on state, the second current source IS2 will increase the value of the adjustment current Isp; when the second switch S2 is in the on state, the second current source IS2 will increase the value of the adjustment current Isp. When the first switch S1 and the second switch S2 are both in a non-conducting state, the value of the adjustment current Isp is 0. At this time, the fast response control signal is disabled, so that the fast response control circuit 140 does not adjust the slope of the ramp signal Vramp.

Please refer to FIG. 6B. FIG. 6B is a schematic circuit diagram of the adjustment circuit 142 in one embodiment of the present invention. The adjustment circuit 142 is used to generate complex adjustment signals AS1-AS4 according to the comparison signals CS1 and CS2. As shown in FIG. 6B , the adjustment circuit 142 includes a counting circuit 1421 and a judgment circuit 1422 , where the counting circuit 1421 is used to count the comparison signals CS1 and CS2 switching to the enable level (i.e. high potential) to generate the enabling number CNT. In some embodiments, the judgment circuit 1422 further generates adjustment signals AS1-AS4 according to the enabling number CNT.

It should be noted that the counting circuit 1421 counts the number of times the comparison signals CS1 and CS2 are switched to the enable level, indicating the number of times the second feedback signal Vfb2 gradually increases and exceeds the first reference threshold Vthr1, or the second feedback signal The number of times Vfb2 gradually decreases and exceeds the second reference threshold Vthr2 generates the enabling number CNT. The judgment circuit 1422 may further generate adjustment signals AS1-AS4 according to the enabling number CNT, which will be described in detail later.

In some embodiments, when the fast response control signal is enabled (that is, when the value of the adjustment current Isp is not 0), the fast response control circuit 140 will superpose the adjustment current Isp and the current Ir of the slope current source ISr to obtain The capacitor Cr of the ramp signal generating circuit 120 is integrated to adjust the slope of the ramp signal Vramp to accelerate the increase or decrease of the duty cycle of the pulse width modulation signal Spwm, thereby accelerating the transient response of the fast response switching power converter 10 . Please refer to FIG. 7. FIG. 7 is a voltage waveform diagram of the ramp signal Vramp, the initial pulse width modulation signal Spwm' and the pulse width modulation signal Spwm in one embodiment of the present invention.

As shown in FIG. 7 , in the ramp signal Vramp of this embodiment, the dotted line waveform W1 represents the initial ramp signal Vramp1 before adjustment, and the solid line waveform W2 represents the ramp signal Vramp2 adjusted by the fast response control circuit 140 . As shown in FIG. 7 , for example, when the value of the second feedback signal Vfb2 is less than the second reference threshold Vthr2, the fast response control circuit 140 reduces the slope of the initial ramp signal Vramp1, so that the slope of the ramp signal Vramp is greater than that of the initial ramp signal Vramp1. The slope is even smaller, so that the time point when the level of the adjusted ramp signal Vramp2 reaches the error amplification signal Vea is later than the time point when the level of the initial ramp signal Vramp1 reaches the error amplification signal Vea, making the pulse width modulation signal Spwm The duty cycle duty2 is greater than the duty cycle duty1 of the initial pulse width modulation signal Spwm′, thus accelerating the transient response of the fast response control circuit 140 .

It should be noted that the pulse width modulation signal shown in Figure 7 is generated by switching the pulse width modulation signal from a high level to a low level at the time point when the level of the ramp signal reaches the error amplification signal. Of course, this The invention is also applicable to other pulse width modulation signal generation methods. It only needs to be adjusted correspondingly to the generation methods of other signals in the conversion control circuit. Those with ordinary knowledge in this field can simply infer based on the teachings of this embodiment. I won’t go into details here.

As shown in FIG. 2 , in some embodiments, the power stage circuit 200 includes a driving circuit 210 , a plurality of power switches Q1 and Q2 and an inductor L. The driving circuit 210 is coupled to the control terminals of the power switches Q1 and Q2 . One end of the switch Q1 is coupled to an input power supply, the other end of the power switch Q1 is coupled to one end of the power switch Q2, the other end of the power switch Q2 is grounded, and one end of the inductor L is coupled to the other end of the power switch Q1 and the power switch Q2. Between one end of the inductor L, the other end is coupled to an output capacitor Cout and an external load LD. The driving circuit 210 is used to generate complex control signals G1 and G2 to respectively control the power switches Q1 and Q2. The power switches Q1 and Q2 are used to switch one end of the inductor L and/or switch the other end of the inductor L to convert the input power. An output power supply is then generated. Taking FIG. 2 as an example, in this embodiment, the power switches Q1 and Q2 switch one end of the inductor L between the input voltage VIN and the ground potential.

In some embodiments, the power switch Q1 is a P-type metal oxide semi-transistor (PMOS), and the power switch Q2 is an N-type metal oxide semi-transistor (NMOS), wherein the control end of the power switch Q1 corresponds to the P-type metal oxide semi-transistor. The gate of the semi-transistor, one end of the power switch Q1 corresponds to the source of the P-type metal oxide semi-transistor, and the other end of the power switch Q1 corresponds to the drain of the P-type metal oxide semi-transistor. ; The control end of the power switch Q2 corresponds to the gate stage of the N-type metal oxide semi-transistor, one end of the power switch Q2 corresponds to the drain electrode of the N-type metal oxide semi-transistor, and the other end of the power switch Q2 corresponds to the N-type metal oxide semi-transistor. The source of it.

Please refer to FIGS. 8A and 8B at the same time. FIGS. 8A and 8B are schematic circuit diagrams of feedback circuits 300A and 300B in some embodiments of the present invention. The feedback circuits 300A and 300B correspond to the feedback circuit 300 in FIG. 2 . As shown in Figure 8A, in this embodiment, the feedback circuit 300A includes complex voltage dividing circuits 301 and 302, wherein the voltage dividing circuit 301 includes complex resistors Rfb1 and Rfb2, and the voltage dividing circuit 302 includes a complex resistor Rfb3. , Rfb4. In some embodiments, the first feedback signal Vfb1 and the second feedback signal Vfb2 are related to the output voltage VOUT, where the value of the resistor Rfb1 and the value of the resistor Rfb2 determine the relationship between the first feedback signal Vfb1 and the output voltage VOUT. The proportional relationship between the resistor Rfb3 and the resistor Rfb4 determines the proportional relationship between the second feedback signal Vfb2 and the output voltage VOUT. Taking the voltage dividing circuit 301 as an example, when the value of the resistor Rfb1 is 4 kiloohms (kΩ) and the value of the resistor Rfb2 is 1 kiloohm, the proportional relationship between the output voltage VOUT and the first feedback signal Vfb1 is: 5 to 1, that is to say, the value of the output voltage VOUT is 5 times the value of the first feedback signal Vfb1.

In some embodiments, the first feedback signal Vfb1 is the second feedback signal Vfb2. As shown in FIG. 8B , in this embodiment, the feedback circuit 300B includes complex resistors Rfb5 and Rfb6, where the values of the resistor Rfb5 and the resistor Rfb6 determine the first feedback signal Vfb1 (the second feedback signal The proportional relationship between Vfb2) and the output voltage VOUT. For example, when the value of the resistor Rfb5 is 4 kilo ohms (kΩ) and the value of the resistor Rfb6 is 1 kilo ohm, the voltage between the output voltage VOUT and the first feedback signal Vfb1 (the second feedback signal Vfb2) The proportional relationship is 5 to 1, that is to say, the value of the output voltage VOUT is 5 times the value of the first feedback signal Vfb1 (the second feedback signal Vfb2).

Please refer to FIG. 2 and FIG. 9A at the same time. FIG. 9A is an operation flow chart of the fast response switching power converter 10 in some embodiments of the present invention. As shown in FIG. 9A , when the fast response switching power converter 10 starts to operate, the conversion control circuit 100 of the fast response switching power converter 10 will receive a first feedback circuit Vfb1 and a second feedback signal Vfb2 ( Step S100), and root A pulse width modulation signal Spwm is generated according to the first feedback circuit Vfb1 and the second feedback signal Vfb2 (step S200). Next, the power stage circuit 200 of the fast-response switching power converter 10 controls the power switches Q1 and Q2 of the power stage circuit 200 according to the pulse width modulation signal Spwm to convert an input power supply and thereby generate an output power supply (step S300). Subsequently, the feedback circuit 300 of the fast response switching power converter 10 generates the first feedback circuit Vfb1 and the second feedback signal Vfb2 according to the output voltage VOUT (step S400). Finally, the fast response switching power converter 10 repeats steps S100 to S400 until the fast response switching power converter 10 stops operating.

Please refer to FIG. 2 and FIG. 9B at the same time. FIG. 9B is an operation flow chart of the conversion control circuit 100 in some embodiments of the present invention. As shown in FIG. 9B , when the conversion control circuit 100 generates the pulse width modulation signal Spwm according to the first feedback circuit Vfb1 and the second feedback signal Vfb2 (corresponding to step S200 in FIG. 9A ), the error of the conversion control circuit 100 is amplified The circuit 110 will amplify the difference between the first feedback signal Vfb1 and the reference signal Vref to generate an error amplification signal Vea (step S210); at the same time, the fast response control circuit 140 of the conversion control circuit 100 will generate an error according to the second feedback signal. Vfb2 is used to perform a quick response control function to generate a quick response control signal, thereby generating the adjustment current Isp (step S220). Then, the ramp signal generating circuit 120 of the conversion control circuit 100 generates a ramp signal Vranp according to the adjustment current Isp (step S230). Finally, the pulse width modulation circuit 130 of the conversion control circuit 100 compares the error amplification signal Vea with the ramp signal Vramp to generate the pulse width modulation signal Spwm (step S240).

Please refer to FIG. 6A and FIG. 9C simultaneously. FIG. 9C is an operation flow chart of the fast response control circuit 140 performing the fast response control function in some embodiments of the present invention. As shown in FIG. 9C , when the quick response control circuit 140 starts to execute the quick response control function (corresponding to step S220 in FIG. 9B ), the quick response control circuit 140 will first reset the enable number CNT of the quick response control signal to 0 (step S221). Then, the comparators 141A and 141B of the fast response control circuit 140 will Determine whether the absolute value of the second feedback signal Vfb2 exceeds at least a reference threshold (step S222). When the absolute value of the second feedback signal Vfb2 gradually increases or decreases to exceed (that is, passes) at least one reference threshold, it indicates that the output voltage VOUT gradually increases or decreases to exceed at least one output threshold. At this time, the fast response control circuit 140 The enable number CNT will be increased by 1 (step S223), and the adjustment current source circuits 143A and 143B of the fast response control circuit 140 will adjust the slope of the ramp signal Vramp according to the enable number CNT (step S224). Subsequently, the comparators 141A and 141B will again determine whether the absolute value of the second feedback signal Vfb2 gradually increases or decreases to exceed at least a reference threshold (step S225). If so, the adjustment current source circuits 143A and 143B will continue to be enabled according to The number of times CNT is used to adjust the slope of the ramp signal Vramp; if not, the adjusting current source circuits 143A and 143B will stop adjusting the slope of the ramp signal Vramp according to the number of times CNT is enabled (step S226), and the comparators 141A and 141B will judge the second time again. Whether the absolute value of the feedback signal Vfb2 gradually increases or decreases to exceed at least a reference threshold (step S222).

Continuing with step S222, when the absolute value of the second feedback signal Vfb2 does not gradually increase or decrease to exceed at least one reference threshold, it indicates that the output voltage VOUT does not gradually increase or decrease to exceed at least one output threshold. At this time, the fast response control circuit 140 It will be determined whether the enabling number CNT is greater than 1 (step S227). If not, the fast response control circuit 140 will again determine whether the absolute value of the second feedback signal Vfb2 gradually increases or decreases to exceed at least a reference threshold (step S222); if so, whether the absolute value of the second feedback signal Vfb2 gradually increases Or if it decreases to exceed at least one reference threshold, it will be further determined whether the fast response control signal exceeds a timeout period since the mth enablement (step S228), where m is a positive integer. When the fast response control signal exceeds the timeout period after the m-th enablement, the quick-response control circuit 140 resets the enabled number CNT; when the fast-response control signal does not exceed the timeout period after the mth enablement During the timeout period, the fast response control circuit 140 will again determine whether the absolute value of the second feedback signal Vfb2 gradually increases or decreases to exceed at least a reference threshold (step S222).

Please refer to FIG. 2 and FIG. 10 at the same time. FIG. 10 is a signal waveform diagram of the fast response switching power converter 10 in one embodiment of the present invention. As shown in Figure 10, in this embodiment, since the second feedback signal Vfb2 (corresponding to the output voltage VOUT) gradually decreases below the second reference threshold Vthr2 (corresponding to the second output threshold Vtho2) three times, the fast response control The signal is enabled a total of 3 times. The adjustment current Isp is generated according to the quick response control signal. The first enablement of the fast response control signal occurs at time point t1 (the number of enablements CNT is 1), and the second feedback signal Vfb2 remains lower than the second reference threshold Vthr2 until time point t2; the second enablement of the fast response control signal The first enablement occurs at time point t3 (the number of enablements CNT is 2), and the second feedback signal Vfb2 remains lower than the second reference threshold Vthr2 until time point t4; the third enablement of the fast response control signal occurs at time point t5 (The enabled number CNT is 3), and the second feedback signal Vfb2 remains lower than the second reference threshold Vthr2 until time point t6. In this embodiment, for example, the signals AS1-AS4 are adjusted according to the fast response control signal and the enabling number CNT to generate the adjustment current Isp. In this embodiment, when the number of enable times CNT is 1, the adjustment current Isp is generated according to the quick response control signal and has a relatively high current level, that is, the adjustment amount is relatively large; when the number of enable times CNT For 2 and 3, the adjustment current Isp is generated according to the fast response control signal and has a relatively low current level, that is, the adjustment amount is relatively small. As shown at time t7, when the output voltage VOUT rises, the second feedback signal Vfb2 rises, but because the second feedback signal Vfb2 (corresponding to the output voltage VOUT) is not higher than the first reference threshold Vthr1 (corresponding to the first output Threshold Vtho1), therefore the fast response control signal is not enabled and the fast response control function is not executed. In addition, in this embodiment, when the fast response control signal is enabled for the first time and exceeds the timeout period TOP (corresponding to the timeout point tto), the fast response control circuit 140 will reset the enabling number CNT to 0.

In some embodiments, when the fast response control signal is enabled for the nth time, the fast response control circuit 140 adjusts the slope of the ramp signal Vramp with an nth adjustment amount; when the fast response control signal is enabled for the n+1th time When Absolute value. As shown in Figure 10, in this embodiment, when the enabling number CNT is 1 (that is, when the fast response control signal is enabled for the first time), the absolute value of the first adjustment amount is greater than the second adjustment amount. Absolute value; and when the number of activations CNT is 2 (that is, when the fast response control signal is activated for the second time), the absolute value of the second adjustment amount is equal to the absolute value of the third adjustment amount.

In some embodiments, when the fast response control signal is enabled, the absolute value of the n-th adjustment amount is greater than the absolute value of the n+1-th adjustment amount at least once. Please refer to FIG. 11A. FIG. 11A is a current waveform diagram (1) of the adjustment current Isp generated according to the fast response control signal in some embodiments of the present invention. As shown in Figure 11A, in this embodiment, the fast response control signal is enabled three times in total, and the absolute value of the second adjustment amount is greater than the absolute value of the third adjustment amount. Therefore, the adjustment current Isp is enabled when The levels when the number of times CNT are 1 and 2 are higher than the level when the number of times CNT is enabled is 3.

In some embodiments, when the fast response control signal is enabled, the absolute value of the n-th adjustment amount will be greater than the absolute value of the n+1-th adjustment amount. Please refer to FIG. 11B. FIG. 11B is a current waveform diagram (2) of the adjustment current Isp generated according to the fast response control signal in some embodiments of the present invention. As shown in Figure 11B, in this embodiment, the fast response control signal is enabled three times in total, in which the absolute value of the first adjustment amount is greater than the absolute value of the second adjustment amount, and the absolute value of the second adjustment amount is The value is greater than the absolute value of the third adjustment amount, so the level of the adjustment current Isp when the number of enablements CNT is 1 is higher than the level when the number of enablements CNT is 2, and the adjustment current Isp is higher than the level when the number of enablements CNT is 2. The level when CNT is 2 is higher than the level when CNT is 3.

In some embodiments, when the fast response control signal is enabled, the absolute value of the n-th adjustment is twice the absolute value of the n+1-th adjustment. Please refer to FIG. 11C. FIG. 11C is a current waveform diagram (3) of the adjustment current Isp generated according to the fast response control signal in some embodiments of the present invention. As shown in Figure 11C, in this embodiment, the fast response control signal is enabled three times in total, in which the absolute value of the first adjustment is twice the absolute value of the second adjustment, and the second adjustment The absolute value of the quantity is twice the absolute value of the third adjustment quantity. Therefore, the level of the adjustment current Isp when the enabling number CNT is 1 is twice the level when the enabling number CNT is 2, and The level of the adjustment current Isp when the enabling number CNT is 2 is twice the level when the enabling number CNT is 3.

Please refer to Figure 12. Figure 12 is a schematic circuit diagram of a ramp signal generating circuit 120' in another embodiment of the present invention. The ramp signal generating circuit 120' corresponds to the ramp signal generating circuit 120 in Figure 2. As shown in FIG. 12 , in some embodiments, compared to the slope signal generation circuit 120 , the slope signal generation circuit 120 ′ further includes an adder (adder), wherein the adder is used to add the current IL of the inductor L and The product of the multiple factor k is added to the ramp signal Vramp, thereby adjusting the slope of the ramp signal Vramp again. The structure and function of the adder are well known to those with ordinary knowledge in the technical field to which the present invention belongs, and therefore will not be described in detail.

Please further refer to FIG. 13. FIG. 13 is a voltage waveform diagram of the ramp signal Vramp, the initial pulse width modulation signal Spwm', the pulse width modulation signal SpwmL and the pulse width modulation signal Spwm in another embodiment of the present invention. As shown in Figure 13, in this embodiment, the dotted line waveform W3 is the initial ramp signal Vramp1 before adjustment, the dotted line waveform W4 is the ramp signal Vramp2 adjusted by the current IL of the inductor L, and the solid line waveform W5 is the adjusted The subsequent ramp signal Vramp3. Due to the fast response of the fast response control circuit 140 and the adjustment of the current IL of the inductor L, the slope of the ramp signal Vramp3 is smaller than the slope of the initial ramp signal Vramp1, so that the pulse width modulation signal Spwm accounts for The duty cycle is greater than the duty cycle of the initial pulse width modulation signal Spwm' and the duty cycle of the pulse width modulation signal SpwmL, thereby accelerating the transient response of the fast response control circuit 140.

Please refer to FIG. 2 and FIG. 14A at the same time. FIG. 14A is a signal waveform diagram of the fast response control circuit 140 in one embodiment of the present invention. As shown in Figure 14A, in some embodiments, when the value of the second feedback signal Vfb2 exceeds a third reference threshold Vthr3 (as shown in the dotted box Sq3 and the dotted waveform W6), the fast response control circuit 140 will stop The power stage circuit 200 is controlled so that the power switches Q1 and Q2 are not conductive, thereby restoring the second feedback signal Vfb2 to stability in advance to accelerate the transient response of the fast response control circuit 140 (as shown by the solid line waveform W7).

Please refer to FIG. 14B , which is a signal waveform diagram of the fast response control circuit 140 in another embodiment of the present invention. As shown in FIG. 14B , in some embodiments, the fast response control circuit 140 clamps the error amplification signal Vea so that it does not exceed a preset clamping value Vclamp (shown as the dotted box Sq4), thereby causing the output voltage VOUT to Return to stability early to accelerate the transient response of the fast response control circuit 140 (as shown at time t8 in the dotted box Sq5). In some embodiments, the dotted line waveforms of the output voltage VOUT and the error amplification signal Vea indicate that the error amplification signal Vea is not clamped, and the amplification signal Vea continues to decrease below the preset clamping value Vclamp, so that the output voltage VOUT reaches time point t9 before adjusting to the preset target level. In contrast, the solid line waveforms of the output voltage VOUT and the error amplification signal Vea indicate that the error amplification signal Vea is clamped. The amplification signal Vea is clamped when it drops to the preset clamping value Vclamp and remains at the preset clamping value Vclamp, so that The output voltage VOUT reaches the time point t8 in advance and is adjusted to the preset target level.

Please refer to FIG. 15 , which is a schematic circuit diagram of the clock signal adjustment circuit 400 in one embodiment of the present invention. As shown in Figure 15, in some embodiments, the clock signal adjustment circuit 400 generates the clock signal CLK based on the second feedback signal Vfb2 and a fourth reference threshold Vthr4, wherein when the value of the second feedback signal Vfb2 When the fourth reference threshold Vthr4 is exceeded, the clock signal adjustment circuit 400 adjusts the frequency of the clock signal CLK to change the frequency of the ramp signal Vramp, thereby adjusting the duty cycle of the pulse width modulation signal Spwm.

Please refer to FIG. 16. FIG. 16A to FIG. 16J are circuit schematic diagrams of the power stage circuit 200 in some embodiments of the present invention. As shown in FIGS. 16A to 16J , the fast response switching power converter 10 of the present invention can be applied to power stage circuits in various types of switching power converters, such as but not limited to boost power stage circuits. , buck power stage circuit, buck-boost power stage circuit, switched-capacitor power converter (switched-capacitor power converter), switched resonant tank power converter (STC, switched tank power converter).

Please refer to FIG. 17 , which is a signal simulation waveform diagram of the fast response switching power converter 10 in one embodiment of the present invention. As shown in the dotted box Sq6 of FIG. 17 , when the value of the output voltage VOUT undershoots, the fast response control circuit 140 adjusts the slope of the ramp signal Vramp according to the enable number CNT of the fast response control signal, and then adjusts the slope of the ramp signal Vramp. Accelerately increase the duty cycle of the pulse width modulation signal Spwm to accelerate the transient response of the fast response switching power converter 10; and as shown in the dotted box Sq7 in Figure 17, when the value of the output signal VOUT overshoots (overshoot ), the fast response control circuit 140 will adjust the slope of the ramp signal Vramp according to the number of enable times CNT of the fast response control signal, thereby accelerating the reduction of the duty cycle of the pulse width modulation signal Spwm to accelerate the fast response switching power conversion. Transient response of device 10.

In summary, the fast response switching power converter 10 and its conversion control circuit 100 in some embodiments of the present invention adjust the slope of the ramp signal Vramp by executing a fast response control function to accelerate the increase or decrease of the pulse width. The duty cycle of the signal Spwm is modulated, thereby accelerating the transient response of the fast-response switching power converter 10 . In this way, the negative impact caused by the load transient response can be effectively mitigated, thereby improving the stability of the output power supply.

The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those familiar with the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace those in another embodiment. Corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or computing according to a certain signal or generating a certain output result", which is not limited to Depending on the signal itself, it also includes performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or calculating the converted signal to produce an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. There are many combinations, and they are not listed here. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes.

10: Fast response switching power converter

100:Conversion control circuit

110: Error amplifier circuit

120:Ramp signal

130: Pulse width modulation circuit

140: Fast response control circuit

200:Power stage circuit

210:Drive circuit

300:Feedback circuit

Cout: output capacitor

CLK: clock signal

G1-G2: control signal

Isp: adjust current

IL: inductor current

ILoad: load current

L:Inductor

LD: external load

Q1-Q2: Power switch

Spwm: pulse width modulation signal

Vea: error amplification signal

Vfb1: first feedback signal

Vfb2: second feedback signal

Vramp: ramp signal

Vref: reference signal

VIN: input power

VOUT: output power

Claims (11)

A conversion control circuit, suitable for a fast response switching power converter, used to control a power stage circuit based on a first feedback signal and a second feedback signal, the conversion control circuit includes: an error amplification circuit, used to amplify the difference between the first feedback signal and a reference signal to generate an error amplification signal; a slope signal generating circuit used to generate a slope signal; a pulse width modulation circuit used to compare the The error amplification signal and the ramp signal generate a pulse width modulation signal, wherein the pulse width modulation signal is used to control the power stage circuit to adjust an output voltage to a preset target level; and a fast response control circuit , used to perform a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least a reference threshold to generate a quick response control signal; and when the second feedback signal exceeds the reference threshold When , adjust the slope of the ramp signal to accelerate the increase or decrease of the duty cycle of the pulse width modulation signal, thereby accelerating the transient response of the fast response switching power converter; wherein, the first feedback signal and The second feedback signal is positively related to the output voltage; when the second feedback signal exceeds the reference threshold, it indicates that the output voltage exceeds an output threshold. The conversion control circuit as described in claim 1, wherein the fast response control function further includes: When the second feedback signal exceeds the reference threshold, the slope of the ramp signal is adjusted according to the number of times the fast response control signal is enabled to adaptively accelerate the increase or decrease of the duty cycle of the pulse width modulation signal. Thus, the transient response of the fast response switching power converter is accelerated. The conversion control circuit of claim 1, wherein the slope signal generating circuit includes a slope current source, a capacitor and at least one control switch, and the at least one control switch is used to control the slope current source according to a reset signal. The capacitor integrates to generate the slope signal; the fast response control circuit includes at least one adjustment current source circuit, wherein the adjustment current source circuit is used to generate an adjustment current, and the fast response control circuit is used to cause the fast response control signal to When possible, the adjustment current and the current of the ramp current source are superimposed to integrate the capacitor, thereby adjusting the slope of the ramp signal to accelerate the increase or decrease of the duty cycle of the pulse width modulation signal, thereby accelerating the rapid Response to the transient response of a switching power converter. The conversion control circuit of claim 3, wherein the at least one reference threshold includes a first reference threshold and/or a second reference threshold, and the output threshold includes a first output threshold and/or a second output threshold; Wherein, when the second feedback signal is higher than the first reference threshold, the fast response control circuit controls the adjustment current to increase the absolute value of the slope of the ramp signal, thereby accelerating the reduction of the duty cycle of the pulse width modulation signal. Ratio, wherein the second feedback signal is higher than the first reference threshold, indicating that the output voltage is higher than the first output threshold, wherein the first output threshold is higher than the preset target level; when the second feedback signal When it is lower than the second reference threshold, the fast response control circuit controls the adjustment current to reduce the absolute value of the slope of the ramp signal, thereby accelerating the increase in the duty cycle of the pulse width modulation signal, wherein the second feedback signal Being lower than the second reference threshold indicates that the output voltage is lower than the second output threshold, wherein the second output threshold is lower than the preset target level. The conversion control circuit as described in claim 2, wherein the fast response control function further includes: adjusting the slope of the slope signal with an nth adjustment amount when the fast response control signal is enabled for the nth time; and when the fast response control signal is enabled for the nth time; When the fast response control signal is enabled for the n+1th time, the slope of the slope signal is adjusted with an n+1th adjustment amount; where n is a positive integer, and the absolute value of the nth adjustment amount is greater than or equal to the The absolute value of the n+1th adjustment amount. The conversion control circuit as described in claim 5, wherein the quick response control function further includes: resetting the enablement of the quick response control signal during a timeout period after the mth time the quick response control signal is enabled. degree, where m is a positive integer. The conversion control circuit as described in claim 5, wherein the fast response control function further includes: executing at least once the absolute value of the n-th adjustment amount to be greater than the absolute value of the n+1-th adjustment amount. The conversion control circuit as claimed in claim 1, wherein the first feedback signal and the second feedback signal have the same signal size. The conversion control circuit of claim 1, wherein the ramp signal further includes an inductor current-related signal, the inductor current-related signal is related to a current of an inductor, a conduction current of at least one power switch, or an output current of an output power supply. . The conversion control circuit as claimed in claim 1, wherein the quick response control function further includes at least one of the following: When the second feedback signal exceeds a third reference threshold, stop controlling the power stage circuit; clamp the error amplification signal so that it does not exceed a preset clamping value; and/or when the second feedback signal exceeds When a fourth reference threshold is used, the frequency of a clock signal is adjusted. A fast response switching power converter includes: a power stage circuit including at least one power switch, the at least one power switch is used to switch one end of an inductor and/or the other end of the inductor to convert an input power supply, An output power supply is then generated; a conversion control circuit as described in any one of claims 1 to 10 is used to generate a signal based on the first feedback signal and the second feedback signal related to the output voltage of the output power supply. Control the at least one power switch; and a feedback circuit for generating the first feedback signal and the second feedback signal according to the output voltage.