TWI834311B - Wafer probing path generation system and method thereof - Google Patents

Abstract

The invention relates to a wafer probe path generation system and method. The main structure includes a wafer map reading module, a coordinate definition unit, a station map reading module, a path direction setting unit, and a contact A conditional loading unit, a conditional identification module, and a file creation module. In this way, all testable points on the wafer and their die characteristics are read, and a coordinate position is assigned to the testable point. The coordinate position is then marked in an array to calculate the relative position relationship between the testable points, and then the coordinate position is set. Prioritize the movement direction among the test points and load at least one contact condition for the testable points, then you can compare the die characteristics and contact conditions for each testable point one by one, and finally write the qualified ones into the blank probe path file. , to accurately and quickly generate needle measurement paths.

Description

Wafer probing path generation system and method thereof

The present invention provides a wafer probe tester that can perform integrated planning and analysis based on wafer diagrams and probe card test station diagrams, and cooperate with various contact conditions to accurately and quickly generate customized or optimized probe test paths. Path generation system and method thereof.

According to reports, semiconductor packaging testing can be divided into two parts, namely wafer testing after wafer processing is completed, and finished product testing after packaging is completed. Wafer testing is to use the probes of the wafer testing device on the wafer testing machine to connect to the pads of each die on the wafer to be tested, and then send the measured data to the testing machine for analysis and judgment, and sort out Based on the repairable data of each die, testers can use the laser repair machine to replace the defective components. After passing the test, it is completed.

There are usually tens of thousands of die on each wafer to be tested. The size, location, function, quality, and items to be tested of each die are different. Therefore, during the testing process, in fact, there will be problems that do not require testing. , cannot be tested, or have to be tested more than twice. However, as far as the pin test path is concerned, although there are currently wafer path generators provided by pin test machine manufacturers, the paths provided are only standardized paths that go through each step in sequence. For each die, the general path planning method is only the shortest path to ensure that each die can travel once. In other words, this path will also pass through die locations that do not need to be tested and cannot be tested, and die locations that need to be tested more than twice. If the grain position is determined, it will wait until all the grains have been measured once before looking back to find the grain position that needs to be tested a second time. Therefore, the generated path will not be optimized with the pin test card test station map, or the path cannot be planned based on the marking points or avoidance points on the wafer, making it not truly accurate in terms of test time or movement path. shortest path.

Therefore, how to solve the above conventional problems and deficiencies is the direction that the inventor of the present invention and related manufacturers engaged in this industry are eager to research and improve.

Therefore, in view of the above shortcomings, the inventor of the present invention collected relevant information, evaluated and considered many aspects, and used his many years of experience in this industry to design such a device that can be based on wafer diagrams through continuous trials and modifications. The inventor and patentee of the wafer probing path generation system and its method, including probing card test station diagrams, and comprehensive planning and analysis based on various contact conditions, to accurately and quickly generate customized or optimized probing paths. .

The main purpose of the present invention is to conduct integrated planning and analysis based on wafer diagrams and pin test card test station diagrams, as well as various contact conditions, to accurately and quickly generate customized or optimized pin test paths.

In order to achieve the above object, the main structure of the present invention includes: a wafer map reading module for reading all testable points on the wafer and its die characteristics. The wafer map reading module is an information link The coordinate definition unit is used to set the testable points on the same coordinate system and assign a coordinate position. The coordinate definition unit is information-linked to a station map reading module to mark the coordinate positions in an array, and Calculate the relative positional relationship between the testable points, and have a path direction setting unit for setting the priority of the movement direction between the coordinate positions, and a contact condition that loads at least one contact condition for the testable points. A loading unit, a condition identification module for comparing the characteristics of the die and the contact condition according to the priority order of the movement direction to the testable points at each coordinate position, and a blank probe path file for generating The file creation module is used to write the coordinate position and die characteristics that the comparison result matches into the blank probe path file.

When the user uses the present invention to plan the wafer probing path, the wafer to be tested and the probing card test station map are loaded to mark the positions of all testable points in an array, and according to the characteristics of the die , and the priority order of movement direction, compare the bare chip characteristics and contact conditions of each testable point one by one, and then write the coordinate positions and bare chip characteristics consistent with the comparison results into the blank probe path file in sequence, and If the comparison result is not consistent, it will be ignored and not processed, and the testable point at the next coordinate position will be searched until the testable points at all coordinate positions are searched. Then during the actual test, the sequence can be arranged according to the coordinate position in the blank probe path file. as a needle measurement path. In this way, not only can path arrangement be completed in a short time, but the actual test path can also be optimized or customized, thereby greatly improving test efficiency.

Through the above technology, the path generated by the conventional wafer path generator is only the standardized shortest path, which is not optimized with the pin test card test station diagram, or cannot be based on the markings on the wafer. Path planning is performed at certain points or avoidance points, resulting in longer path planning time and lower testing efficiency. The problem points must be broken through to achieve the practical and progressive nature of the above advantages.

1: Wafer map reading module

11: Coordinate definition unit

2: Station map reading module

3: Path direction setting unit

31: Path starting point setting unit

4: Contact condition loading unit

5: Condition identification module

6: File creation module

7: Statistical unit

8: Analysis unit

The first figure is a structural block diagram of a preferred embodiment of the present invention.

The second figure is a usage state diagram of the preferred embodiment of the present invention.

The third figure is a schematic diagram of the settings of the preferred embodiment of the present invention.

The fourth figure is a step block flow chart of the preferred embodiment of the present invention.

The fifth figure is a schematic diagram of path planning according to the preferred embodiment of the present invention.

Figure 6 is a schematic diagram of yet another preferred embodiment of the present invention.

In order to achieve the above-mentioned objects and effects, the technical means and structures adopted by the present invention are described in detail below with respect to the preferred embodiments of the present invention, so as to facilitate a complete understanding.

Please refer to Figures 1 to 5, which are structural block diagrams and path planning schematic diagrams of preferred embodiments of the present invention. It can be clearly seen from the figures that the present invention includes:

A wafer map reading module 1 is used to read all testable points on the wafer and its die characteristics, wherein the die characteristics are normal die, test-free die, need to avoid die, or One of the bare dies cannot be tested;

A coordinate definition unit 11 is information-linked to the wafer map reading module 1 to set the testable points on the same coordinate system and assign a coordinate position;

A station map reading module 2 is information-linked to the coordinate definition unit 11 to mark the coordinate positions in an array and calculate the relative positional relationship between the testable points;

A path direction setting unit 3 is used to set the priority order of movement directions between the coordinate positions;

A contact condition loading unit 4 loads at least one contact condition for the testable points, where the contact condition is allowed to contact the test-free die, allowed to contact the bare die that needs to be avoided, allowed to contact or exceed the wafer boundary, Either allow site-wide testing or limit the maximum number of bare die contacts;

A condition identification module 5 compares the characteristics of the die with the contact conditions at each testable point at the coordinate position one by one according to the priority order of the movement direction; and

A file creation module 6 is used to generate a blank probe path file and is information-linked to the condition identification module 5 to write the coordinate position and the die characteristics that the comparison result matches into the blank probe path file. middle.

The wafer probing path generation method of the present invention mainly includes:

(a) Reading the wafer: using a wafer map reading module to read all testable points on the wafer and its die characteristics;

(b) Coordinate definition: Use an information link to the coordinate definition unit of the wafer map reading module to set the testable points on the same coordinate system and assign a coordinate position;

(c) Read the station map: use an information link to the station map reading module of the coordinate definition unit, mark the coordinate positions in an array, and calculate the relative position relationship between the testable points;

(d) Set the path direction: use a path direction setting unit to set the priority of the movement direction between each coordinate position;

(e) Loading contact conditions: Use a contact condition loading unit to load at least one contact condition for the testable points;

(f) Contact condition comparison: Use a condition identification module to compare the characteristics of the die with the contact conditions at each testable point at the coordinate position one by one according to the priority order of the movement direction;

(g) Whether the comparison results are consistent: If the comparison results are not consistent, go back to step (f) to search for the testable point at the next coordinate position. If the comparison results are consistent, go to step (h);

(h) Write a blank probing path file: Use a file to create a module to generate a blank probing path file, and write the coordinate position and die characteristics that match the comparison result into the blank probing path file in; and

(i) Search for the next testable point: Return to step (f) to search for the testable point at the next coordinate position until all testable points at the coordinate position are searched.

Through the above description, we can understand the structure of this technology, and based on the corresponding coordination of this structure, we can also conduct integrated planning and analysis based on the wafer diagram and the pin test card test station diagram, as well as various contact conditions, to achieve The purpose of accurately and quickly generating customized or optimized needle measurement paths, and it can be clearly seen from the figure that the path generation system of the present invention is software designed by a software development program (such as NI LabVIEW). When the user loads the wafer map, the circle map reading module 1 interprets the testable points and die characteristics in the map, and sets the entire wafer map on the same coordinate system through the coordinate definition unit 11 , and assign a coordinate position to each testable point. As for the die characteristics, they include normal die, test-free die, avoidance die, and untestable die. Among them, test-free die, or wafer Marking point (Marking die on wafer) is a position where the probe can pass through normally but does not need to be probed (such as a general circuit). As shown in Figure 5, it is marked (M) in this embodiment and needs to be avoided. The die, or Skip die on wafer, is a die that needs to be ignored or skipped during testing, otherwise it will cause damage to some probes. In this embodiment, it is marked (S) and cannot be The test die, or Not test die on wafer, is a die that the probe can pass through normally, but may not be probed due to damage or dirt. In this embodiment, it is marked ( N), as for normal wafers, in this embodiment, they are marked as continuous natural numbers in order according to the adjacent position relationship.

In addition, the test station map reading module 2 allows users to load the probe card test station map to mark the array (Dut Array) according to the coordinate position of each testable point. For example, the coordinate position of die 1 is (215,200), the coordinate position of die 2 is (215,180), the coordinate position of die 3 is (190,180), and the coordinate position of die 4 is (190,215), then each grid in the array is spaced in units of 5 Arrangement, in this way, assuming that the coordinate position of die 1 is used as the starting point, the position of die 1 in the array is marked as 1, and die 2 is located at a distance of 20 below die 1, so die 2 is located at the The fourth grid below die 1 (20/5=4), and the position of bare die 2 is marked as 2. The three grids between die 1 and die 2 without bare die are marked as 0. In the same way, the position of the other bare die is marked as 0. After the chip position is arrayed, it is marked as Dut Array in the third picture. Based on this array mark, the relative position relationship between each testable point is calculated, as shown in the Dut Index Relation in the third picture. Die 1 is the starting point, so the relative position The relationship is (0,0), the positional relationship of bare die 2 relative to the starting point is (0,-4), the positional relationship of bare die 3 relative to the starting point is (5,-4), the positional relationship of bare die 4 relative to the starting point is ( 5,0), and use the positional relationship in the Dut Index Relation table to process it in order from top to bottom as the moving path of the needle testing machine.

Furthermore, the path direction setting unit 3 is used to set the priority of the movement direction between each coordinate position. As shown in the Direction in the second figure, it has top to down and left to right (Top to Down+Left to Right), Top to Down+Right to Left, Down to Top+Left to Right, Down to Top+Right to Left), right to left and top to down (Right to Left+Top to Down), right to left and bottom to top (Right to Left+Down to Top), left to right and Setting options include Left to Right+Top to Down, Left to Right and Bottom to Top, and the above-mentioned die 1 to die 4 are from top to bottom. It is arranged in the priority order of moving directions from down to left and from left to right.

Finally, the contact condition loading unit 4 loads at least one contact condition for the testable point, such as: allowing contact with the wafer avoidance point (Enable Contact Skip Die), allowing contact with the wafer marking point (Enable Contact Mark Die), allow contact with or exceed the wafer boundary (Enable Contact Wafer Edge), only allow full site testing (Full Site Contact Only), and the maximum number of contacts of the die (Max.Contact Count). Most of the conventional path generators only allow full-site testing as a contact condition, and must go through all testable points. However, if there is a bare die in the testable point, it needs to be avoided, and the probe tester is not allowed to touch the wafer. For models with wafer points, testing under this condition is likely to cause damage to the bare chip or the probe tester due to collision. However, the contact conditions provided by the present invention that allow contact with the wafer avoidance point are used for the probe tester to allow When contacting the model with wafer avoidance points, the contact conditions provided by the present invention that only allow full-station testing are used for those that do not have bare wafers that need to be avoided among the testable points. As for the setting conditions such as the allowed contact with wafer marking points, the allowed contact with or beyond the wafer boundary, and the maximum number of bare chip contacts, they are selectively set based on the distribution position of testable points or the items to be inspected to shorten the time required for path planning. time.

After all parameter conditions are set, as shown in step (f), the contact condition comparison process is entered, and the condition identification module 5 is used to determine the testable points at each coordinate position one by one according to the priority of the movement direction, and conduct the bare chip characteristics and contact Comparison of conditions, if the comparison result does not match, search for the testable point at the next coordinate position, if the comparison result matches, use the file creation module 6 to generate a blank needle test path file, and match the comparison result The coordinate position and the characteristics of the die are written into the blank probe path file, and then the testable point at the next coordinate position is searched and the comparison operation is repeated until the testable points at all coordinate positions are searched. In this way, the final needle measurement path is based on the order of coordinate positions in the blank needle measurement path file. Since those who do not meet the comparison results will not be in the blank needle measurement path file, there will be no redundant ones. The moving stroke, or meaningless contact probing action, generates the optimal path that is most suitable for the wafer, or the customized path that best meets the customer's needs, becoming the most efficient probing path.

For example, as shown in the fifth figure, the coordinate positions defined by the wafer map reading module 1 are continued for die 1 to 4 mentioned above, and die 1 to 9 and two wafer marking points are marked in the figure ( M), a wafer avoidance point (S), and a wafer failure point (N). The wafer marking point (M) and the wafer failure point (N) are for the purpose of path optimization and will still be It is planned in the moving path, but does not stop or conduct needle testing. The wafer avoidance point (S) avoids the path for the safety of the bare chip and equipment. In addition, since all testable points that match the coordinate positions of the comparison results are written into the same blank needle measurement path file, it can shorten the time for the processor to search for data in different files during operation, and also shorten the time spent in the path arrangement process. The time required, since the related information including the items to be tested are also written in the same blank test path file, so even if a certain die has multiple items to be tested, it can be completed at one time by passing the die only once. all Items to be inspected, greatly saving time.

Please also refer to the sixth figure, which is a schematic diagram of another preferred embodiment of the present invention. It can be clearly seen from the figure that this embodiment is similar to the above-mentioned embodiment, except that the path direction setting unit 3 is an information link to a path starting point setting unit 31, and the path generation system has an information link to the statistics unit 7 of the wafer map reading module 1, and an information link to the condition identification module 5 and the file creation module Analysis unit 8 of 6. If the needle test is performed on a single wafer, the starting point of the path can be selected arbitrarily. However, if the needle test is performed on multiple wafers, the starting point of the needle test path can be determined according to the position of the measuring station, so as to achieve a smoother process. Connecting to the next probe point, a more efficient path can be obtained. Therefore, the user can use the path starting point setting unit 31 to set the starting point of the probe path for each wafer to be tested, so as to use the coordinates of the wafer to be tested. Select one of the positions as the starting point of the path for the wafer to be tested. In addition, since the difference in setting of contact conditions will lead to completely different path results, the statistical unit 7 can be used to calculate the statistical data related to the number of die for each path and make a statistical list, such as the path direction (Direction) shown in the Summary Table in the figure. , Start Coordinate (X, Y), Test Die Count, Touch Down Count, Actual Test Die Count, and Untested Die Count (Loss Die Count) and untested rate (Loss Rate (%)) for users to view and compare, and then select the most suitable path from each test path, and the analysis unit 8 will arrange the The time is marked on one side for user reference.

However, the above descriptions are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Therefore, any simple modifications and equivalent structural changes made by using the description and drawings of the present invention should be treated in the same way. It is included in the patent scope of the present invention and is hereby stated.

In summary, the wafer probe path generation system and method of the present invention can indeed achieve its effects and purposes when used. Therefore, the present invention is an invention with excellent practicality and meets the application requirements for an invention patent. , I have filed an application in accordance with the law, and hope that the review committee will approve the invention as soon as possible to protect the inventor's hard work. If the review committee of the Jun Bureau has any doubts, please feel free to write a letter for instructions. The inventor will try his best to cooperate, and it will be greatly appreciated.

1: Wafer map reading module

11: Coordinate definition unit

2: Station map reading module

3: Path direction setting unit

4: Contact condition loading unit

5: Condition identification module

6: File creation module

Claims (8)

A wafer probe path generation system. The path generation system mainly includes: a wafer map reading module for reading all testable points on the wafer and its die characteristics; a coordinate definition unit for information Connect the wafer map reading module to set the testable points on the same coordinate system and assign a coordinate position; a station map reading module is information-connected to the coordinate definition unit to set the test points The coordinate positions are arrayed and marked, and the relative position relationship between the testable points is calculated; a path direction setting unit is used to set the priority order of the movement direction between the coordinate positions; a contact condition loading unit is used for the Some testable points are loaded with at least one contact condition; a condition identification module compares the characteristics of the die with the contact condition for each testable point at the coordinate position according to the priority order of the movement direction; a file Establish a module to generate a blank probing path file, and connect the information to the condition identification module to write the coordinate position and the die characteristics that the comparison result matches into the blank probing path file; and a The analysis unit is an information link between the condition identification module and the file creation module. For example, in the wafer probing path generation system described in item 1 of the patent application, the path direction setting unit is information-linked to a path starting point setting unit. The wafer probing path generation system described in item 1 of the patent application, wherein the path generation system has a statistical unit that is information-linked to the wafer map reading module. For example, the wafer probing path generation system described in item 1 of the patent application scope, wherein the characteristics of the die are one of normal die, test-free die, need-to-avoid die, or untestable die, and The contact conditions are one of allowing contact with the test-free die, allowing contact with the bare die that needs to be avoided, allowing contact with or beyond the wafer boundary, allowing full site testing, or limiting the maximum number of contacts with the die. A method for generating a wafer probe path, which mainly includes: (a) using a wafer map reading module to read all testable points on the wafer and its die characteristics; (b) using an information link The coordinate definition unit of the wafer map reading module sets the testable points on the same coordinate system and assigns them a coordinate position; (c) uses an information link to the station map reading module of the coordinate definition unit , mark the coordinate positions in an array, and calculate the relative position relationship between the testable points; (d) use a path direction setting unit to set the priority of the movement direction between the coordinate positions; (e) Use a contact condition loading unit to load at least one contact condition for the testable points; (f) Use a condition identification module to load the testable points of each coordinate position one by one according to the priority order of the movement direction , compare the characteristics of the die and the contact conditions; (g) If the comparison results are not consistent, return to step (f) to search for the testable point at the next coordinate position. If the comparison results are consistent, proceed to step (h); (h) Use a file to create a module to generate a blank probe path file, and write the coordinate position and die characteristics that the comparison result matches into the blank probe path file; (i ) Return to step (f) to search for the testable point at the next coordinate position until all testable points at the coordinate position are searched; and (j) use information to link the analysis unit of the condition identification module and the file creation module, Analyze the time required to generate the route. For example, in the wafer probing path generation method described in item 5 of the patent application, after executing step (d), step (d1) is entered, and a path starting point setting unit is used to select one of the coordinate positions as the The starting point of the path. For example, in the wafer probing path generation method described in Item 5 of the patent application, when performing step (j), an information is used to connect the statistical unit of the wafer map reading module to calculate the correlation with the number of die statistics. For example, in the wafer probing path generation method described in item 5 of the patent application, the characteristics of the die are one of a normal die, a test-free die, a need-to-avoid die, or an untestable die, and The contact conditions are one of allowing contact with the test-free die, allowing contact with the bare die that needs to be avoided, allowing contact with or beyond the wafer boundary, allowing full site testing, or limiting the maximum number of contacts with the die.

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