TWI833263B - Semiconductor device with contact structure - Google Patents

Abstract

The present application discloses a semiconductor device. The semiconductor device includes a bottom dielectric layer positioned on a substrate; a bottom conductive layer positioned in the bottom dielectric layer; an etch stop layer positioned on the bottom conductive layer; a first inter-dielectric layer positioned on the etch stop layer; and a contact structure including a body portion positioned along the first inter-dielectric layer and extending to the etch stop layer, and a contact portion positioned in the etch stop layer and contacting the body portion and the bottom conductive layer. A width of the body portion is greater than a width of the contact portion.

Description

Semiconductor component with plug structure

This application claims priority to U.S. Patent Application Nos. 17/824,012 and 17/824,481 (that is, the priority date is "May 25, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and more specifically, the present disclosure relates to a semiconductor device having a plug structure.

Semiconductor components are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor components continue to shrink in size to meet growing demands for computing power. However, shrinking the size has led to various problems in the manufacturing process, and these problems have continuously led to different situations. Therefore, challenges remain in improving quality, yield, performance and reliability, and reducing complexity.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device, including a bottom dielectric layer disposed on a substrate; a bottom conductive layer disposed in the bottom dielectric layer; and an etch stop layer disposed on the bottom conductive layer layer; a first inner dielectric layer disposed on the etch stop layer; and a plug structure including: a body portion disposed along the first inner dielectric layer and extending to the etch stop layer; and a plug portion disposed in the etch stop layer and in contact with the body portion and the bottom conductive layer. The width of the body portion is greater than the width of the plug portion.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a photomask, which includes an opaque layer on a mask substrate and surrounding a semi-transmissive layer on the mask substrate, wherein the The semi-transparent layer includes a plug portion of the mask opening, which exposes a portion of the mask substrate; a stacked structure is provided, which includes an etch stop layer on a bottom conductive layer and a first intermediary an electrical layer on the etch stop layer; and forming a pre-process mask layer on the stacked structure; patterning the pre-process mask layer using the photomask to form an imaged mask layer, which includes a The mask area corresponds to the opaque layer, a main body portion area corresponds to the semi-transparent layer, and a hole corresponds to the mask opening of the plug portion, wherein the thickness of the main body portion area is smaller than the thickness of the mask area ; Performing an opening etching process to form an opening of the body portion and an opening of the plug portion in the stacked structure, and exposing a portion of the bottom conductive layer; and forming a plug structure in the opening of the body portion and in the opening of the plug part. The width of the area of the body portion is greater than the width of the mask opening of the plug portion.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a photomask, which includes: a semi-transmissive layer on a mask substrate and including a plug portion of the mask opening that exposes the mask. a portion of the mask base; and an opaque layer on the semi-transparent layer and including a mask opening of a body portion that exposes portions of the semi-transmissive layer and portions of the mask base; providing a stack A structure including an etch stop layer on a bottom conductive layer and a first inner dielectric layer on the etch stop layer; and forming a pre-process mask layer on the stacked structure; utilizing the The pre-process mask layer is patterned with a photomask to form an imaged mask layer, which includes a mask area corresponding to the opaque layer, a main body area corresponding to the semi-transparent layer, and a hole corresponding to the mask opening of the plug portion; perform an opening etching process to form an opening of the body portion and an opening of the plug portion in the stacked structure, and expose a portion of the bottom conductive layer; and form a plug structure in the opening of the main body part and the opening of the plug part. The thickness of the area of the body portion is smaller than the thickness of the mask area. The width of the opening of the body portion is greater than the width of the opening of the plug portion.

Due to the design of the semiconductor element of the present invention, a plug structure formed using a photomask including a semi-transmissive layer can have vertical plug sidewalls while keeping the coverage window of the plug structure to the bottom conductive layer sufficiently large. Therefore, the contact resistance can be increased and the risk of underetching can be reduced. As a result, the yield and/or performance of the resulting semiconductor device will be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

The following description of the disclosure, accompanied by the drawings, which are incorporated in and constitute a part of the specification, illustrates embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

"One embodiment", "an embodiment", "exemplary embodiment", "other embodiments", "another embodiment", etc. mean that the embodiments described in the present disclosure may include specific features, structures or characteristics. However, Not every embodiment must include a particular feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

In order that the disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the practice of the present disclosure will not be limited to the specific details known to those skilled in the art. In addition, known structures and steps are not described in detail to avoid unnecessarily limiting the present disclosure. Preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the contents of the detailed description, but is defined by the patent claims.

In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits and electronic elements are all included in the category of semiconductor elements.

It should be noted that in the description of the present invention, upper (or upper) corresponds to the direction of the Z-direction arrow, and lower (or lower) corresponds to the opposite direction of the Z-direction arrow.

It should be noted that the word "forming" means any method of creating, establishing, patterning, implanting or depositing an element, a dopant or a material. Examples include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, crystal growth, implantation, lithography, dry etching and wet etching, etc. But it is not limited to this.

It should be noted that in the description of the present disclosure, functions or steps may occur in an order different from the order noted in the figures. For example, two figures shown in succession may actually be executed concurrently or sometimes in the reverse order, depending on the functions or steps involved.

FIG. 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A using a photomask 500A according to an embodiment of the present disclosure. 2 to 16 are cross-sectional schematic diagrams illustrating a process of manufacturing a semiconductor device 1A using a photomask 500A according to an embodiment of the present disclosure.

Referring to Figures 1 to 3, in step S11, a mask substrate 501 is provided, an opaque layer 503 is formed on the mask substrate 501, and the opaque layer 503 is patterned to form a main portion of the mask opening. 503O in the opaque layer 503.

Referring to Figure 2, mask substrate 501 may be formed of, for example, quartz, glass, or any other substantially transparent material. The glass may be, for example, aluminosilicate glass, calcium or magnesium fluoride and soda-lime glass. In some embodiments, mask substrate 501 has a thickness between about 0.125 inches and about 0.25 inches.

Referring to FIG. 2 , an opaque layer 503 may be formed on the mask substrate 501 . The opaque layer 503 may be formed of, for example, chromium, or other suitable materials that are sufficiently opaque to the incident wavelength of the energy source of the exposure process of the lithography process, as will be described later. In some embodiments, the opaque layer 503 may be formed by, for example, chemical vapor deposition, radio frequency sputtering, or other suitable deposition processes. In some embodiments, the thickness T1 of the opaque layer 503 is between about 500 angstroms and about 1000 angstroms. In some embodiments, the opaque layer 503 has an opacity of 100% or substantially about 100%.

In some embodiments, the opaque layer 503 may alternatively be formed through an electroplating process. In detail, the mask substrate 501 may be coated with a covering layer (not shown) on the bottom surface 501BS and the side surface 501LS of the mask substrate 501 . Then, the mask substrate 501 covered with the cover layer is soft-baked to enhance the adhesion between the mask substrate 501 and the cover layer and to expel all solvent in the cover layer. Subsequently, the mask substrate 501 coated with the cover layer is immersed in an electroless chromium plating activator for surface activation. A suitable electroless chromium plating activator may be an alkaline solution of chromium chloride and 2-propanol. The activation mask substrate 501 coated with the cover layer is then immersed in an electroless chromium plating solution to coat the opaque layer 503 . After the light-opaque layer 503 is formed on the mask substrate 501 covered with the cover layer, the cover layer can be peeled off from the mask substrate 501 .

Referring to FIG. 2 , a first mask layer 601 is formed on the opaque layer 503 through a photolithography process. The first mask layer 601 includes a pattern of mask openings 503O of the body portion. In some embodiments, the first mask layer 601 may be a photoresist, such as commercially available photoresist OCG895i or other suitable photoresist.

Referring to FIG. 3 , a first etching process using the first mask layer 601 as a mask is performed to remove portions of the opaque layer 503 . After the first etching process, a mask opening 503O of the main body portion is formed in the opaque layer 503 . A first portion of the top surface of the mask base 501 may be exposed through the mask opening 503O of the body portion. In some embodiments, during the first etching process, the etching rate ratio of the opaque layer 503 to the mask substrate 501 may be between about 100:1 and about 1.05:1, about 15:1 and about 2:1. 1, or between about 10:1 and about 2:1. After forming the mask opening 503O of the body portion, the first mask layer 601 will be removed.

Referring to FIGS. 1 and 4 to 6 , in step S13 , a semi-transmissive layer 505 is formed in the mask opening 503O of the main body part, and the semi-transmissive layer 505 is patterned to form a mask opening 505O of the plug part. , wherein the mask substrate 501, the opaque layer 503 and the semi-transmissive layer 505 together constitute the photomask 500A.

Referring to FIG. 4 , the semi-transmissive layer 505 may include, for example, molybdenum silicide or silicon nitride. In some embodiments, the semi-transparent layer 505 may be formed by, for example, chemical vapor deposition, sputtering, or other suitable deposition processes. In some embodiments, the first mask layer 601 may be removed after the semi-transmissive layer 505 is formed.

In some embodiments, the thickness T2 of the semi-transparent layer 505 is substantially the same as the thickness T1 of the opaque layer 503 . In some embodiments, the thickness T2 of the semi-transparent layer 505 and the thickness T1 of the opaque layer 503 may be different. For example, the thickness T2 of the semi-transmissive layer 505 may be greater or smaller than the thickness T1 of the opaque layer 503 . In some embodiments, the opacity ratio of the opacity of the semi-transmissive layer 505 to the opacity of the opaque layer 503 is between about 5% and about 95%. In some embodiments, the opacity ratio of the opacity of the semi-transmissive layer 505 to the opacity of the opaque layer 503 is between about 45% and about 75%. It should be noted that the exposed first portion of the top surface of the mask substrate 501 is completely covered by the light-transmitting layer 505 at this stage.

Referring to FIG. 5 , a second mask layer 603 is formed through a photolithography process to cover the opaque layer 503 and the partially semi-transmissive layer 505 . The second mask layer 603 includes a pattern of mask openings 505O of plug portions. In some embodiments, the second mask layer 603 may be a photoresist, such as commercially available photoresist OCG895i or other suitable photoresist.

Referring to FIG. 6 , a second etching process using the second mask layer 603 as a mask is performed to remove the exposed portion of the semi-transparent layer 505 . After the second etching process, a mask opening 505O of the plug portion is formed in the semi-transparent layer 505 . A second portion of the top surface of the mask base 501 may be exposed through the mask opening 505O of the plug portion. In some embodiments, during the second etching process, the etching rate ratio of the semi-transparent layer 505 to the mask substrate 501 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2 :1, or between about 10:1 and about 2:1. After forming the mask opening 505O of the plug portion, the second mask layer 603 will be removed. The surface area S1 of the first portion of the top surface of the mask substrate 501 is greater than the surface area S2 of the second portion of the top surface of the mask substrate 501 .

Referring to Figures 1 and 7 to 14, in step S15, a stacked structure 100 is provided, a hard mask structure 200 is formed on the stacked structure 100, and a pre-process mask layer 401 is formed on the hard mask structure 200, using The photomask 500A patterns the pre-process mask layer 401 to form an imaged mask layer 403, patterns the hard mask structure 200 using the imaged mask layer 403 as a mask, and performs an opening etching process to form the An opening 310O of the main body part and an opening 320O of the plug part are formed in the stacked structure 100 .

Referring to FIG. 7 , the stacked structure 100 includes a substrate 101 , a bottom dielectric layer 103 , a bottom conductive layer 105 , an etch stop layer 107 , a first inner dielectric layer 109 and a second dielectric layer 111 . In some embodiments, the substrate 101 includes a bulk semiconductor substrate composed entirely of at least one semiconductor material. The bulk semiconductor substrate may be composed of element semiconductors such as silicon and germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and phosphorus. It is formed of gallium, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or a combination thereof.

In some embodiments, substrate 101 may include a semiconductor-on-insulator structure consisting, from bottom to top, of a processing substrate, an insulator layer, and a topmost layer of semiconductor material. The handling substrate and the topmost semiconductor material layer may be formed from the same materials as the bulk semiconductor substrate described above. The insulator layer may be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the insulator layer may be a dielectric oxide, such as silicon oxide. As another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulator layer may include a stack of dielectric oxide and dielectric nitride, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer may have a thickness of between approximately 10 nm and 200 nm.

It should be noted that the term "about" changes an amount of an ingredient, component, or reactant of the present disclosure refers to the numerical change that may occur in a concentrate or solution, such as by typical measurements and liquid handling procedures for preparation. In addition, variations may arise from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used in making compositions or performing methods, for example. In some aspects, the term "about" refers to a variation within 10% of the indicated value. In other aspects, the term "about" refers to a variation within 5% of the indicated value. However, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

Alternatively, in some embodiments, substrate 101 may also include a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). not shown for reasons).

Device elements may be formed on a bulk semiconductor substrate or a topmost layer of semiconductor material. Portions of the device elements may be formed in the bulk semiconductor substrate or in the topmost layer of semiconductor material. The device elements may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect transistors, etc., or combinations thereof.

The dielectric layer may be formed over the bulk semiconductor substrate or the topmost layer of semiconductor material and covers the device elements. In some embodiments, the dielectric layer may be formed from, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, etc., or combinations thereof . Low dielectric constant dielectric materials may have a dielectric constant less than 3.0 or less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0. The dielectric layer may be formed by a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like. A planarization process can be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps.

The conductive features include multiple interconnect layers and multiple conductive vias. The interconnect layers are separated from each other and are arranged horizontally in the dielectric layer along the direction Z. Conductive vias connect adjacent interconnect layers along direction Z, as well as adjacent device elements and interconnect layers. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive features may be formed from, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (eg, Titanium nitride), transition metal aluminides, or combinations thereof. The conductive features may be formed during formation of the dielectric layer.

The device elements and conductive features together constitute multiple functional units in substrate 101 . In the description of the present disclosure, a functional unit generally refers to a functionally related circuit that has been divided into different units for functional purposes. In some embodiments, functional units may typically be highly complex circuits, such as processor cores, memory controllers, or accelerator units. In some other embodiments, the degree of complexity and functionality of the functional units may depend on actual needs.

Referring to FIG. 7 , in some embodiments, bottom dielectric layer 103 may be formed on substrate 101 and may be made of, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass , or a combination thereof. In some embodiments, the bottom dielectric layer 103 may be made of, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low-k dielectric layer, Formed by chemical vapor deposition of a low-k dielectric layer, or a combination thereof. In some embodiments, bottom dielectric layer 103 may include a self-planarizing material such as spin-on glass or a spin-on low-k dielectric material such as SiLK ^™ . The use of self-planar dielectric materials can avoid the need to perform subsequent planarization steps. In some embodiments, bottom dielectric layer 103 may be formed by a deposition process, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 7 , a bottom conductive layer 105 may be formed in the bottom dielectric layer 103 . The bottom conductive layer 105 may be formed of, for example, tungsten. In some embodiments, the bottom conductive layer 105 may be made of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides ( For example, titanium nitride), transition metal aluminides, or combinations thereof. In this embodiment, the bottom conductive layer 105 can be regarded as M0.

Referring to FIG. 7 , an etch stop layer 107 is formed on the bottom dielectric layer 103 . Typically, an etch stop layer provides a mechanism to stop the etch process while forming conductive features. The etch stop layer may preferably be formed of a dielectric material having a different etch selectivity than adjacent layers. For example, the etch stop layer 107 may be formed of silicon nitride, silicon carbonitride, silicon oxycarbonate, etc., or a combination thereof. Etch stop layer 107 may be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition.

Referring to FIG. 7 , a first inner dielectric layer 109 may be formed on the etch stop layer 107 . The first inner dielectric layer 109 may be formed of, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low-k dielectric layer, chemical vapor deposition A low-k dielectric layer, or a combination thereof. In some embodiments, first inner dielectric layer 109 may include a self-planarizing material such as spin-on glass or a spin-on low-k dielectric material such as SiLK ^™ . The use of self-planar dielectric materials can avoid the need to perform subsequent planarization steps. In some embodiments, the first inner dielectric layer 109 may be formed by a deposition process, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 7 , a second dielectric layer 111 is formed on the first inner dielectric layer 109 . In some embodiments, second dielectric layer 111 may be formed of the same material as first inner dielectric layer 109 . In some embodiments, second dielectric layer 111 may be formed of a different material than first inner dielectric layer 109 . For example, the second dielectric layer 111 may be made of, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-coated low-k dielectric layer, chemical vapor deposition A low dielectric constant dielectric layer, or a combination thereof. In some embodiments, the second dielectric layer 111 may include a self-planarizing material such as spin-on glass or a spin-on low-k dielectric material such as SiLK ^™ . The use of self-planar dielectric materials can avoid the need to perform subsequent planarization steps. In some embodiments, the second dielectric layer 111 may be formed by a deposition process, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to FIG. 7 , the thickness of the first inner dielectric layer 109 may be greater than the thickness of the second dielectric layer 111 . In some embodiments, second dielectric layer 111 is optional.

Referring to FIG. 7 , the hard mask structure 200 may be formed on the second dielectric layer 111 or, if the second dielectric layer 111 is not present, the first inner dielectric layer 109 . The hard mask structure 200 may include a first hard mask layer 201 and an anti-reflective coating 203 .

In some embodiments, first hard mask layer 201 may have a thickness T3 between about 80 nm and about 500 nm. In some embodiments, the thickness T3 of the first hard mask layer 201 may be between about 100 nm and about 200 nm.

In some embodiments, the first hard mask layer 201 may be formed of, for example, a carbon film. The term "carbon film" is used herein to describe a material whose mass is primarily carbon, whose structure is defined primarily by carbon atoms, or whose physical and chemical properties are dominated by its carbon content. The term "carbon film" is intended to exclude materials that are simple mixtures or compounds that include carbon, such as dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polycrystalline silicon.

In some embodiments, the first hard mask layer 201 may be formed through a high-density plasma chemical vapor deposition process. High-density plasmas can be generated using inductively coupled radio frequencies with powers between about 500 watts and about 4000 watts. In some embodiments, high density plasma may be generated using capacitively coupled radio frequency with power between about 500 watts and about 4000 watts. The carbon source can be methane, ethane, acetylene, benzene, or combinations thereof. The flow rate of the carbon source may be between about 50 standard cubic feet per minute (sccm) and about 150 sccm. The carbon source can polymerize carbon to form carbon-carbon chains. An inert gas such as argon, neon or helium can be used as a carrier gas to carry the carbon source. The flow rate of the carrier gas may be between about 10 seem and about 150 seem. The process pressure of the high-density plasma chemical vapor deposition process may be about 5 mTorr and about 20 mTorr. The process temperature of the high-density plasma chemical vapor deposition process can be between about 240°C and about 340°C.

Alternatively, in some embodiments, first hard mask layer 201 may be formed of, for example, boron nitride, silicon boron nitride, boron nitride phosphorus, silicon boron carbon nitride, or the like. The first hard mask layer 201 may be formed through a film forming process and a processing process. In detail, during the film formation process, a first precursor may be introduced above the second dielectric layer 111 (or the first inner dielectric layer 109) to form a boron-based layer, and the first precursor may be a boron-based precursor. Subsequently, during the processing process, a second precursor, which may be a nitrogen-based precursor, may be introduced to react with the boron-based layer and turn the boron-based layer into the first hard mask layer 201 . In some embodiments, the first precursor is an alkyl-substituted boron derivative such as diborane, borazine, or borazane. In some embodiments, the second precursor may be ammonia or hydrazine, for example.

Referring to FIG. 7 , an anti-reflective coating 203 may be formed on the first hard mask layer 201 . Anti-reflective coating 203 can be used to reduce reflections from underlying materials, standing waves, thin film interference, and specular reflections. In some embodiments, anti-reflective coating 203 may be composed of a thin film structure having alternating layers of contrasting refractive index. In some embodiments, anti-reflective coating 203 may be, for example, AR 40 Anti-Reflectant, commercially available from Rohm and Haas Electronic Materials (Phoenix, Ariz.). In some embodiments, the thickness T4 of the anti-reflective coating 203 is between about 30 nm and about 50 nm. In some embodiments, anti-reflective coating 203 is optional.

Referring to FIG. 7 , a pre-process mask layer 401 may be formed on the hard mask structure 200 by, for example, spin coating. A soft bake process may be performed to remove solvent remaining in the pre-process mask layer 401 . In some embodiments, the pre-process mask layer 401 may be a photoresist, such as commercially available photoresist OCG895i or other suitable photoresist.

Referring to 7, the photomask 500A may be placed over and aligned with the stacked structure 100.

Referring to FIG. 8 , the exposure process may be performed using a photomask 500A. A radiation source can be used to perform the exposure process. The radiation source may be, for example, ultraviolet radiation, deep ultraviolet radiation (usually 193 nm or 248 nm) or extreme ultraviolet radiation (usually 13.5 nm). The post-exposure bake process can be performed immediately after the exposure process. Subsequently, the development process can be performed. During the development process, an alkaline aqueous solution is added to the exposed and baked pre-process mask layer 401 and dissolves part of the pre-process mask layer 401 . After the exposure process, post-exposure bake process, and development process, the pre-process mask layer 401 will be converted into an imaged mask layer 403.

Referring to FIG. 8 , the imaged mask layer 403 includes a mask region 403M, a body portion region 403B, and a plug portion hole 403C. The mask area 403M surrounds the area 403B of the body portion. The mask area 403M may correspond to the opaque layer 503 . That is, the mask area 403M and the opaque layer 503 may completely overlap each other in a top view (not shown). The area 403B of the body portion may correspond to the semi-transmissive layer 505 . That is, the area 403B of the main body part and the semi-transparent layer 505 may completely overlap each other in a top view (not shown). The space enclosed by the area 403B of the body portion can be considered as the hole 403C of the plug portion. A portion of the top surface of the hard mask structure 200 may be exposed through the plug portion hole 403C. The hole 403C of the plug portion may correspond to the mask opening 505O of the plug portion. That is, the hole 403C of the plug portion and the mask opening 505O of the plug portion may completely overlap each other in a top view (not shown).

Referring to FIG. 8 , the thickness T5 of the mask area 403M may be greater than the thickness T6 of the area 403B of the body part. In some embodiments, the thickness ratio of the thickness T6 of the body portion region 403B to the thickness T5 of the mask region 403M is between about 25% and about 85%. In some embodiments, the thickness ratio of the thickness T6 of the body portion region 403B to the thickness T5 of the mask region 403M is between about 45% and about 65%.

Referring to FIGS. 9-12 , a hard mask etching process using the imaged mask layer 403 as a mask is performed to pattern the hard mask structure 200 . In some embodiments, the hard mask etch process may be an anisotropic etch process. In some embodiments, the hard mask etching process may include multiple stages, such as four stages, but is not limited thereto.

Referring to FIG. 9 , in the first stage of the hard mask etching process, the hard mask structure 200 beneath the body region 403B may be temporarily protected by the body region 403B of the imaged mask layer 403 . In detail, during the first stage of the hard mask etching process, the region 403B of the main portion of the imaged mask layer 403 may serve as an etch buffer layer to protect the underlying anti-reflective coating 203 . As a result, the anti-reflective coating 203 corresponding to the area 403B of the body portion will remain intact during the first stage of the hard mask etch process. It should be noted that the area 403B of the main part of the imaged mask layer 403 will continue to be consumed in the first stage of the hard mask etching process. After the first stage of the hard mask etching process, the area 403B of the body portion will be completely consumed or only a little will remain.

In contrast, for the anti-reflective coating 203 corresponding to the hole 403C in the plug portion of the imaged mask layer 403, no imaged mask layer 403 is present to serve as a temporary etch buffer. Therefore, in the first stage of the hard mask etching process, the anti-reflective coating 203 corresponding to the hole 403C of the plug portion will be removed, while the anti-reflective coating 203 corresponding to the area 403B of the body portion will still be formed by the image. The main body portion of the mask layer 403 is protected by the region 403B. As a result, after the first stage hard mask etching process, the anti-reflective coating 203 corresponding to the plug portion hole 403C will be removed to form the opening 320O along the plug portion of the anti-reflective coating 203 . A portion of the first hard mask layer 201 may be exposed through the opening 320O of the plug portion. In some embodiments, during the first stage of the hard mask etching process, a small portion of the first hard mask layer 201 exposed through the opening 320O of the plug portion is also removed. In other words, the opening 320O of the plug portion will extend to the first hard mask layer 201 (not shown).

In some embodiments, in the first stage of the hard mask etch process, the etch rate ratio of the imaged mask layer 403 to the anti-reflective coating 203 is between about 20:1 and about 1.5:1, about 10 :1 and about 2:1, or between about 5:1 and about 2:1. In some embodiments, during the first stage of the hard mask etch process, the etch rate ratio of the imaged mask layer 403 to the first hard mask layer 201 may be between about 100:1 and about 2:1 , between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

Referring to FIG. 10 , in the second stage of the hard mask etching process, since the area 403B of the body part is completely consumed in the first stage of the hard mask etching process, the anti-reflective coating 203 corresponding to the area 403B of the body part will be removed. . As a result, the opening 320O along the plug portion of the anti-reflective coating 203 will be widened to form an opening 310O along the body portion of the anti-reflective coating 203 . In some embodiments, a small portion of the first hard mask layer 201 corresponding to the area 403B of the body portion is also removed. In other words, the opening 310O of the body portion may extend to the first hard mask layer 201 (not shown).

At the same time, the first hard mask layer 201 exposed through the opening 320O of the plug portion (before widening) will be removed to extend the opening 320O of the plug portion to the first hard mask layer 201 . It should be noted that the opening 320O of the plug part is deeper than the opening 310O of the main part, and the opening 310O of the main part is connected with the opening 320O of the plug part. After the second stage of the hard mask etch process, the imaged mask layer 403 will be completely consumed or only a little will remain (eg, a mask area 403M may be left, not shown).

In some embodiments, the second stage of the hard mask etch process and the first stage of the hard mask etch process can be performed using the same etch recipe. In some embodiments, during the second stage of the hard mask etch process, the etch rate ratio of the imaged mask layer 403 to the anti-reflective coating 203 may be between about 20:1 and about 1.5:1, about Between 10:1 and about 2:1, or between about 5:1 and about 2:1. In some embodiments, in the second stage of the hard mask etch process, the etch rate ratio of the imaged mask layer 403 to the first hard mask layer 201 may be between about 100:1 and about 2:1 , between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

Referring to FIG. 11 , in the third stage of the hard mask etching process, the first hard mask layer 201 exposed through the opening 310O of the body part and the opening 320O of the plug part will be removed simultaneously. That is, the opening 320O of the plug portion will be deepened toward the second dielectric layer 111 , and the opening 310O of the body portion will extend to the first hard mask layer 201 . In some embodiments, a portion of the second dielectric layer 111 exposed through the opening 320O of the plug portion is also removed. In other words, the opening 320O of the plug portion will extend to the second dielectric layer 111 . It should be noted that the opening 320O of the plug part is still deeper than the opening 310O of the main body part.

In some embodiments, the third stage of the hard mask etch process and the second stage of the hard mask etch process may be performed using different etch recipes. In some embodiments, in the third stage of the hard mask etching process, the etch rate ratio of the first hard mask layer 201 to the anti-reflective coating 203 may be between about 100:1 and about 1.5:1, between about Between 50:1 and about 2:1, or between about 5:1 and about 2:1. In some embodiments, in the third stage of the hard mask etching process, the etch rate ratio of the second dielectric layer 111 to the anti-reflective coating 203 may be between about 50:1 and about 2:1, about 15:1. Between 1 and about 2:1, or between about 5:1 and about 2:1.

Referring to FIG. 12 , in the fourth stage of the hard mask etching process, the anti-reflective coating 203 will be completely removed. The body portion opening 310O and the plug portion opening 320O may remain at the same depth/profile as in the third stage of the hard mask etch process, or the body portion opening 310O and the plug portion opening 320O may be the same as those of the hard mask etch process. Compared with the third stage, it is slightly deeper.

In some embodiments, the fourth stage of the hard mask etch process and the third stage of the hard mask etch process may be performed using different etch recipes. In some embodiments, in the fourth stage of the hard mask etching process, the etch rate ratio of the anti-reflective coating 203 to the first hard mask layer 201 may be between about 100:1 and about 1.5:1, between about Between 50:1 and about 2:1, or between about 5:1 and about 2:1. In some embodiments, in the fourth stage of the hard mask etching process, the etch rate ratio of the anti-reflective coating 203 to the second dielectric layer 111 may be between about 100:1 and about 2:1, about 50:1. Between 1 and about 2:1, or between about 5:1 and about 2:1.

In some embodiments, the fourth stage of the hard mask etch process is optional and the remaining anti-reflective coating 203 can be used as part of the mask in the subsequent opening etch process.

Referring to FIGS. 13 and 14 , an opening etching process using the imaged first hard mask layer 201 as a mask is performed. In some embodiments, the opening etching process may be an anisotropic process. In some embodiments, the opening etching process may include multiple stages, such as two stages, but is not limited thereto. In some embodiments, the opening etch process is a polymer-free process, which results in less polymer redeposition on the sidewalls of the opening. Openings prepared with less polymer redeposition can have straighter sidewall profiles.

Referring to FIG. 13 , in the first stage of the opening etching process, the opening 320O of the plug part and the opening 310O of the body part will be deepened simultaneously. The opening 320O of the plug portion will extend to the first inner dielectric layer 109, and the opening 310O of the body portion will extend to the second dielectric layer 111. The first hard mask layer 201 will continue to be consumed during the first stage of the opening etching process.

In some embodiments, in the first stage of the opening etching process, the etch rate ratio of the second dielectric layer 111 to the first hard mask layer 201 may be between about 50:1 and about 1.5:1, about 15:1. Between 1 and about 2:1, or between about 5:1 and about 2:1. In some embodiments, in the first stage of the opening etching process, the etch rate ratio of the first inner dielectric layer 109 to the first hard mask layer 201 may be between about 50:1 and about 2:1, about 15 :1 and about 2:1, or between about 5:1 and about 2:1.

Referring to FIG. 14 , in the second stage of the opening etching process, the opening 320O of the plug part and the opening 310O of the body part will be deepened simultaneously. The opening 320O of the plug portion will extend to the etch stop layer 107 . A portion of the bottom conductive layer 105 may be exposed through the opening 320O of the plug portion. The opening 310O of the body portion will extend to the etch stop layer 107 . It should be noted that the opening 320O of the plug part is still deeper than the opening 310O of the main body part. The first hard mask layer 201 will continue to be consumed during the second stage of the opening etching process. After the opening etching process, the first hard mask layer 201 will be completely removed or only left a little, and an additional removal process may be performed to remove the remaining first hard mask layer 201 .

In some embodiments, in the second stage of the opening etching process, the etch rate ratio of the second dielectric layer 111 to the first hard mask layer 201 is between about 100:1 and about 1.5:1, about 50:1 and between John 2:1, or between John 5:1 and John 2:1. In some embodiments, in the second stage of the opening etching process, the etch rate ratio of the first inner dielectric layer 109 to the first hard mask layer 201 is between about 100:1 and about 2:1, between about 50 :1 and about 2:1, or between about 5:1 and about 2:1. In some embodiments, in the second stage of the opening etching process, the etch rate ratio of the etch stop layer 107 to the first hard mask layer 201 is between about 100:1 and about 2:1, about 50:1 and about Between 2:1, or between about 5:1 and about 2:1.

In some embodiments, the width W1 of the opening 310O of the body portion may be greater than the width W2 of the opening 320O of the plug portion. In some embodiments, the width ratio of the width W2 of the plug portion opening 320O to the width W1 of the body portion opening 310O may be between about 10% and about 75%, or between about 30% and about 60%. . In some embodiments, the width W3 of the bottom conductive layer 105 may be greater than the width W1 of the opening 310O of the body portion. In some embodiments, the width ratio of the width W1 of the opening 310O of the body portion to the width W3 of the bottom conductive layer 105 is between about 5% and about 70%, or between about 10% and about 50%.

1, 15 and 16, in step S17, a plug structure 300 is formed in the opening 310O of the main body part and the opening 320O of the plug part.

Referring to FIG. 15 , a layer of first conductive material 605 may be deposited into the opening 310O of the body part and the opening 320O of the plug part through a deposition process. The first conductive material 605 is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (eg, titanium nitride) , transition metal aluminides, or combinations thereof.

Referring to FIG. 16 , after the deposition process, a planarization process, such as chemical mechanical polishing, may be performed until the top surface of the second dielectric layer 111 is exposed to remove excess material, provide a substantially flat surface for subsequent process steps, and form The plug structure 300 is disposed in the opening 310O of the main body part and the opening 320O of the plug part. The substrate 101, the bottom dielectric layer 103, the bottom conductive layer 105, the etching stop layer 107, the first inner dielectric layer 109, the second dielectric layer 111 and the plug structure 300 together form the semiconductor device 1A.

Referring to FIG. 16 , in this embodiment, the plug structure 300 can be regarded as C0 and includes a main body part 310 and a plug part 320 . The main body portion 310 is formed in the opening 310O of the main body portion, and the plug portion 320 is formed in the opening 320O of the plug portion and contacts the bottom conductive layer 105 and the main body portion 310 . In this embodiment, the bottom surface 310B of the body portion 310 may be at a lower vertical level V1 than the vertical level V2 of the top surface 107T of the etch stop layer 107 .

In some embodiments, sidewalls 310S of body portion 310 may be substantially vertical. In some embodiments, sidewalls 320S of plug portion 320 may be substantially vertical. It should be noted that in the description of the present disclosure, a surface (for example, the side wall 310S or the side wall 320S) is "substantially vertical", which means that there is a vertical plane, and the vertical plane deviates from the surface by no more than the surface roughness. three times the root mean square of the degree. Alternatively, in some embodiments, if the second stage of the opening process uses a polymer-rich etch process, the sidewalls 320S of the plug portion 320 will be tapered.

In some embodiments, the width W4 of the body portion 310 may be greater than the width W5 of the plug portion 320 . In some embodiments, the width ratio of the width W5 of the plug portion 320 to the width W4 of the body portion 310 is between about 10% and about 75%, or between about 30% and about 60%. In some embodiments, the width W3 of the bottom conductive layer 105 may be greater than the width W4 of the body portion 310 . In some embodiments, the width ratio of the width W4 of the body portion 310 to the width W3 of the bottom conductive layer 105 is between about 5% and about 70%, or between about 10% and about 50%.

In some embodiments, the height H1 of the body portion 310 may be greater than the height H2 of the plug portion 320 . The sum of the height H1 of the body portion 310 and the height H2 of the plug portion 320 may be considered the total height HT of the plug structure 300 . In some embodiments, the height ratio of height H2 of plug portion 320 to the total height HT of plug structure 300 is between 5% and about 45%, between about 5% and about 25%, or between about 5% % and about 15%.

Traditionally, to increase the C0 to M0 coverage window, a polymer-rich etching process can be used and a plug with tapered sidewalls can be obtained. However, the tapered sidewalls of the plug may increase contact resistance and increase the risk of under-etching.

In contrast, by using the photomask 500A including the semi-transmissive layer 505, the plug structure 300 can be formed with vertical plug sidewalls 310S, 320S while keeping the coverage window of C0 to M0 sufficiently large. That is, the contact resistance will increase and the risk of under-etching will decrease. As a result, the yield and/or performance of the resulting semiconductor element 1A will be improved.

FIG. 17 is a flow chart illustrating a method 20 for manufacturing a semiconductor device 1B using a photomask 500B according to another embodiment of the present disclosure. 18 to 26 are schematic cross-sectional views illustrating a process of manufacturing a semiconductor device 1B using a photomask 500B according to another embodiment of the present disclosure.

Referring to FIGS. 17 to 19 , in step S21 , a mask substrate 501 is provided, a light-transmitting layer 505 is formed on the mask substrate 501 , and an opaque layer 503 is formed on the light-transmitting layer 505 .

Referring to FIG. 18 , the mask base 501 has a similar structure to the mask base 501 shown in FIG. 2 , which will not be described again. The semi-transparent layer 505 is formed on the mask substrate 501 and completely covers the mask substrate 501 . The thickness T2, material, and opacity of the semi-transparent layer 505 are similar to those of the semi-transmissive layer 505 shown in FIG. 4, and will not be described again here.

Referring to FIG. 19 , an opaque layer 503 is formed on the semi-transmissive layer 505 . It should be noted that in this embodiment, the opaque layer 503 may be opposite to the mask base 501 with the light-transmitting layer 505 sandwiched therebetween. The thickness T1, material, and opacity of the opaque layer 503 are similar to the opaque layer 503 shown in FIG. 2 and will not be described again here.

Referring to FIGS. 17 , 20 and 21 , in step S23 , the opaque layer 503 is patterned to form a main portion of the mask opening 503O in the opaque layer 503 .

Referring to FIG. 20 , a first mask layer 601 is formed on the opaque layer 503 . The first mask layer 601 has a similar structure to the first mask layer 601 shown in FIG. 2 , which will not be described again here.

Referring to FIG. 21 , a first etching process using the first mask layer 601 as a mask is performed to remove a portion of the opaque layer 503 . After the first etching process, a mask opening 503O of the main body portion may be formed in the opaque layer 503 . A first portion of the top surface of the semi-transmissive layer 505 may be exposed through the mask opening 503O of the main body portion. In some embodiments, during the first etching process, the etching rate ratio of the opaque layer 503 to the semi-transmissive layer 505 may be between about 100:1 and about 1.05:1, about 15:1 and about 2 :1, or between about 10:1 and about 2:1. After forming the mask opening 503O of the body portion, the first mask layer 601 will be removed.

17, 22 and 23, in step S25, the semi-transparent layer 505 is patterned to form a plug-part mask opening 505O, in which the mask base 501, the opaque layer 503 and the semi-transmissive layer 505 together form a photomask 500B.

Referring to Figure 22, a second mask layer 603 is formed on the opaque layer 503 and the semi-transparent layer 505. The second mask layer 603 has a similar structure to the second mask layer 603 shown in FIG. 5 , which will not be described again here.

Referring to FIG. 23 , a process similar to that shown in FIG. 6 may be used to perform the second etching process, which will not be described again.

Referring to Figures 17 and 24 to 26, in step S27, a stacked structure 100 is provided, a hard mask structure 200 is formed on the stacked structure 100, and a pre-process mask layer 401 is formed on the hard mask structure 200, using The photomask 500B patterns the pre-process mask layer 401 to form an imaged mask layer 403, patterns the hard mask structure 200 using the imaged mask layer 403 as a mask, and performs an opening etching process to form the An opening 310O of the main body part and an opening 320O of the plug part are formed in the stacked structure 100 .

Referring to Figure 24, the stacked structure 100, the hard mask structure 200 and the pre-process mask layer 401 may have a structure similar to that shown in Figure 7. The same or similar elements in Figure 24 as those in Figure 7 have been labeled with the same or similar label, and omit repeated descriptions.

Referring to FIG. 25 , the pre-process mask layer 401 is patterned to form the imaged mask layer 403 . The process is similar to the process shown in FIG. 8 and will not be described again.

Referring to FIG. 26 , the hard mask etching process and the opening etching process can be performed using procedures similar to those shown in FIGS. 9 to 14 , and will not be described again.

17, 25 and 26, in step S29, a plug structure 300 is formed in the opening 310O of the main body part and the opening 320O of the plug part.

Referring to Figure 25, the plug structure 300 can be formed using a procedure similar to that shown in Figures 15 and 16, which will not be described again. The substrate 101, the bottom dielectric layer 103, the bottom conductive layer 105, the etching stop layer 107, the first inner dielectric layer 109, the second dielectric layer 111 and the plug structure 300 together constitute the semiconductor element 1B.

FIG. 27 is a schematic cross-sectional view illustrating a semiconductor device 1C according to another embodiment of the present disclosure.

Referring to FIG. 27 , the semiconductor element 1C may have a similar structure to that shown in FIG. 16 . The same or similar elements in FIG. 27 as those in FIG. 16 have been marked with the same or similar numbers, and repeated descriptions are omitted.

Referring to FIG. 27 , the bottom surface 310B of the body portion 310 may be at a higher vertical level V1 than the vertical level V2 of the top surface 107T of the etch stop layer 107 . The height ratio of the height H2 of the plug portion 320 to the total height HT of the plug structure 300 may be between 15% and about 45%, between about 15% and about 25%, or between about 15% and about 20% between.

One aspect of the present invention provides a semiconductor device, including a bottom dielectric layer disposed on a substrate; a bottom conductive layer disposed in the bottom dielectric layer; and an etch stop layer disposed on the bottom conductive layer layer; a first inner dielectric layer disposed on the etch stop layer; and a plug structure including: a body portion disposed along the first inner dielectric layer and extending to the etch stop layer; and a plug portion disposed in the etch stop layer and in contact with the body portion and the bottom conductive layer. The width of the body portion is greater than the width of the plug portion.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a photomask, which includes an opaque layer on a mask substrate and surrounding a semi-transmissive layer on the mask substrate, wherein the The semi-transparent layer includes a plug portion of the mask opening, which exposes a portion of the mask substrate; a stacked structure is provided, which includes an etch stop layer on a bottom conductive layer and a first intermediary an electrical layer on the etch stop layer; and forming a pre-process mask layer on the stacked structure; patterning the pre-process mask layer using the photomask to form an imaged mask layer, which includes a The mask area corresponds to the opaque layer, a main body portion area corresponds to the semi-transparent layer, and a hole corresponds to the mask opening of the plug portion, wherein the thickness of the main body portion area is smaller than the thickness of the mask area ; Performing an opening etching process to form an opening of the body portion and an opening of the plug portion in the stacked structure, and exposing a portion of the bottom conductive layer; and forming a plug structure in the opening of the body portion and in the opening of the plug part. The width of the area of the body portion is greater than the width of the mask opening of the plug portion.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a photomask, which includes: a semi-transmissive layer on a mask substrate and including a plug portion of the mask opening that exposes the mask. a portion of the mask base; and an opaque layer on the semi-transmissive layer and including a mask opening of a body portion that exposes portions of the semi-transmissive layer and portions of the mask base; providing a stack A structure, which includes an etch stop layer on a bottom conductive layer and a first inner dielectric layer on the etch stop layer; and forming a pre-process mask layer on the stacked structure; utilizing the The pre-process mask layer is patterned with a photomask to form an imaged mask layer, which includes a mask area corresponding to the opaque layer, a main body area corresponding to the semi-transparent layer, and a hole corresponding to the mask opening of the plug portion; perform an opening etching process to form an opening of the body portion and an opening of the plug portion in the stacked structure, and expose a portion of the bottom conductive layer; and form a plug structure in the opening of the main body part and the opening of the plug part. The thickness of the area of the body portion is smaller than the thickness of the mask area. The width of the opening of the body portion is greater than the width of the opening of the plug portion.

Due to the design of the semiconductor device of the present disclosure, the plug structure 300 formed using the photomask 500A including the semi-transparent layer 505 can have vertical plug sidewalls while maintaining an overlay of the plug structure 300 to the bottom conductive layer 105 windows) are large enough. Therefore, the contact resistance can be increased and the risk of underetching can be reduced. As a result, the yield and/or performance of the resulting semiconductor device will be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1A: Semiconductor components 1B:Semiconductor components 1C: Semiconductor components 10:Preparation method 100:Stacked structure 101: Base 103: Bottom dielectric layer 105: Bottom conductive layer 107: Etch stop layer 107T:Top surface 109: First inner dielectric layer 111: Second dielectric layer 20:Preparation method 200: Hard mask structure 201: First hard mask layer 203: Anti-reflective coating 300: Plug structure 310: Ontology part 310B: Bottom 310O:Open your mouth 310S: Side wall 320: Plug part 320O:Open your mouth 320S: Sidewall 401: Mask layer before process 403: Imaged mask layer 403B:Region 403C:hole 403M: Mask area 500A: Photomask 500B: Photomask 501: Mask base 501BS: Bottom 501LS: Side 503: Opaque layer 503O: Mask opening 505: Semi-transparent layer 505O: Mask opening 601: First mask layer 603: Second mask layer 605: First conductive material H1: height H2: height HT: total height S1: surface area S2: surface area T1:Thickness T2:Thickness T3:Thickness T4:Thickness T5:Thickness T6:Thickness V1: vertical horizontal V2: vertical horizontal W1: Width W2: Width W3: Width W4: Width W5: Width

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a flow chart illustrating a method of manufacturing a semiconductor device using a photomask according to an embodiment of the present disclosure; 2 to 16 are cross-sectional schematic diagrams illustrating a process of preparing a semiconductor device using a photomask according to an embodiment of the present disclosure; FIG. 17 is a flow chart illustrating a method of manufacturing a semiconductor device using a photomask according to another embodiment of the present disclosure; 18 to 26 are cross-sectional schematic diagrams illustrating a process of preparing a semiconductor device using a photomask according to another embodiment of the present disclosure; FIG. 27 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components 100:Stacked structure 101: Base 103: Bottom dielectric layer 105: Bottom conductive layer 107: Etch stop layer 107T:Top surface 109: First inner dielectric layer 111: Second dielectric layer 300: Plug structure 310: Ontology part 310B: Bottom 310O:Open your mouth 310S: Side wall 320: Plug part 320O:Open your mouth 320S: Sidewall H1: height H2: height HT: total height V1: vertical horizontal V2: vertical horizontal W3: Width W4: Width W5: Width

Claims (10)

A semiconductor element includes: a bottom dielectric layer disposed on a substrate; a bottom conductive layer disposed in the bottom dielectric layer; an etching stop layer disposed on the bottom conductive layer; a first an inner dielectric layer disposed on the etch stop layer; and a plug structure including: a body portion disposed along the first inner dielectric layer and extending to the etch stop layer; and a plug portion , which is disposed in the etching stop layer and in contact with the main body part and the bottom conductive layer; wherein the width of the main body part is greater than the width of the plug part, and the width of the plug part is less than the width of the bottom conductive layer, And a bottom surface height of the main body part is lower than a top surface height of the etching stop layer. The semiconductor device of claim 1, wherein the sidewalls of the body portion are substantially vertical. The semiconductor device of claim 2, wherein the side walls of the plug portion are substantially vertical. The semiconductor device as claimed in claim 3, wherein the plug portion has a width equal to that of the body portion The width-to-width ratio is between about 10% and about 75%. The semiconductor component as claimed in claim 4, wherein the height of the body part is greater than the height of the plug part. The semiconductor device of claim 5, wherein a height ratio of the height of the plug portion to the total height of the plug structure is between about 5% and about 45%. The semiconductor device of claim 6, wherein a width ratio of the width of the body portion to the width of the bottom conductive layer is between about 5% and about 70%. The semiconductor device of claim 7, further comprising a second dielectric layer disposed on the first inner dielectric layer, wherein the main body portion of the plug structure is along the second dielectric layer and the third An inner dielectric layer is provided and extends to the etch stop layer. The semiconductor device of claim 8, wherein the first inner dielectric layer and the second dielectric layer include the same material. The semiconductor device of claim 9, wherein the etching stop layer includes silicon nitride, silicon carbonitride, silicon oxycarbonate or a combination thereof.

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