TWI831222B - Test circuit for controlling stress voltage and semiconductor memory device - Google Patents

Abstract

The present invention provides a test circuit for contolling stress voltage including a control circuit. In a test mode, the control circuit controls a supply voltage which is supplied to a precharge circuit including transistors in a semiconductor memory device. The control circuit controls the supply voltage according to a voltage of an external power supply and a threshold voltage of the transistors included in the precharge circuit.

Description

Test circuits and semiconductor records for controlling pressure voltages memory device

The present invention relates to a test circuit for controlling pressure voltage and a semiconductor memory device.

Traditionally, before and after the packaging process of semiconductor memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM), a burn-in test is implemented to evaluate the reliability of the integrated circuit. Check. Specifically, the burn-in test is, for example, by setting the precharge voltage applied to the bit line to the voltage of the external power supply or a higher high voltage (referred to as the pressure voltage) for a long time, and then judging the memory integrated in the chip. Good and bad cells. To this end, a pressure test circuit is provided in a test device or a semiconductor memory device to supply a pressure voltage for burning (for example, Japanese Patent Application Laid-Open No. 5-325547).

In addition, the conventional precharge circuit of the bit line includes more than one transistor (for example, N-type or P-type Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)) etc.), and is configured to set the precharge voltage of the output bit line to the pressure voltage by turning more than one transistor into a conductive state during the burn-in test.

However, since the magnitude of the pressure voltage supplied by the precharge circuit of the bit line depends on the threshold voltage of the transistor and the reverse bias effect, the actual supplied pressure voltage may be smaller than the expected pressure voltage. As a result, it may be difficult to provide sufficient pressure voltage during the burn-in test.

In view of the above problems, an object of the present invention is to provide a test circuit and a semiconductor memory device for controlling the pressure voltage that can supply an appropriate pressure voltage.

The present invention provides a test circuit for controlling pressure voltage, including: a control circuit that controls a supply voltage in a test mode, the supply voltage being a voltage supplied to a precharge circuit including a transistor in a semiconductor memory device; wherein , the aforementioned control circuit controls the aforementioned supply voltage based on the voltage of the external power supply and the threshold voltage of the transistor included in the aforementioned precharge circuit.

According to the above invention, since the supply voltage can be controlled based on the voltage of the external power supply and/or based on the threshold voltage of the transistor of the precharge circuit, even when the threshold voltage of the transistor changes, the threshold can be used in the burn-in test. Voltage supply provides sufficient supply voltage to the precharge circuit. Thereby, an appropriate pressure voltage can be supplied.

According to the above invention, an appropriate pressure voltage can be supplied to the semiconductor memory device to perform a reliability check on the semiconductor memory device.

1: Internal voltage adjustment circuit

10: Test circuit for controlling pressure voltage

11: Boost circuit

12:Oscillator

13:Control circuit

13a: Constant current source

13b, 13c, 13d: MOSFET

13e: Comparator

20: Precharge circuit

21, 22, 23: N-type MOSFET

I0, I1: current

BL, /BL: bit line

BLEQ: gate voltage

en_CLK:signal

pump_CLK:clock signal

SW: switch

VBBSA: reverse bias

VDD: voltage of external power supply

VEQL: supply voltage

Vm, Vp: potential

VREF: reference voltage

VSS: low supply voltage

FIG. 1 is a block diagram showing a structural example of a test circuit for controlling pressure voltage and a semiconductor memory device according to an embodiment of the present invention.

Figure 2 is a schematic diagram showing an example of the configuration of a control circuit.

Figure 3 is a distribution diagram showing changes in threshold voltage of a transistor.

Figure 4 is a schematic diagram showing the relationship between the voltage of the external power supply and the supply voltage.

As shown in FIG. 1 , in this embodiment, the semiconductor memory device includes an internal voltage adjustment circuit 1 , a test circuit 10 for controlling the pressure voltage, a switch SW and a precharge circuit 20 . In addition, here, in order to simplify the description, conventional structures such as the instruction decoder, memory cell array, and input/output interface portion (interface pins, etc.) of the semiconductor memory device are not shown.

The internal voltage adjustment circuit 1 is configured to receive an external power supply and generate an internal voltage based on the voltage VDD of the external power supply. In addition, the internal voltage generated by the internal voltage adjustment circuit 1 can be used as the supply voltage VEQL provided to one or more other circuits (including the precharge circuit 20 ) driven by the internal voltage. The level of the internal voltage can be lower than the level of the external power supply voltage VDD. In some embodiments, the internal voltage adjustment circuit 1 may also include other conventional components such as a level converter, which converts the level of the internal voltage according to other circuits that are supplied with the internal voltage.

The test circuit 10 for controlling the pressure voltage includes a boost circuit 11, an oscillator 12 and a control circuit 13.

The boost circuit 11 is configured to boost the received power supply voltage. to generate the supply voltage VEQL. For example, the boost circuit 11 is configured to boost the voltage VDD of the external power supply and output the boosted voltage as the supply voltage VEQL (in this case, VEQL>VDD). The boost circuit 11 may also be configured to utilize a conventional charge pump circuit.

The oscillator 12 is configured to generate a clock signal pump_CLK for driving the boost circuit 11 . For example, when the oscillator 12 is activated by the signal en_CLK1 output from the control circuit 13 , the clock signal pump_CLK is generated to the boost circuit 11 . In addition, since the operation of the boost circuit 11 based on the clock signal pump_CLK is the same as that of the conventional technology, the description is omitted in this embodiment.

In the burn-in test mode, the control circuit 13 is configured to control the supply voltage VEQL, which is the voltage supplied to the precharge circuit 20 including the N-type MOSFETs 21, 22, and 23 in the semiconductor memory device. Here, the burn-in test mode is an example of the "test mode" of the present invention.

In addition, the control circuit 13 may also monitor the supply voltage VEQL output from the boost circuit 11. In detail, the control circuit 13 can control the supply voltage VEQL by controlling the oscillator 12 to set the supply voltage VEQL generated by the boost circuit 11 to a specific level. Therefore, by controlling the threshold voltage Vth of the oscillator 12, the boost circuit 11 and the N-type MOSFETs 21, 22, and 23 included in the precharge circuit 20, the supply voltage VEQL can be set to enable the precharge circuit 20 to generate an appropriate pressure voltage. .

The switch SW is configured such that one end is connected to the internal voltage adjustment circuit 1 or the test circuit 10 for controlling the pressure voltage, and the other end is connected to the precharge circuit 20 . For example, when the semiconductor memory device operates in the normal operating mode, the switch SW is controlled as One end is connected to the internal voltage adjustment circuit 1. Therefore, in the normal operation mode, the supply voltage VEQL supplied to the precharge circuit 20 is an internal voltage smaller than the voltage VDD of the external power supply. On the other hand, when the semiconductor memory device operates in the burn-in test mode, the switch SW is controlled to have one end connected to the test circuit 10 for controlling the pressure voltage. Therefore, in the burn-in test mode, the supply voltage VEQL supplied to the precharge circuit 20 is a voltage greater than the voltage VDD of the external power supply.

In this embodiment, the precharge circuit 20 is configured to precharge a pair of complementary bit lines BL, /BL coupled to a memory cell array (omitted in the illustration). Therefore, during the burn-in test, the bit lines BL and /BL in the semiconductor memory device can be precharged with appropriate pressure voltages. In addition, in this embodiment, the precharge circuit 20 includes three N-type MOSFETs 21, 22, and 23.

In the precharge circuit 20, the drain terminals of the N-type MOSFETs 21 and 22 are connected to the voltage VDD of the external power supply. The source of the N-type MOSFET 21 and the drain of the MOSFET 23 are connected to the bit line BL. The sources of N-type MOSFETs 22 and 23 are connected to bit line /BL. The supply voltage VEQL output from the internal voltage adjustment circuit 1 or the test circuit 10 for controlling the pressure voltage is applied to the gates of the N-type MOSFETs 21 and 22 as the gate voltage BLEQ. In addition, N-type MOSFETs 21, 22, and 23 are applied with equal reverse bias voltages VBBSA. Here, N-type MOSFET 21 is an example of the "fourth transistor" of the present invention, N-type MOSFET 22 is an example of the "fifth transistor" of the present invention, and N-type MOSFET 23 is an example of the "sixth transistor" of the present invention. ” an example. In addition, bit line BL is an example of the "first bit line" of the present invention, and bit line /BL is an example of the "second bit line" of the present invention.

In addition, in this embodiment, the N-type MOSFETs 21, 22, and 23 may also have equal dimensions (width and length of the channel). In this case, the respective gain coefficients of the N-type MOSFETs 21, 22, and 23 may be equal.

In addition, a pair of complementary bit lines BL and /BL are respectively connected to sense amplifiers (omitted in the illustration). In addition, since in the normal operation mode, the details of the data control and precharge operation of the memory cells (omitted in the illustration) in the memory cell array (omitted in the illustration) are the same as those in the conventional technology, in this implementation Explanation is omitted in the example.

As shown in FIG. 2 , the control circuit 13 includes a constant current source 13a, three N-type MOSFETs 13b, 13c, and 13d, and a comparator 13e.

The constant current source 13a is coupled between the source of the N-type MOSFET 13b and the low power supply voltage VSS (VSS<VDD, VEQL).

The drain and gate of the N-type MOSFET 13b are connected to the supply voltage VEQL output from the boost circuit 11. In addition, in this embodiment, a reverse bias voltage VBBSA equal to the reverse bias voltage VBBSA applied to the N-type MOSFETs 21, 22, and 23 in the precharge circuit 20 is applied to the N-type MOSFET 13b. Therefore, the supply voltage VEQL can be set in a state where the threshold voltage Vth of the N-type MOSFET 13b is equal to the threshold voltage Vth of the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20. Furthermore, in this embodiment, the N-type MOSFET 13b may also have the same size (channel width and length) as the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20. Therefore, the supply voltage VEQL can be set in a state where the gain coefficient of the N-type MOSFET 13b is equal to the gain coefficient of the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20. The N-type MOSFET 13b is an example of the "first transistor" of the present invention.

The drain and gate of the N-type MOSFET 13c are connected to the voltage VDD of the external power supply. The source of N-type MOSFET 13c is connected to the drain of N-type MOSFET 13d. The low power supply voltage VSS is applied to the N-type MOSFET 13c as a reverse bias voltage. In addition, the N-type MOSFET 13c is an example of the "second transistor" of the present invention.

The gate of the N-type MOSFET 13d is connected to the reference voltage VREF. Here, the reference voltage VREF can be adjustably generated by a reference voltage adjustment unit (omitted in the illustration). The reference voltage VREF can also be lower than the voltage VDD of the external power supply. The source of the N-type MOSFET 13d is connected to the low supply voltage VSS. The low power supply voltage VSS is applied to the N-type MOSFET 13d as a reverse bias voltage. In addition, the N-type MOSFET 13d is an example of the "third transistor" of the present invention.

The + terminal of the comparator 13e is connected to the connection node between the source of the N-type MOSFET 13b and the constant current source 13a. The - terminal of the comparator 13e is connected to the connection node between the source of the N-type MOSFET 13c and the drain of the N-type MOSFET 13d. The comparator 13e outputs a signal en_CLK for controlling activation and deactivation of the oscillator 12. In addition, in this embodiment, the oscillator 12 is configured to be activated when the signal en_CLK is at a low level, and to be inactivated when the signal en_CLK is at a high level.

Next, the operation of the control circuit 13 in this embodiment will be described. When the current flowing through the N-type MOSFET 13c and the N-type MOSFET 13d of the control circuit 13 is set to I1, I1 can be expressed using the current formula in the saturation region of the MOSFET as shown below.

[Mathematical formula 1]

In addition, in the mathematical formula (1), β is the gain coefficient, Vm is the potential of the connection node between the source of the N-type MOSFET 13c and the drain of the N-type MOSFET 13d, and Vth is the threshold voltage of the N-type MOSFETs 13c and 13d. . Next, based on the mathematical formula (1), the following mathematical formula (2) can be expressed.

[Math 2] Vm = VDD - VREF …(2)

Next, when the current flowing through the N-type MOSFET 13b and the constant current source 13a of the control circuit 13 is set to I0, I0 can be expressed by the current formula of the saturation region of the MOSFET as follows.

In addition, in the mathematical expression (3), Vp is the potential of the connection node between the source of the N-type MOSFET 13b and the constant current source 13a, and Vth is the threshold voltage of the N-type MOSFET 13b. Next, based on the mathematical formula (3), the following mathematical formula (4) can be expressed.

In addition, assuming that Vm and Vp are equal, the following mathematical expression (5) can be expressed based on mathematical expression (2) and mathematical expression (4).

[Mathematical formula 5]

Furthermore, based on mathematical formula (5), the following mathematical formula (6) can be expressed.

As shown in the above mathematical formula (6), in the control circuit 13, as the voltage VDD of the external power supply increases, the control supply voltage VEQL increases. Therefore, since the supply voltage VEQL can be raised by raising the voltage VDD of the external power supply, the supply voltage VEQL can be easily controlled.

In addition, as shown in the above mathematical formula (6), in the control circuit 13, the threshold voltage of the N-type MOSFET 13b (which is equal to the threshold voltage Vth of the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20) As Vth increases, the supply voltage VEQL can be controlled to increase. Therefore, since the supply voltage VEQL can be increased as the threshold voltage Vth of the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20 increases, the precharge circuit 20 can be controlled to supply sufficient pressure voltage according to the threshold voltage Vth.

Furthermore, as shown in the above mathematical formula (6), in the control circuit 13, the supply voltage VEQL can be adjusted by adjusting the reference voltage VREF.

In addition, when the supply voltage VEQL output from the boost circuit 11 is smaller than the right side of the mathematical expression (6), a low-level signal en_CLK is output from the comparator 13e. On the other hand, when the supply voltage VEQL output from the boosting circuit 11 is When the right-hand side of equation (6) is greater or equal, a high-level signal en_CLK is output from the comparator 13e.

In addition, the changes in the threshold voltage Vth of the MOSFET generally follow the standard normal distribution as shown in Figure 3. Here, when the standard deviation σ becomes larger than 0, the threshold voltage Vth of the MOSFET included in the standard deviation σ becomes higher than the threshold voltage Vth of the MOSFET of the standard (σ±0). In this case, the saturation current of the MOSFET becomes lower and the response time becomes slower. Therefore, in this embodiment, a MOSFET having a standard deviation σ=+3 is called a low-speed MOSFET. On the other hand, when the standard deviation σ becomes smaller than 0, the threshold voltage Vth of the MOSFET included in the standard deviation σ becomes lower than the threshold voltage Vth of the MOSFET of the standard (σ±0). In this case, the saturation current of the MOSFET becomes higher and the response time becomes faster. Therefore, in this embodiment, a MOSFET with a standard deviation of σ=-3 is called a high-speed MOSFET.

As shown in Figure 4, the supply voltage VEQL of high-speed MOSFET, standard MOSFET and low-speed MOSFET changes in proportion to the voltage VDD of the external power supply. In addition, when the voltage VDD of the external power supply is equal (unchanged), as the threshold voltage Vth decreases (that is, as the MOSFET becomes high-speed), the supply voltage VEQL can be reduced. Therefore, an appropriate pressure voltage can be provided according to the change of the threshold voltage Vth of the MOSFET in the precharge circuit 20 .

As mentioned above, according to the test circuit 10 and the semiconductor memory device for controlling the pressure voltage of this embodiment, due to the voltage VDD of the external power supply and/or the threshold voltage of the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20 vth To control the supply voltage VEQL, even when the threshold voltage Vth of the N-type MOSFETs 21, 22, and 23 changes, sufficient supply can still be provided to the precharge circuit 20 according to the change of the threshold voltage Vth during the burn-in test. voltage.

In addition, according to the test circuit 10 and the semiconductor memory device for controlling the pressure voltage of this embodiment, the supply voltage VEQL is based on the voltage VDD of the external power supply and the threshold voltage Vth of the N-type MOSFETs 21, 22, and 23 of the precharge circuit 20. Therefore, the supply voltage VEQL can be set by controlling the oscillator 12 and the boost circuit 11 so that the precharge circuit 20 that receives the supply voltage VEQL can provide an appropriate pressure voltage.

Furthermore, according to the test circuit 10 for controlling the pressure voltage and the semiconductor memory device of this embodiment, the oscillator 12 and the boost circuit 11 can be controlled based on the voltage VDD of the external power supply and the voltage included in the voltage supply part 20 The threshold voltage Vth of the N-type MOSFETs 21, 22, and 23 sets the supply voltage VEQL.

Furthermore, according to the test circuit 10 and the semiconductor memory device for controlling the pressure voltage of this embodiment, a pair of complementary bit lines BL and /BL can be precharged through the precharge circuit 20 .

Each of the embodiments described above is described to make the present invention easier to understand, and the above description is not intended to limit the present invention. Therefore, each element disclosed in the above embodiments is intended to include all design changes or equivalents that fall within the technical scope of the present invention.

For example, in the above-mentioned embodiment, the case where the test circuit 10 for controlling the pressure voltage is provided in the DRAM has been described as an example. Not limited to this case. For example, the test circuit 10 for controlling the stress voltage can also be provided in SRAM, flash memory or other semiconductor memory devices.

In addition, in the above-mentioned embodiment, although the case where the control circuit 13 includes three N-type MOSFETs 13b, 13c, and 13d is described as an example, the present invention is not limited to this. For example, the control circuit 13 may be configured to replace three N-type MOSFETs 13b, 13c, and 13d with three P-type MOSFETs.

Furthermore, in the above-mentioned embodiment, although the case where the precharge circuit 20 is configured to include three N-type MOSFETs 21, 22, and 23 has been described as an example, the present invention is not limited to this. For example, the precharge circuit 20 may be configured to replace three N-type MOSFETs 21, 22, and 23 with three P-type MOSFETs.

Furthermore, in the above-mentioned embodiment, although the case where the precharge circuit 20 is configured to precharge a pair of complementary bit lines BL and /BL is described as an example, the present invention is not limited thereto. For example, the precharge circuit 20 may also be configured to precharge a pair of word lines or IO lines (local IO lines/main IO lines), etc., or may be configured to precharge adjacent bit lines or adjacent zigzag lines. Yuanxian et al.

In addition, the test circuit 10 for controlling the pressure voltage, the precharge circuit 20 and the control circuit 13 shown in FIG. 2 shown in FIG. 1 are only examples and can be appropriately changed, or a conventional structure or a conventional configuration can be adopted. Various other compositions.

13:Control circuit

13a: Constant current source

13b, 13c, 13d: MOSFET

13e: Comparator

en_CLK:signal

I0, I1: current

VBBSA: reverse bias

VDD: voltage of external power supply

Vm, Vp: potential

VEQL: supply voltage

VREF: reference voltage

VSS: low supply voltage

Claims (9)

A test circuit for controlling pressure voltage, including: a boost circuit that boosts the voltage of an external power supply and generates a supply voltage; an oscillator that generates a clock signal for driving the boost circuit; and a control circuit that is coupled Between the boost circuit and the oscillator, the control circuit includes a first transistor coupled to the supply voltage, and a second transistor coupled to the voltage of the external power supply, the control circuit being configured to A signal for controlling the oscillator is output in the test mode to control a voltage supplied to a precharge circuit including a transistor in the semiconductor memory device in the test mode; wherein the control circuit is based on the voltage of the external power supply, And the threshold voltage of the transistor included in the precharge circuit controls the voltage; wherein the control circuit controls the voltage by controlling the oscillator to set the supply voltage generated by the boost circuit to a specific level. A test circuit for controlling a stress voltage as claimed in claim 1, wherein the precharge circuit is configured to precharge bit lines in a semiconductor memory device. A test circuit for controlling pressure voltage as claimed in claim 1, wherein as the voltage of the external power supply increases, the control circuit controls the voltage increase. A test circuit for controlling a pressure voltage as claimed in claim 1, wherein as the threshold voltage increases, the control circuit controls the voltage to increase. The test circuit for controlling pressure voltage as claimed in claim 1, wherein the control circuit further includes: a constant current source, wherein the first transistor is connected to the supply voltage and the constant current source. between; a third transistor connected between the second transistor and the low power supply voltage; and a comparator including a first input terminal and a second input terminal, the first input terminal connecting the first transistor and the low power supply voltage. The node between the constant current sources, the second input terminal is connected to the node between the second transistor and the third transistor, based on the signals respectively input to the first input terminal and the second input terminal, the output is used to The signal that controls the oscillator. The test circuit for controlling the pressure voltage of claim 1, wherein the first transistor is applied with a reverse bias voltage, and the reverse bias voltage is equal to the reverse bias voltage applied to the transistor of the precharge circuit. . The test circuit for controlling pressure voltage as claimed in claim 1 or 6, wherein the first transistor has the same size as the transistor of the precharge circuit. The test circuit for controlling pressure voltage according to any one of claims 2 to 6, wherein: the precharge circuit includes: a fourth transistor connected to the voltage of the external power supply and the first bit in the semiconductor memory device between the bit lines; the fifth transistor is connected between the voltage of the external power supply and the second bit line in the semiconductor memory device; and the sixth transistor is connected between the first bit line and the second bit line. between bit lines. A semiconductor memory device, including: a test circuit for controlling pressure voltage according to any one of claims 1 to 8; The precharge circuit generates a pressure voltage based on the supply voltage when the semiconductor memory device operates in the test mode; the internal voltage adjustment circuit is configured to receive the external power supply and generate an internal voltage based on the voltage of the external power supply; and the switch , is configured such that one end is connected to the internal voltage adjustment circuit or the test circuit for controlling the pressure voltage, and the other end is connected to the precharge circuit, wherein, when operating in the test mode, the switch is controlled to be connected to the Test circuit for controlling pressure voltage.