TWI829380B - Serialization system and clock generating circuit - Google Patents

Abstract

A serialization system includes a clock channel for generating clock outputs, and a data channel for generating data outputs. The clock channel includes a first serializer configured to convert parallel clocks to serial clocks, and a first flip-flop configured to store the serial clocks to provide the clock outputs. The data channel includes a second serializer configured to convert parallel data to serial data, and a second flip-flop configured to store the serial data to provide the data outputs. A clock generating circuit receives phase-locked clocks, according to which a serialization clock is generated and provided to the first serializer and the second serializer, a lagging clock is generated and provided to the first flip-flop, and a leading clock is generated and provided to the second flip-flop. Sum of a lagging amount of the lagging clock with respect to the serialization clock and a leading amount of the leading clock with respect to the serialization clock is equal to half of a unit interval.

Description

Serialization system and pulse generation circuit

The present invention relates to a communication system, and in particular to a serialization system and a clock generator thereof.

Data transmission between electronic devices usually uses serial communication, which only transmits one bit at a time, thereby achieving a higher transmission rate and saving costs. However, electronic devices usually use parallel communication to transmit multiple bits at the same time. Therefore, before data is transmitted from one electronic device to another, serialization processing must be performed to convert the data from parallel format to serial format.

The clock signal is a very important control signal in the serial communication system. It is generated by the clock signal generator and is used to effectively and correctly control and coordinate the transmission of bits in the communication channel. When the data transfer rate of the serial communication system increases, a skew will occur between the data channel and the clock channel. If the clock is sampled before the data is stable, data transmission errors will occur. In addition, the circuit of the traditional clock signal generator is complex, takes up circuit area and consumes considerable power.

Therefore, there is an urgent need to propose a novel mechanism to solve the many shortcomings of traditional communication systems in terms of high frequency and power consumption.

In view of the above, one purpose of embodiments of the present invention is to provide a serialization system and its clock generator, which can effectively reduce power consumption and cost, and can be suitable for high-frequency serial communication.

According to an embodiment of the present invention, the serialization system includes a clock channel for generating a clock output; and a data channel for outputting a data output. The clock channel includes a first serializer and a first flip-flop. The first serializer is used to convert the parallel clock into a serial clock, and the first flip-flop is used to store the serial clock in sequence to provide a clock output. The data channel includes a second serializer and a second flip-flop. The second serializer is used to convert parallel data into serial data, and the second flip-flop is used to store serial data in sequence to provide data output. The clock generation circuit receives the phase-locked clock, generates a serialization clock to the first serializer and the second serializer, generates a lagging clock to the first flip-flop, and generates a leading clock to the second flip-flop. Countermeasures. The sum of the lag amount of the lagging clock relative to the serialization clock and the lead amount of the leading clock relative to the serialization clock is one-half unit interval.

Figure A shows a block diagram of a serialization system 100 according to an embodiment of the present invention. In this embodiment, the serialization system 100 may include a clock channel 100A and a data channel 100B. Among them, the clock channel 100A generates a differential clock output CLKp/CLKn, and the data channel 100B generates a differential data output Datap/Datan. Figure B shows the timing diagram of clock output CLKp/CLKn and data output Datap/Datan. There is a half unit interval (UI) T/2 between the clock output CLKp/CLKn and the data output Datap/Datan to ensure that before the clock output CLKp/CLKn is triggered, the data output Datap/Datan has reached Stable to avoid the impact of process errors. In this embodiment, the unit interval (UI) T may refer to the transmission time of one bit, which may be half of the system clock cycle.

In this embodiment, the clock channel 100A may include a first serializer 11A for converting the parallel clock D_CLK into a serial clock. The first serializer 11A can be implemented using traditional technology, such as the Figure 2 architecture of "A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS" proposed by Tomas Geurts et al.

According to one of the features of this embodiment, the clock channel 100A may include a first flip-flop 12A (such as a D-type flip-flop) for sequentially storing the serial clock. The serial clock output by the first flip-flop 12A can be processed by a first pre-driver (pre-driver) 13A and a first post-driver (post-driver) 14A to generate clock output CLKp/CLKn. Among them, the first pre-driver 13A (for example, multiple buffers) can be used to increase the driving capability (for example, increase the current), and the first post-driver 14A can be used to convert a single-ended serial clock into a differential clock. Pulse output CLKp/CLKn or/and improve electrostatic discharge (ESD) protection capability.

According to another feature of this embodiment, the clock channel 100A may include a first clock generator 15A, which (self-phase locked loop) receives a phase-locked clock, such as an in-phase phase-locked clock CLKI and a quadrature phase-locked clock. CLKQ (the two are 90 degrees different), thereby generating the serialization clock CLK_S to the first serializer 11A and generating the lagging clock CLK_lag to the first flip-flop 12A. The lagging clock CLK_lag lags behind the serialization clock CLK_S. . In one embodiment, the lagging clock CLK_lag has a lag amount of one quarter unit interval T/4 relative to the serialization clock CLK_S, but is not limited thereto.

In this embodiment, the data channel 100B may include a second serializer 11B (which is similar or identical to the first serializer 11A of the clock channel 100A) for converting the parallel data D_Data into serial data. The data channel 100B may include a second flip-flop 12B (which is similar or identical to the first flip-flop 12A of the clock channel 100A) for sequentially storing serial data. The serial data output by the second flip-flop 12B can be processed by the second pre-driver 13B and the second post-driver 14B (which are similar or identical to the first pre-driver 13A and the first post-driver 14A of the clock channel 100A). , to generate data output Datap/Datan.

The data channel 100B may include a second clock generator 15B, which (self-phase locked loop) receives a phase-locked clock, such as an in-phase locked clock CLKI and a quadrature phase-locked clock CLKQ, thereby generating a serialization clock CLK_S To the serializer 11 and generate a leading clock CLK_lead to the second flip-flop 12B, the leading clock CLK_lead is ahead of the serialization clock CLK_S. In one embodiment, the leading clock CLK_lead has a leading amount of one quarter unit interval T/4 relative to the serialization clock CLK_S, but is not limited thereto. In this embodiment, the sum of the lag amount of the lagging clock CLK_lag relative to the serialization clock CLK_S and the lead amount of the leading clock CLK_lead relative to the serialization clock CLK_S is one-half unit interval T/2 . Thereby, there is a half unit interval T/2 between the clock output CLKp/CLKn and the data output Datap/Datan to ensure that the data output Datap/Datan has reached stability before the clock output CLKp/CLKn is triggered. Avoid the impact caused by process errors. For example, the lagging clock CLK_lag has a lag amount of three-eighths of the unit interval 3T/8, and the leading clock CLK_lead has a lead amount of one-eighth of the unit interval T/8, and the sum of the two is one-half The unit interval is T/2. It is worth noting that the clock generation circuit of this embodiment includes a first clock generator 15A and a second clock generator 15B that are independent of each other and generate a lagging clock CLK_lag to the first flip-flop 12A and a leading clock respectively. The clock CLK_lead is given to the second flip-flop 12B.

The second diagram A shows a detailed block diagram of the first clock generator 15A of the first diagram A, and the second diagram B shows the timing diagram of the corresponding signals of the first clock generator 15A of the second diagram A. In this embodiment, the first clock generator 15A may include a buffer (amplifier) 151A that provides impedance matching and receives the in-phase locked clock CLKI. The first clock generator 15A may include a flip-flop 152A (eg, a D-type flip-flop) that receives the in-phase locked clock CLKI output from the buffer 151A to generate the serialization clock CLK_S. The first clock generator 15A may include an exclusive OR (XOR) gate 153A, which generates a first intermediate clock CLK_AA to the flip-flop 152A according to the in-phase locked clock CLKI and the quadrature phase-locked clock CLKQ. . The first clock generator 15A may include a delayer 154A for delaying the first intermediate clock CLK_AA to generate a second intermediate clock CLK_BB such that the second intermediate clock CLK_BB is synchronized with the serialization clock CLK_S. The first clock generator 15A may include a lagging clock generator 155A to generate a lagging clock CLK_lag.

The third figure A shows a detailed block diagram of the second clock generator 15B of the first figure A, and the third figure B shows the timing diagram of the corresponding signals of the second clock generator 15B of the third figure A. In this embodiment, the second clock generator 15B may include a buffer (amplifier) 151B, a flip-flop 152B, an exclusive OR (XOR) gate 153B, and a delay 154B, whose functions are similar to those of the first clock generator. 15A, no further details will be given. The second clock generator 15B may include a lead clock generator 155B to generate the lead clock CLK_lead.

The fourth figure shows a block diagram of a serialization system 200 according to another embodiment of the present invention. The serialization system 200 (the fourth figure) is similar to the serialization system 100 (the first figure A), and the differences between the two are explained as follows.

In this embodiment, the clock generation circuit of the serialization system 200 may include a single (or integrated) clock generator 16 that (self-phase locked loop) receives a phase-locked clock, such as an in-phase phase-locked clock. CLKI and the quadrature phase-locked clock CLKQ generate the serialization clock CLK_S to the first serializer 11A and the second serializer 11B, generate the lagging clock CLK_lag to the first flip-flop 12A, and generate the leading clock. CLK_lead is given to the second flip-flop 12B. Wherein, the sum of the lag amount of the lagging clock CLK_lag (relative to the serialization clock CLK_S) and the lead amount of the leading clock CLK_lead (relative to the serialization clock CLK_S) is one-half unit interval T/ 2. Thereby, there is a half unit interval T/2 between the clock output CLKp/CLKn and the data output Datap/Datan to ensure that the data output Datap/Datan has reached stability before the clock output CLKp/CLKn is triggered. Avoid the impact caused by process errors.

Figure 5A shows a detailed block diagram of the clock generator 16 of Figure 4, and Figure 5B shows the timing diagram of the corresponding signals of the clock generator 16 of Figure 5A. In this embodiment, the clock generator 16 may include a buffer (amplifier) 161, a flip-flop 162, an exclusive OR (XOR) gate 163, and a delay 164, the functions of which are similar to the first clock generator 15A or The second clock generator 15B will not be described again. The clock generator 16 of this embodiment may include a lagging clock generator 165 to generate a lagging clock CLK_lag, and a leading clock generator 166 to generate a leading clock CLK_lead.

Figure 6A shows the circuit diagram of the lagging clock generator 300A and the timing diagram of the corresponding signals in the first embodiment of the present invention, which can be applied to the lagging clock generator 155A (Figure 2A) and the lagging clock of the previous embodiments. Generator 165 (fifth A).

In this embodiment, the lagging clock generator 300A may include a first reverse selection circuit 301A to output a first output signal “1” according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the first output signal "1" is output. The first reverse selection circuit 301A includes a P-type first transistor P1, a P-type second transistor P2, an N-type first transistor N1, and an N-type second transistor N2, which are connected in series between the power supply and the ground. between. Among them, the P-type second transistor P2 and the N-type first transistor N1 form a reverse circuit, and the P-type first transistor P1 and the N-type second transistor N2 form a selection circuit. Specifically, the gate of the P-type first transistor P1 is connected to the clock signal CLK, the gate of the N-type second transistor N2 is connected to the reverse clock signal CLKB, and the P-type second transistor P2 and the N-type second transistor N2 are connected to the reverse clock signal CLKB. The gate of a transistor N1 is connected to the signal "0", and the drains of the P-type second transistor P2 and the N-type first transistor N1 provide the first output signal "1".

The lagging clock generator 300A may include a second reverse selection circuit 302A to output a second output signal “0” according to the clock signal CLK. Thereby, when the clock signal CLK is at a high level, the first output signal "0" is output. The second reverse selection circuit 302A includes a P-type third transistor P3, a P-type fourth transistor P4, an N-type third transistor N3, and an N-type fourth transistor N4, which are connected in series between the power supply and the ground. between. Among them, the P-type fourth transistor P4 and the N-type third transistor N3 form a reverse circuit, and the P-type third transistor P3 and the N-type fourth transistor N4 form a selection circuit. Specifically, the gate of the P-type third transistor P3 is connected to the reverse clock signal CLKB, the gate of the N-type fourth transistor N4 is connected to the clock signal CLK, and the P-type fourth transistor P4 and the N-type third transistor N4 are connected to the reverse clock signal CLKB. The gate of the three transistors N3 is connected to the signal "1", and the drains of the P-type fourth transistor P4 and the N-type third transistor N3 provide the second output signal "0".

The lagging clock generator 300A may include a first latch for latching the lagging clock signal Q generated by the lagging clock generator 300A. The first latch may include a third reverse selection circuit 303A to output a third output signal according to the reset signal RST. Thereby, when the reset signal RST is at a high level, the reverse backward clock signal Q is output as the third output signal. The third reverse selection circuit 303A includes a P-type fifth transistor P5, a P-type sixth transistor P6, an N-type fifth transistor N5, and an N-type sixth transistor N6, which are connected in series between the power supply and the ground. between. Specifically, the gate of the P-type fifth transistor P5 is connected to the reverse reset signal RSTB, the gate of the N-type sixth transistor N6 is connected to the reset signal RST, and the P-type sixth transistor P6 is connected to the N-type sixth transistor N6. The drain of the fifth transistor N5 provides the third output signal, and the lagging clock signal Q is fed back to the gates of the P-type sixth transistor P6 and the N-type fifth transistor N5. The lagging clock generator 300A may include a first multiplexer (MUX) 304A that passes the third output signal according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the third output signal is used as the output signal of the first latch.

The lagging clock generator 300A may include a first NOT gate 305A, which receives the first output signal, the second output signal and the first latch (ie, the third NOT select circuit 303A and the first multiplexer The output signal of 304A) is used to generate the lagging clock signal Q.

Figure 6B shows the circuit diagram and the timing diagram of the corresponding signals of the leading clock generator 400A of the first embodiment of the present invention. It can be used with the lagging clock generator 300A of Figure 6A and is suitable for the leading clock of the previous embodiment. Generator 155B (third diagram A), leading clock generator 166 (fifth diagram A). The leading clock generator 400A (sixth figure B) is similar to the lagging clock generator 300A (sixth figure A), and the differences between the two are explained as follows.

In this embodiment, the leading clock generator 400A may include a fourth reverse selection circuit 301B to output a fourth output signal “0” according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the fourth output signal "0" is output.

The leading clock generator 400A may include a fifth reverse selection circuit 302B to output a fifth output signal “1” according to the clock signal CLK. Thereby, when the clock signal CLK is at a high level, the fifth output signal "1" is output.

The leading clock generator 400A may include a second latch for latching the leading clock signal R generated by the leading clock generator 400A. The second latch may include a sixth reverse selection circuit 303B to output a sixth output signal according to the reset signal RST. Thereby, when the reset signal RST is at a high level, the reverse leading clock signal R is output as the sixth output signal. The leading clock generator 400A may include a second multiplexer (MUX) 304B that passes the sixth output signal according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the sixth output signal is used as the output signal of the second latch.

The lead clock generator 400A may include a second NOT gate 305B that receives the fourth output signal, the fifth output signal and the second latch (ie, the sixth NOT select circuit 303B and the second multiplexer The output signal of 304B) is used to generate the leading clock signal R.

Figure 7A shows a circuit diagram of the lagging clock generator 300B of the second embodiment of the present invention, which can be applied to the lagging clock generator 155A (second Figure A) and the lagging clock generator 165 (fifth figure) of the previous embodiments. Figure A).

In this embodiment, the lagging clock generator 300B may include a first multiplexer 306A that generates a first output signal “0” according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the first output signal "0" is generated. The lagging clock generator 300B may include a second multiplexer 307A that generates a second output signal “1” according to the clock signal CLKB. Thereby, when the clock signal CLK is at a high level, the second output signal "1" is generated.

The lagging clock generator 300B may include a first latch for latching the first node signal M. The first latch may include a first reverse selection circuit 308A to output a third output signal according to the reset signal RST. Thereby, when the reset signal RST is at a high level, the inverted first node signal M is output as the third output signal. The first reverse selection circuit 308A includes a P-type fifth transistor P5, a P-type sixth transistor P6, an N-type fifth transistor N5, and an N-type sixth transistor N6, which are connected in series between the power supply and the ground. between. Specifically, the gate of the P-type fifth transistor P5 is connected to the reverse reset signal RSTB, the gate of the N-type sixth transistor N6 is connected to the reset signal RST, and the P-type sixth transistor P6 is connected to the N-type sixth transistor N6. The drain of the five-type transistor N5 provides the third output signal, and the first node signal M is fed back to the gates of the P-type sixth transistor P6 and the N-type fifth transistor N5. The lagging clock generator 300B may include a third multiplexer (MUX) 309A that passes the third output signal according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the third output signal is used as the output signal of the first latch.

The lagging clock generator 300B may include a first NOT gate 310A that receives the first output signal, the second output signal, and the first latch (ie, the first NOT select circuit 308A and the third multiplexer The output signal of 309A) is used to generate the first node signal M. The lagging clock generator 300B may include a fourth multiplexer 311A for passing the first node signal M to generate a fourth output signal. The lagging clock generator 300B may include a second anti-gate 312A, which receives the fourth output signal of the fourth multiplexer 311A and generates the lagging clock signal Q accordingly.

Figure 7B shows a circuit diagram of the leading clock generator 400B of the second embodiment of the present invention, which can be used with the lagging clock generator 300B of Figure 7A and is suitable for the leading clock generator 155B (third) of the previous embodiment. A), the leading clock generator 166 (fifth A). The leading clock generator 400B (seventh figure B) is similar to the lagging clock generator 300A (seventh figure A), and the differences between the two are explained as follows.

In this embodiment, the leading clock generator 400B may include a fifth multiplexer 306B that generates a fifth output signal “1” according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the fifth output signal "1" is generated. The leading clock generator 400B may include a sixth multiplexer 307B that generates a sixth output signal “0” according to the clock signal CLKB. Thereby, when the clock signal CLK is at a high level, the sixth output signal "0" is generated.

The leading clock generator 400B may include a second latch for latching the second node signal N. The second latch may include a second reverse selection circuit 308B to output a seventh output signal according to the reset signal RST. Thereby, when the reset signal RST is at a high level, the inverted second node signal N is output as the seventh output signal. The leading clock generator 400B may include a third multiplexer (MUX) 309B that passes the seventh output signal according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the seventh output signal is used as the output signal of the second latch.

The lead clock generator 400B may include a third NOT gate 310B that receives the fifth output signal, the sixth output signal and the second latch (ie, the second NOT select circuit 308B and the seventh multiplexer 309B), thereby generating the second node signal N. The lagging clock generator 300B may include an eighth multiplexer 311B for passing the second node signal N. The leading clock generator 400B may include a fourth reverse gate 312B, which receives the output signal of the eighth multiplexer 311B and generates the leading clock signal R accordingly.

Figure 8A shows a circuit diagram of the lagging clock generator 300C of the third embodiment of the present invention, which can be applied to the lagging clock generator 155A (second Figure A) and the lagging clock generator 165 (fifth) of the previous embodiments. Figure A). The lagging clock generator 300C (the eighth figure A) is similar to the lagging clock generator 300B (the seventh figure A), and the differences between the two are explained as follows.

In this embodiment, the fifth reverse gate 313A is used instead of the first reverse selection circuit 308A to receive the first node signal M and thereby generate the reversed first node signal M as the third output signal.

Figure 8B shows a circuit diagram of the leading clock generator 400C of the third embodiment of the present invention, which can be used with the lagging clock generator 300C of Figure 8A and is suitable for the leading clock generator 155B (third embodiment) of the previous embodiment. A), the leading clock generator 166 (fifth A). The leading clock generator 400C (the eighth figure B) is similar to the lagging clock generator 300C (the seventh figure A), and the differences between the two are explained as follows.

In this embodiment, the sixth reverse gate 313B is used to replace the second reverse selection circuit 308B to receive the second node signal N and thereby generate the reverse second node signal N as the third output signal.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patentable scope of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention shall be included in the following. Within the scope of patent application.

100: Serialization system 200: Serialization system 100A: Clock channel 100B: Data channel 11A: First serializer 11B: Second serializer 12A: The first flip-flop 12B: Second flip-flop 13A: First pre-driver 13B: Second pre-driver 14A: First rear driver 14B: Second rear drive 15A: First clock generator 151A:Buffer 152A: flip-flop 153A: Mutual exclusion or gate 154A: Delay 155A: Lagging clock generator 15B: Second clock generator 151B:Buffer 152B: Flip-flop 153B: Mutual exclusion or gate 154B: Delay 155B: Leading clock generator 16: Clock generator 161:Buffer 162: flip-flop 163: Mutual exclusion or gate 164:Delayer 165: Lagging clock generator 166:Advanced clock generator 300A: Lagging clock generator 300B: Lagging clock generator 300C: Lagging clock generator 400A: Leading clock generator 400B: Leading clock generator 400C: Leading clock generator 301A: First reverse selection circuit 301B: The fourth reverse selection circuit 302A: Second reverse selection circuit 302B: The fifth reverse selection circuit 303A: The third reverse selection circuit 303B: The sixth reverse selection circuit 304A: First multiplexer 304B: Second multiplexer 305A: First reverse gate 305B: Second reverse gate 306A: First multiplexer 306B: Fifth multiplexer 307A: Second multiplexer 307B: Sixth multiplexer 308A: First reverse selection circuit 308B: Second reverse selection circuit 309A: The third multiplexer 309B: The third multiplexer 310A: First reverse gate 310B: The third reverse gate 311A: The fourth multiplexer 311B: Eighth multiplexer 312A: Second reverse gate 312B: The fourth reverse gate 313A: The fifth reverse gate 313B: The sixth reverse gate T: unit interval D_CLK: parallel clock D_Data: parallel data CLKI: phase-locked clock CLKQ: quadrature phase locked clock CLK_S: Serialization clock CLK_lag: lagging clock CLK_lead: leading clock CLKp, CLKn: clock output Datap, Datan: data output CLK_AA: first intermediate clock CLK_BB: second intermediate clock CLK: clock signal CLKB: reverse clock signal RST: reset signal RSTB: reverse reset signal Q: Lagging clock signal R: leading clock signal M: first node signal N: second node signal P1: P-type first transistor P2: P-type second transistor P3: P-type third transistor P4: P-type fourth transistor P5: P-type fifth transistor P6: P-type sixth transistor N1: N-type first transistor N2: N-type second transistor N3: N-type third transistor N4: N-type fourth transistor N5: N-type fifth transistor N6: N-type sixth transistor VDD: power supply GND: ground

Figure A shows a block diagram of a serialization system according to an embodiment of the present invention. Figure B shows the timing diagram of clock output and data output. Figure 2A shows a detailed block diagram of the first clock generator of Figure 1A. Figure 2B shows the timing diagram of the corresponding signals of the first clock generator of Figure 2A. Figure 3A shows a detailed block diagram of the second clock generator of Figure 1A. Figure 3B shows the timing diagram of the corresponding signals of the second clock generator of Figure 3A. The fourth figure shows a block diagram of a serialization system according to another embodiment of the present invention. Figure 5A shows a detailed block diagram of the clock generator of Figure 4. Figure 5B shows the timing diagram of the corresponding signals of the clock generator of Figure 5A. Figure 6A shows the circuit diagram of the lagging clock generator and the timing diagram of the corresponding signals according to the first embodiment of the present invention. Figure 6B shows the circuit diagram of the leading clock generator and the timing diagram of the corresponding signals according to the first embodiment of the present invention. Figure 7A shows a circuit diagram of a lagging clock generator according to the second embodiment of the present invention. Figure 7B shows a circuit diagram of the leading clock generator according to the second embodiment of the present invention. Figure 8A shows a circuit diagram of a lagging clock generator according to the third embodiment of the present invention. Figure 8B shows a circuit diagram of the leading clock generator according to the third embodiment of the present invention.

100: Serialization system

100A: Clock channel

100B: Data channel

11A: First serializer

11B: Second serializer

12A: The first flip-flop

12B: Second flip-flop

13A: First pre-driver

13B: Second pre-driver

14A: First rear driver

14B: Second rear drive

15A: First clock generator

15B: Second clock generator

D_CLK: parallel clock

D_Data: parallel data

CLKI: phase-locked clock

CLKQ: quadrature phase locked clock

CLK_S: Serialization clock

CLK_lag: lagging clock

CLK_lead: leading clock

CLKp, CLKn: clock output

Datap, Datan: data output

Claims (19)

A serialization system includes: a clock channel for generating a clock output, the clock channel includes: a first serializer for converting a parallel clock into a serial clock; a first forward and reverse A device for sequentially storing the serial clock to provide the clock output; a data channel for outputting data, the data channel including: a second serializer for converting parallel data into serial serial data; a second flip-flop for sequentially storing the serial data to provide the data output; a clock generation circuit that receives a phase-locked clock and generates a serialization clock to the first serial data converter and the second serializer, generate a lagging clock to the first flip-flop, and generate a leading clock to the second flip-flop; wherein the lagging clock is lagging relative to the serialization clock The sum of the lead amount of the lead clock relative to the serialized clock is one-half unit interval. The serialization system of claim 1, wherein the clock channel further includes: a first pre-driver that receives the serial clock from the first flip-flop to increase driving capability; and a first post-driver, Used to convert single-ended serial clock to differential clock output. As claimed in claim 1, the serialization system further includes: a second pre-driver for receiving the serial data from the second flip-flop to increase drive capability; and a second post-driver for Convert single-ended serial data to differential data output. The serialization system of claim 1, wherein the clock generation circuit includes: a first clock generator, generates the serialization clock to the first serializer, and generates the lagging clock to the first a flip-flop; and a second clock generator that generates the serialization clock to the second serializer and generates the leading clock to the second flip-flop; The first clock generator and the second clock generator are independent of each other. Such as the serialization system of claim 4, wherein the first clock generator includes: a buffer that provides impedance matching and receives the in-phase locked clock; a flip-flop that receives the in-phase locked clock output by the buffer a clock to generate the serialized clock; a mutex or gate to generate a first intermediate clock to the flip-flop according to the in-phase locked clock and the quadrature phase-locked clock; a delay to Delaying the first intermediate clock to generate a second intermediate clock so that the second intermediate clock is synchronized with the serialization clock; and a lagging clock generator to generate the lagging clock. Such as the serialization system of claim 4, wherein the second clock generator includes: a buffer that provides impedance matching and receives the in-phase locked clock; a flip-flop that receives the in-phase locked clock output by the buffer a clock to generate the serialized clock; a mutex or gate to generate a first intermediate clock to the flip-flop according to the in-phase locked clock and the quadrature phase-locked clock; a delay to Delaying the first intermediate clock to generate a second intermediate clock so that the second intermediate clock is synchronized with the serialization clock; and a leading clock generator to generate the leading clock. The serialization system of claim 1, wherein the clock generation circuit includes: a single clock generator, which generates the serialization clock to the first serializer and the second serializer, and generates the lagging clock. The leading clock pulse is supplied to the first flip-flop, and the leading clock pulse is supplied to the second flip-flop. The serialization system of claim 7, wherein the clock generator includes: a buffer that provides impedance matching and receives the in-phase phase-locked clock; A flip-flop receives the in-phase locked clock pulse output from the buffer to generate the serialization clock; a mutual exclusive OR gate generates the first phase-locked clock pulse based on the in-phase locked clock pulse and the quadrature phase-locked clock pulse. An intermediate clock is supplied to the flip-flop; a delayer is used to delay the first intermediate clock to generate a second intermediate clock so that the second intermediate clock is synchronized with the serialization clock; a lagging clock a generator that generates the lagging clock to the first flip-flop; and a leading clock generator that generates the leading clock to the second flip-flop. A clock generation circuit includes: a lagging clock generator, which generates a lagging clock signal to a first flip-flop of a clock channel according to the clock signal, wherein the clock channel includes a first serializer to Convert the parallel clock to the serial clock; and the first flip-flop is used to store the serial clock in sequence to provide the clock output; and a leading clock generator according to the clock signal A second flip-flop for generating an advanced clock signal to a data channel, wherein the data channel includes a second serializer for converting parallel data into serial data; and the second flip-flop for sequentially The serial data is stored to provide the data output, wherein the sum of the lagging amount of the lagging clock signal and the leading amount of the leading clock signal is one-half unit interval. The clock generation circuit of claim 9, wherein the lagging clock generator includes: a first reverse selection circuit that outputs a first output signal “1” according to the reverse clock signal; a second reverse selection circuit , to output a second output signal "0" according to the clock signal; a first latch to lock the lagging clock signal; and a first reverse gate to receive the first output signal and the second The output signal and the output signal of the first latch are used to generate the lagging clock signal. For example, the clock generation circuit of claim 10, wherein the first latch includes: A third reverse selection circuit outputs a third output signal according to the reset signal; and a first multiplexer passes the third output signal according to the reverse clock signal. The clock generation circuit of claim 10, wherein the leading clock generator includes: a fourth reverse selection circuit that outputs a fourth output signal "0" according to the reverse clock signal; a fifth reverse selection circuit a circuit to output a fifth output signal "1" according to the clock signal; a second latch to latch the leading clock signal; and a second reverse gate to receive the fourth output signal and the third The five output signals and the output signal of the second latch are used to generate the leading clock signal. The clock generation circuit of claim 12, wherein the second latch includes: a sixth reverse selection circuit to output a sixth output signal according to the reset signal; and a second multiplexer to output a sixth output signal according to the reverse selection circuit. The clock signal passes through the sixth output signal. The clock generation circuit of claim 9, wherein the lagging clock generator includes: a first multiplexer to generate the first output signal "0" according to the reverse clock signal; a second multiplexer to generate the first output signal "0" according to the reverse clock signal; The clock signal is used to generate a second output signal "1"; a first latch is used to lock the first node signal; a first reverse gate is used to receive the first output signal, the second output signal and the The output signal of the first latch is used to generate the first node signal; a fourth multiplexer is used to pass the first node signal to generate the fourth output signal; and a second reverse gate is used to receive the A fourth output signal is used to generate the lagging clock signal. The clock generation circuit of claim 14, wherein the first latch includes: a first reverse selection circuit to output a third output signal according to the reset signal; and a third multiplexer to output a third output signal according to the reverse selection circuit. The clock signal passes through the third output signal. The clock generation circuit of claim 14, wherein the first latch includes: a fifth reverse gate that receives the first node signal and generates an inverse first node signal as a third output signal; and A third multiplexer passes the third output signal according to the reverse clock signal. The clock generation circuit of claim 14, wherein the leading clock generator includes: a fifth multiplexer to generate a fifth output signal "1" according to the reverse clock signal; a sixth multiplexer according to The clock signal is used to generate the sixth output signal "0"; a second latch is used to lock the second node signal; a third reverse gate is used to receive the fifth output signal, the sixth output signal and the The output signal of the second latch is used to generate the second node signal; an eighth multiplexer is used to pass the second node signal; and a fourth reverse gate is used to receive the output of the eighth multiplexer. signal, based on which the advanced clock signal is generated. The clock generation circuit of claim 17, wherein the second latch includes: a second reverse selection circuit to output the seventh output signal according to the reset signal; and a third multiplexer to output the seventh output signal according to the reverse clock signal. pulse signal to pass through the seventh output signal. The clock generation circuit of claim 17, wherein the second latch includes: a sixth reverse gate that receives the second node signal and generates an inverted second node signal as a seventh output signal; and A third multiplexer passes the seventh output signal according to the reverse clock signal.

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