TW202416675A - Serialization system and clock generating circuit - Google Patents

Abstract

A serialization system includes a clock channel for generating clock outputs, and a data channel for generating data outputs. The clock channel includes a first serializer configured to convert parallel clocks to serial clocks, and a first flip-flop configured to store the serial clocks to provide the clock outputs. The data channel includes a second serializer configured to convert parallel data to serial data, and a second flip-flop configured to store the serial data to provide the data outputs. A clock generating circuit receives phase-locked clocks, according to which a serialization clock is generated and provided to the first serializer and the second serializer, a lagging clock is generated and provided to the first flip-flop, and a leading clock is generated and provided to the second flip-flop. Sum of a lagging amount of the lagging clock with respect to the serialization clock and a leading amount of the leading clock with respect to the serialization clock is equal to half of a unit interval.

Description

Serial system clock generation circuit

The present invention relates to a communication system, and more particularly to a serialization system and a clock generator thereof.

Data transmission between electronic devices usually adopts serial communication, which only transmits one bit at a time, so as to achieve a higher transmission rate and save costs. However, electronic devices usually use parallel communication inside, which transmits multiple bits at the same time. Therefore, before data is transmitted from one electronic device to another, it must be serialized to convert the data from parallel format to serial format.

The clock signal is a very important control signal in the serial communication system. It is generated by the clock signal generator to effectively and correctly control the transmission of the coordination bits in the communication channel. When the data transmission rate of the serial communication system increases, a skew will occur between the data channel and the clock channel. If the clock is sampled before the data is stable, data transmission errors will occur. In addition, the circuit of the traditional clock signal generator is complex, occupies the circuit area and consumes a lot of power.

Therefore, it is urgent to propose a novel mechanism to solve the many deficiencies of traditional communication systems in terms of high frequency and power consumption.

In view of the above, one of the purposes of the embodiments of the present invention is to provide a serial system and a clock generator thereof, which can effectively reduce power consumption and cost and can be applicable to high-frequency serial communication.

According to an embodiment of the present invention, a serialization system includes a clock channel for generating a clock output and a data channel for outputting data output. The clock channel includes a first serializer and a first flip-flop. The first serializer is used to convert a parallel clock into a serial clock, and the first flip-flop is used to store the serial clock in sequence to provide a clock output. The data channel includes a second serializer and a second flip-flop. The second serializer is used to convert parallel data into serial data, and the second flip-flop is used to store the serial data in sequence to provide data output. The clock generation circuit receives a phase-locked clock, and generates a serialization clock to the first serializer and the second serializer, generates a lagging clock to the first flip-flop, and generates an advanced clock to the second flip-flop. The sum of the amount by which the lagging clock pulse lags behind the serialization clock pulse and the amount by which the leading clock pulse leads the serialization clock pulse equals half a unit interval.

FIG. 1A shows a block diagram of a serialization system 100 of an embodiment of the present invention. In this embodiment, the serialization system 100 may include a clock channel 100A and a data channel 100B. The clock channel 100A generates a differential clock output CLKp/CLKn, and the data channel 100B generates a differential data output Datap/Datan. FIG. 1B shows a timing diagram of the clock output CLKp/CLKn and the data output Datap/Datan. There is a unit interval (UI) T/2 between the clock output CLKp/CLKn and the data output Datap/Datan to ensure that the data output Datap/Datan has reached stability before the clock output CLKp/CLKn is triggered, so as to avoid the influence caused by process errors. In this embodiment, the unit interval (UI) T may refer to the transmission time of one bit, which may be half of the system clock cycle.

In this embodiment, the clock channel 100A may include a first serializer 11A for converting the parallel clock D_CLK into a serial clock. The first serializer 11A may be implemented using conventional technology, such as the architecture of FIG. 2 of “A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS” proposed by Tomas Geurts et al.

According to one of the features of the present embodiment, the clock channel 100A may include a first flip-flop 12A (e.g., a D-type flip-flop) for sequentially storing the serial clock. The serial clock output by the first flip-flop 12A may be processed by a first pre-driver 13A and a first post-driver 14A to generate a clock output CLKp/CLKn. The first pre-driver 13A (e.g., a plurality of buffers) may be used to increase the driving capability (e.g., increase the current), and the first post-driver 14A may be used to convert the single-ended serial clock into a differential clock output CLKp/CLKn or/and enhance the electrostatic discharge (ESD) protection capability.

According to another feature of the present embodiment, the clock channel 100A may include a first clock generator 15A, which receives a phase-locked clock (from a phase-locked loop), such as an in-phase phase-locked clock CLKI and a quadrature phase-locked clock CLKQ (the two phases are 90 degrees apart), and generates a serialization clock CLK_S for the first serializer 11A and a lag clock CLK_lag for the first flip-flop 12A, wherein the lag clock CLK_lag lags behind the serialization clock CLK_S. In one embodiment, the lag clock CLK_lag has a lag of one quarter unit interval T/4 relative to the serialization clock CLK_S, but is not limited thereto.

In this embodiment, the data channel 100B may include a second serializer 11B (similar to or the same as the first serializer 11A of the clock channel 100A) for converting the parallel data D_Data into serial data. The data channel 100B may include a second flip-flop 12B (similar to or the same as the first flip-flop 12A of the clock channel 100A) for sequentially storing the serial data. The serial data output by the second flip-flop 12B may be processed by a second pre-driver 13B and a second post-driver 14B (similar to or the same as the first pre-driver 13A and the first post-driver 14A of the clock channel 100A) to generate data output Datap/Datan.

The data channel 100B may include a second clock generator 15B, which receives a phase-locked clock (from a phase-locked loop), such as an in-phase phase-locked clock CLKI and a quadrature phase-locked clock CLKQ, and generates a serialization clock CLK_S for the serializer 11 and generates a lead clock CLK_lead for the second flip-flop 12B, the lead clock CLK_lead being ahead of the serialization clock CLK_S. In one embodiment, the lead clock CLK_lead has a lead amount of one quarter of a unit interval T/4 relative to the serialization clock CLK_S, but is not limited thereto. In this embodiment, the sum of the lag amount of the lag clock CLK_lag relative to the serialization clock CLK_S and the lead amount of the lead clock CLK_lead relative to the serialization clock CLK_S is half a unit interval T/2. Thus, there is a half unit interval T/2 between the clock output CLKp/CLKn and the data output Datap/Datan to ensure that the data output Datap/Datan has reached stability before the clock output CLKp/CLKn is triggered, thereby avoiding the impact caused by process errors. For example, the lagging clock CLK_lag has a lag of three eighths of the unit interval 3T/8, and the leading clock CLK_lead has a lead of one eighth of the unit interval T/8, and the sum of the two is one half of the unit interval T/2. It is worth noting that the clock generation circuit of this embodiment includes a first clock generator 15A and a second clock generator 15B which are independent of each other, and respectively generate the lagging clock CLK_lag for the first flip-flop 12A and the leading clock CLK_lead for the second flip-flop 12B.

FIG. 2A shows a detailed block diagram of the first clock generator 15A of FIG. 1A, and FIG. 2B shows a timing diagram of the corresponding signal of the first clock generator 15A of FIG. 2A. In this embodiment, the first clock generator 15A may include a buffer (amplifier) 151A, which provides impedance matching and receives the in-phase phase-locked clock CLKI. The first clock generator 15A may include a flip-flop 152A (e.g., a D-type flip-flop), which receives the in-phase phase-locked clock CLKI output by the buffer 151A to generate a serialized clock CLK_S. The first clock generator 15A may include an exclusive OR (XOR) gate 153A, which generates a first intermediate clock CLK_AA to the flip-flop 152A according to the in-phase phase-locked clock CLKI and the quadrature phase-locked clock CLKQ. The first clock generator 15A may include a delayer 154A, which is used to delay the first intermediate clock CLK_AA to generate a second intermediate clock CLK_BB, so that the second intermediate clock CLK_BB is synchronized with the serialized clock CLK_S. The first clock generator 15A may include a lag clock generator 155A to generate a lag clock CLK_lag.

FIG. 3A shows a detailed block diagram of the second clock generator 15B of FIG. 1A, and FIG. 3B shows a timing diagram of the corresponding signal of the second clock generator 15B of FIG. 3A. In this embodiment, the second clock generator 15B may include a buffer (amplifier) 151B, a flip-flop 152B, an exclusive OR (XOR) gate 153B, and a delay 154B, and its functions are similar to those of the first clock generator 15A, which will not be described in detail. The second clock generator 15B may include an advance clock generator 155B to generate an advance clock CLK_lead.

FIG. 4 is a block diagram of a serialization system 200 according to another embodiment of the present invention. The serialization system 200 (FIG. 4) is similar to the serialization system 100 (FIG. 1A), and the differences between the two are described as follows.

In this embodiment, the clock generation circuit of the serialization system 200 may include a single (or integrated) clock generator 16, which receives (from a phase-locked loop) a phase-locked clock, such as an in-phase phase-locked clock CLKI and a quadrature phase-locked clock CLKQ, and generates a serialization clock CLK_S for the first serializer 11A and the second serializer 11B, generates a lag clock CLK_lag for the first flip-flop 12A, and generates a lead clock CLK_lead for the second flip-flop 12B. The sum of the lag amount of the lag clock CLK_lag (relative to the serialization clock CLK_S) and the lead amount of the lead clock CLK_lead (relative to the serialization clock CLK_S) is half a unit interval T/2. Thereby, there is a half unit interval T/2 between the clock output CLKp/CLKn and the data output Datap/Datan to ensure that the data output Datap/Datan has reached stability before the clock output CLKp/CLKn is triggered, thereby avoiding the impact caused by process errors.

FIG. 5A shows a detailed block diagram of the clock generator 16 of FIG. 4, and FIG. 5B shows a timing diagram of the corresponding signal of the clock generator 16 of FIG. 5A. In this embodiment, the clock generator 16 may include a buffer (amplifier) 161, a flip-flop 162, an exclusive OR (XOR) gate 163, and a delay 164, whose functions are similar to those of the first clock generator 15A or the second clock generator 15B, and will not be described in detail. The clock generator 16 of this embodiment may include a lagging clock generator 165 to generate a lagging clock CLK_lag, and an advancing clock generator 166 to generate a leading clock CLK_lead.

FIG. 6A shows a circuit diagram of the delayed clock generator 300A of the first embodiment of the present invention and a timing diagram of corresponding signals, which can be applied to the delayed clock generator 155A (FIG. 2A) and the delayed clock generator 165 (FIG. 5A) of the aforementioned embodiments.

In this embodiment, the lagging clock generator 300A may include a first reverse selection circuit 301A, which outputs a first output signal "1" according to the reverse clock signal CLKB. Thus, when the reverse clock signal CLKB is at a high level, the first output signal "1" is output. The first reverse selection circuit 301A includes a P-type first transistor P1, a P-type second transistor P2, an N-type first transistor N1, and an N-type second transistor N2, which are sequentially connected in series between a power source and a ground. Among them, the P-type second transistor P2 and the N-type first transistor N1 form a reverse circuit, and the P-type first transistor P1 and the N-type second transistor N2 form a selection circuit. In detail, the gate of the P-type first transistor P1 is connected to the clock signal CLK, the gate of the N-type second transistor N2 is connected to the reverse clock signal CLKB, the gates of the P-type second transistor P2 and the N-type first transistor N1 are connected to the signal "0", and the drains of the P-type second transistor P2 and the N-type first transistor N1 provide the first output signal "1".

The lagging clock generator 300A may include a second reverse selection circuit 302A, which outputs a second output signal "0" according to the clock signal CLK. Thus, when the clock signal CLK is at a high level, the first output signal "0" is output. The second reverse selection circuit 302A includes a P-type third transistor P3, a P-type fourth transistor P4, an N-type third transistor N3, and an N-type fourth transistor N4, which are connected in series between a power source and a ground in sequence. Among them, the P-type fourth transistor P4 and the N-type third transistor N3 form a reverse circuit, and the P-type third transistor P3 and the N-type fourth transistor N4 form a selection circuit. In detail, the gate of the P-type third transistor P3 is connected to the reverse clock signal CLKB, the gate of the N-type fourth transistor N4 is connected to the clock signal CLK, the gates of the P-type fourth transistor P4 and the N-type third transistor N3 are connected to the signal "1", and the drains of the P-type fourth transistor P4 and the N-type third transistor N3 provide the second output signal "0".

The lagging clock generator 300A may include a first latch for latching the lagging clock signal Q generated by the lagging clock generator 300A. The first latch may include a third reverse selection circuit 303A for outputting a third output signal according to the reset signal RST. Thus, when the reset signal RST is at a high level, the reverse lagging clock signal Q is output as the third output signal. The third reverse selection circuit 303A includes a P-type fifth transistor P5, a P-type sixth transistor P6, an N-type fifth transistor N5, and an N-type sixth transistor N6, which are connected in series between the power supply and the ground in sequence. In detail, the gate of the P-type fifth transistor P5 is connected to the reverse reset signal RSTB, the gate of the N-type sixth transistor N6 is connected to the reset signal RST, the drains of the P-type sixth transistor P6 and the N-type fifth transistor N5 provide the third output signal, and the lagging clock signal Q is fed back to the gates of the P-type sixth transistor P6 and the N-type fifth transistor N5. The lagging clock generator 300A may include a first multiplexer (MUX) 304A, which passes the third output signal according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the third output signal is passed as the output signal of the first latch.

The delayed clock generator 300A may include a first NOT gate 305A, which receives the first output signal, the second output signal and the output signal of the first latch (ie, the third reverse selection circuit 303A and the first multiplexer 304A) to generate a delayed clock signal Q.

FIG. 6B shows the circuit diagram of the advanced clock generator 400A of the first embodiment of the present invention and the timing diagram of the corresponding signal, which can be used with the delayed clock generator 300A of FIG. 6A, and is applicable to the advanced clock generator 155B (FIG. 3A) and the advanced clock generator 166 (FIG. 5A) of the aforementioned embodiments. The advanced clock generator 400A (FIG. 6B) is similar to the delayed clock generator 300A (FIG. 6A), and the difference between the two is explained as follows.

In this embodiment, the advanced clock generator 400A may include a fourth reverse selection circuit 301B to output a fourth output signal "0" according to the reverse clock signal CLKB. Thus, when the reverse clock signal CLKB is at a high level, the fourth output signal "0" is output.

The advanced clock generator 400A may include a fifth reverse selection circuit 302B, which outputs a fifth output signal "1" according to the clock signal CLK. Thus, when the clock signal CLK is at a high level, the fifth output signal "1" is output.

The advance clock generator 400A may include a second latch for latching the advance clock signal R generated by the advance clock generator 400A. The second latch may include a sixth reverse selection circuit 303B for outputting a sixth output signal according to the reset signal RST. Thus, when the reset signal RST is at a high level, the reverse advance clock signal R is output as the sixth output signal. The advance clock generator 400A may include a second multiplexer (MUX) 304B for passing the sixth output signal according to the reverse clock signal CLKB. Thus, when the reverse clock signal CLKB is at a high level, the sixth output signal is passed as the output signal of the second latch.

The advance clock generator 400A may include a second NOT gate 305B, which receives the fourth output signal, the fifth output signal and the output signal of the second latch (ie, the sixth reverse selection circuit 303B and the second multiplexer 304B) to generate the advance clock signal R.

FIG. 7A shows a circuit diagram of a delayed clock generator 300B of the second embodiment of the present invention, which can be applied to the delayed clock generator 155A (FIG. 2A) and the delayed clock generator 165 (FIG. 5A) of the aforementioned embodiments.

In this embodiment, the lagging clock generator 300B may include a first multiplexer 306A, which generates a first output signal "0" according to the reverse clock signal CLKB. Thus, when the reverse clock signal CLKB is at a high level, the first output signal "0" is generated. The lagging clock generator 300B may include a second multiplexer 307A, which generates a second output signal "1" according to the clock signal CLKB. Thus, when the clock signal CLK is at a high level, the second output signal "1" is generated.

The lagging clock generator 300B may include a first latch for latching the first node signal M. The first latch may include a first reverse selection circuit 308A for outputting the third output signal according to the reset signal RST. Thus, when the reset signal RST is at a high level, the reverse first node signal M is output as the third output signal. The first reverse selection circuit 308A includes a P-type fifth transistor P5, a P-type sixth transistor P6, an N-type fifth transistor N5, and an N-type sixth transistor N6, which are connected in series between the power supply and the ground in sequence. In detail, the gate of the P-type fifth transistor P5 is connected to the reverse reset signal RSTB, the gate of the N-type sixth transistor N6 is connected to the reset signal RST, the drains of the P-type sixth transistor P6 and the N-type fifth transistor N5 provide the third output signal, and the first node signal M is fed back to the gates of the P-type sixth transistor P6 and the N-type fifth transistor N5. The lagging clock generator 300B may include a third multiplexer (MUX) 309A, which passes the third output signal according to the reverse clock signal CLKB. Thereby, when the reverse clock signal CLKB is at a high level, the third output signal is passed as the output signal of the first latch.

The lag clock generator 300B may include a first NOT gate 310A, which receives the first output signal, the second output signal, and the output signal of the first latch (i.e., the first reverse selection circuit 308A and the third multiplexer 309A), and generates a first node signal M. The lag clock generator 300B may include a fourth multiplexer 311A, which is used to pass the first node signal M to generate a fourth output signal. The lag clock generator 300B may include a second NOT gate 312A, which receives the fourth output signal of the fourth multiplexer 311A, and generates a lag clock signal Q.

FIG. 7B shows the circuit diagram of the advanced clock generator 400B of the second embodiment of the present invention, which can be used with the delayed clock generator 300B of FIG. 7A, and is applicable to the advanced clock generator 155B (FIG. 3A) and the advanced clock generator 166 (FIG. 5A) of the aforementioned embodiments. The advanced clock generator 400B (FIG. 7B) is similar to the delayed clock generator 300A (FIG. 7A), and the difference between the two is described as follows.

In this embodiment, the advanced clock generator 400B may include a fifth multiplexer 306B, which generates a fifth output signal "1" according to the reverse clock signal CLKB. Thus, when the reverse clock signal CLKB is at a high level, the fifth output signal "1" is generated. The advanced clock generator 400B may include a sixth multiplexer 307B, which generates a sixth output signal "0" according to the clock signal CLKB. Thus, when the clock signal CLK is at a high level, the sixth output signal "0" is generated.

The advance clock generator 400B may include a second latch for latching the second node signal N. The second latch may include a second reverse selection circuit 308B for outputting a seventh output signal according to the reset signal RST. Thus, when the reset signal RST is at a high level, the reverse second node signal N is output as the seventh output signal. The advance clock generator 400B may include a third multiplexer (MUX) 309B for passing the seventh output signal according to the reverse clock signal CLKB. Thus, when the reverse clock signal CLKB is at a high level, the seventh output signal is passed as the output signal of the second latch.

The advanced clock generator 400B may include a third NOT gate 310B, which receives the fifth output signal, the sixth output signal and the output signal of the second latch (i.e., the second reverse selection circuit 308B and the seventh multiplexer 309B), and generates the second node signal N. The delayed clock generator 300B may include an eighth multiplexer 311B, which is used to pass the second node signal N. The advanced clock generator 400B may include a fourth NOT gate 312B, which receives the output signal of the eighth multiplexer 311B, and generates the advanced clock signal R.

FIG8A shows a circuit diagram of a lag clock generator 300C of the third embodiment of the present invention, which can be applied to the lag clock generator 155A (FIG2A) and the lag clock generator 165 (FIG5A) of the aforementioned embodiments. The lag clock generator 300C (FIG8A) is similar to the lag clock generator 300B (FIG7A), and the difference between the two is described as follows.

In this embodiment, the fifth gate 313A is used to replace the first reverse selection circuit 308A to receive the first node signal M and generate the reversed first node signal M as the third output signal.

FIG. 8B shows the circuit diagram of the advanced clock generator 400C of the third embodiment of the present invention, which can be used in conjunction with the delayed clock generator 300C of FIG. 8A, and is applicable to the advanced clock generator 155B (FIG. 3A) and the advanced clock generator 166 (FIG. 5A) of the aforementioned embodiments. The advanced clock generator 400C (FIG. 8B) is similar to the delayed clock generator 300C (FIG. 7A), and the difference between the two is described as follows.

In this embodiment, the sixth gate 313B is used to replace the second reverse selection circuit 308B to receive the second node signal N and generate the reversed second node signal N as the third output signal.

The above description is only the preferred embodiment of the present invention and is not intended to limit the scope of the patent application of the present invention; any other equivalent changes or modifications that are completed without departing from the spirit disclosed by the invention should be included in the scope of the patent application below.

100: Serialization system 200: Serialization system 100A: Clock channel 100B: Data channel 11A: First serializer 11B: Second serializer 12A: First flip-flop 12B: Second flip-flop 13A: First pre-driver 13B: Second pre-driver 14A: First post-driver 14B: Second post-driver 15A: First clock generator 151A: Buffer 152A: Flip-flop 153A: Mutex OR gate 154A: Delay 155A: Lag clock generator 15B: Second clock generator 151B: Buffer 152B: Flip-flop 153B: Mutually exclusive OR gate 154B: Delay 155B: Leading pulse generator 16: Pulse generator 161: Buffer 162: Flip-flop 163: Mutually exclusive OR gate 164: Delay 165: Lagging pulse generator 166: Leading pulse generator 300A: Lagging pulse generator 300B: Lagging pulse generator 300C: Lagging pulse generator 400A: Leading pulse generator 400B: Leading pulse generator 400C: Leading pulse generator 301A: First reverse selection circuit 301B: fourth reverse selection circuit 302A: second reverse selection circuit 302B: fifth reverse selection circuit 303A: third reverse selection circuit 303B: sixth reverse selection circuit 304A: first multiplexer 304B: second multiplexer 305A: first anti-gate 305B: second anti-gate 306A: first multiplexer 306B: fifth multiplexer 307A: second multiplexer 307B: sixth multiplexer 308A: first reverse selection circuit 308B: second reverse selection circuit 309A: third multiplexer 309B: third multiplexer 310A: first anti-gate 310B: third anti-gate 311A: fourth multiplexer 311B: eighth multiplexer 312A: second gate 312B: fourth gate 313A: fifth gate 313B: sixth gate T: unit interval D_CLK: parallel clock D_Data: parallel data CLKI: in-phase phase-locked clock CLKQ: quadrature phase-locked clock CLK_S: serialized clock CLK_lag: lagging clock CLK_lead: leading clock CLKp, CLKn: clock output Datap, Datan: data output CLK_AA: first intermediate clock CLK_BB: second intermediate clock CLK: clock signal CLKB: reverse clock signal RST: reset signal RSTB: reverse reset signal Q: lagging clock signal R: Leading clock signal M: First node signal N: Second node signal P1: P-type first transistor P2: P-type second transistor P3: P-type third transistor P4: P-type fourth transistor P5: P-type fifth transistor P6: P-type sixth transistor N1: N-type first transistor N2: N-type second transistor N3: N-type third transistor N4: N-type fourth transistor N5: N-type fifth transistor N6: N-type sixth transistor VDD: Power supply GND: Ground

FIG. 1A shows a block diagram of a serialization system of an embodiment of the present invention. FIG. 1B shows a timing diagram of a clock output and a data output. FIG. 2A shows a detailed block diagram of a first clock generator of FIG. 1A. FIG. 2B shows a timing diagram of a corresponding signal of the first clock generator of FIG. 2A. FIG. 3A shows a detailed block diagram of a second clock generator of FIG. 1A. FIG. 3B shows a timing diagram of a corresponding signal of the second clock generator of FIG. 3A. FIG. 4 shows a block diagram of a serialization system of another embodiment of the present invention. FIG. 5A shows a detailed block diagram of a clock generator of FIG. 4. FIG. 5B shows a timing diagram of a corresponding signal of the clock generator of FIG. 5A. FIG. 6A shows the circuit diagram of the lagging clock generator of the first embodiment of the present invention and the timing diagram of the corresponding signal. FIG. 6B shows the circuit diagram of the leading clock generator of the first embodiment of the present invention and the timing diagram of the corresponding signal. FIG. 7A shows the circuit diagram of the lagging clock generator of the second embodiment of the present invention. FIG. 7B shows the circuit diagram of the leading clock generator of the second embodiment of the present invention. FIG. 8A shows the circuit diagram of the lagging clock generator of the third embodiment of the present invention. FIG. 8B shows the circuit diagram of the leading clock generator of the third embodiment of the present invention.

100:Serial system

100A: Clock channel

100B: Data channel

11A: First serializer

11B: Second serializer

12A: The first flip-flop

12B: Second flip-flop

13A: First pre-driver

13B: Second pre-driver

14A: First rear drive

14B: Second rear drive

15A: First pulse generator

15B: Second pulse generator

D_CLK: parallel clock

D_Data: Parallel data

CLKI: In-phase locked clock

CLKQ: Quadrature-locked clock

CLK_S: serialization clock

CLK_lag: lagging clock

CLK_lead: Leading clock

CLKp, CLKn: clock output

Datap,Datan:Data output

Claims (19)

A serialization system comprises: A clock channel for generating a clock output, the clock channel comprising: A first serializer for converting a parallel clock into a serial clock; A first flip-flop for storing the serial clock in sequence to provide the clock output; A data channel for outputting data output, the data channel comprising: A second serializer for converting parallel data into serial data; A second flip-flop for storing the serial data in sequence to provide the data output; A clock generating circuit receives a phase-locked clock and generates a serialized clock to the first serializer and the second serializer, generates a lagging clock to the first flip-flop, and generates an advanced clock to the second flip-flop; wherein the sum of the lag amount of the lagging clock relative to the serialized clock and the advance amount of the advanced clock relative to the serialized clock is one-half of a unit interval. The serialization system of claim 1, wherein the clock channel further comprises: a first pre-driver, receiving the serial clock from the first flip-flop to increase the driving capability; and a first post-driver, for converting the single-ended serial clock into a differential clock output. The serialization system of claim 1, wherein the data channel further comprises: a second pre-driver, receiving the serial data from the second flip-flop to increase the driving capability; and a second post-driver, for converting the single-ended serial data into differential data output. The serialization system of claim 1, wherein the clock generation circuit comprises: a first clock generator, generating the serialization clock to the first serializer, and generating the lagging clock to the first flip-flop; and a second clock generator, generating the serialization clock to the second serializer, and generating the leading clock to the second flip-flop; wherein the first clock generator and the second clock generator are independent of each other. The serialization system of claim 4, wherein the first clock generator comprises: a buffer, providing impedance matching and receiving an in-phase phase-locked clock; a flip-flop, receiving the in-phase phase-locked clock output by the buffer to generate the serialization clock; a mutex gate, generating a first intermediate clock for the flip-flop according to the in-phase phase-locked clock and the quadrature phase-locked clock; a delay device, used to delay the first intermediate clock to generate a second intermediate clock, so that the second intermediate clock is synchronized with the serialization clock; and a lag clock generator, generating the lag clock. The serialization system of claim 4, wherein the second clock generator comprises: a buffer, providing impedance matching and receiving a common-phase locked clock; a flip-flop, receiving the common-phase locked clock output by the buffer to generate the serialization clock; a mutex gate, generating a first intermediate clock for the flip-flop according to the common-phase locked clock and the quadrature locked clock; a delay device, used to delay the first intermediate clock to generate a second intermediate clock, so that the second intermediate clock is synchronized with the serialization clock; and an advance clock generator, to generate the advance clock. The serialization system of claim 1, wherein the clock generation circuit comprises: A single clock generator, generating the serialization clock to the first serializer and the second serializer, generating the lagging clock to the first flip-flop, and generating the leading clock to the second flip-flop. The serialization system of claim 7, wherein the clock generator comprises: a buffer, providing impedance matching and receiving an in-phase phase-locked clock; a flip-flop, receiving the in-phase phase-locked clock output by the buffer to generate the serialization clock; a mutex gate, generating a first intermediate clock for the flip-flop according to the in-phase phase-locked clock and the quadrature phase-locked clock; a delay device, used to delay the first intermediate clock to generate a second intermediate clock, so that the second intermediate clock is synchronized with the serialization clock; a lag clock generator, generating the lag clock for the first flip-flop; and An advance clock generator generates the advance clock to the second flip-flop. A clock generation circuit includes: a lagging clock generator for generating a lagging clock signal according to a clock signal; and an advancing clock generator for generating an advancing clock signal according to the clock signal; wherein the sum of the lag amount of the lagging clock signal and the leading amount of the advancing clock signal is half a unit interval. The clock generation circuit of claim 9, wherein the lagging clock generator comprises: a first reverse selection circuit, outputting a first output signal "1" according to the reverse clock signal; a second reverse selection circuit, outputting a second output signal "0" according to the clock signal; a first latch, used to lock the lagging clock signal; and a first anti-gate, receiving the first output signal, the second output signal and the output signal of the first latch, and generating the lagging clock signal accordingly. The clock generation circuit of claim 10, wherein the first latch comprises: a third reverse selection circuit, outputting a third output signal according to a reset signal; and a first multiplexer, passing the third output signal according to the reverse clock signal. The clock generation circuit of claim 10, wherein the advanced clock generator comprises: a fourth reverse selection circuit, outputting a fourth output signal "0" according to the reverse clock signal; a fifth reverse selection circuit, outputting a fifth output signal "1" according to the clock signal; a second latch, for latching the advanced clock signal; and a second anti-gate, receiving the fourth output signal, the fifth output signal and the output signal of the second latch, and generating the advanced clock signal accordingly. The clock generating circuit of claim 12, wherein the second latch comprises: a sixth reverse selection circuit, outputting a sixth output signal according to a reset signal; and a second multiplexer, passing the sixth output signal according to the reverse clock signal. The clock generation circuit of claim 9, wherein the delayed clock generator comprises: a first multiplexer, generating a first output signal "0" according to a reverse clock signal; a second multiplexer, generating a second output signal "1" according to the clock signal; a first latch, used to lock the first node signal; a first anti-gate, receiving the first output signal, the second output signal and the output signal of the first latch, thereby generating the first node signal; a fourth multiplexer, generating a fourth output signal through the first node signal; and a second anti-gate, receiving the fourth output signal, thereby generating the delayed clock signal. The clock generation circuit of claim 14, wherein the first latch comprises: a first reverse selection circuit, outputting a third output signal according to a reset signal; and a third multiplexer, passing the third output signal according to the reverse clock signal. The clock generation circuit of claim 14, wherein the first latch comprises: a fifth anti-gate, receiving the first node signal, thereby generating a reverse first node signal as a third output signal; and a third multiplexer, passing the third output signal according to the reverse clock signal. The clock generation circuit of claim 14, wherein the advanced clock generator comprises: a fifth multiplexer, generating a fifth output signal "1" according to the reverse clock signal; a sixth multiplexer, generating a sixth output signal "0" according to the clock signal; a second latch, used to lock the second node signal; a third inverting gate, receiving the fifth output signal, the sixth output signal and the output signal of the second latch, thereby generating the second node signal; an eighth multiplexer, used to pass the second node signal; and a fourth inverting gate, receiving the output signal of the eighth multiplexer, thereby generating the advanced clock signal. The clock generating circuit of claim 17, wherein the second latch comprises: a second reverse selection circuit, outputting a seventh output signal according to a reset signal; and a third multiplexer, passing the seventh output signal according to a reverse clock signal. The clock generation circuit of claim 17, wherein the second latch comprises: a sixth anti-gate, receiving the second node signal, thereby generating a reverse second node signal as a seventh output signal; and a third multiplexer, passing the seventh output signal according to the reverse clock signal.