TWI829230B - Asymmetric feed-forward equalizer for high-speed optical transmitter - Google Patents
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本發明涉及光發射器技術領域,特別是一種用於高速光發射器之非對稱前饋等化器。The present invention relates to the technical field of optical transmitters, and in particular to an asymmetric feedforward equalizer for high-speed optical transmitters.
現今許多電子系統需要傳輸大量資訊(數據),因而導致頻寬(bandwidth) 的需求快速增長。伴隨著未來高性能計算系統和網路數據速率的不斷提高,其可以達到數百 Gb/s 甚至更高,對這些電子系統互連 (interconnects)的 I/O 頻寬的需求也隨之增加。但是,用於晶片間 (inter-chip)通訊的電氣通道(electrical channels) 的頻寬並沒有以相同的方式擴展。在通訊路徑中,傳輸電訊號,高速數據可能會受到,例如電纜、電路板、輸出設備中的符碼間干擾(inter-symbol interference) 而劣化。為此,數種用於發射器 (transmitter)和接收器(receiver)的等化技術 (equalization techniques) 已經被提出來用於補償頻寬受限電信通道 (band-limited channels) 的頻率相關損耗。然而,這些等化技術需要相當大的晶粒面積並且相當消耗電力。Many electronic systems today need to transmit large amounts of information (data), resulting in rapid growth in bandwidth requirements. As future high-performance computing systems and network data rates continue to increase, reaching hundreds of Gb/s or even higher, the demand for I/O bandwidth in the interconnects of these electronic systems will also increase. However, the bandwidth of the electrical channels used for inter-chip communication has not expanded in the same way. In communication paths, electrical signals are transmitted and high-speed data may be degraded by inter-symbol interference in cables, circuit boards, and output devices. To this end, several equalization techniques for transmitters and receivers have been proposed to compensate for frequency-dependent losses in band-limited telecommunications channels. However, these equalization techniques require considerable die area and are quite power-consuming.
利用光學互連可以克服上述 I/O 頻寬的問題。光通道 (optical channels) 具有可忽略的頻率相關損耗。由於目前與 CMOS 技術整合的更高數據速率的光鏈路 (optical link) 設計正在成為可能,並且不會導致等化問題的額外複雜性。對於光通訊而言,電訊號是透過雷射二極體等非線性元件轉換為光訊號。垂直共振腔面射型雷射 (vertical cavity surface emitting lasers, VCSELs) 廣泛用於高速光通訊,因為它們之中的各自都具有較小的閾值電流並且可以用於構建二維陣列。因此,VCSEL 是光互連系統中的關鍵組件。然而,在互連中整合基於 VCSEL 的光發射器的最大挑戰在於是否能夠提供足夠的頻寬以在高數據速率(例如 > 25Gb/s)下運行,同時保持低電力消耗以最大限度地提高功率效率(通常以 mW/Gb/s 或 pJ/bit表示:亦即,傳輸一位元資訊所需的能量)。The aforementioned I/O bandwidth issues can be overcome using optical interconnects. Optical channels have negligible frequency-dependent losses. Due to the current integration of CMOS technology, higher data rate optical link designs are becoming possible without the additional complexity of equalization issues. For optical communications, electrical signals are converted into optical signals through nonlinear components such as laser diodes. Vertical cavity surface emitting lasers (VCSELs) are widely used in high-speed optical communications because each of them has a small threshold current and can be used to construct two-dimensional arrays. Therefore, VCSELs are critical components in optical interconnect systems. However, the biggest challenge in integrating VCSEL-based optical transmitters in interconnects is the ability to provide sufficient bandwidth to operate at high data rates (e.g., >25Gb/s) while maintaining low power consumption to maximize power Efficiency (usually expressed in mW/Gb/s or pJ/bit: that is, the energy required to transmit one bit of information).
隨著數據速率的增加,設計者採用了預加重 (pre-emphasis) 技術,該技術使用有限脈衝響應 (finite impulse response, FIR) 濾波器來補償 VCSEL 頻寬約束並允許較低的偏壓電流。然而,由於 FIR 濾波器是線性系統,而 VCSEL 的響應是非線性的,因此這種線性 FIR 濾波器技術對於未來的高性能計算系統和網路來說並不是最佳的選擇。As data rates increased, designers adopted pre-emphasis techniques, which use finite impulse response (FIR) filters to compensate for VCSEL bandwidth constraints and allow lower bias currents. However, since FIR filters are linear systems and the response of VCSELs is nonlinear, this linear FIR filter technology is not the best choice for future high-performance computing systems and networks.
為了解決上述問題,本發明提出將非對稱前饋等化器用於高速光發射器機系統上。In order to solve the above problems, the present invention proposes to use an asymmetric feedforward equalizer in a high-speed optical transmitter system.
在本發明中,上升沿和下降沿偵測電路是於於光發射器驅動器的低速狀態中實現,然後在數據訊號被多工選擇 (been multiplexed) 前利用相位內插器(phase interpolators, PIs)來提供等化延遲 (equaization delay) 以補償VCSEL的上升和下降響應,亦即透過非對稱非對稱前饋等化器 (feed-forward equalizer, FFE) 技術與用於可調節延遲的各別相位內插器 (phase interpolator, PI)相結合,用於對 VCSEL 提供等化的數據訊號。In the present invention, the rising and falling edge detection circuits are implemented in the low-speed state of the optical transmitter driver, and then use phase interpolators (PIs) before the data signal is multiplexed. To provide an equalization delay to compensate for the rising and falling responses of the VCSEL, that is, through an asymmetric feed-forward equalizer (FFE) technology and separate phase internals for adjustable delays Combined with a phase interpolator (PI), it is used to provide equalized data signals to the VCSEL.
基於上述目的,根據本發明的第一觀點,提出了一種用於高速光發射器的非對稱前饋等化器(feed-forward equalizer, FFE),其包括:一主驅動器,被配置用於接收一輸入數據訊號,以及放大該輸入數據訊號產生之增益主驅動器數據訊號;一第一相位調整單元,被配置用於對齊該輸入數據訊號的相位;一上升沿等化驅動器,被配置用於偵測該輸入數據訊號的上升沿,並生成一第一調整數據訊號;一下降沿等化驅動器,被配置用於偵測該輸入數據訊號的下降沿,並生成一第二調整數據訊號;一第二相位調整單元,被配置用於對齊該輸入數據訊號的上升沿與該輸入數據訊號的下降沿之間的相位;一等化延遲模組,由該第一相位調整單元以及該第二相位調整單元所組成,被配置透過調整該第一相位調整單元與該第二相位調整單元之間的相對相位以生成一延遲訊號,用於確定等化延遲;一垂直共振腔面射型雷射(VCSEL),被配置用於輸出該增益主驅動數據訊號、該第一調整數據訊號以及該第二調整數據訊號的線性組合訊號。Based on the above objectives, according to the first aspect of the present invention, an asymmetric feed-forward equalizer (FFE) for high-speed optical transmitters is proposed, which includes: a main driver configured to receive An input data signal, and a gain main driver data signal generated by amplifying the input data signal; a first phase adjustment unit configured to align the phase of the input data signal; a rising edge equalization driver configured to detect detecting the rising edge of the input data signal and generating a first adjustment data signal; a falling edge equalization driver configured to detect the falling edge of the input data signal and generating a second adjustment data signal; a first Two phase adjustment units are configured to align the phases between the rising edge of the input data signal and the falling edge of the input data signal; an equalization delay module is configured by the first phase adjustment unit and the second phase adjustment unit. The unit is configured to generate a delay signal by adjusting the relative phase between the first phase adjustment unit and the second phase adjustment unit for determining the equalization delay; a vertical resonant cavity surface emitting laser (VCSEL) ) is configured to output a linear combination signal of the gain main driving data signal, the first adjustment data signal and the second adjustment data signal.
以一實施例而言,上述第一相位調整單元以及上述第二相位調整單元均為相位內插器。In one embodiment, the first phase adjustment unit and the second phase adjustment unit are both phase interpolators.
以一實施例而言,上述主驅動器更包含:一第一N對1多工器,接收該輸入數據訊號,並對其多工選擇以產生多工的輸入數據訊號;以及一個與該垂直共振腔面射型雷射(VCSEL)耦合的第一放大級,被配置用以接收該多工的輸入數據訊號並對其放大,產生對應於該增益主驅動器數據訊號的第一電流脈衝。In one embodiment, the above-mentioned main driver further includes: a first N-to-1 multiplexer that receives the input data signal and multiplexes it to generate multiplexed input data signals; and a vertical resonance with the A first amplification stage of a cavity surface emitting laser (VCSEL) coupling is configured to receive the multiplexed input data signal and amplify it to generate a first current pulse corresponding to the gain main driver data signal.
以一實施例而言,上述上升沿等化驅動器包含:一上升沿偵測器,被配置用於偵測該輸入數據訊號的上升沿脈衝;一第二N對1多工器,與該上升沿偵測器耦合,用以接收該上升沿脈衝,並利用該第二相位調整單元的時鐘訊號來調整對該第二N對1多工器之核心的對齊;以及一第二放大級,耦合該上升沿偵測器以及該垂直共振腔面射型雷射(VCSEL),用於產生對應於該第一調整數據訊號的第二電流脈衝,其中該第二電流脈衝對應於將該輸入數據訊號經過上升沿轉換和等化延遲後之電流訊號。In one embodiment, the above-mentioned rising edge equalization driver includes: a rising edge detector configured to detect the rising edge pulse of the input data signal; a second N-to-1 multiplexer connected to the rising edge pulse. An edge detector is coupled to receive the rising edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the second N-to-1 multiplexer; and a second amplification stage, coupled The rising edge detector and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a second current pulse corresponding to the first adjustment data signal, wherein the second current pulse corresponds to the input data signal The current signal after rising edge conversion and equalization delay.
以一實施例而言,上述下降沿等化驅動器包含:一下降沿偵測器,被配置用於偵測該輸入數據訊號的下降沿脈衝;一第三N對1多工器,與該下降沿偵測器耦合,用以接收該下降沿脈衝,並利用該第二相位調整單元的時鐘訊號來調整對該第三N對1多工器之核心的對齊;以及一第三放大級,耦合該下降沿偵測模組以及該垂直共振腔面射型雷射(VCSEL),用於產生對應於該第一調整數據訊號的第三電流脈衝,其中該第三電流脈衝對應於將該輸入數據訊號經過下降沿轉換和等化延遲後之電流訊號。In one embodiment, the falling edge equalization driver includes: a falling edge detector configured to detect the falling edge pulse of the input data signal; a third N-to-1 multiplexer connected to the falling edge pulse. An edge detector is coupled to receive the falling edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the third N-to-1 multiplexer; and a third amplification stage, coupled The falling edge detection module and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a third current pulse corresponding to the first adjustment data signal, wherein the third current pulse corresponds to the input data The signal is the current signal after falling edge conversion and equalization delay.
以一實施例而言,上述上升沿偵測器包括:一第一脈衝產生器,用於產生第一上升訊號脈衝,其包括具有兩個輸入端的第一邏輯AND閘,一個輸入端用於接收和反相該輸入數據訊號的第一分支,而另一個輸入端用於接收該輸入數據訊號的第二分支;以及一第二脈衝產生器,用於產生第二上升訊號脈衝,其包括具有兩個輸入端的第二邏輯AND閘,一個輸入端用於接收該輸入數據訊號的該第一分支,而另一個輸入端耦合到反相器以及由接收時鐘訊號控制的延遲元件,該延遲元件輸入該輸入數據訊號的該第二分支,其中該第一上升訊號脈衝和該第二上升訊號脈衝,分別透過它們所對應的該第一邏輯AND閘和該第二邏輯AND閘的輸出端,輸入到該第二N對1多工器。In one embodiment, the above-mentioned rising edge detector includes: a first pulse generator for generating a first rising signal pulse, which includes a first logical AND gate with two input terminals, one input terminal for receiving and inverting the first branch of the input data signal, and the other input terminal is used to receive the second branch of the input data signal; and a second pulse generator for generating a second rising signal pulse, which includes two A second logical AND gate with input terminals, one input terminal for receiving the first branch of the input data signal, and the other input terminal is coupled to an inverter and a delay element controlled by receiving a clock signal, the delay element inputs the The second branch of the input data signal, wherein the first rising signal pulse and the second rising signal pulse are respectively input to the output terminals of the first logical AND gate and the second logical AND gate. Second N-to-1 multiplexer.
以一實施例而言,上述下降沿偵測器包括:一第三脈衝產生器,用於產生第一下降訊號脈衝,其包括具有兩個輸入端的第三邏輯AND閘,一個輸入端用於接收該輸入數據訊號的第一分支,而另一個輸入端用於接收和反相該輸入數據訊號的第二分支;以及一第四脈衝產生器,用於產生第二下降訊號脈衝,其包括具有兩個輸入端的第四邏輯AND閘,一個輸入端用於接收和反相該輸入數據訊號的該第一分支,而另一個輸入端耦合到由接收時鐘訊號控制的延遲元件,該延遲元件輸入該輸入數據訊號的該第二分支,其中該第一下降訊號脈衝和該第二下降訊號脈衝,分別透過它們所對應的該第三邏輯AND閘和該第四邏輯AND閘的輸出端,輸入到該第三N對1多工器。In one embodiment, the falling edge detector includes: a third pulse generator for generating a first falling signal pulse, which includes a third logical AND gate with two input terminals, one input terminal for receiving The first branch of the input data signal, and the other input terminal is used to receive and invert the second branch of the input data signal; and a fourth pulse generator for generating a second falling signal pulse, which includes two A fourth logical AND gate with input terminals, one input terminal for receiving and inverting the first branch of the input data signal, and the other input terminal is coupled to a delay element controlled by receiving a clock signal, the delay element inputting the input The second branch of the data signal, in which the first falling signal pulse and the second falling signal pulse are respectively input to the third logical AND gate through their corresponding output terminals of the third logical AND gate and the fourth logical AND gate. Three N-to-1 multiplexers.
根據本發明的第二觀點,提出一種用於高速光發射器之非對稱前饋等化器,包括:一主驅動器,被配置用於接收一輸入數據訊號,以及放大該輸入數據訊號產生之增益主驅動器數據訊號; 一第一相位調整單元,被配置用於對齊該輸入數據訊號的相位;一上升沿等化驅動器,被配置用於偵測該輸入數據訊號的上升沿,並生成一第一調整數據訊號;一第二相位調整單元,被配置用於對齊該輸入數據訊號的上升沿的相位;一下降沿等化驅動器,被配置用於偵測該輸入數據訊號的下降沿,並生成一第二調整數據訊號;一第二相位調整單元,被配置用於對齊該輸入數據訊號的上升沿與該輸入數據訊號的下降沿之間的相位;一第三相位調整單元,用於對齊該輸入數據訊號的下降沿的相位;一等化延遲模組,由該第一相位調整單元、該第二相位調整單元以及該第三相位調整單元所組成,被配置為透過調整該第一相位調整單元與該第二相位調整單元之間的相對相位以生成一第一延遲訊號,以及透過調整該第一相位調整單元與該第三相位調整單元之間的相對相位以生成一第二延遲訊號,用於確定相對應的等化延遲;一垂直共振腔面射型雷射(VCSEL),被配置用於輸出該增益主驅動數據訊號、該第一調整數據訊號以及該第二調整數據訊號的線性組合訊號。According to a second aspect of the present invention, an asymmetric feedforward equalizer for a high-speed optical transmitter is proposed, including: a main driver configured to receive an input data signal and amplify the gain generated by the input data signal The main driver data signal; a first phase adjustment unit configured to align the phase of the input data signal; a rising edge equalization driver configured to detect the rising edge of the input data signal and generate a first Adjust the data signal; a second phase adjustment unit is configured to align the phase of the rising edge of the input data signal; a falling edge equalization driver is configured to detect the falling edge of the input data signal and generate a a second adjustment data signal; a second phase adjustment unit configured to align the phase between the rising edge of the input data signal and the falling edge of the input data signal; a third phase adjustment unit configured to align the input The phase of the falling edge of the data signal; the equalization delay module is composed of the first phase adjustment unit, the second phase adjustment unit and the third phase adjustment unit, and is configured to adjust the first phase adjustment unit by The relative phase between the first phase adjustment unit and the third phase adjustment unit is used to generate a first delay signal, and the relative phase between the first phase adjustment unit and the third phase adjustment unit is adjusted to generate a second delay signal. In order to determine the corresponding equalization delay; a vertical resonant cavity surface emitting laser (VCSEL) is configured to output a linear combination of the gain main drive data signal, the first adjustment data signal and the second adjustment data signal signal.
以一實施例而言,上述主驅動器更包含:一第一N對1多工器,接收該輸入數據訊號,並對其多工選擇以產生多工的輸入數據訊號;以及一個與該垂直共振腔面射型雷射(VCSEL)耦合的第一放大級,被配置用以接收該多工的輸入數據訊號並對其放大,產生對應於該增益主驅動器數據訊號的第一電流脈衝。In one embodiment, the above-mentioned main driver further includes: a first N-to-1 multiplexer that receives the input data signal and multiplexes it to generate multiplexed input data signals; and a vertical resonance with the A first amplification stage of a cavity surface emitting laser (VCSEL) coupling is configured to receive the multiplexed input data signal and amplify it to generate a first current pulse corresponding to the gain main driver data signal.
以一實施例而言,上述上升沿等化驅動器包含:一上升沿偵測器,被配置用於偵測該輸入數據訊號的上升沿脈衝;一第二N對1多工器,與該上升沿偵測器耦合,用以接收該上升沿脈衝,並利用該第二相位調整單元的時鐘訊號來調整對該第二N對1多工器之核心的對齊;以及一第二放大級,耦合該上升沿偵測器以及該垂直共振腔面射型雷射(VCSEL),用於產生對應於該第一調整數據訊號的第二電流脈衝,其中該第二電流脈衝對應於將該輸入數據訊號經過上升沿轉換和等化延遲後之電流訊號。In one embodiment, the above-mentioned rising edge equalization driver includes: a rising edge detector configured to detect the rising edge pulse of the input data signal; a second N-to-1 multiplexer connected to the rising edge pulse. An edge detector is coupled to receive the rising edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the second N-to-1 multiplexer; and a second amplification stage, coupled The rising edge detector and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a second current pulse corresponding to the first adjustment data signal, wherein the second current pulse corresponds to the input data signal The current signal after rising edge conversion and equalization delay.
以一實施例而言,上述下降沿等化驅動器包含:一下降沿偵測器,被配置用於偵測該輸入數據訊號的下降沿脈衝;一第三N對1多工器,與該下降沿偵測器耦合,用以接收該下降沿脈衝,並利用該第二相位調整單元的時鐘訊號來調整對該第三N對1多工器之核心的對齊;以及一第三放大級,耦合該下降沿偵測模組以及該垂直共振腔面射型雷射(VCSEL),用於產生對應於該第一調整數據訊號的第三電流脈衝,其中該第三電流脈衝對應於將該輸入數據訊號經過下降沿轉換和等化延遲後之電流訊號。In one embodiment, the falling edge equalization driver includes: a falling edge detector configured to detect the falling edge pulse of the input data signal; a third N-to-1 multiplexer connected to the falling edge pulse. An edge detector is coupled to receive the falling edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the third N-to-1 multiplexer; and a third amplification stage, coupled The falling edge detection module and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a third current pulse corresponding to the first adjustment data signal, wherein the third current pulse corresponds to the input data The signal is the current signal after falling edge conversion and equalization delay.
此處本發明將針對發明具體實施例及其觀點加以詳細描述,此類描述為解釋本發明之結構或步驟流程,其係供以說明之用而非用以限制本發明之申請專利範圍。因此,除說明書中之具體實施例與較佳實施例外,本發明亦可廣泛施行於其他不同的實施例中。以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技術之人士可藉由本說明書所揭示之內容輕易地瞭解本發明之功效性與其優點。且本發明亦可藉由其他具體實施例加以運用及實施,本說明書所闡述之各項細節亦可基於不同需求而應用,且在不悖離本發明之精神下進行各種不同的修飾或變更。Here, the present invention will be described in detail with respect to specific embodiments and viewpoints of the invention. Such descriptions are to explain the structure or step process of the present invention, and are for illustration purposes rather than limiting the patentable scope of the present invention. Therefore, in addition to the specific embodiments and preferred embodiments in the specification, the present invention can also be widely implemented in other different embodiments. The following describes the implementation of the present invention through specific embodiments. Those familiar with the art can easily understand the efficacy and advantages of the present invention through the content disclosed in this specification. Moreover, the present invention can also be applied and implemented through other specific embodiments. Various details described in this specification can also be applied based on different needs, and various modifications or changes can be made without departing from the spirit of the present invention.
如背景部分所陳述,利用有限脈衝響應(finite impulse response, FIR)濾波器的預加重 (pre-emphasis) 技術無法處理VCSEL光發射器系統的非線性響應問題。為了解決此一問題,一種習知的非線性VCSEL 等化技術被提出,其整合了動態 VCSEL 模型方式來補償 VCSEL 光發射器固有的非線性響應。圖1顯示非線性VCSEL等化的實施方式。As stated in the background section, pre-emphasis techniques using finite impulse response (FIR) filters cannot handle the nonlinear response of VCSEL light emitter systems. In order to solve this problem, a conventional nonlinear VCSEL equalization technology is proposed, which integrates a dynamic VCSEL model approach to compensate for the inherent nonlinear response of the VCSEL optical emitter. Figure 1 shows an implementation of non-linear VCSEL equalization.
於圖1中,其描繪一個習知的VCSEL光發射器系統範例,被配置為用於執行非線性VCSEL等化。此一VCSEL光發射器系統可包括被配置為輸出光訊號162的VCSEL 102。輸入數據訊號A和B是由2:1多工器 (MUX) 110多工選擇,並且成為VCSEL 102的多工輸入訊號
D
in 。多工輸入訊號
D
in 可以是電數據的輸入訊號,2:1多工器 (MUX) 110的輸出可以耦合到放大級112的輸入端子、等化延遲模組120的輸入端子、上升沿偵測器130的輸入端子以及下降沿偵測器140的輸入端子。等化延遲模組120又可以耦合到上升沿偵測器130和下降沿偵測器 140。上升沿偵測器130可以耦合等化延遲模組120和放大級132,並且可以具有耦合到輸入訊號
D
in 的輸入端子。類似地,下降沿偵測器140可以耦合到等化延遲模組120和放大級142,並且可以具有耦合到輸入訊號
D
in 的輸入端子。其中,放大級112、132和142又可以透過加法器160耦合到VCSEL 102和偏壓電流源150。
In Figure 1, an example of a conventional VCSEL light emitter system configured to perform nonlinear VCSEL equalization is depicted. Such a VCSEL optical emitter system may include a
VCSEL系統100可以被配置為透過調整輸入訊號
D
in 來執行等化,用以消除或減少光訊號162中的脈衝失真。在一些實施例中,VCSEL系統100可以基於等化延遲、上升沿增益和下降沿增益來調整輸入訊號
D
in 中脈衝的上升沿和下降沿。其中,等化延遲模組120可以基於在一個模型化VCSEL調製響應和偏壓電流 150的頻率峰值來確定和/或提供等化延遲(equalization delay)。上升沿偵測器130,其可以利用互補金屬氧化物半導體 (CMOS) 技術來實現,作為檢測輸入數據訊號
D
in 中的脈衝上升沿。放大級132可以在偵測到的輸入數據訊號
D
in 的上升沿處提供上升增益,例如,作為基於模型化的VCSEL調製響應和輸入數據訊號
D
in 的速率所確定的上升沿抽頭參數 (tap parameter)。下降沿偵測器140,可以使用CMOS技術實現,其可以被配置為偵測輸入數據訊號
D
in 中的脈衝下降沿。與放大級132類似,放大級142可以提供下降沿增益,例如作為基於模型化的VCSEL調製響應和輸入數據訊號
D
in 的數據速率所確定的下降沿抽頭參數 (tap parameter)。在一些實施例中,控制器還可以調整VCSEL的調製響應。
The
圖1中所描繪的技術考慮了VCSEL 光發射器的隔離訊號“壹”和“零”的響應之間的不對稱響應的影響,透過偵測上升沿和下降沿並以不同方式來等化它們。然而,為了實現執行非線性 VCSEL 等化的範例 VCSEL 系統 100 的電路配置,該電路含有等化延遲模組 120,其可以包含多個反相器 (inverters) 或其他延遲元件,在高速狀態下執行操作,可能會潛在地增加電力消耗和由於等化模組中的大量電晶體增加了RC常數,因此而降低了頻寬。在執行上述非線性等化所整合 VCSEL 光發射器的互連中,由於上述等化延遲模組所引起的 VCSEL 頻寬限制,在不歸零 (non-return-to-zero, NRZ) 調製下數據速率高於 56Gb/s 之條件下,該技術會出現瓶頸。The technique depicted in Figure 1 takes into account the effect of the asymmetric response between the one and zero responses of the isolation signal of the VCSEL optical emitter by detecting rising and falling edges and equalizing them in different ways. . However, in order to implement the circuit configuration of the
為了對高速光發射器提供非對稱前饋等化(asymmetric FFE),即在 NRZ 調製下數據速率高於 56Gb/s,本發明提議在光發射器驅動器的低速狀態下實現上升沿和下降沿偵測。然後,利用低功率相位內插器 (phase interpolators, PIs) 提供可調節延遲,用於在數據訊號被多工選擇(been multiplexed)之前補償 VCSEL 的上升和下降響應,亦即,利用非對稱 FFE 技術與用於可調節延遲的個別 PI相結合,以提供等化數據訊號(equalized data signal)來補償 VCSEL 的固有非線性響應。In order to provide asymmetric feedforward equalization (asymmetric FFE) for high-speed optical transmitters, that is, data rates higher than 56Gb/s under NRZ modulation, the present invention proposes to implement rising and falling edge detection in the low-speed state of the optical transmitter driver. Test. Low-power phase interpolators (PIs) are then used to provide adjustable delays to compensate for the rising and falling responses of the VCSEL before the data signal has been multiplexed, that is, using asymmetric FFE technology Combined with an individual PI for adjustable delay, it provides an equalized data signal to compensate for the inherent nonlinear response of the VCSEL.
在傳統的方法中,VCSEL的輸出波形是利用基於速率方程的VCSEL模型來計算,並且電流響應由理想電流源施加到VCSEL。模擬的結果表明,由於弛豫振盪,在上升沿和下降沿都會出現振鈴(ringing),而且在上升沿/下降沿會出現一定幅度的下衝/過衝(undershoot/overshoot)。這些下衝 (undershoot)和過衝 (overshoot)嚴重劣化了數據的波形。因此,在本發明中,提出了一種解決此問題的概念,亦即,利用對上升沿處的下衝進行補償的正加重脈衝 (positive emphasis pulse)和對下降沿處的過衝進行補償的負加重脈衝(negative emphasis pulse)的非對稱加重(前饋均衡)技術。每個預加重脈衝(pre-emphasis pulse)的寬度和建立時間都可以針對下衝和過衝進行調整。In the traditional method, the output waveform of the VCSEL is calculated using a VCSEL model based on the rate equation, and the current response is applied to the VCSEL by an ideal current source. The simulation results show that due to relaxation oscillation, ringing will occur on the rising edge and falling edge, and there will be a certain amount of undershoot/overshoot on the rising edge/falling edge. These undershoots and overshoots severely degrade the data waveform. Therefore, in the present invention, a concept is proposed to solve this problem, that is, using a positive emphasis pulse to compensate for the undershoot at the rising edge and a negative emphasis pulse to compensate for the overshoot at the falling edge. Asymmetric emphasis (feedforward equalization) technology of negative emphasis pulse. The width and settling time of each pre-emphasis pulse can be adjusted for undershoot and overshoot.
圖2顯示了根據本發明的一個較佳實施例中,具有被配置為執行非線性(非對稱)VCSEL等化的非對稱FFE的光發射器系統200的建議架構。Figure 2 shows a proposed architecture of an
光發射器系統200可以包括VCSEL 202,其被配置為輸出光訊號262。輸入數據訊號A和B可以是電數據輸入訊號,可以被分支並輸入到與第一放大級212的輸入端子耦合的第一多工器 (MUX) 210、被分支並輸入到與第二多工器(MUX) 210a 的輸入端子耦合的上升沿偵測器230,以及被分支並輸入到與第三多工器(MUX) 210b 的輸入端子耦合的下降沿偵測器 240,其中,第二多工器 210a 和第三多工器 210b 分別耦合到第二放大級232和第三放大級 242 的輸入端子。第一、第二和第三放大級(212、232和242)透過加法器260耦合到VCSEL 202。第一多工器(MUX) 210接收輸入數據訊號A、B並產生多工數據
D
in 。上升沿偵測器230接收輸入數據訊號A、B,並於該數據訊號存在上升轉變時為數據訊號A和B產生相應的訊號脈衝
R
1 和
R
2 。生成的訊號脈衝
R
1 和
R
2 接著被多工選擇 (been multiplexed) 並產生多工的上升訊號脈衝
R。類似地,下降沿偵測器240接收輸入數據訊號A、B,並於該數據訊號存在下降轉變時為數據訊號A和B產生相應的訊號脈衝
F 1和
F 2。生成的訊號脈衝
F
1 和
F
2 接著被多工選擇並產生多工的下降訊號脈衝
F。
多工的主驅動數據訊號
D
in 由第一多工器 (MUX) 210核心中的低功率相位內插器(第一相位調整單元)270對齊其相位,隨著被施加到第一放大級212並輸出增益主驅動數據訊號
I
data 。經過多工選擇上升訊號脈衝
R和下降訊號脈衝
F,兩者的相位均分別由第二多工器(MUX) 210a和第三多工器(MUX) 210b核心中的低功率相位內插器 (第二相位調整單元) 272對齊,然後分別輸入到第二放大級232以及第三放大級242並且分別提供上升增益訊號
I
R 和下降增益訊號
I F。接著,光發射器系統200可以透過應用上述上升增益訊號
I
R 和下降增益訊號
I
F 來等化上升沿和下降沿,以達到等化延遲
t
eq 。在一個較佳實施例中,上述多工的主驅動訊號
D
in 的相位可以由相位內插器(第一相位調整單元) 270來固定。經過多工選擇的上升訊號脈衝
R和下降訊號脈衝
F的等化延遲
t
eq 可以由相位內插器(第二相位調整單元) 272控制,並且被設置為
不是 位元週期 (bit period) 的倍數,其中,第一相位調整單元270和第二相位調整單元272可以被配置為形成等化延遲模組,用於經由調整第一相位調整單元270和第二相位調整單元272之間的相對相位來產生延遲訊號,以確定等化延遲
t
eq 。其中,上述增益主驅動數據訊號
I
data 、上升增益訊號
I
R 和下降增益訊號
I F均為電流脈衝訊號。
The multiplexed main driving data signal D in is phase-aligned by the low-power phase interpolator (first phase adjustment unit) 270 in the first multiplexer (MUX) 210 core, and is then applied to the
其中,相位內插器(第一相位調整單元) 270以及272(第二相位調整單元)由時脈訊號產生器280提供同相 (I) 以及正交 (Q) 時脈訊號。Among them, the phase interpolators (first phase adjustment unit) 270 and 272 (second phase adjustment unit) are provided with in-phase (I) and quadrature (Q) clock signals by the
上升訊號脈衝
R和下降訊號脈衝,經由第二放大級232和第三放大級242的個別調整以及執行等化延遲
t
eq ,其等化脈衝的幅度和寬度在上升沿和下降沿可以被分別控制。這意味著,多工的上升訊號脈衝
R和下降訊號脈衝
F的增益對等化脈衝的幅度有貢獻,而由相位內插器272控制的等化延遲
t
eq 對等化脈衝的寬度有貢獻。
The rising signal pulse R and the falling signal pulse are individually adjusted by the
等化(equalization)可以透過主驅動器增益數據訊號(電流脈衝) I data 、生成的上升增益訊號 I R 和生成的下降增益訊號 I F 的線性組合來實現,亦即,生成的上升增益訊號(電流脈衝) I R 與主驅動器增益數據訊號(電流脈衝) I data 相加或是相減以對上升沿調整波形,且生成的下降增益訊號(電流脈衝) I F 與主驅動器增益訊號(電流脈衝) I data 相加或相減以對下降沿調整波形。 Equalization can be achieved through the linear combination of the main driver gain data signal (current pulse) I data , the generated rising gain signal I R and the generated falling gain signal IF , that is, the generated rising gain signal (current Pulse) I R is added or subtracted from the main driver gain data signal (current pulse) I data to adjust the waveform for the rising edge, and the generated falling gain signal (current pulse) I F is added to the main driver gain signal (current pulse) I data is added or subtracted to adjust the waveform for falling edges.
圖3顯示根據本發明的另一個較佳實施例中,具有被配置為執行非線性(非對稱)VCSEL等化的非對稱FFE的光發射器系統300的建議架構。圖 3 中所實現電路幾乎與圖2所示的相同,唯一的區別是,在本實施例中,相位內插器數目為三個,即三個低功率相位內插器 270、272 和 274,分別代表第一、第二和第三相位調整單元,被配置為用於個別調整多工數據訊號
D
in 、
R和
F之間的等化延遲。在一個較佳實施例中,主驅動數據訊號
I
data 的相位可以透過第一多工器 (MUX) 210之核心中的相位內插器(第一相位調整單元) 270來固定。上升增益訊號
I
R 的等化延遲
t
eq1 可由 第二多工器 (MUX) 210a 之核心中的相位內插器(第二相位調整單元)272 單獨控制,而下降增益訊號
I
F 的等化延遲
t
eq2 可由位於第三多工器 (MUX) 210b之核心中的相位內插器(第三相位調整單元)274單獨控制。其中,等化延遲
t
eq1 和
t
eq2 均被設置為
不是 位元週期 (bit period) 的倍數,其中第一相位調整單元270、第二相位調整單元272和第三相位調整單元274可以配置為形成等化延遲模組,透過調整第一相位調整單元270和第二相位調整單元272之間的相對相位來產生第一延遲訊號,以及透過調整第一相位調整單元270和第三相位調整單元274之間的相對相位來產生第二延遲訊號。
Figure 3 shows a proposed architecture of an
其中,第一相位調整單元 270、第二相位調整單元 272以及第三相位調整單元 274由時脈訊號產生器280提供同相 (I) 以及正交 (Q) 時脈訊號。Among them, the first
等化脈衝的幅度和寬度,分別經由上升沿和下降沿,透過第二放大級232和第三放大級242以及等化延遲
t
eql 和
t
eq2 來進行個別調整。這意味著,多工上升訊號脈衝
R和多工下降訊號脈衝
F的增益貢獻於等化脈衝的幅度,而由相位內插器 272 和 274 個別控制的等化延遲
t
eq1 和
t
eq2 貢獻於等化脈衝的寬度。
The amplitude and width of the equalization pulse are individually adjusted through the rising edge and falling edge respectively through the
對於本發明而言,上升沿和下降沿偵測器係透過數位CMOS邏輯來實現。其中,圖4A-4B分別揭示了根據本發明的一個實施例的上升沿偵測器和下降沿偵測器的電路功能方塊圖。於圖4A中,其顯示用於輸入數據訊號A和B的上升沿偵測器430,其係由用於生成輸入數據訊號B的上升訊號脈衝
R
1 的第一脈衝產生器和用於生成輸入數據A的上升訊號脈衝
R 2的第二脈衝產生器所組成。其中,第一脈衝產生器包括具有兩個輸入端的第一邏輯AND閘422,用於分別接收輸入數據訊號B和反相輸入數據訊號A(透過一反相器),輸入數據訊號B的上升沿,即上升訊號脈衝
R 1,可由第一邏輯AND閘422偵測並透過其輸出端輸出。第二脈衝產生器包括具有兩個輸入端的第二邏輯AND閘424,其中一個輸入端耦接接收輸入數據訊號A,而另一個輸入端耦接反相器和延遲元件(例如,D型觸發器:DFF)並由時鐘訊號 (CK) 控制,用於將反相輸入訊號B轉換為具有一位元(one bit)延遲,輸入數據訊號A的上升沿,即上升訊號脈衝
R
2 ,可以被第二邏輯AND閘424偵測並經由其輸出端輸出。
For the present invention, the rising edge and falling edge detectors are implemented through digital CMOS logic. 4A-4B respectively reveal circuit functional block diagrams of a rising edge detector and a falling edge detector according to an embodiment of the present invention. In FIG. 4A, there is shown a rising
如圖4B所示,用於輸入數據訊號A和B的下降沿偵測器440,由用於產生輸入數據訊號B的下降訊號脈衝
F
1 的第三脈衝產生器和用於生成輸入數據訊號A的下降訊號脈衝
F
2 的第四脈衝產生器所組成。其中,用於產生下降訊號脈衝
F
1 的第三脈衝產生器,包括具有兩個輸入端的第三邏輯AND閘422a,用於分別接收輸入數據訊號A和反相輸入數據訊號B(透過反相器),輸入數據訊號B的下降沿,即下降訊號脈衝
F
1 ,可以被第三邏輯AND閘422a檢測並透過其輸出端輸出。用於產生下降訊號脈衝
F
2 的第四脈衝產生器,包括具有兩個輸入端的第四邏輯AND閘424a,其中一個輸入端耦合到接收反相輸入數據訊號A,而另一個輸入端耦合到延遲元件(例如,D型觸發器:DFF) 由時鐘訊號 (CK) 所控制,用於以一位元 (one bit) 延遲轉換輸入訊號B,輸入數據訊號A的下降沿,即下降訊號脈衝
F
2 ,可以被第四邏輯AND閘偵測到並且透過其輸出端輸出。
As shown in FIG. 4B , the falling
圖4C-4D顯示了根據本發明的一個實施例中,使用兩個相位內插器的相位對齊操作的範例性時序圖。其中,上升沿訊號,包括上升訊號脈衝
R
1 和
R
2 ,可以被相位內插器272偵測並調整等化延遲時間
t
eq ,用於補償由於VCSEL對每個躍遷的響應所造成的訊號失真。類似地,包括下降訊號脈衝
F
1 和
F
2 的下降沿訊號可以被相位內插器272偵測並調整等化延遲時間
t
eq ,用於補償由於VCSEL對每個躍遷的響應而引起的訊號失真。透過這種方式,可以消除VCSEL的典型響應中的峰值。
4C-4D show exemplary timing diagrams of phase alignment operations using two phase interpolators in accordance with one embodiment of the present invention. Among them, the rising edge signal, including the rising signal pulses R 1 and R 2 , can be detected by the
簡而言之,透過本發明所提出的非對稱FFE技術能夠改善由於非線性VCSEL響應引起的波形劣化。In short, the waveform degradation caused by the nonlinear VCSEL response can be improved through the asymmetric FFE technology proposed in the present invention.
以上實施例僅用以說明本發明的技術方案,而非對其限制;儘管參照前述實施例對本發明及其效益進行詳細說明,本領域的普通技術人員應當理解:其依然可以對前述各實施例所記載的進行修改,或者對其中部分技術特徵進行等同替換;而這些修改或替換,並不使相應技術方案的本質脫離本發明權利要求的範圍。The above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them. Although the present invention and its benefits are described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the foregoing embodiments. Modifications are made as described, or equivalent substitutions are made to some of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the claims of the present invention.
102:VCSEL102:VCSEL
110:多工器110:Multiplexer
112,132,142:放大級112,132,142: Amplification stage
120:等化延遲模組120: Equalization delay module
130:上升沿偵測器130: rising edge detector
140:下降沿偵測器140: Falling edge detector
160:加法器160: Adder
150:偏壓電流源150: Bias current source
162:光訊號162:Light signal
200:光發射器系統200:Light transmitter system
202:VCSEL202:VCSEL
210:第一多工器210:First multiplexer
210a:第二多工器210a: Second multiplexer
210b:第三多工器210b: Third multiplexer
230:上升沿偵測器230: rising edge detector
240:下降沿偵測器240: Falling edge detector
212:第一放大級212: First amplification stage
232:第二放大級232: Second amplification stage
242:第三放大級242: The third amplification stage
260:加法器260: Adder
262:光訊號262:Light signal
270:第一相位調整單元270: First phase adjustment unit
272:第二相位調整單元272: Second phase adjustment unit
274:第三相位調整單元274: The third phase adjustment unit
280:時脈訊號產生器280: Clock signal generator
300:光發射器系統300:Light transmitter system
430:上升沿偵測器430: rising edge detector
440:下降沿偵測器440: Falling edge detector
422:第一邏輯AND閘422: First logical AND gate
424:第二邏輯AND閘424: Second logical AND gate
422a:第三邏輯AND閘422a: The third logical AND gate
424a:第四邏輯AND閘424a: The fourth logical AND gate
本發明的組成、特徵和優點可以透過說明書中概述的較佳實施例的詳細描述和附圖來理解:The composition, features and advantages of the present invention can be understood through the detailed description of the preferred embodiments summarized in the specification and the accompanying drawings:
[圖1]顯示習知技術中執行非線性VCSEL等化的垂直共振腔面射型雷射(VCSEL) 光發射器系統範例。[Figure 1] shows an example of a vertical cavity surface-emitting laser (VCSEL) light emitter system that performs nonlinear VCSEL equalization in the prior art.
[圖2]顯示根據本發明的一個實施例中所提出,被配置為用於執行非線性(不對稱)VCSEL等化之具有非對稱FFE之光發射器系統架構。[Fig. 2] shows an optical transmitter system architecture with asymmetric FFE configured to perform nonlinear (asymmetric) VCSEL equalization according to one embodiment of the present invention.
[圖3]顯示根據本發明的另一個實施例中所提出,被配置為用於執行非線性(不對稱)VCSEL等化之具有非對稱FFE之光發射器系統架構。[Fig. 3] shows an optical transmitter system architecture with asymmetric FFE configured to perform nonlinear (asymmetric) VCSEL equalization according to another embodiment of the present invention.
[圖4A-4B]顯示根據本發明的一個實施例所提出的上升沿偵測和下降沿偵測的電路功能方塊圖。[Figure 4A-4B] shows a functional block diagram of a circuit for rising edge detection and falling edge detection proposed according to an embodiment of the present invention.
[圖4C-4D]顯示根據本發明的一個實施例所提出的執行上升沿偵測器的相位對齊之操作的時序圖範例。[FIG. 4C-4D] shows an example of a timing diagram of an operation of performing phase alignment of a rising edge detector according to an embodiment of the present invention.
200:光發射器系統 200:Light transmitter system
202:VCSEL 202:VCSEL
210:第一多工器 210:First multiplexer
210a:第二多工器 210a: Second multiplexer
210b:第三多工器 210b: Third multiplexer
230:上升沿偵測器 230: rising edge detector
240:下降沿偵測器 240: Falling edge detector
212:第一放大級 212: First amplification stage
232:第二放大級 232: Second amplification stage
242:第三放大級 242: The third amplification stage
260:加法器 260: Adder
262:光訊號 262:Light signal
270:第一相位調整單元 270: First phase adjustment unit
272:第二相位調整單元 272: Second phase adjustment unit
280:時脈訊號產生器 280: Clock signal generator
Claims (8)
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US20150104196A1 (en) * | 2013-10-14 | 2015-04-16 | Korea Advanced Institute Of Science And Technology | Electronic dispersion compensation for low-cost distributed feedback-directly modulated laser |
US20160006596A1 (en) * | 2014-07-01 | 2016-01-07 | International Business Machines Corporation | 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases |
US20160149730A1 (en) * | 2014-11-26 | 2016-05-26 | Rambus Inc. | Equalized multi-signaling mode driver |
US20170187463A1 (en) * | 2015-12-28 | 2017-06-29 | Fujitsu Limited | Delay-based nonlinear equalizer |
US20190305851A1 (en) * | 2018-03-30 | 2019-10-03 | Mellanox Technologies Denmark ApS. | Transition based feedforward equalization method and apparatus implemented with lookup table circuits |
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US20150104196A1 (en) * | 2013-10-14 | 2015-04-16 | Korea Advanced Institute Of Science And Technology | Electronic dispersion compensation for low-cost distributed feedback-directly modulated laser |
US20160006596A1 (en) * | 2014-07-01 | 2016-01-07 | International Business Machines Corporation | 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases |
US20160149730A1 (en) * | 2014-11-26 | 2016-05-26 | Rambus Inc. | Equalized multi-signaling mode driver |
US20170187463A1 (en) * | 2015-12-28 | 2017-06-29 | Fujitsu Limited | Delay-based nonlinear equalizer |
US20190305851A1 (en) * | 2018-03-30 | 2019-10-03 | Mellanox Technologies Denmark ApS. | Transition based feedforward equalization method and apparatus implemented with lookup table circuits |
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