TW202404288A - Asymmetric feed-forward equalizer for high-speed optical transmitter - Google Patents

Abstract

An asymmetric feed-forward equalizer for optical transmitters includes a main driver configured to receive an input data signal and generate a gained main driver signal, a first phase adjustment unit for aligning the phase of the input data signal, a rising edge equalization driver for detecting a rising edge of the input data signal and generating a first adjusted data signal, a falling edge equalization driver for detecting a falling edge of the input data signal and generating a second adjusted data signal, a second phase adjustment unit for aligning the phases between the rising and falling edges of the input data signal, an equalization delay module generating a delay signal for determining an equalization delay, and a VCSEL output a combination of the gained main driver, the first adjusted data and the second adjusted data signals.

Description

Asymmetric feedforward equalizer for high-speed optical transmitters

The present invention relates to the technical field of optical transmitters, and in particular to an asymmetric feedforward equalizer for high-speed optical transmitters.

Many electronic systems today need to transmit large amounts of information (data), resulting in rapid growth in bandwidth requirements. As future high-performance computing systems and network data rates continue to increase, reaching hundreds of Gb/s or even higher, the demand for I/O bandwidth in the interconnects of these electronic systems will also increase. However, the bandwidth of the electrical channels used for inter-chip communication has not expanded in the same way. In communication paths, electrical signals are transmitted and high-speed data may be degraded by inter-symbol interference in cables, circuit boards, and output devices. To this end, several equalization techniques for transmitters and receivers have been proposed to compensate for frequency-dependent losses in band-limited telecommunications channels. However, these equalization techniques require considerable die area and are quite power-consuming.

The aforementioned I/O bandwidth issues can be overcome using optical interconnects. Optical channels have negligible frequency-dependent losses. Due to the current integration of CMOS technology, higher data rate optical link designs are becoming possible without the additional complexity of equalization issues. For optical communications, electrical signals are converted into optical signals through nonlinear components such as laser diodes. Vertical cavity surface emitting lasers (VCSELs) are widely used in high-speed optical communications because each of them has a small threshold current and can be used to construct two-dimensional arrays. Therefore, VCSELs are critical components in optical interconnect systems. However, the biggest challenge in integrating VCSEL-based optical transmitters in interconnects is the ability to provide sufficient bandwidth to operate at high data rates (e.g., >25Gb/s) while maintaining low power consumption to maximize power Efficiency (usually expressed in mW/Gb/s or pJ/bit: that is, the energy required to transmit one bit of information).

As data rates increased, designers adopted pre-emphasis techniques, which use finite impulse response (FIR) filters to compensate for VCSEL bandwidth constraints and allow lower bias currents. However, since FIR filters are linear systems and the response of VCSELs is nonlinear, this linear FIR filter technology is not the best choice for future high-performance computing systems and networks.

In order to solve the above problems, the present invention proposes to use an asymmetric feedforward equalizer in a high-speed optical transmitter system.

In the present invention, the rising and falling edge detection circuits are implemented in the low-speed state of the optical transmitter driver, and then utilize phase interpolators (PIs) before the data signal has been multiplexed. To provide an equalization delay to compensate for the rise and fall response of the VCSEL, that is, through an asymmetric feed-forward equalizer (FFE) technology and separate phase internals for adjustable delays Combined with a phase interpolator (PI), it is used to provide equalized data signals to the VCSEL.

Based on the above objectives, according to the first aspect of the present invention, an asymmetric feed-forward equalizer (FFE) for high-speed optical transmitters is proposed, which includes: a main driver configured to receive An input data signal, and a gain main driver data signal generated by amplifying the input data signal; a first phase adjustment unit configured to align the phase of the input data signal; a rising edge equalization driver configured to detect detecting the rising edge of the input data signal and generating a first adjustment data signal; a falling edge equalization driver configured to detect the falling edge of the input data signal and generating a second adjustment data signal; a first Two phase adjustment units are configured to align the phases between the rising edge of the input data signal and the falling edge of the input data signal; an equalization delay module is configured by the first phase adjustment unit and the second phase adjustment unit. The unit is configured to generate a delay signal by adjusting the relative phase between the first phase adjustment unit and the second phase adjustment unit for determining the equalization delay; a vertical resonant cavity surface emitting laser (VCSEL) ) is configured to output a linear combination signal of the gain main driving data signal, the first adjustment data signal and the second adjustment data signal.

In one embodiment, the first phase adjustment unit and the second phase adjustment unit are both phase interpolators.

In one embodiment, the above-mentioned main driver further includes: a first N-to-1 multiplexer that receives the input data signal and multiplexes it to generate multiplexed input data signals; and a vertical resonance with the A first amplification stage of a cavity surface emitting laser (VCSEL) coupling is configured to receive the multiplexed input data signal and amplify it to generate a first current pulse corresponding to the gain main driver data signal.

In one embodiment, the above-mentioned rising edge equalization driver includes: a rising edge detector configured to detect the rising edge pulse of the input data signal; a second N-to-1 multiplexer connected to the rising edge pulse. An edge detector is coupled to receive the rising edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the second N-to-1 multiplexer; and a second amplification stage, coupled The rising edge detector and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a second current pulse corresponding to the first adjustment data signal, wherein the second current pulse corresponds to the input data signal The current signal after rising edge conversion and equalization delay.

In one embodiment, the falling edge equalization driver includes: a falling edge detector configured to detect the falling edge pulse of the input data signal; a third N-to-1 multiplexer connected to the falling edge pulse. An edge detector is coupled to receive the falling edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the third N-to-1 multiplexer; and a third amplification stage, coupled The falling edge detection module and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a third current pulse corresponding to the first adjustment data signal, wherein the third current pulse corresponds to the input data The signal is the current signal after falling edge conversion and equalization delay.

In one embodiment, the above-mentioned rising edge detector includes: a first pulse generator for generating a first rising signal pulse, which includes a first logical AND gate with two input terminals, one input terminal for receiving and inverting the first branch of the input data signal, and the other input terminal is used to receive the second branch of the input data signal; and a second pulse generator for generating a second rising signal pulse, which includes two A second logical AND gate with input terminals, one input terminal for receiving the first branch of the input data signal, and the other input terminal is coupled to an inverter and a delay element controlled by receiving a clock signal, the delay element inputs the The second branch of the input data signal, wherein the first rising signal pulse and the second rising signal pulse are respectively input to the output terminals of the first logical AND gate and the second logical AND gate. Second N-to-1 multiplexer.

In one embodiment, the falling edge detector includes: a third pulse generator for generating a first falling signal pulse, which includes a third logical AND gate with two input terminals, one input terminal for receiving The first branch of the input data signal, and the other input terminal is used to receive and invert the second branch of the input data signal; and a fourth pulse generator for generating a second falling signal pulse, which includes two A fourth logical AND gate with input terminals, one input terminal for receiving and inverting the first branch of the input data signal, and the other input terminal is coupled to a delay element controlled by receiving a clock signal, the delay element inputting the input The second branch of the data signal, in which the first falling signal pulse and the second falling signal pulse are respectively input to the third logical AND gate through their corresponding output terminals of the third logical AND gate and the fourth logical AND gate. Three N-to-1 multiplexers.

According to a second aspect of the present invention, an asymmetric feedforward equalizer for a high-speed optical transmitter is proposed, including: a main driver configured to receive an input data signal and amplify the gain generated by the input data signal The main driver data signal; a first phase adjustment unit configured to align the phase of the input data signal; a rising edge equalization driver configured to detect the rising edge of the input data signal and generate a first Adjust the data signal; a second phase adjustment unit is configured to align the phase of the rising edge of the input data signal; a falling edge equalization driver is configured to detect the falling edge of the input data signal and generate a a second adjustment data signal; a second phase adjustment unit configured to align the phase between the rising edge of the input data signal and the falling edge of the input data signal; a third phase adjustment unit configured to align the input The phase of the falling edge of the data signal; the equalization delay module is composed of the first phase adjustment unit, the second phase adjustment unit and the third phase adjustment unit, and is configured to adjust the first phase adjustment unit by The relative phase between the first phase adjustment unit and the third phase adjustment unit is used to generate a first delay signal, and the relative phase between the first phase adjustment unit and the third phase adjustment unit is adjusted to generate a second delay signal. In order to determine the corresponding equalization delay; a vertical resonant cavity surface emitting laser (VCSEL) is configured to output a linear combination of the gain main drive data signal, the first adjustment data signal and the second adjustment data signal signal.

In one embodiment, the above-mentioned main driver further includes: a first N-to-1 multiplexer that receives the input data signal and multiplexes it to generate multiplexed input data signals; and a vertical resonance with the A first amplification stage of a cavity surface emitting laser (VCSEL) coupling is configured to receive the multiplexed input data signal and amplify it to generate a first current pulse corresponding to the gain main driver data signal.

In one embodiment, the above-mentioned rising edge equalization driver includes: a rising edge detector configured to detect the rising edge pulse of the input data signal; a second N-to-1 multiplexer connected to the rising edge pulse. An edge detector is coupled to receive the rising edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the second N-to-1 multiplexer; and a second amplification stage, coupled The rising edge detector and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a second current pulse corresponding to the first adjustment data signal, wherein the second current pulse corresponds to the input data signal The current signal after rising edge conversion and equalization delay.

In one embodiment, the falling edge equalization driver includes: a falling edge detector configured to detect the falling edge pulse of the input data signal; a third N-to-1 multiplexer connected to the falling edge pulse. An edge detector is coupled to receive the falling edge pulse and use the clock signal of the second phase adjustment unit to adjust the alignment of the core of the third N-to-1 multiplexer; and a third amplification stage, coupled The falling edge detection module and the vertical resonant cavity surface emitting laser (VCSEL) are used to generate a third current pulse corresponding to the first adjustment data signal, wherein the third current pulse corresponds to the input data The signal is the current signal after falling edge conversion and equalization delay.

Here, the present invention will be described in detail with respect to specific embodiments and viewpoints of the invention. Such descriptions are to explain the structure or step process of the present invention, and are for illustration purposes rather than limiting the patentable scope of the present invention. Therefore, in addition to the specific embodiments and preferred embodiments in the specification, the present invention can also be widely implemented in other different embodiments. The following describes the implementation of the present invention through specific embodiments. Those familiar with the art can easily understand the efficacy and advantages of the present invention through the content disclosed in this specification. Moreover, the present invention can also be applied and implemented through other specific embodiments. Various details described in this specification can also be applied based on different needs, and various modifications or changes can be made without departing from the spirit of the present invention.

As stated in the background section, pre-emphasis techniques using finite impulse response (FIR) filters cannot handle the nonlinear response of VCSEL light emitter systems. In order to solve this problem, a conventional nonlinear VCSEL equalization technology is proposed, which integrates a dynamic VCSEL model approach to compensate for the inherent nonlinear response of the VCSEL optical emitter. Figure 1 shows an implementation of non-linear VCSEL equalization.

In Figure 1, an example of a conventional VCSEL light emitter system configured to perform nonlinear VCSEL equalization is depicted. Such a VCSEL optical emitter system may include a VCSEL 102 configured to output an optical signal 162 . Input data signals A and B are multiplexed by a 2:1 multiplexer (MUX) 110 and become the multiplex input signal D _in of the VCSEL 102 . The multiplex input signal D _in can be an input signal of electrical data, and the output of the 2:1 multiplexer (MUX) 110 can be coupled to the input terminal of the amplifier stage 112 , the input terminal of the equalization delay module 120 , and rising edge detection. The input terminal of the detector 130 and the input terminal of the falling edge detector 140 . The equalization delay module 120 may in turn be coupled to the rising edge detector 130 and the falling edge detector 140 . The rising edge detector 130 may be coupled to the equalization delay module 120 and the amplifier stage 132, and may have an input terminal coupled to the input signal D _in . Similarly, falling edge detector 140 may be coupled to equalization delay module 120 and amplifier stage 142, and may have an input terminal coupled to input signal _Din . Among them, the amplification stages 112, 132 and 142 can be coupled to the VCSEL 102 and the bias current source 150 through the adder 160.

The VCSEL system 100 may be configured to perform equalization by adjusting the input signal D _in to eliminate or reduce pulse distortion in the optical signal 162 . In some embodiments, the VCSEL system 100 may adjust the rising and falling edges of the pulses _in the input signal Din based on the equalization delay, rising edge gain, and falling edge gain. The equalization delay module 120 may determine and/or provide an equalization delay based on a modeled VCSEL modulation response and a frequency peak of the bias current 150 . The rising edge detector 130 can be implemented using complementary metal oxide semiconductor (CMOS) technology to detect the rising edge of the pulse in the input data signal _Din . The amplification stage 132 may provide rising gain at the detected rising edge of the input data signal _Din , for example, as a rising edge tap parameter determined based on the modeled VCSEL modulation response and the rate of the input data signal _Din . ). The falling edge detector 140 can be implemented using CMOS technology, and can be configured to detect the falling edge of the pulse in the input data signal _Din . Similar to amplification stage 132, amplification stage 142 may provide falling edge gain, for example, as a falling edge tap parameter determined based on the modeled VCSEL modulation response and the data rate of the input data signal _Din . In some embodiments, the controller may also adjust the modulation response of the VCSEL.

The technique depicted in Figure 1 takes into account the effect of the asymmetric response between the one and zero responses of the isolation signal of the VCSEL optical emitter by detecting rising and falling edges and equalizing them in different ways. . However, in order to implement the circuit configuration of the example VCSEL system 100 that performs nonlinear VCSEL equalization, the circuit includes an equalization delay module 120, which may include multiple inverters or other delay elements and perform at high speed. operation, may potentially increase power consumption and reduce bandwidth due to the increased RC constant due to the large number of transistors in the equalization module. In the interconnection of the integrated VCSEL optical transmitter that performs the above nonlinear equalization, due to the VCSEL bandwidth limitation caused by the above equalization delay module, under non-return-to-zero (NRZ) modulation At data rates higher than 56Gb/s, this technology will experience bottlenecks.

In order to provide asymmetric feedforward equalization (asymmetric FFE) for high-speed optical transmitters, that is, data rates higher than 56Gb/s under NRZ modulation, the present invention proposes to implement rising and falling edge detection in the low-speed state of the optical transmitter driver. Test. Low-power phase interpolators (PIs) are then used to provide adjustable delays to compensate for the rising and falling responses of the VCSEL before the data signal has been multiplexed, that is, using asymmetric FFE technology Combined with individual PIs for adjustable delay to provide an equalized data signal to compensate for the inherent nonlinear response of the VCSEL.

In the traditional method, the output waveform of the VCSEL is calculated using a VCSEL model based on the rate equation, and the current response is applied to the VCSEL by an ideal current source. The simulation results show that due to relaxation oscillation, ringing will occur on the rising edge and falling edge, and there will be a certain amount of undershoot/overshoot on the rising edge/falling edge. These undershoots and overshoots severely degrade the data waveform. Therefore, in the present invention, a concept is proposed to solve this problem, that is, using a positive emphasis pulse to compensate for the undershoot at the rising edge and a negative emphasis pulse to compensate for the overshoot at the falling edge. Asymmetric emphasis (feedforward equalization) technology of negative emphasis pulse. The width and settling time of each pre-emphasis pulse can be adjusted for undershoot and overshoot.

Figure 2 shows a proposed architecture of an optical transmitter system 200 with an asymmetric FFE configured to perform non-linear (asymmetric) VCSEL equalization in accordance with a preferred embodiment of the present invention.

Optical transmitter system 200 may include a VCSEL 202 configured to output an optical signal 262 . Input data signals A and B may be electrical data input signals that may be branched and input to a first multiplexer (MUX) 210 coupled to an input terminal of the first amplification stage 212, branched to and input to a second multiplexer (MUX) 210 coupled to an input terminal of the first amplifier stage 212. The rising edge detector 230 is coupled to the input terminal of the multiplexer (MUX) 210a, and is branched and input to the falling edge detector 240 coupled to the input terminal of the third multiplexer (MUX) 210b, wherein the second multiplexer (MUX) 210b The multiplexer 210a and the third multiplexer 210b are coupled to the input terminals of the second amplification stage 232 and the third amplification stage 242, respectively. The first, second and third amplification stages (212, 232 and 242) are coupled to VCSEL 202 through adder 260. The first multiplexer (MUX) 210 receives input data signals A and B and generates multiplexed data D _in . The rising edge detector 230 receives the input data signals A and B, and generates corresponding signal pulses R ₁ and R ₂ for the data signals A and B when there is a rising transition in the data signal. The generated signal pulses R ₁ and R ₂ are then multiplexed and generate a multiplexed rising signal pulse R . Similarly, the falling edge detector 240 receives the input data signals A and B, and generates corresponding signal pulses F ₁ and F ₂ for the data signals A and B when there is a falling transition in the data signal. The generated signal pulses F ₁ and F ₂ are then multiplexed and generate a multiplexed falling signal pulse F .

The multiplexed main driving data signal D _in is phase-aligned by the low-power phase interpolator (first phase adjustment unit) 270 in the first multiplexer (MUX) 210 core, and is then applied to the first amplification stage 212 And output the gain main driving data signal I _data . After multiplexing, the rising signal pulse R and the falling signal pulse F are selected, and the phases of both are determined by the low-power phase interpolator ( The second phase adjustment unit) 272 is aligned, and then input to the second amplification stage 232 and the third amplification stage 242 respectively and provides the rising gain signal _IR and _{the falling gain signal IF} respectively . Then, the optical transmitter system 200 can equalize the rising edges and falling edges by applying the above-mentioned rising gain signal _IR and falling gain signal _IF to achieve the equalized delay _teq . In a preferred embodiment, the phase of the multiplexed main driving signal D _in can be fixed by a phase interpolator (first phase adjustment unit) 270 . The equalization delay t _eq of the multiplexed rising signal pulse R and falling signal pulse F can be controlled by the phase interpolator (second phase adjustment unit) 272 and is set to not be a multiple of the bit period (bit period) , wherein the first phase adjustment unit 270 and the second phase adjustment unit 272 may be configured to form an equalized delay module for adjusting the relative phase between the first phase adjustment unit 270 and the second phase adjustment unit 272 . A delay signal is generated to determine the equalization delay _teq . Among them, the above-mentioned gain main driving data signal I _data , rising gain signal _IR and falling gain signal IF are all current _pulse signals.

Among them, the phase interpolators (first phase adjustment unit) 270 and 272 (second phase adjustment unit) are provided with in-phase (I) and quadrature (Q) clock signals by the clock signal generator 280.

The rising signal pulse R and the falling signal pulse are individually adjusted by the second amplification stage 232 and the third amplification stage 242 and the equalization delay t _eq is performed. The amplitude and width of the equalization pulse can be controlled respectively on the rising edge and the falling edge. . This means that the gain of the multiplexed rising signal pulse R and falling signal pulse F contributes to the amplitude of the equalized pulse, and the equalizing delay t _eq controlled by the phase interpolator 272 contributes to the width of the equalized pulse.

Equalization can be achieved through the linear combination of the main driver gain data signal (current pulse) I _data , the generated rising gain signal I _R and the generated falling gain signal _IF , that is, the generated rising gain signal (current Pulse) I _R is added or subtracted from the main driver gain data signal (current pulse) I _data to adjust the waveform for the rising edge, and the generated falling gain signal (current pulse) I _F is added to the main driver gain signal (current pulse) I _data is added or subtracted to adjust the waveform for falling edges.

Figure 3 shows a proposed architecture of an optical transmitter system 300 with an asymmetric FFE configured to perform non-linear (asymmetric) VCSEL equalization in accordance with another preferred embodiment of the present invention. The circuit implemented in Figure 3 is almost the same as that shown in Figure 2. The only difference is that in this embodiment, the number of phase interpolators is three, namely three low-power phase interpolators 270, 272 and 274. Represent first, second and third phase adjustment units respectively, configured for individually adjusting equalization delays between multiplexed data signals _Din , R and F. In a preferred embodiment, the phase of the main driving data signal I _data can be fixed through the phase interpolator (first phase adjustment unit) 270 in the core of the first multiplexer (MUX) 210 . The equalization delay _teq1 of the rising gain signal I _R can be independently controlled by the phase interpolator (second phase adjustment unit) 272 in the core of the second multiplexer (MUX) 210a, while the equalization delay t eq1 of the falling gain signal _IF t _eq2 can be controlled solely by the phase interpolator (third phase adjustment unit) 274 located in the core of the third multiplexer (MUX) 210b. Wherein, the equalization delays _teq1 and _teq2 are both set to not be multiples of the bit period, wherein the first phase adjustment unit 270, the second phase adjustment unit 272 and the third phase adjustment unit 274 may be configured to form The equalization delay module generates a first delay signal by adjusting the relative phase between the first phase adjustment unit 270 and the second phase adjustment unit 272, and by adjusting the relationship between the first phase adjustment unit 270 and the third phase adjustment unit 274. The relative phase between them is used to generate a second delayed signal.

Among them, the first phase adjustment unit 270, the second phase adjustment unit 272 and the third phase adjustment unit 274 are provided with in-phase (I) and quadrature (Q) clock signals by the clock signal generator 280.

The amplitude and width of the equalization pulse are individually adjusted through the rising edge and falling edge respectively through the second amplification stage 232 and the third amplification stage 242 and the equalization delays _teq1 and _teq2 . This means that the gains of the multiplexed rising signal pulse R and the multiplexed falling signal pulse F contribute to the amplitude of the equalizing pulses, while the equalizing delays t _eq1 and t _eq2 controlled individually by the phase interpolators 272 and 274 contribute to the equalizing pulses. The width of the pulse.

For the present invention, the rising edge and falling edge detectors are implemented through digital CMOS logic. 4A-4B respectively reveal circuit functional block diagrams of a rising edge detector and a falling edge detector according to an embodiment of the present invention. In FIG. 4A, there is shown a rising edge detector 430 for input data signals A and B, which is composed of a first pulse generator for generating a rising signal pulse R ₁ of the input data signal B and a first pulse generator for generating the input The rising signal pulse R2 _of data A is composed of the second pulse generator. Among them, the first pulse generator includes a first logical AND gate 422 with two input terminals for respectively receiving the input data signal B and the inverted input data signal A (through an inverter). The rising edge of the input data signal B , that is, the rising signal pulse R ₁ can be detected by the first logical AND gate 422 and output through its output terminal. The second pulse generator includes a second logical AND gate 424 having two input terminals, one of which is coupled to receive the input data signal A, and the other input terminal is coupled to an inverter and a delay element (eg, a D-type flip-flop :DFF) and controlled by the clock signal (CK), used to convert the inverted input signal B into a signal with one bit delay. The rising edge of the input data signal A, that is, the rising signal pulse R ₂ , can be The two logic AND gates 424 detect and output via its output terminals.

As shown in FIG. 4B , the falling edge detector 440 for the input data signals A and B is composed of a third pulse generator for generating the falling signal pulse F ₁ of the input data signal B and a third pulse generator for generating the input data signal A. The falling signal pulse _F2 consists of the fourth pulse generator. Among them, the third pulse generator for generating the falling signal pulse F ₁ includes a third logical AND gate 422a with two input terminals for respectively receiving the input data signal A and the inverted input data signal B (through an inverter ), the falling edge of the input data signal B, that is, the falling signal pulse F ₁ , can be detected by the third logic AND gate 422a and output through its output terminal. The fourth pulse generator for generating the falling signal pulse _F2 includes a fourth logical AND gate 424a having two input terminals, one of which is coupled to receive the inverted input data signal A, and the other input terminal is coupled to the delay The component (for example, D-type flip-flop: DFF) is controlled by the clock signal (CK) and is used to delay the conversion of the input signal B with one bit (one bit). The falling edge of the input data signal A, that is, the falling signal pulse F ₂ , can be detected by the fourth logic AND gate and output through its output terminal.

4C-4D show exemplary timing diagrams of phase alignment operations using two phase interpolators in accordance with one embodiment of the present invention. Among them, the rising edge signal, including the rising signal pulses R ₁ and R ₂ , can be detected by the phase interpolator 272 and the equalization delay time _teq is adjusted to compensate for the signal distortion caused by the VCSEL's response to each transition. . Similarly, falling edge signals including falling signal pulses F ₁ and F ₂ can be detected by the phase interpolator 272 and the equalization delay time _teq can be adjusted to compensate for the signal distortion caused by the VCSEL's response to each transition. . In this way, the peaks in the typical response of VCSELs are eliminated.

In short, the waveform degradation caused by the nonlinear VCSEL response can be improved through the asymmetric FFE technology proposed in the present invention.

The above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them. Although the present invention and its benefits are described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the foregoing embodiments. Modifications are made as described, or equivalent substitutions are made to some of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the claims of the present invention.

102:VCSEL 110:Multiplexer 112,132,142: Amplification stage 120: Equalization delay module 130: rising edge detector 140: Falling edge detector 160: Adder 150: Bias current source 162:Light signal 200:Light transmitter system 202:VCSEL 210:First multiplexer 210a: Second multiplexer 210b: Third multiplexer 230: rising edge detector 240: Falling edge detector 212: First amplification stage 232: Second amplification stage 242: The third amplification stage 260: Adder 262:Light signal 270: First phase adjustment unit 272: Second phase adjustment unit 274: The third phase adjustment unit 280: Clock signal generator 300:Light transmitter system 430: rising edge detector 440: Falling edge detector 422: First logical AND gate 424: Second logical AND gate 422a: The third logical AND gate 424a: The fourth logical AND gate

The composition, features and advantages of the present invention can be understood through the detailed description of the preferred embodiments summarized in the specification and the accompanying drawings:

[Figure 1] shows an example of a vertical cavity surface-emitting laser (VCSEL) light emitter system that performs nonlinear VCSEL equalization in the prior art.

[Fig. 2] shows an optical transmitter system architecture with asymmetric FFE configured to perform nonlinear (asymmetric) VCSEL equalization according to one embodiment of the present invention.

[Fig. 3] shows an optical transmitter system architecture with asymmetric FFE configured to perform nonlinear (asymmetric) VCSEL equalization according to another embodiment of the present invention.

[Figure 4A-4B] shows a functional block diagram of a circuit for rising edge detection and falling edge detection proposed according to an embodiment of the present invention.

[FIG. 4C-4D] shows an example of a timing diagram of an operation of performing phase alignment of a rising edge detector according to an embodiment of the present invention.

200:Light transmitter system

202:VCSEL

210:First multiplexer

210a: Second multiplexer

210b: Third multiplexer

230: rising edge detector

240: Falling edge detector

212: First amplification stage

232: Second amplification stage

242: The third amplification stage

260: Adder

262:Light signal

270: First phase adjustment unit

272: Second phase adjustment unit

280: Clock signal generator

Claims (10)

An asymmetric feedforward equalizer for high-speed optical transmitters, including: a main driver configured to receive an input data signal and amplify the gain main driver data signal generated by the input data signal; a first phase adjustment unit configured to align the phase of the input data signal; a rising edge equalization driver configured to detect the rising edge of the input data signal and generate a first adjustment data signal; a falling edge equalization driver configured to detect the falling edge of the input data signal and generate a second adjustment data signal; a second phase adjustment unit configured to align the phase between the rising edge of the input data signal and the falling edge of the input data signal; The equalized delay module is composed of the first phase adjustment unit and the second phase adjustment unit and is configured to generate a delay by adjusting the relative phase between the first phase adjustment unit and the second phase adjustment unit. Signal used to determine equalization delay; A vertical resonant cavity surface emitting laser (VCSEL) is configured to output a linear combination signal of the gain main driving data signal, the first adjustment data signal and the second adjustment data signal. The asymmetric feedforward equalizer for a high-speed optical transmitter as claimed in claim 1, wherein the first phase adjustment unit and the second phase adjustment unit are both phase interpolators. The asymmetric feedforward equalizer for high-speed optical transmitter as described in claim 1, wherein the above main driver further includes: a first N-to-1 multiplexer that receives the input data signal and multiplexes it to generate a multiplexed input data signal; and A first amplifier stage coupled to the vertical resonant cavity surface emitting laser (VCSEL) is configured to receive the multiplexed input data signal and amplify it to generate a first amplifier stage corresponding to the gain main driver data signal. current pulse. The asymmetric feedforward equalizer for high-speed optical transmitter as described in claim 1, wherein the above-mentioned rising edge equalization driver includes: a rising edge detector configured to detect rising edge pulses of the input data signal; A second N-to-1 multiplexer coupled to the rising edge detector for receiving the rising edge pulse and using the clock signal of the second phase adjustment unit to adjust the second N-to-1 multiplexer core alignment; and a second amplification stage coupled to the rising edge detector and the vertical resonant cavity surface emitting laser (VCSEL) for generating a second current pulse corresponding to the first adjustment data signal, wherein the second current pulse Corresponds to the current signal after rising edge conversion and equalization delay of the input data signal. The asymmetric feedforward equalizer for high-speed optical transmitter as described in claim 1, wherein the falling edge equalization driver includes: a falling edge detector configured to detect falling edge pulses of the input data signal; A third N-to-1 multiplexer coupled to the falling edge detector for receiving the falling edge pulse and using the clock signal of the second phase adjustment unit to adjust the third N-to-1 multiplexer core alignment; and A third amplification stage, coupled to the falling edge detection module and the vertical resonant cavity surface emitting laser (VCSEL), for generating a third current pulse corresponding to the first adjustment data signal, wherein the third current The pulse corresponds to the current signal after falling edge conversion and equalization delay of the input data signal. The asymmetric feedforward equalizer for high-speed optical transmitter as described in claim 4, wherein the rising edge detector includes: A first pulse generator for generating a first rising signal pulse, which includes a first logical AND gate having two input terminals, one input terminal for receiving and inverting the first branch of the input data signal, and the other input terminal for receiving and inverting the first branch of the input data signal. The input terminal is used to receive the second branch of the input data signal; and A second pulse generator for generating a second rising signal pulse, which includes a second logical AND gate having two input terminals, one input terminal for receiving the first branch of the input data signal, and the other input terminal Coupled to the inverter and controlled by the received clock signal, the delay element inputs the second branch of the input data signal, wherein the first rising signal pulse and the second rising signal pulse pass through their corresponding The output terminals of the first logical AND gate and the second logical AND gate are input to the second N-to-1 multiplexer. The asymmetric feedforward equalizer for high-speed optical transmitter as claimed in claim 5, wherein the falling edge detector includes:. A third pulse generator for generating a first falling signal pulse, which includes a third logical AND gate having two input terminals, one input terminal for receiving the first branch of the input data signal, and the other input terminal for receiving the first branch of the input data signal. a second branch for receiving and inverting the input data signal; and A fourth pulse generator for generating a second falling signal pulse, which includes a fourth logical AND gate having two input terminals, one input terminal for receiving and inverting the first branch of the input data signal, and the other input terminal for receiving and inverting the first branch of the input data signal. An input terminal is coupled to a delay element controlled by receiving a clock signal, and the delay element inputs the second branch of the input data signal, wherein the first falling signal pulse and the second falling signal pulse respectively pass through their corresponding The output terminals of the third logical AND gate and the fourth logical AND gate are input to the third N-to-1 multiplexer. An asymmetric feedforward equalizer for high-speed optical transmitters, including: a main driver configured to receive an input data signal and amplify the gain main driver data signal generated by the input data signal; a first phase adjustment unit configured to align the phase of the input data signal; a rising edge equalization driver configured to detect the rising edge of the input data signal and generate a first adjustment data signal; a second phase adjustment unit configured to align the phase of the rising edge of the input data signal; a falling edge equalization driver configured to detect the falling edge of the input data signal and generate a second adjustment data signal; a second phase adjustment unit configured to align the phase between the rising edge of the input data signal and the falling edge of the input data signal; a third phase adjustment unit for aligning the phase of the falling edge of the input data signal; The equalization delay module is composed of the first phase adjustment unit, the second phase adjustment unit and the third phase adjustment unit, and is configured to adjust the relationship between the first phase adjustment unit and the second phase adjustment unit. The relative phase between the first phase adjustment unit and the third phase adjustment unit is adjusted to generate a first delay signal, and a second delay signal is generated by adjusting the relative phase between the first phase adjustment unit and the third phase adjustment unit for determining the corresponding equalization delay. ; A vertical resonant cavity surface emitting laser (VCSEL) is configured to output a linear combination signal of the gain main driving data signal, the first adjustment data signal and the second adjustment data signal. The asymmetric feedforward equalizer for high-speed optical transmitter as described in claim 1, wherein the above main driver further includes: a first N-to-1 multiplexer that receives the input data signal and multiplexes it to generate a multiplexed input data signal; and A first amplifier stage coupled to the vertical resonant cavity surface emitting laser (VCSEL) is configured to receive the multiplexed input data signal and amplify it to generate a first amplifier stage corresponding to the gain main driver data signal. current pulse. The asymmetric feedforward equalizer for high-speed optical transmitter as described in claim 1, wherein the above-mentioned rising edge equalization driver includes: a rising edge detector configured to detect rising edge pulses of the input data signal; A second N-to-1 multiplexer coupled to the rising edge detector for receiving the rising edge pulse and using the clock signal of the second phase adjustment unit to adjust the second N-to-1 multiplexer core alignment; and a second amplification stage coupled to the rising edge detector and the vertical resonant cavity surface emitting laser (VCSEL) for generating a second current pulse corresponding to the first adjustment data signal, wherein the second current pulse Corresponds to the current signal after rising edge conversion and equalization delay of the input data signal; The falling edge equalization drivers described above include: a falling edge detector configured to detect falling edge pulses of the input data signal; A third N-to-1 multiplexer coupled to the falling edge detector for receiving the falling edge pulse and using the clock signal of the second phase adjustment unit to adjust the third N-to-1 multiplexer core alignment; and A third amplification stage, coupled to the falling edge detection module and the vertical resonant cavity surface emitting laser (VCSEL), for generating a third current pulse corresponding to the first adjustment data signal, wherein the third current The pulse corresponds to the current signal after falling edge conversion and equalization delay of the input data signal.