TWI828844B - Substrate processing device and substrate processing method - Google Patents

Abstract

An object of the present invention is to suppress the load on the substrate transport mechanism and improve the processing capability of the apparatus when processing multiple batches of substrates having different required residence times for the modules. The solution is: Basis: The transfer time of the substrate corresponding to the number of transfer processes of the main transfer mechanism required to transfer the substrate loaded into the processing block to the unloading module, or the transfer time of the substrate including multiple modules and capable of performing multiple steps on the substrate The method is set in the module group of the processing block, and the necessary residence time of the substrate is divided by the number of modules that can be used in the same step, so as to obtain the time parameter for the maximum time among the times of each step. , and the necessary residence time and cycle time of the substrates of the modules constituting the multi-module set, the number of modules serving as the transfer destination for the substrates in the multi-module set and the number of residence cycles are determined.

Description

Substrate processing device and substrate processing method

This case is about a substrate processing device and a substrate processing method.

In the manufacturing process of a semiconductor device, photolithography is performed on a semiconductor wafer (hereinafter referred to as a wafer) as a substrate. A substrate processing apparatus for performing this photolithography method may be configured such that a transport mechanism sequentially transports wafers to a plurality of processing modules that perform different processes. In addition, a plurality of the same processing modules may be installed, and the same processing may be performed in parallel on the same batch of wafers.

Patent Document 1 shows that a processing block is provided with a plurality of stacked unit blocks. As described above, processing modules that perform different processes on the wafer and processing modules that perform the same process are provided in each unit block. Coating and developing device for unit block. In this coating and developing apparatus, the maximum value of the processing time of each processing module divided by the number of processing modules that perform the same processing and the shortest time for the substrate transport mechanism to cycle one unit block are determined. The longer one is the time (cycle time) for the substrate transport mechanism to circulate the unit block 1. Based on this cycle time and the processing time of the heating module included in the processing module, the number of dwell cycles of the wafer in the heating module (the number of cyclic operations of the substrate transport mechanism) is determined, and the number of wafers in the unit block is set. moving itinerary. [Prior technical literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Publication No. 2010-147424

(The problem that the invention aims to solve)

This project aims to provide a technology that suppresses the load on the substrate transport mechanism and improves the processing capability of the device when processing multiple batches of substrates that have different required residence times for the modules. (Means used to solve problems)

The substrate processing apparatus of this application is equipped with processing blocks that sequentially transport and process substrates from the upstream module to the downstream module. It is characterized by: A transport mechanism for loading and unloading, which transfers the substrates between a carrier storing the substrates and the processing block, and carries out loading and unloading of the substrates to the processing block; An unloading module for placing the processed substrates that are unloaded from the processing block by the unloading and unloading transport mechanism; A multi-module group is composed of a plurality of modules on the upstream side of the unloading module in which the order of conveying the substrates in the processing block is the same; and The main transport mechanism is equipped with a plurality of substrate holding parts that advance and retreat independently of each other for each module, circulates in the transport path provided in the processing block, and transfers the substrate between modules, If the time it takes for the main transport mechanism to make one revolution around the transport path is regarded as a cycle time, the control unit responds to the main transport required to transport the substrate carried into the processing block to the unloading module. The transport time of the substrates in the transport process of the mechanism, or the module group including the above-mentioned multiple modules and being arranged in the above-mentioned processing block in a manner that can perform multiple steps of processing on the above-mentioned substrates, the necessity of the modules for this step The residence time of the substrate is divided by the number of modules that can be used in the same step, and the time parameters of the maximum time among the times obtained for each step are obtained, and the aforementioned necessary parameters of the modules constituting the multi-module module The residence time of the substrate and the cycle time include the determination of the number of modules in the multi-module set to which the substrate is to be transported and the main transfer from after the substrate is carried into the multi-module set until the substrate is carried out. The setting of the first conveyance stroke determines the number of dwell cycles that the mechanism circulates. [Effects of the invention]

According to this aspect, when a plurality of batches of substrates with different required residence times of the modules are sequentially transported and processed, the load on the substrate transport mechanism can be suppressed and the processing capability of the device can be improved.

The coating and developing device 1 according to one embodiment of the substrate processing device of the present invention will be described with reference to the plan view of FIG. 1 and the longitudinal sectional side view of FIG. 2 . The coating and developing device 1 is configured by connecting the carrier block D1, the processing block D2, and the interface block D3 divided from each other in order from the front to the rear. Behind the interface block D3 is connected the exposure machine D4. The carrier block D1 is provided with a mounting table 11 for a carrier 10 storing a plurality of wafers W, an opening and closing portion 12 , and a transport mechanism 13 for transporting the wafers W from the carrier 10 via the opening and closing portion 12 .

The processing block D2 is composed of unit blocks E1 to E6 that perform liquid processing and heat processing on the wafer W. The unit blocks E1 to E6 are sequentially stacked from below. The unit blocks E1 to E6 are partitioned from each other. In this example, the unit blocks E1 to E3 are configured similarly to each other, and the formation of the anti-reflection film by application of a chemical solution and the formation of the resist film by application of a resist are performed as liquid processes. In addition, the unit blocks E4 to E6 are configured similarly to each other, and the resist pattern is formed by development as a liquid process. In each unit block E (E1 to E6), the wafer W is transported and processed in parallel with each other.

A description will be given of the unit block E6 shown in FIG. 1 as a representative one of the unit blocks E1 to E6. A transfer path 14 for the wafer W extending in the front-to-back direction is formed in the left and right centers of the unit block E6. Four imaging modules are provided on either side of the conveyance path 14, and each of the imaging modules is represented by DEV1 to DEV4. On the other side of the transport path 14, many heating modules equipped with hot plates are arranged in front and back, so that the placed wafer W can be heated. The temperature of the hot plate, that is, the heating temperature of the wafer W, can be changed freely. As this heating module, there are PEB (Post Exposure Bake) CSWP1 to CSWP3 that perform heat treatment before development after exposure, and CGHP1 to CGHP3 that perform heat treatment after development.

The above-mentioned transport path 14 is provided with a transport arm F6 for transporting the wafer W in the unit block E6. The transfer arm F6 has a base 21 that can move up and down, move forward and backward on the transfer path 14, and can rotate about a vertical axis. The base 21 is provided with two substrate holding portions 22 that can respectively support the wafer W. The substrate holding portions 22 can move forward and backward with respect to the base 21 independently of each other. As will be described later, when the wafer W is transported to a module on the downstream side of the transport flow, the wafer W is received from the module by advancing and retracting one of the substrate holding parts 22, and then the other substrate holding part 22 enters the module. , the held wafer W can be sent out to the module. That is, the wafer W can be transported by exchanging the wafer W in the module, and such transport is regarded as replacement transport. The module is a place where the wafer W is placed, and a module that processes the wafer W is sometimes described as a processing module.

Regarding the unit blocks E1~E3, if we focus on the differences from the unit block E6, the unit blocks E1~E3 replace the imaging modules DEV (DEV1~DEV4) and have an anti-reflection film forming module. The assembly and resist film form the module. The resist film forming module supplies a resist as a chemical solution to the wafer W to form a resist film. The anti-reflective film forming module supplies an anti-reflective film forming chemical solution to the wafer W to form an anti-reflective film. Moreover, in the unit blocks E1 to E3, instead of the heating modules CSWP (CSWP1 to CSWP3) and CGHP (CGHP1 to CGHP3), there are provided modules for respectively heating the wafer W after the resist film is formed after the anti-reflection film is formed. Heating module. In FIG. 2 , the transfer arms of the unit blocks E1 to E5 corresponding to the transfer arm F6 are shown as F1 to F5, and the transfer arms F1 to F6 of the main transfer mechanism are configured similarly to each other.

On the side of the carrier block D1 of the processing block D2, a tower T1 composed of a plurality of modules extending up and down across the unit blocks E1 to E6 and stacked on each other is provided. In this tower T1, there are handover modules TRS10, TRS20, TRS1~TRS3, temperature adjustment modules SCPL1, SCPL2, and temperature adjustment modules SCPL’1, SCPL’2.

The transfer modules TRS1 to TRS3 are set to a height where the transfer arms F1 to F3 can respectively access. The temperature adjustment modules SCPL (SCPL1, SCPL2) and SCPL’ (SCPL’1, SCPL’2) are set to a height that can be accessed by the transfer arms F4, F5, and F6 respectively. The temperature adjustment modules SCPL and SCPL' are platforms that cool the mounted wafer W and adjust the temperature. Let the temperature adjustment module that transfers the wafer W next to the heating module CSWP be SCPL, and let the temperature adjustment module that transfers the wafer W next to the heating module CGHP be SCPL'. The temperature adjustment module SCPL' is an unloading module placed in order to unload the wafers W processed in the unit blocks E4 to E6 from the unit blocks E4 to E6. In addition, a transport mechanism 15 is provided near the tower T1 so that each module constituting the tower T1 can be freely moved up and down.

Next, the relevant interface block D3 is explained. The interface block D3 has towers T2 to T4 extending up and down across the unit blocks E1 to E6. In this tower T2, most of the handover modules TRS will be stacked. Moreover, the handover module TRS is set to correspond to each height of the unit blocks E1 to E6. The handover modules corresponding to the heights of the unit blocks E1 to E3 are displayed as TRS11 to TRS13, and the handover modules corresponding to the heights of the unit blocks E4 to E6 are displayed as TRS4 to TRS6. The transfer modules TRS4 to TRS6 are loading modules for loading the wafers W into the unit blocks E4 to E6 respectively.

Towers T3 and T4 are arranged so as to sandwich tower T2 from the left and right. Towers T3 and T4 contain various modules, but illustrations and descriptions are omitted. In addition, the interface block D3 is provided with transfer mechanisms 16 to 18 for transferring the wafer W to each of the towers T2 to T4. The transfer mechanism 16 is an elevating transfer mechanism for transferring the wafer W to the tower T2 and the tower T3. The transfer mechanism 17 is an elevating transfer mechanism for transferring the wafer W to the tower T2 and the tower T4. The transport mechanism 18 is a transport mechanism for transferring the wafer W between the tower T2 and the exposure machine D4. The transport mechanisms 13, 15, 16 to 18 are transport mechanisms for transferring the wafer W between the carrier 10 and the processing block D2.

Next, the transfer flow of the wafer W in the coating and developing device 1 will be described. The wafer W is transported from the carrier 10 to the transfer module TRS10 of the tower T1 by the transport mechanism 13 . The wafer W is distributed from the transfer module TRS10 to the transfer modules TRS1 to TRS3 by the transport mechanism 15 . Then, the wafer W is taken from the transfer modules TRS1 to TRS3 through the transfer arms F1 to F3 to the unit blocks E1 to E3, and is processed by the anti-reflection film forming module → heating module → resist film forming module →Sequential transportation of heating modules. Thereby, the anti-reflection film and the resist film are sequentially formed on the wafer W. The wafer W is transported to the transfer modules TRS11 to TRS13 and transported to the exposure machine D4 by the transport mechanisms 16 and 18. The resist film is The film is exposed according to a predetermined pattern.

The exposed wafer W is taken out from the exposure machine D4 by the transport mechanism 18 and is received by the transport mechanism 17 via the module of the tower T4. The transport mechanism 17 repeatedly transports the wafer W in the order of the transfer modules TRS4, TRS5, and TRS6, and distributes the wafer W to these transfer modules. Then, the wafer W transported to the transfer modules TRS4 to TRS6 is transported by the transfer arms F4 to F6 in the heating module CSWP → temperature adjustment module SCPL → development module DEV → heating module CGHP → temperature adjustment module Sequential transfer of group SCPL'. Thereby, PEB, temperature adjustment, development, and temperature adjustment are performed sequentially on the resist film formed on the wafer W. Then, the wafer W is carried out from the unit blocks E4 to E6 by the transport mechanism 15 and transported to the transfer module TRS20 , and returned to the carrier 10 by the transport mechanism 13 .

However, when the wafer W is transferred as described above, the same plurality of modules whose transfer order is the same in the unit block E are considered to be multi-modules. Therefore, the imaging modules DEV1 to DEV4 constitute the same multi-module, the temperature adjustment modules SCPL1 and SCPL2 constitute the same multi-module, and the temperature adjustment modules SCPL’1 and SCPL’2 constitute the same multi-module. In addition, the heating modules CSWP1 to CSWP3 constitute the same multi-module group, and the heating modules CGHP1 to CGHP3 constitute the same multi-module group. Moreover, each processing process of the above-mentioned transfer flow may be described as a step. That is, each module constituting the same multi-module group is a module for executing the same steps as each other. In addition, since the transport flow is set as described above, the heating module CSWP and the temperature adjustment module SCPL are equivalent to the multi-module on the upstream side, and the development module DEV and heating module CGHP are equivalent to the multi-module on the downstream side. Mods.

Furthermore, the wafer W transported in the coating and developing device 1 is set based on the process operation (PJ). PJ is the processing prescription of the wafer W (which also includes the transportation prescription to which type of module it is to be transported to for processing) and the information specifying the wafer W to be transported. The wafers W set as the same PJ are the wafers W of the same batch that have undergone the same kind of processing. Based on the above processing recipe, the number of usable modules or the processing content are specified, and the processing time of the wafer W for each module is calculated based on the processing content. In addition, various calculations are performed according to the processing prescription, thereby calculating OHT (Over Head Time) which will be described later. In addition, the above-mentioned processing contents (processing parameters) are the temperatures of the hot plates including the heating modules CSWP1 to CSWP3 and CGHP1 to CGHP3.

Describe each parameter specified in the above treatment recipe or calculated based on the treatment recipe. The number of usable modules refers to the number of modules that can be used when processing the wafer W by configuring the same multiple modules. The following description is for the processing of the wafer W in each PJ, and all the modules mentioned are made available for use. Therefore, for example, the relevant imaging module DEV is equipped with 4 DEV1~DEV4, so the number of usable modules is 4. In addition, OHT is the total time required from the loading of the wafer W into the module until processing, and the time required from the module until the wafer W can be unloaded after processing. However, the total processing time of the wafer W of the module and the OHT is at least the necessary residence time (MUT: Module Using Time) when the wafer W stays in the module. As described above, the processing time and OHT of the wafer W are calculated based on the processing prescription, and further calculated based on the MUT.

For example, different batches of wafers W are stored in different carriers 10 . Once the release of the wafers W from one carrier 10 is completed, the wafers W from the next carrier 10 are released. In the coating and developing apparatus 1, the wafer W loaded into the apparatus is sequentially transported downstream. That is, the wafer W loaded later is transported in such a manner that the wafer W loaded first does not move toward the downstream module beyond the wafer W loaded first. Therefore, in each unit block E, the wafers W of the same batch, that is, the wafers W of the same PJ are gathered and loaded.

The transfer arms F (F1 to F6) move sequentially and cyclically between the modules accessed in the unit block E (E1 to E6), and transfer one wafer W each from the module on the upstream side to Periodic transport for module handover on the downstream side. That is, if it is the unit block E6, the transport arm F6 will repeatedly move in a circular motion on the transport path 14, repeating the temperature adjustment module from the transfer module TRS6 side of the load-in module to the unit block E6 toward the load-out module. Transfer of wafer W on SCPL' side. The time it takes for the conveyance arm F to circle the conveyance path 14 once is defined as a cycle time. Then, the order of wafers W is assigned, the order of wafers W is associated with the module to which the wafers are to be transported, and the data specifying the cycle using the above-mentioned transport arm F is arranged in time series to create a transport schedule. The wafer W is transported in the coating and developing device 1 according to a transport schedule that is prepared in advance before being loaded into the coating and developing device 1 .

In the following, in order to explain the conveyance stroke of the coating and developing device 1 and its setting method, the conveyance stroke of the comparative example will be described first. The table in FIG. 3 shows Comparative Example 1 in a case where the first batch of PJ-A wafers W and the second batch of PJ-B wafers W are set to be continuously and sequentially transported by the transfer arm F6 Moving trip. Explain the transport schedule shown in the table. One column of cells arranged in the horizontal direction represents one cycle, and the further down the table, the later the time cycle. The rows of cells arranged in the vertical direction are modules indicating the transfer destinations of the wafers W. In addition, the ID number written in the unit and the arrow extending downward from the ID number indicate which cycle, which module, and which wafer W is transported and stopped.

If we look at it specifically in terms of time series, in the cycle of the unit with the ID number, the wafer W is transported to the module, and in the cycle corresponding to the unit with the arrow, the wafer W is moved from the beginning of the cycle. Stay with the mod until the end. Then, in the cycle of the unit without an arrow next to the unit with an arrow, the wafer W is moved out from the module. Furthermore, the number of cycles in which the wafer W stays in the module is set to the number of cycles in which the wafer W stays in the module. Specifically, in the transport schedule table, the number of units with an ID number (=1) + the number of units with arrows located below the unit with the ID number = the number of dwell cycles. For example, in Figure 3, the heating module CSWP has two units with arrows arranged below the unit with the ID number, so the number of dwell cycles of the heating module CSWP is 3.

Regarding the above-mentioned ID numbers displayed as A01 to A20 and B01 to B20, the English letters indicate the PJ set on the wafer W, and the numbers indicate the order of loading into the unit block E6 of one PJ. Therefore, this transfer process represents an example in which 20 wafers W are transferred for each of PJ-A and PJ-B. In the following description, when referring to each wafer W, an ID number may be used.

Table 1 and Table 2 below show the parameters set for each module of the unit block E6 for PJ-A and PJ-B respectively.

Hereinafter, the rules applied when setting the conveyance stroke of Comparative Example 1 will be described. In Comparative Example 1, the number of dwell cycles of the wafer W in each module constituting the multi-module set, PJ-A and PJ-B, is set to be the same number as the number of usable modules constituting the multi-module set. Therefore, for PJ-A and PJ-B, the number of stay cycles of CSWP, SCPL, DEV, CGHP, and CGHP will be set to 3, 2, 4, and 3 respectively. In addition, the conveyance stroke shown in this FIG. 3 and each figure mentioned later is a conveyance stroke concerning the movement of the conveyance arm F6. Regarding the SCPL' that carries out the module from the unit block E6, the transport arm F6 only carries out the transport, and the transport of the wafer W from the SCPL' is carried out by another transport mechanism. Therefore, the number of dwell cycles for SCPL’ counts only the cycles required for loading into SCPL’, and is set to 1.

Furthermore, in Comparative Example 1, the wafers W were repeatedly transported in a predetermined order regarding the modules constituting the same multi-module group. Furthermore, regarding the cycle time, when one cycle contains only one PJ, the cycle time corresponding to that PJ is set. When one cycle contains multiple PJs, the cycle time corresponding to the slowest PJ is set. cycle time. The calculation method will be explained later. The cycle time of PJ-A is 12 seconds and the cycle time of PJB is 18 seconds. Therefore, the cycle time of each cycle of the period R0 in which both the wafer W of PJ-A and the wafer W of PJ-B are loaded into the unit block E6 is 18 seconds of the cycle time of PJ-B.

The reason why the transport stroke is set according to the above-mentioned rules is to increase the number of replacement transports for each module on the upstream side of the SCPL' of the module being moved out. As mentioned above, in the exchange transportation, since one module is loaded and unloaded with the wafer W, the more the exchange transportation is performed, the more the movement of the transfer arm F6 between the modules is suppressed, and the transfer arm F6 can be moved The number of action projects is reduced. Furthermore, as a result of the reduction in the number of operation processes of the transfer arm F6, a series of processes in the unit block E6 can be prevented from being speed-limited due to the operation of the transfer arm F6, and therefore a decrease in the processing capacity of the unit block E6 can be suppressed. In addition, the table of transfer strokes is shown based on the above-mentioned rules. Therefore, as long as a module is shown to stop other wafers W in the cycle immediately before (one before) the cycle in which one wafer W is carried in. , then the wafers W can be replaced and transported.

As is clear from FIG. 3 , in the transfer process of Comparative Example 1, each module of CSWP, SCPL, DEV, and CGHP is replaced and transferred when the transfer arm F6 accesses the modules after the second time. Then, each access to CSWP, SCPL, DEV, CGHP, and SCPL' of the transfer arm F6 in one cycle is pressed less than once. That is, the number of operation processes is suppressed for the transfer arm F6.

However, in the transfer process of Comparative Example 1, as described above, the number of dwell cycles of the wafer W constituting the multi-module set = the number of usable modules of the multi-module set. Therefore, if the number of usable modules is large, the waiting time in the module will be relatively long after the wafer W can be moved out of the module. In addition, when one cycle includes a plurality of PJs as described above, the cycle time is set to a slow PJ cycle time. Therefore, the transfer of the wafer W that can be transferred in the originally short cycle time will be slowed down. Specifically, the transfer interval of the wafer W to PJ-A of SCPL' that becomes the exit of the unit block E6 is 12 seconds before the above-mentioned period R0. However, as mentioned above, the period R0 is this The transfer interval is 18 seconds. Therefore, during the period R0 is PJ-A, the processing capability of the wafer W is reduced. In addition, regarding one PJ, if the period from the period in which the first wafer W is transported to CSWP to the period in which the last wafer W is transported to SCPL' is regarded as the residence period of PJ, then in Comparative Example 1, The stay period R1 of PJ-A is 456 seconds, and the stay period R2 of PJ-B is 576 seconds.

A transfer process having a higher processing capacity than that of the above-described Comparative Example 1 was examined. In order to achieve such a high throughput, the cycle time of each cycle is set to, for example, the smallest cycle time among the cycle times of each PJ of the wafer W transported to the unit block E6. Furthermore, the number of dwell cycles of the wafer W in each step of the transfer flow is set to the value of MUT/cycle time (the values below the decimal point are rounded up). The conveyance courses of PJ-A and PJ-B created in accordance with these rules are shown in FIG. 4 as a conveyance course of Comparative Example 2.

The conveyance course of Comparative Example 2 will be described focusing on the differences from the conveyance course of Comparative Example 1. Among the cycle times of each PJ of the wafer W transported to the coating and developing device 1, the smallest cycle time is the cycle time of PJ-A. Therefore, in Comparative Example 2, the cycle time of each cycle is set to 12 seconds of the cycle time of PJ-A according to the above-mentioned rule.

Furthermore, in Comparative Example 2, the number of dwell cycles is set according to the above-mentioned rules. Therefore, regarding the wafer W of PJ-A, the number of dwell cycles of CSWP, SCPL, DEV, and CGHP is the same as in Comparative Example 1, and is set to 3 respectively. ,2,4,3. However, regarding the PJ-B wafer W, the dwell cycle numbers of CSWP, SCPL, DEV, and CGHP are set to 4, 2, 6, and 4 respectively. Specifically, when calculating the number of dwell cycles for the CSWP of PJ-B wafer W, MUT (47.0 seconds)/cycle time (12 seconds) = 3.9. Therefore, rounding up the decimal point, the number of dwell cycles is 4. In Comparative Example 2, the number of dwell cycles in each module of PJ-A and PJ-B is different. Therefore, in Comparative Example 1, the wafer B01 is loaded in the cycle following the SCPL' in which the wafer A20 is loaded into the exit of the unit block E6 in each cycle, but in the comparative example 2, the wafer A20 is loaded several cycles later. Wafer B01. In addition, this Comparative Example 2 relates to each module constituting a multi-module set, and is set to transport the wafer W in a predetermined order set in the modules, similar to Comparative Example 1.

In Comparative Example 2, the cycle time between PJs is set to be constant as described above, and the transfer stroke is set so that the wafer W of each PJ stays in the module for the necessary number of dwell cycles calculated only based on the cycle time. This suppresses a situation in which the time from when the wafer W can be moved out from the module to when the wafer W is moved out becomes longer.

However, in Comparative Example 2, as described above, due to the setting of the cycle time and the number of dwell cycles, the step that the number of dwell cycles > the number of usable modules occurs occurs. Due to such a procedure, there may be cases where replacement and transportation are not performed in other steps within the unit block F6. Specifically, in the PJ-B imaging module DEV, since the number of dwell cycles = 6 and the number of usable modules = 4, the number of dwell cycles > the number of usable modules. Then, in order to carry out replacement and transportation of this development module DEV, there are cases where replacement and transportation are not performed in CSWP, SCPL, and CGHP. Since replacement transportation is not performed, the number of operation steps of the transportation arm F6 increases as mentioned above.

The operation of the transport arm F6 in the cycle C1 shown in FIG. 4 will be specifically described. The transfer arm F6 receives the wafer B05 from the heating module CSWP1 and sends out the wafer B08. Next, the wafer B05 is sent out to the temperature adjustment module SCPL1, but the wafer is not accepted. Next, the wafer B04 is received in the temperature adjustment module SCPL2, and the wafer W is not sent out. Then, the wafer B04 is sent to the development module DEV4, and the wafer W is not received. Then, the wafer A19 is received in the heating module CGHP1, and the wafer W is not sent out. Then, the wafer A19 is sent to the temperature adjustment module SCPL'1. In this way, the transfer arm F6 transfers the wafer W to both SCPL1 and SCPL2 in one cycle. That is, this cycle C1 is a cycle in which the operation process of the transport arm F6 is many compared with the cycle of Comparative Example 1. As shown in the figure, in addition to this cycle C1, there are also cycles in which there are many operation processes of the transfer arm F6, just like this cycle C1.

The conveyance stroke of Embodiment 1 shown in FIG. 5 is set so that it can reduce the number of conveyances which would not become such a replacement conveyance. Regarding the transfer process of Example 1, the cycle time and the number of dwell cycles are determined in the same manner as the transfer process of Comparative Example 2, but the transfer destination of the multi-module wafer W is set according to different rules from Comparative Example 2.

Hereinafter, in Example 1, the rules for determining the transfer destination of the wafer W will be described. In this Embodiment 1, according to the order in which each wafer W is carried into the unit block E6, which module among the plurality of modules constituting the multi-module set is determined as the transfer destination. Then, regarding the determination of the transfer destination, first, it is determined which multi-module sets can be used in the cycle (for convenience of explanation, this is regarded as the reference cycle) that the wafer W is transferred to the multi-module set at the determined transfer destination. , can be moved to several modules. That is, it is determined how many modules are not occupied by the wafer W when the wafer W is transported in the reference period. As a result of this judgment, if there is only one transportable module among multiple modules, the transportable module is determined as the transport destination.

On the other hand, when there are a plurality of modules determined to be transportable among multiple module groups, among the modules determined to be transportable, the cycle closest to the reference cycle precedes the wafer W to which the transport destination is determined. The module from which the wafer W transported to the multi-module group is transported. As the period closest to this base period, periods identical to the base period are also included. Furthermore, the module that is judged to have been moved out of the wafer W in such a recent period is determined as the transfer destination of the wafer W. Regarding each wafer W of PJ-A and PJ-B, the transfer destination of each wafer W is further determined based on such a rule for each multi-module.

For example, in SCPL (SCPL1, SCPL2), when determining the transfer destination of wafer W in the order of wafers A01, A02･･･A20, and B01･･･B20, determining the transfer destination of wafer B04 will be explained specifically. project. In FIG. 5 , the cycle in which wafer B04 is transferred to SCPL is shown as C2. In this example, cycle C2 is the above-mentioned reference cycle. As shown in the table of the transfer process, in the cycle one before cycle C2, wafer B02 is carried out from SCPL1, and in cycle C2, wafer B03 is carried out from SCPL2. Therefore, wafer B04 can be transported in either SCPL1 or SCPL2. Moreover, from the perspective of cycle C2, SCPL2 is closer to the cycle in which wafer W is moved out than SCPL1, and is the same as cycle C2. Therefore, SCPL2 is decided as the transfer destination of wafer B04.

In the conveyance course (second conveyance course) of this Example 1, the residence period R1 of PJ-A is 384 seconds, and the residence period R2 of PJ-B is 540 seconds. Therefore, when the conveyance stroke of Example 1 is compared with the conveyance stroke of Comparative Example 1, both the residence periods R1 and R2 are shorter than the conveyance stroke of Example 1. Moreover, if the conveyance course of Example 1 and the conveyance course of Comparative Example 2 are compared, the residence period R1 of PJ-A and the residence period R2 of PJ-B are the same as each other. However, in Example 1, the transfer destination of the wafer W is set as described above. Therefore, as is clear from comparing FIGS. 4 and 5 , the transfer steps of Example 1 require more replacements than the transfer steps of Comparative Example 2. The number of transfers. Therefore, in the transportation process of this embodiment 1, the load on the transportation arm F6 is suppressed, and the processing capability of the unit block E6 can be improved.

However, the already mentioned FIG. 5 is a table showing the transfer strokes in which the temperatures of PJ-A, PJ-B, and the hot plate of the heating module CGHP (the heating temperature of the wafer W) are determined to be the same as each other. Hereinafter, regarding PJ-A and PJ-B, a case where the temperatures of the hot plates of the heating module CGHP are different from each other will be described. In this case, a rule (as a normal rule) different from the rule explained in FIG. 5 (as a normal rule) is applied to the wafers W counting from the front in PJ-B as the number of usable modules of the heating module CGHP. Exception rules), determine which of CGHP1~CGHP3 will be used as the transfer destination. Since the number of usable modules of the heating module CGHP is 3, exception rules apply to the three wafers B01~B03. In addition, regarding the wafer W of PJ-A and the wafer W of PJ-B other than wafers B01 to wafers B03, normal rules are applied to determine the transfer destination.

The exceptions to the above rules will be explained focusing on their differences from the normal rules. If the cycle in which the wafer W, which is determined to be transported, is transported to the multi-module is used as the reference cycle, then the cycle that is farthest (farthest in time) from the reference cycle is determined, and the wafer W that is transported to the multi-module first is moved out. Which module is it. Then, the module judged to have moved the wafer W in the farthest cycle is determined as the transfer destination of the wafer W.

The process of applying exception rules to determine the transfer destination of wafers B01 to B03 will be described with reference to FIG. 6 . In addition, for the convenience of explanation, the number of residence cycles of PJ-B of CGHP is shown as 2 in FIG. 6 . Furthermore, the cycles in which wafers B01, B02, and B03 are transported to the CGHP are respectively C3, C4, and C5. That is, the cycles C3 to C5 are the reference cycles for determining the transfer destinations of the wafers B01 to B03.

First, decide where to transport wafer B01. From the table in FIG. 6 , wafer B01 can be transferred to any one of CGHP1 to CGHP3. However, among CGHP1 to CGHP3, wafer W (A18) is transferred in the cycle farthest from cycle C3. Therefore, the transfer destination of wafer B01 is determined to be CGHP3. Next, decide where to move wafer B02. Wafer B02 can be transferred to any one of CGHP1 and CGHP2. However, among CGHP1 and CGHP2, wafer W (A19) is unloaded in the cycle furthest from cycle C4. Therefore, the transfer destination of wafer B02 is determined to be CGHP1. Next, the transfer destination of wafer B03 is determined. Wafer B03 can be transferred to either CGHP2 or CGHP3. However, among CGHP2 and CGHP3, wafer W (A20) is unloaded in the cycle furthest from cycle C4. Therefore, the transfer destination of wafer B03 is determined to be CGHP2.

In addition, if the relevant exception rules are first supplemented, as mentioned above, in the cycle farthest from the reference cycle, the module from which the wafer W is transported to the multi-module group first is determined as the transport destination. The wafer W carried out from this module means the wafer W carried out from each module in the cycle closest to each reference cycle. Therefore, in the transfer process of FIG. 6 , CGHP1 to CGHP3 are carried out before wafers A18 to A20, and wafers A15 to A17 are carried out. However, as mentioned above, wafer B01 is determined based on the carrying status of wafers A18 to A20. ~The moving destination of B03.

The reason why wafers B01 to B03 are transported according to such an exception rule is that after the heating module CGHP completes the processing of the wafer W of PJ-A and until the wafer W of PJ-B is transported, Adjust the temperature of the hot plate to stabilize the temperature. In addition, for example, when the temperature of the hot plate of the heating module CSWP is different between PJ-A and PJ-B, this exception rule is also applied to determine the transfer destination of the wafer W.

Further explanation will be given on setting examples of other conveyance strokes. When setting the transfer schedule described below, the transfer mechanism 17 of the transfer modules TRS4 to TRS6 that transfers the wafer W to the transfer module to the unit block is set to be synchronized with the cycle time of the unit block E4 to E6. Action person. Specifically, the transport mechanism 17 repeatedly and sequentially transports the wafers W to the transfer modules TRS4 to TRS6 as described above, but transports one wafer W every one cycle. That is, one wafer W is transferred to each of the unit blocks E4 to E6 every three cycles. Furthermore, for convenience of explanation, regarding PJ-A, parameter values different from the parameter values shown in Table 1 above are shown in Table 3. The cycle time of PJ-A shown in Table 3 is the same as that of PJ-A shown in Table 1, which is 12 seconds, and is the smallest among the PJs of the wafer W transported to the unit block E6.

This cycle time is used to determine the number of dwell cycles for each module according to the same rules as Comparative Example 2. By performing the above-mentioned calculations, the dwell cycle numbers of CSWP, SCPL, DEV, CGHP, and SCPL' of PJ-A in Table 3 are 8, 2, 11, 2, and 1 respectively. Use this as the number of dwell periods before correction. 7 shows PJ-A using the dwell cycle number before correction and setting the wafer W to the unit block E6 of each module constituting the multi-module set in a predetermined order in the same manner as Comparative Examples 1 and 2. moving itinerary. The conveyance stroke is given as Comparative Example 3.

The conveyance stroke of Comparative Example 3 is as shown in FIG. 7 , and is set so that conveyance other than replacement conveyance is performed relatively frequently. Then, the above-mentioned correction of the dwell cycle number is performed for each module on the upstream side of the SCPL' of the unloaded module. This correction is performed so that the value of the dwell period before correction is equal to or greater than the value of N, and is an integer multiple of N, and, for example, the value after correction is as small as possible. The wafer W is transported once in N cycles (N is an integer). Unit block E6. As mentioned above, this example is N=3. Therefore, for CSWP, SCPL, DEV, and CGHP, the number of stay periods that were 8, 2, 11, and 2 before the correction were corrected to 9, 3, 12, and 3 respectively.

FIG. 8 is a conveyance stroke of PJ-A set using the number of dwell cycles corrected in this way, as a conveyance stroke of Comparative Example 4. The transport stroke of Comparative Example 4 is for transporting the modules constituting the multi-module group, and is set to be transported in a predetermined order similarly to Comparative Examples 1 to 3. As is clear from FIGS. 7 and 8 , in the transfer process of Comparative Example 4, the number of replacement transfers is greater than in the transfer process of Comparative Example 3. Therefore, compared with Comparative Example 3, the unit block E6 can be improved. processing power.

After correcting the dwell cycle number in the same manner as in Comparative Example 4, the transfer destination of the wafer W is determined using the normal rules and exception rules described in Example 1, thereby setting the transfer stroke. That is, the procedures for calculating the number of dwell cycles, correcting the calculated dwell cycle number, and determining the transfer destination of the wafer W are executed, and the transfer stroke is set. FIG. 9 is a conveyance course of PJ-A set by such a program as a conveyance course of Embodiment 2. As is clear from FIGS. 8 and 9 , in the transfer process of Example 2, compared with Comparative Example 4, the number of replacement transfers is performed more, so the processing capacity of the unit block E6 can be further improved. In addition, as mentioned above, the unit blocks E4 to E6 are configured similarly to each other. Therefore, the unit blocks E4 and E5 are also set to the same transfer stroke as the unit block E6, so that the processing capabilities of the unit blocks E4 to E6 can be improved.

FIG. 10 shows the transfer stroke of PJ-A in Table 3 as the transfer destination of the wafer W, which is set according to the rule explained in the first embodiment without correcting the number of dwell cycles, as the transfer stroke of the third embodiment. That is, the transfer schedule of the third embodiment is set by executing a program that calculates the number of dwell cycles and determines the transfer destination of the wafer W. When Example 2 and Example 3 are compared with each other, the number of times of replacement conveyance in the conveyance process of Example 2 is larger. Therefore, it is more preferable to set the transfer stroke by a process of calculating the number of dwell cycles, correcting the number of dwell cycles, and determining the transfer destination of the wafer W, as in the second embodiment. In addition, in Examples 2 and 3, only the transfer process of the PJ-A wafer W is exemplified. However, similarly to Example 1, the transfer process is also set for other PJ wafers W.

Returning to FIG. 1 , the control unit 100 provided in the coating and developing device 1 will be described. The control unit 100 is a computer and has installed programs stored in storage media such as CDs, hard disks, memory cards, and DVDs. The installed program outputs control signals to each part of the coating and developing device 1 . Therefore, commands (each step) are incorporated into the program to enable the transportation and processing of the wafer W as described above. Furthermore, this program sets the conveyance stroke in the same program as the program for setting the conveyance stroke in Example 2 of FIG. 9 . Therefore, each judgment regarding the setting of the conveyance stroke described in each Example and each Comparative Example is performed by this program.

In addition, the control unit 100 includes a data receiving unit and a memory. The data receiving unit is, for example, connected to a host computer that controls the transportation of the wafer W to the coating and developing device 1 . Furthermore, the data receiving unit receives information about the wafer W sequentially transferred to the coating and developing device 1 from the host computer. Various related data are stored in the memory, so that the above-mentioned PJ can be generated based on the information obtained in this way, and the above-mentioned processing prescription and the designation of the wafer W to be transferred can be performed. Furthermore, for example, the cycle time commonly used in the transportation of each PJ is stored in the memory in advance. That is, the memory stores various types of information necessary for setting the transport schedule described in the above-mentioned embodiment.

FIG. 11 is a flowchart showing the setting flow of the conveyance stroke of the unit block E6 implemented by the control unit 100 described above. First, information on each PJ of the wafer W transported to the unit block E6 is obtained. Then, as explained in detail in Comparative Example 2, for CSWP, SCPL, DEV, and CGHP, the number of dwell cycles is calculated for each PJ based on the MUT (processing time + OHT) specified in PJ and the cycle time memorized in the memory. (Step S1).

Next, as described in detail in Comparative Example 3, the calculated number of dwell cycles is corrected based on the loading interval of the wafer W into the unit block E6 (step S2). Then, using the corrected number of dwell cycles, as described in detail in Embodiment 1, the transfer destination of the wafer W carried into the unit block E6 is sequentially determined using the general rules and exception rules described above. That is, the transfer destination of the wafer W that is subsequently transferred to the multi-module is determined based on the cycle in which the wafer W that was first transferred to the multi-module is transferred out of the multi-module. In this way, the transportation destination of the multi-module group of each wafer W is determined, and the transportation stroke is set (step S3). After the transfer stroke is set, the wafer W of each PJ is transferred and processed according to the transfer stroke.

According to the above-mentioned coating and developing device 1, the conveyance stroke is set as described in the above-mentioned flow. According to this transfer process, the wafer W can be suppressed from staying in the module for a long time after being transferred from the module, and by performing frequent exchange transfers, the load on the transfer arms F4 to F6 can be suppressed. As a result, the processing capabilities of the unit blocks E4 to E6 can be improved. In addition, in the coating and developing device 1, the conveyance stroke of the second embodiment is set, but the conveyance stroke of other embodiments may be set. Therefore, the correction of the dwell cycle number in step S2 of the flow of FIG. 11 may not be performed. However, as mentioned above, it is ideal to perform the correction in order to reliably improve the processing capability.

However, in the unit block E6 described above, an exposure module including a light irradiation part for irradiating the entire resist film on the surface of the wafer W may be laminated on the heating modules CSWP and CGHP, for example, as a multi-mode module. group. After the exposure module is PEB, the resist film on the surface of the wafer W before development is exposed. By exposure using the exposure module, the total amount of exposure energy supplied to the portion of the resist film exposed by exposure machine D4 alone exceeds the reference value and deteriorates, so that a resist pattern is formed during development. The irradiation intensity of light to the wafer W is set to be freely changeable by the light irradiation part of the exposure module.

Furthermore, the irradiation intensity of the light irradiation part is also included as the processing parameter specified in PJ. Furthermore, as shown in FIG. 5 and others, the wafer W of PJ-A and the wafer W of PJ-B are continuously transported to the unit block E6, and the irradiation intensity between PJ-A and PJ-B is different. . That is, after the PJ-A wafer W is processed and before the PJ-B wafer W is processed, the exposure module changes the irradiation intensity. In this case, the same exception rule applies as when changing the temperature of the hot plate between PJs, and each wafer W of PJ-B can determine which of the plurality of exposure modules should be transported. By determining the transfer destination in this way, the PJ-B wafer W can be processed in a stable state with the irradiation intensity changed.

That is, when predetermined process parameters such as the temperature of the hot plate or the irradiation intensity are set to different values between PJ, the control unit 100 can be configured to apply the above-mentioned exception rules to determine the wafer W. Moving place. In addition, regarding the exposure module, in order to remove unnecessary resist films, only the peripheral portion of the wafer W may be exposed before development.

However, in Comparative Example 1, the cycle time corresponding to each PJ is determined such that PJ-A is 12 seconds and PJ-B is 18 seconds. This cycle time is determined so that the transfer arm F can access the unit block E once per cycle, and the processing capacity of the unit block E becomes a bottleneck for multi-modules. More specifically, for each module, a division value of the MUT divided by the number of usable modules is obtained, and the cycle time is set to a value greater than or equal to the maximum value among the obtained division values.

If explained specifically, from the above Table 1, for the above-mentioned divisor values of PJ-A, the CSWP is 36.0 seconds/3=12.0 seconds, the SCPL is 22.5 seconds/2=11.25 seconds, and the DEV is 47.0 seconds /4=11.75 seconds, CGHP is 33.0 seconds/3=11.0 seconds, SCPL' is 19.0 seconds/2=9.5 seconds. Therefore, the maximum value among the obtained divided values is 12.0 seconds of CSWP, and this 12.0 seconds is set as the cycle time of PJ-A.

Moreover, from the above Table 2, for the above-mentioned divisor values of PJ-B, the relevant CSWP is 47.0 seconds/3=15.66 seconds, the relevant SCPL is 22.5 seconds/2=11.25 seconds, and the relevant DEV is 72.0 seconds/4=18.0 Seconds, the relevant CGHP is 47.0 seconds/3=15.6 seconds, and the relevant SCPL' is 19.0 seconds/2=9.5 seconds. The maximum value among the obtained divided values is 18.0 seconds of DEV, and this 18.0 seconds is set as the cycle time of PJ-A.

In this way, the cycle time can be calculated based on the above-mentioned treatment recipe and the parameters specified in the treatment recipe. Therefore, the minimum value among the cycle times of each PJ estimated to be transported to the coating and developing device 1 is not limited to being stored in the memory of the control unit 100 in advance. That is, the cycle time is not limited to being stored in the memory when the device is started. After the apparatus is started, the control unit 100 that receives information on each PJ of the wafer W being transported to the apparatus can calculate the cycle time from each PJ, select the smallest one among the calculated cycle times, and set the transport stroke. Furthermore, the smaller of the cycle time obtained from one PJ and the cycle time obtained from other PJs may be used for setting the conveyance stroke. That is, not only the smallest cycle time among the cycle times obtained from a plurality of PJs is used for setting the conveyance stroke.

In addition, the multi-module may be installed in the tower T2 of the interface block D3, for example. When the multi-module is installed in this way, the installation location of the multi-module is also included in the processing block. That is, the multi-module group is within the accessible range of the transfer arm F, and the place where the multi-module group is installed is included in the processing block.

However, this method is not limited to the setting of the conveying stroke that is applied to the unit blocks E4 to E6. For example, the setting of the conveying stroke of the unit blocks E1 to E3 can also be applied. The number of unit blocks is not limited to the above-mentioned number, and the processing blocks may also be divided into plural units as unit blocks. Furthermore, the module mounted on the processing block is not limited to the above-mentioned example, and therefore the substrate processing device of the present invention is not limited to the coating and developing device 1 . For example, a module for applying a chemical solution for forming an insulating film, a module for supplying a cleaning solution for cleaning the wafer W, a module for supplying an adhesive for bonding the wafers W to each other, etc. may be provided. The device structure of the processing block.

In addition, various setting examples have been described regarding the cycle time (CT), but the cycle time (CT) is not limited to the above-described setting examples. For example, in the coating and developing device 1 , the CT corresponding to a specific PJ that is expected to be designated relatively frequently may be used as a common CT when setting the transfer stroke of the wafer W for each PJ. That is, when a common CT is set for a plurality of PJs, the conveyance stroke is not limited to the one with a shorter time selected among the CTs corresponding to each PJ designated by the coating and developing device 1 .

However, the unit blocks E1 to E3 of the coating and developing device 1 are configured in the same manner as the unit blocks E4 to E6 except for the type of module to be mounted. Furthermore, the unit blocks E1 to E3 are configured similarly to each other, and the wafer W is processed in the same manner as each other. In the example shown in Figure 12, the unit blocks E1 to E3 are equipped with the temperature adjustment module SCPL, the resist film forming module COT, the heating module CGHP, the peripheral exposure module WEE, and the transfer module TRS. The wafer W is transported in sequence. Moreover, in one unit block, two temperature adjustment modules SCPL and resist film forming module COT are each installed, three heating modules CGHP are each installed, and peripheral exposure modules WEE and transfer modules TRS are installed 1 each. Moreover, the relevant MUTs are the temperature adjustment module SCPL is 28 seconds, the resist film forming module COT is 67.1 seconds, the heating module CGHP is 77.0 seconds, and the peripheral exposure module WEE is 18.0 seconds.

The value obtained by dividing the MUT of modules in the same step by the total number of modules usable between unit blocks is set as the MUT cycle time (MUTCT). The MUTCT for the case where there are no unusable modules is SCPL is 28.0 seconds/6≒4.67 seconds, COT is 67.1 seconds/6≒11.18 seconds, CGHP is 77.0 seconds/9≒8.56 seconds, and WEE is 18.0 seconds/3=6.0 seconds , of which 11.18 seconds of COT is the maximum value (maximum time). Therefore, the processing capacity of the unit blocks E1 to E3 is limited by the processing speed of the COT if the arm cycle time does not take into account the transfer time of the substrate described later.

On the other hand, if the number of transfer processes (number of arm processes) of the transfer arms F1 to F3 in the unit blocks E1 to E3 is large, then the transfer operation of the wafer W using the transfer arms F1 to F3 is not performed by the module. It will become the speed limit of the processing capacity of unit blocks E1~E3. The number of arm processes is the number of processes of the transfer arm F required to transport the substrate carried into the processing block (unit block) to the unloading module of the processing block (unit block). In this example, the wafer W is transferred between five modules: SCPL (import module) → COT → CGHP → WEE → TRS (import module), so the number of arm processes is the number between these modules. The time required for the 4.1 arm project is determined in advance, for example, it is set to 3.7 seconds. Moreover, if it is assumed that arm cycle time (ACT) = number of arm processes × setting time ÷ number of stacks of the corresponding unit blocks, then the ACT of each unit block E1 to E3 is 4 × 3.7 ÷ 3 ≒ 4.9 seconds. In this way, ACT corresponds to the number of transfer processes of the transfer arm F and the number of stacked unit blocks N (N is an integer) for performing the same processing on the wafer W.

If you compare the maximum value of MUTCT with ACT, in this example, the maximum value of MUTCT, 11.18 seconds, is longer than the 9.2 seconds of ACT. Therefore, in this example, it is not the operations of the transfer arms F1 to F3 that limit the productivity of the unit blocks E1 to E3, but the processing of the resist film forming module COT. Compare the maximum value of MUTCT and ACT in this way, and use the larger one as the block cycle time (block CT). Therefore, in this example, 11.18 seconds of COT’s MUTCT is the block CT. That is, the block CT is the block through which the wafer W passes (here, the unit blocks E1 to E3). In the cycle of processing the wafer W, the time required most among the modules and the transfer arm is parameters.

However, as mentioned above, the unit blocks E1 to E3 are configured identically to each other. Therefore, when all modules are used, the ratio of the number of wafers W to be loaded is equalized among the unit blocks E1 to E3. The case of wafer W has the highest processing capability. However, the module cannot be used. In this case, it is considered that the control unit 100 changes the above-mentioned ratio of the number of loaded pieces between the unit blocks E1 to E3 so as to correspond to the number of usable modules. Specifically, for example, if 1 CGHP in unit block E3 is unusable, and the total number of CGHPs in unit blocks E1 to E3 becomes 8, then the ratio of the number of imported slices can be considered to be changed to unit block E1. :E2:E3=3:3:2.

However, even if one CGHP becomes unusable, the MUTCT of this CGHP is 77.0 seconds/8≒9.63 seconds, which is smaller than the MUTCT of the above-mentioned COT of 11.18 seconds. In other words, without changes in block CT, the processing capabilities of the relevant unit blocks E1~E3 are still not affected by COT. Therefore, changing the ratio of the number of loaded wafers W corresponding to the number of CGHPs described above is not an appropriate change, and if this change is made, the processing capabilities of the unit blocks E1 to E3 will be reduced. Next, Example 5 regarding appropriately setting the ratio of the number of wafers W loaded between the unit blocks E1 to E3 will be described.

(Example 4) Next, the method of setting the dwell cycle number of each multi-module unit in accordance with the above-mentioned block CT procedure in order to exchange and transport the multi-module unit in each step will be explained focusing on the differences from the above-described embodiments. Example 4. This Embodiment 4 shows the setting method of the conveyance stroke of PJ-A and PJ-B of the unit block E6 mentioned above. If we describe the outline of this Embodiment 4, the number of modules used in the multi-module of each step will not reduce the processing capability of the unit block E6, and the number of modules will be smaller, as the necessary modules. The number is determined. Then, the number of dwell cycles of the wafer W in the modules of each step is determined based on the determined necessary number of modules.

The cycle time (CT) is set to 12 seconds, and the CT of each block of PJ-A and PJ-B is 18.5 seconds. Table 4 and Table 5 below show parameters related to PJ-A and PJ-B respectively. The calculation method of the necessary number of dwell cycles, the number of necessary modules, the correction value, and the number of dwell cycles described in the table is explained below. In addition, unlike Embodiment 5 in which the wafer W is transported in each of the unit blocks E4 to E6 having the same configuration, this Embodiment 4 is limited to the transport stroke of E6 among the unit blocks E4 to E6. Setting example.

This will be explained with reference to Fig. 13 . First, as the program R1, the number of dwell cycles (integer value) necessary for processing is calculated in the module of each step. This number of dwell cycles is the operation MUT/CT. If the value below the decimal point of this operation value is not 0, it is carried as the number of necessary dwell cycles. If the example specifically shows the calculation used to obtain the number of dwell cycles for CSWP, the number of dwell cycles in PJ-A = 36.0 seconds/12 seconds = 3, and the number of dwell cycles in PJ-B = 47.0 seconds/12 seconds = 3.9 ≒4.

Then, as program R2, the number of modules (integer value) necessary to comply with the block CT of each step is calculated. Specifically, the MUT/block CT of the module of each step is calculated, and when the value below the decimal point of the calculated value is not 0, it is rounded up and used as the necessary module number. In other words, this program R2 is a program that determines how many modules to use among the usable modules, but as mentioned above, the block CT determined by MUTCT and ACT is not changed and the number is minimized. Decide on the number of modules.

If the example specifically shows the calculation example used to obtain the necessary module number for CSWP, in PJ-A it is the number of necessary modules = 36.0 seconds/18.5 seconds = 1.94≒2, and in PJ-B it is the number of necessary modules = 47.0 Seconds/18.5 seconds=2.54≒3. The number of necessary modules is the value corresponding to MUT/CT (the calculated value itself, or the value rounded up below the decimal point). In addition, this Embodiment 4 is different from the Embodiment 5 described later in which the wafer W is allocated to the unit blocks E4 to E6. As mentioned above, the wafer W only passes through E6 among the unit blocks E4 to E6. Therefore, when calculating the number of dwell cycles described later, the value calculated here is used as it is. In addition, the modules to be used are determined in order of the smallest numbers preset for the modules constituting the multi-module set so that the number is determined as the number of necessary modules. Therefore, the determination of this necessary number of modules is equivalent to the decision of the modules used.

After executing the programs R1 and R2, the calculation result of the program R1/the calculation result of the program R2 is calculated as a correction value for the module of each step. When the value below the decimal point of the operation value is not 0, carry is carried out, and the relevant correction value is also calculated as an integer value. The correction value calculated in this way is equivalent to the number of cycles that the wafer W needs to be replaced in the module once in order to comply with the above-described block CT (without changing the block CT). Then, after acquiring each correction value for each module, the maximum value (maximum correction value) is selected from among the acquired correction values. That is, in the modules of all steps, the number of cycles that can replace the wafer W at least once is determined as the maximum correction value. Let the series of programs that obtain this maximum correction value be R3.

If the calculation of the correction value for each step of PJ-A is specifically shown, the correction value of CSWP=3/2=1.5≒2, the correction value of SCPL=2/2=1, and the correction value of DEV=4 /3=1.33≒2, CGHP’s correction value=3/2=1.5≒2. The maximum value among them is 2 for CSWP, DEV, and CGHP, so 2 is determined as the maximum correction value. Similarly, if the calculation of the correction value of each step of PJ-B is specifically shown, the correction value of CSWP=4/3≒2, the correction value of SCPL=2/2=1, and the correction value of DEV=6/4≒ 2. The correction value of CGHP=4/3≒2. Among them, the maximum values are two related to CSWP, DEV, and CGHP, so these two are determined as the maximum correction value.

Then, as the program R4, a calculation using the following Mathematical Expression 1 is performed on the module of each step, and the calculated value using the Mathematical Expression 1 is determined as the dwell cycle number. In order to perform replacement transportation for a certain module, it is necessary to set the number of dwell cycles to a multiple of the number of modules necessary for that module. By using the above-mentioned maximum correction value as this multiple, it is possible to perform the process as a module that can be used in all steps. Replace the number of dwell cycles for transportation. The maximum correction value calculated in program R3 × the number of necessary modules calculated in program R2 = the number of dwell cycles･･･Equation 1

Specifically, for PJ-A, the number of stay periods for CSWP = 2×2=4, the number of stay periods for SCPL = 2×2=4, the number of stay periods for DEV = 3×2=6, and the number of stay periods for CGHP Number of dwell cycles = 2×2=4. Similarly, regarding PJ-B, the number of dwell periods of CSWP = 3×2=6, the number of dwell periods of SCPL = 2×2=4, the number of dwell periods of DEV = 4×2=8, and the number of dwell periods of CGHP are respectively determined. Number=3×2=6.

Once the necessary number of modules and the number of dwell cycles are determined in this way, transfer destinations are sequentially assigned to each PJ starting from the wafer W with the smallest number. When the number of necessary modules is plural, that is, when a plurality of modules are determined to be used, the transfer stroke is set so that the wafer W can be repeatedly transferred in sequence to the determined module to be used. That is, for example, for PJ-A, if CSWP1 and CSWP2 among the CSWPs are determined as the modules to be used, the transfer stroke is set so that the wafer W can be transferred in the order of CSWP1, CSWP2, CSWP1, and CSWP2･･･.

FIG. 14 shows the conveyance strokes (first conveyance stroke) of PJ-A and PJ-B of the unit block E6 that are set after determining the necessary number of modules for each step and the number of dwell cycles for each step as shown in Table 4. ). As shown in the table of the transfer course in FIG. 14 , in the unit blocks E1 to E3, replacement transfer is performed in each of CSWP, SCPL, DEV, and CGHP. In addition, in these modules, the wafer W is transferred every time it is unloaded. Therefore, by setting the transport stroke in this way, the load on the transport arm F6 can be suppressed, thereby improving the processing capability of the unit block E6.

(Example 5) Next, a setting example of the conveyance strokes of the unit blocks E1 to E3 having the same configuration will be described as Embodiment 5, focusing on differences from Embodiment 4. In this Embodiment 5, the ratio of the number of wafers W loaded in will be appropriate between the unit blocks E1 to E3, and the ratio is determined based on the blocks CT and MUT and the number of usable modules. settings. In this Embodiment 5, similarly to Embodiment 4, the procedures R1 to R4 are performed so that the modules in each step can be exchanged and transported, and the number of necessary modules and the number of dwell cycles are calculated.

In addition, for the sake of convenience of description, the unit blocks E1 to E3 of this embodiment 5 include module groups of different types from the example shown in FIG. 12 . Specifically, they are equipped with temperature adjustment module SCPL, resist film forming module COT, heating module CPHP, temperature adjustment module SCPL', chemical liquid coating module ITC, heating module CGHP, and peripheral exposure module. WEE and transfer module TRS transport wafer W in this order. The temperature adjustment modules SCPL and SCPL' are provided in the tower T1, for example. Furthermore, the temperature adjustment module SCPL is a module for loading the wafers W into the unit blocks E1 to E3, and the wafers W are transported by the transport mechanism 15 . That is, once the ratio of the number of wafers W loaded between the unit blocks E1 to E3 is determined, the transfer of the SCPL to the unit blocks E1 to E3 by the transport mechanism 15 is controlled based on this determination. .

The transfer module TRS is an unloading module (export) for unloading the wafer W from the unit blocks E1 to E3, and is installed in the tower T2. The chemical coating module ITC is a liquid processing module that applies a chemical liquid for forming a protective film to protect the resist film to the wafer W. COT and ITC are set at positions corresponding to DEV in unit blocks E4~E6, and CPHP, CGHP, and WEE are set at positions corresponding to CSWP and CGHP in unit blocks E4~E6. Location.

The setting numbers of SCPL, COT, CPHP, SCPL’, ITC, CGHP, WEE, and TRS for one unit block are 2, 2, 4, 2, 2, 4, 1, and 2 respectively. Moreover, the processing times of SCPL, COT, CPHP, SCPL’, ITC, CGHP, and WEE are 20.0 seconds, 55.0 seconds, 75.0 seconds, 30.0 seconds, 65.0 seconds, 75.0 seconds, and 10.0 seconds respectively. Further, the MUTs of SCPL, COT, CPHP, SCPL’, ITC, CGHP, WEE, and TRS are 28.0 seconds, 62.0 seconds, 87.0 seconds, 32.5 seconds, 72.0 seconds, 87.0 seconds, and 18.0 seconds respectively. In addition, the cycle time (CT) is set to 10 seconds.

Table 6 and Table 7 below are a collection of parameters calculated for setting the conveyance stroke of the unit blocks E1 to E3 in a state where CT or MUT is set as described above. When setting this transfer schedule, the COT of the unit block E1 is set to 1, and the CGHP of the unit block E2 is set to 2, and each is unusable. That is, the number of COTs available in the unit block E1 is 2, and the number of CGHPs available in the unit block E2 is 2.

The calculation procedures for each parameter described in Table 6 and Table 7 will be described below. The MUTCT shown in Figure 12 is calculated from the MUT and the number of usable modules. The calculation method of MUTCT for COT and CPHP will be explained in detail representatively. Regarding COT, the total number of modules that can be used in unit blocks E1~E3 is 1+2+2=5. Therefore, COT's MUTCT=62.0 seconds/5=12.4 seconds. Regarding CPHP, the total number of modules that can be used in unit blocks E1~E3 is 4+4+4=12. Therefore, the MUTCT of CPHP=87.0 seconds/12≒7.3 seconds. The MUTCT is calculated in the same way for other modules, but the TRS for the exit from the unit block is the same as the SCPL' of the unit block E4 to E6, and the number of dwell cycles is fixed to 1, so the MUTCT is calculated and used. The parameters of programs R1 to R4 are not calculated.

The MUTCT for each module is calculated in this way, and the maximum value is selected from the calculated value. In this example, the MUTCT of COT is the maximum value. Then, as mentioned above, ACT (arm cycle time) = number of arm processes × setting time / number of stacks of unit blocks E1 to E3 = 7 × 3.7 seconds ÷ 3 = 8.63 seconds, and the size is compared. For comparison, since the MUTCT of COT is larger, this MUTCT is decided to be the block CT. In addition, as mentioned above, if the ACT of the time required for the operation of the transport arm is large, this ACT is used as the block CT.

Next, as the program R1, the number of dwell cycles necessary for the module processing of each step is calculated. That is, MUT/CT is calculated. Specifically, a program example for calculating the number of dwell cycles of COT and CPHP is shown. The necessary number of dwell cycles for COT = 62.0 seconds/10 seconds = 6.2≒7. Moreover, the number of necessary dwell periods for CPHP = 87.0 seconds/10 seconds = 8.7≒9. Then, as program R2, the number of modules necessary to comply with MUTCT in each step is calculated. That is, MUT/block CT is calculated. A program example that specifically calculates the number of modules required for COT and CPHP is shown. The number of necessary modules for COT = 62.0 seconds/12.4 seconds ≒ 5. Moreover, the number of necessary modules for CPHP = 87.0 seconds / 12.4 seconds = 7.01≒8. In addition, the number of necessary modules calculated in this way is the number of necessary modules for the entire unit blocks E1 to E3. In other words, 5 COTs are required in the unit blocks E1 to E3.

From this, the number of necessary modules for each unit block E1 to E3 is determined based on the number of usable modules for each unit block. Regarding the procedure for including unusable modules, it is determined that all usable modules of the unit block containing unusable modules are used. Furthermore, the shortfall is divided evenly between unit blocks that do not include unusable modules. On the other hand, if we look at steps that do not include unavailable modules, the number of required modules for all unit blocks E1 to E3 will be evenly distributed among each unit block. In addition, since the number of modules is an integer, the number below the decimal point of the amortized number is rounded if it is not 0.

Specifically for COT and CPHP, the procedure for determining the necessary number of modules for each unit block E1 to E3 will be explained. The relevant COT is that the COT of the unit block E1 is unusable. Among the COTs of the unit block E1, another module that can be used is determined to be used. As mentioned above regarding COT, the total number of required modules in unit blocks E1~E3 is 5, so the remaining 4 is divided equally among unit blocks E2 and E3. The required number of modules for each is set to 2. Regarding CPHP, there are no unavailable users in unit blocks E1~E3. Furthermore, the total number of required modules in the unit blocks E1 to E3 is 8. Therefore, 2.6≒3, which is the value of 3 divided by the number of unit blocks E1 to E3, is set as the required modules of the unit blocks E1 to E3. Number of groups. In addition, the setting of the transfer strokes of the unit blocks E1 to E3 shown in the fifth embodiment is to set the operator using the transfer arms F1 to F3. However, as mentioned above, the loading of the wafer W in the loading module SCPL is It is carried out by the transport mechanism 15. Therefore, the calculation of the necessary number of modules to be loaded into the module SCPL, and the correction value and dwell period based on the calculation are not performed.

Then, as the program R3, the calculation result of the program R1/the calculation result of the program R2 is calculated, and the correction value of each step is calculated. In program R2, the necessary number of modules for each step is calculated for each unit block, so the correction value of this program R3 is also calculated for each step of each unit block. As a specific example, a calculation program for the correction values of COT and CPHP is shown. The relevant COT is the correction value of unit block E1 = the necessary number of dwell cycles of unit block E1 / the necessary number of modules of unit block E1 = 7/1=7. Similarly, the relevant COT is the correction value of unit blocks E2 and E3 = 7/2 = 3.5≒4. In addition, the CPHP is the correction value of unit blocks E1, E2, and E3 = 9/3 = 3.

After the correction value is calculated in this way, the maximum value of the correction value is selected for each unit block and is determined as the maximum correction value. In the example shown in Table 6, the correction values of unit block E1 are COT is 7, CPHP is 3, SCPL' is 4, ITC is 4, CGHP is 5, WEE is 2, among which COT is 7. maximum, so 7 was decided as the maximum correction value. Similarly, the maximum correction values of unit blocks E2 and E3 are determined to be 5 and 4 respectively.

Next, as program R4, a calculation is performed of the maximum correction value calculated in program R3 × the necessary number of modules calculated in program R2, and the number of dwell cycles of the wafer W of the module in each step is calculated for each unit block. If the calculation procedures for the number of stay cycles of COT and CPHP are shown specifically, the number of stay cycles for COT is calculated separately. In the unit block E1, it is 7×1=7, and in the unit block E2, it is 5×2=10. In unit block E3 it is 4×2=8. Similarly, regarding CPHP, the number of stay periods is calculated separately. In unit block E1, it is 7×3=21, in unit block E2, it is 5×3=15, and in unit block E3, it is 4×3=12.

Furthermore, for each unit block E1 to E3, the MUT/available module of the module in each step is calculated, and the maximum value among them is determined as the stack cycle time (stack CT). Then, the stack CT/block CT of each unit block E1 to E3 is calculated, and is rounded up when the decimal point is not 0. The obtained value is used as the loading interval of the wafer W to each unit block E1 to E3. This loading interval of each unit block indicates how many times the wafers W are transported to the entire unit blocks E1 to E3 in order to carry the wafer W once into the target unit block.

Specifically, the calculation program of this move-in interval is shown. If the MUT/available modules of each step of unit block E1 are displayed, the relevant COT is 62.0 seconds/1, the relevant CPHP is 87.0 seconds/4, the relevant SCPL' is 32.5 seconds/2, and the relevant ITC is 72.0 seconds/2 , the relevant CGHP is 87.0 seconds/4, and the relevant WEE is 18.0 seconds/1. Therefore, among these, 62.0 seconds/1=62.0 seconds of COT is the maximum value, and this 62.0 seconds is set as the stack CT. Therefore, the loading interval is 62.0 seconds/12.4 seconds = 5. Therefore, in the entire unit blocks E1 to E3, the loading destination for one of the five wafer W loads becomes the unit block E1. That is, the unit block E1 can process one wafer W in 62 seconds, and when looking at the unit blocks E1 to E3 as a whole, it is calculated in a manner suitable for processing one wafer W in 12.4 seconds. The loading interval of the wafer W in the unit block E1.

Similarly, in unit block E2, SCT=CGHP is 87.0 seconds/2=43.5 seconds, and the related SCT/block CT is 43.5 seconds/12.4 seconds=3.5≒4. Therefore, the unit block E2 is the place where the wafer W is moved four times into the unit blocks E1 to E3. In unit block E3, SCT=ITC is 72.0 seconds/2=36.0 seconds, and the related SCT/block CT is 36.0 seconds/12.4 seconds=2.9≒3. Therefore, the wafer W is moved into the unit block E3 once among the unit blocks E1 to E3 three times. If we look at the number of wafers W, the unit blocks E1:E2:E3=(5+4+3)/5: (5+4+3)/4: (5+4+3)/3 =12:15:20. That is, as the wafers W are sequentially transported at equal intervals in the entire unit blocks E1 to E3, the wafers W are transported to the unit blocks E1 and E2 at a rate of 12, 15, and 20 wafers per unit time. , E3 method, determines the ratio of the number of pieces moved in.

15 and 16 are the transfer strokes of the wafer W corresponding to PJ-A in Tables 6 and 7. That is, the transfer process is determined as described above by determining the ratio of the number of wafers W loaded into the unit blocks E1 to E3, the number of necessary modules for each step, and the number of dwell cycles for each step. As in the embodiment, As mentioned in 4, assign and set the transfer destination. In addition, for the convenience of illustration, the stroke table is divided into upper and lower parts and shown in FIGS. 15 and 16 , and the lower end of the stroke table in FIG. 15 and the upper end of the stroke table in FIG. 16 show the same cycle, and the stroke In the table, WEE is shown as WE. The wafer W of PJ-A is represented by the numbers A01 to A50 according to the order of loading into the unit blocks E1 to E3. Then, as shown in this transportation process, in the unit blocks E1 to E3, replacement transportation is performed in each of COT, CPHP, SCPL', ITC, CGHP, and WEE. In addition, in these modules, each time the wafer W is transported out, it is a replacement transport. Therefore, the load on the transfer arms F1 to F3 can be suppressed.

(Example 6) If the ratio of the number of wafers W loaded is set as described in Embodiment 5, then in the unit block where the ratio of the number of wafers W loaded is small, the ratio of the number of wafers W loaded will be larger than the ratio of the number of wafers W loaded. In the unit block, the interval from when the previous wafer W is transported to the TRS that becomes the exit of the unit block until the arrival of the next wafer W becomes longer. Furthermore, in the subsequent stages of the unit blocks E1 to E3, the transfer order of the wafers W is also maintained, and the wafers W are moved out of the TRS in the order in which they were loaded into the unit blocks E1 to E3. That is, they are moved out from TRS in the order of A01, A02, and A03･･･. Therefore, when the ratio of the number of loaded wafers per unit block is small (the loading interval is long), the wafer W may remain in the TRS for a long time. In addition, the unit block with a long loading interval of the wafer W is from when the wafer W is transported in each module other than the exit TRS until the subsequent wafer W to be replaced with the wafer W is transported. Long intervals. Therefore, the time required to transport the wafer W from one step to the next step also becomes longer. In Embodiment 6, the number of dwell periods is set in a manner that prevents such a situation from occurring. Hereinafter, Example 6 will be described focusing on the differences from Example 5.

Referring to the outline of Embodiment 6, the unit block with the largest ratio of the number of wafers W loaded in is calculated by executing the procedures R1 to R4 in the same manner as in Embodiment 5 so that the wafers can be exchanged and transported in each module. The number of dwell periods of circle W. Regarding other unit blocks, programs R1 to R3 are executed, but program R4 is not executed. Instead, the program R5 described later is used to calculate the dwell cycle number as the dwell cycle number that does not necessarily require replacement and transportation in each module. Program R5 is as follows. If the necessary number of modules obtained in program R2 = a, the maximum correction value obtained in program R3 = b, and the number of dwell cycles necessary for processing obtained in program R1 = c, then (a -1)×b+1 operation. Then, this calculated value is compared with the value of c, and the larger value is determined as the dwell cycle number. In this way, in Embodiment 6, in order of the ratio of the number of loaded wafers W, the first calculation expression of the program R4 or the second calculation expression of the program R5 is used to determine the module of each unit block based on the calculation result. Number of dwell cycles. In addition, as mentioned above, the calculation expression 2 of the program R5 uses the maximum correction value of the program R3. Therefore, like the calculation expression 1 of the program 1, in addition to the number of necessary modules, the MUT and CT are also applied as parameters to the calculation expression.

In order to explain the reason for performing the above-mentioned routine R5, or for the modules of the step, it is assumed that the necessary module number a=2 and the maximum correction value b=7 are calculated. That is, by using two modules, the wafer W can be loaded once every 7 cycles. At this time, according to the second calculation formula, the number of dwell cycles is calculated to be 8. If the number of dwell cycles is assumed to be 7, which is one less than 8, then the wafer W can be loaded once every 7 cycles as described above. Therefore, the number of necessary modules can be one instead of two. That is, the second calculation expression is an expression for calculating the minimum number of dwell cycles so that the number of necessary modules does not change. However, in order to perform the processing, it is necessary to set the dwell cycle number to be c or more, so the operation value using the second calculation expression is compared with c as described above to determine the dwell cycle number. For the unit block where the ratio of the number of wafers W loaded is not the maximum, the number of dwell cycles is determined based on the program R5 as described above, thereby suppressing the number of dwell cycles after the wafer W is loaded in each unit block until it is transferred to the TRS at the exit. time difference.

In Embodiment 6, the configuration of the unit blocks E1 to E3, the number of unusable modules, the processing time, and the MUT are the same as those in Embodiment 5. In addition, the CT time was also set to 10 seconds in the same manner as in Example 5. Therefore, the loading intervals of the wafers W in the unit blocks E1 to E3 are as shown in Table 7 above. Table 8 below shows the parameters calculated as described above in Example 6. Perform procedures R1 to R3 for each unit block E1 to E3. Furthermore, as shown in the description of Embodiment 5, in this example, the unit block with the largest ratio of the number of wafers W loaded in (the load-in interval is short) is E3. Therefore, the process R5 is performed for the unit blocks E1 and E2 respectively. , perform program R4 for unit block E3 to calculate the number of dwell cycles. Therefore, Table 8 is the same as Table 6 except for the number of stay cycles in the unit blocks E1 and E2.

If the procedure for calculating the number of dwell cycles of the COT of the unit block E1 is explained specifically, the number of necessary modules = 1, the maximum correction value = 7, the number of dwell cycles necessary for processing = 7, according to the above-mentioned program R5 The second calculation formula is (1-1)×7+1=0. The number of dwell cycles required for processing = 7 is larger than 0 in the operation result of this calculation expression, so 7 is decided as the number of dwell cycles. Similarly, if the procedure for calculating the number of dwell cycles of COT in unit block E2 is described, the number of necessary modules = 2, the maximum correction value = 5, the number of dwell cycles necessary for processing = 7, according to the above-mentioned program R5 The second calculation formula is (2-1)×5+1=6. The number of dwell cycles (7) necessary for the processing is larger than the calculation result of the second calculation expression (6), so 7 is determined as the number of dwell cycles. If the procedure for calculating the number of dwell cycles of the CPHP in unit block E1 is described, the number of required modules = 3, the maximum correction value = 7, the number of dwell cycles necessary for processing = 9, according to the second step of the above-mentioned program R5 Operational formula, (3-1)×7+1=15. Since 15 in the calculation result of this calculation expression is larger than 9, the number of dwell cycles necessary for processing, 15 is determined as the number of dwell cycles. Similarly, if the procedure for calculating the number of dwell cycles of CPHP in unit block E2 is explained, the number of necessary modules = 3, the maximum correction value = 5, the number of dwell cycles necessary for processing = 7, according to the above-mentioned program R5 The second calculation formula is (3-1)×5+1=11. Since 11 in the calculation result of this calculation expression is larger than 7, the number of dwell cycles necessary for processing, 11 is determined as the number of dwell cycles.

17 , 18 , and 19 respectively show the transfer strokes of the wafer W corresponding to PJ-A in the unit blocks E1, E2, and E3. In addition, FIG. 16 is a table showing the transfer strokes of the unit blocks E1 to E3 in one diagram, but in FIGS. 17 to 19 , one unit block is shown in one diagram for easy viewing. E's transport schedule. That is, similarly to Figure 16, in the tables of Figures 17 to 19, cells with the same height represent the same period. Regarding the unit block E3, COT, CPHP, SCPL', ITC, CGHP, and WEE are replaced and transported in the same manner as in Embodiment 5. That is, for the module determined to transport the wafer W, the subsequent wafer W is loaded into the module in a cycle in which the wafer W carried in earlier is carried out. COT, CPHP, SCPL’, ITC, CGHP, and WEE in unit blocks E1 and E2 will not be replaced and moved. That is, for the module determined to transport the wafer W, the subsequent wafer W is loaded in a later cycle than the cycle in which the wafer W carried earlier is carried out. In the unit blocks E1 and E2 that do not perform replacement transfer, the number of cycles of the TRS from when the wafer W is transferred to the unit block to when the wafer W is transferred to the exit is suppressed. As a result, the number of cycles from when the first wafer W of PJ-A is moved to the unit blocks E1 to E3 until the last wafer W of PJ-A is moved to TRS will be shorter than in the fifth embodiment. Therefore, according to Embodiment 6, the processing capabilities of the unit blocks E1 to E3 can be further improved.

In addition, the various calculations of the programs R1 to R5 described above and the setting of the conveyance stroke using the calculated number of necessary modules and the number of dwell cycles are performed by the control unit 10 . That is, the program of the control part 10 is configured so that such a conveyance stroke can be set. However, in the above example, the block CT is determined by comparing the maximum value in MUTCT with ACT as mentioned above. However, when the unit block is configured to have a very small number of steps and the maximum value of MUTCT is more reliably larger than ACT, the control unit 10 may not perform the above comparison and determine the block CT based only on MUTCT. On the other hand, when the unit block is configured to have an extremely large number of steps, the control unit 10 may determine ACT as the block CT without performing the above comparison. In this way, the comparison between the maximum value of MUTCT and ACT by the control unit 10 does not need to be performed.

In addition, in the above-described Embodiment 6, the program R4 for enabling replacement and transportation is performed only for the unit block with the largest ratio of the number of wafers W loaded, but the invention is not limited to this. When there are three or more unit blocks with the same configuration, for example, for the unit block with the largest ratio of the number of loaded pieces and the second largest unit block, the program R4 may be executed to determine the number of dwell cycles. However, in order to improve the throughput, it is effective to perform the process R4 only for the unit block with the largest ratio of the number of wafers W loaded in, as in Embodiment 6. Furthermore, as mentioned above, the substrate processing apparatus may be configured such that the processing blocks are not divided into a plurality of unit blocks (layers), that is, only one unit block may be provided. In this case, by executing the procedures R1 to R4 described above, the transfer stroke of the unit block can be set. In addition, although Embodiments 1 to 3 are shown in which the transfer stroke of the wafer W is not set according to the procedures R1 to R5, when performing these Embodiments 1 to 3, it can also be set in the unit block as explained in Embodiment 5. The ratio of the number of wafers W loaded into room E.

In addition, the embodiments disclosed this time are illustrative in all respects and are not restrictive. The above-described embodiments may be omitted, replaced, changed, or combined with each other in various forms without departing from the scope of the patent application and its gist.

Evaluation test 1 Evaluation test 1 by simulation will be explained. In this evaluation test 1, the wafer W group of PJ-A and the wafer of PJ-B were sequentially transported from the carrier 10 to a test device equipped with the unit block E6 like the coating and developing device 1 The W group, the PJ-C wafer group W, and the PJ-D wafer group W are processed and returned to the carrier 10 . When transporting the four PJ wafers W, the arrival time and unit area to the unit block of each PJ were measured when the transport stroke was set by the method of Comparative Example 1 and when the transfer stroke was set by the method of Example 2. Intra-block processing time, PJ processing time. The arrival time to the unit block is from the time when the leading wafer W of PJ is unloaded from the carrier 10 to the time when the leading wafer W is loaded into the entrance of the unit block E6 (transfer module TRS6) time. The processing time in the unit block is from the time when the leading wafer W of PJ is carried into the entrance of the unit block E6 to the time when the leading wafer W is carried into the exit of the unit block (temperature adjustment module SCPL' ) to the time point. The PJ processing time is the time from the time when the first wafer W of the PJ is unloaded from the carrier 10 to the time when the final wafer of the PJ is loaded into the carrier 10 . Furthermore, the arrival time to the unit blocks, the processing time in the unit block, and the PJ processing time were obtained by subtracting the results obtained when the transportation stroke was set using the method of Example 2 from the results obtained when the transportation stroke was set using the method of Example 2. The difference value of the result.

Table 4 below summarizes the above-mentioned difference values. Moreover, when the conveyance stroke is set by the method of Comparative Example 1, the processing time in the unit block is PJ-C>PJ-A>PJ-D>PJ-B. When the conveyance stroke is set by the method of Example 2 , the relevant processing time within the unit block is PJ-B>PJ-D>PJ-C>PJ-A.

As shown in Table 9, the processing time in the unit block of PJ-A and PJ-C is significantly shortened by setting the transfer stroke using the method of Embodiment 2. This is because by setting the conveyance stroke in the manner of Embodiment 2, PJ-A and PJ-C, which originally have high processing capabilities, are not affected by PJ-B and PJ-D, which have low processing capabilities. By shortening the processing time within the unit block, the processing time for PJ-A, PJ-C and PJ is also greatly shortened. Furthermore, as shown in Table 4, by setting the transport stroke in the same manner as in Embodiment 2, the unit block processing time and PJ processing time for PJ-B and PJ-D can also be shortened. Therefore, this evaluation test confirms the effect of the above-described coating and developing device 1 that can achieve high processing capabilities.

Evaluation test 2 As the evaluation test 2, in a coating and developing device having substantially the same structure as the coating and developing device 1, the conveyance stroke is set using the method of the Example or the method of the Comparative Example, and a simulation is performed to measure one The time required to move PJ. The time required for this transfer is the time required after the first wafer W of PJ is unloaded from the carrier C until the last wafer W of PJ is returned to the carrier C. Furthermore, the method of the above-described embodiment is a method of determining the number of dwell cycles and the import ratio of each unit block using the programs R1 to R5 described in the above-described Embodiment 6. The method of the comparative example is a method of determining the import ratio of each unit block according to the number of usable modules between unit blocks without using programs R1 to R5.

As the coating and developing device used in this evaluation test 2, the carrier C→TRS→ADH→SCPL→block CT→CPHP→SCPL→CPT→CGCH→WEE→TRS→BST→ICPL→TRS was transported in this order. Wafer W before exposure. The exposed wafer W is transported back to the carrier C in the order of TRS→CPHP→SCPL→DEV→CLHA→SCPL→TRS. ADH is a hydrophobic treatment module, BCT is an anti-reflection film forming module, BST is a backside cleaning module, ICPL is a temperature adjustment module, and CLHA is a heating module. In addition, the above-mentioned PJ is a PJ that transports 25 wafers W. Table 10 below shows the usable quantity and processing time of each module. In addition, the simulation was performed on a case where a part of usable modules are blocked (modules set as import-prohibited) and a case where the blocking is not performed. Blocking is performed on one block CT of the unit block E1 and two PABs of the unit block E2. In other words, the blocking module is in the same state as the unusable module.

The results of this evaluation test 2 show that the time required for transportation is shorter when the method of the Example is used than when the method of the Comparative Example is used, both when the blocking is performed and when the blocking is not performed. The difference in the time required for transportation when the method of the Example is used and the time required for transportation when the method of the Comparative Example is used is 57.12 seconds when blocking is performed and 235.13 seconds when blocking is not performed. By blocking in this way, the time required for transportation can be shortened. Therefore, the evaluation test 2 shows the effect of Example 6 which can improve the processing capability of the device.

1: Coating and developing device 10: Carrier 17:Transportation mechanism 100:Control Department 22:Substrate holding part SCPL: temperature adjustment module D2: Processing block F1~F6: Transport arm

[Fig. 1] is a cross-sectional side view showing a coating and developing device according to an embodiment of the present invention. [Fig. 2] is a longitudinal sectional side view of the coating and developing device. [Fig. 3] is a table diagram showing a conveyance stroke of a comparative example. [Fig. 4] is a table diagram showing a conveyance stroke of a comparative example. [Fig. 5] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 6] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 7] is a table diagram showing a conveyance stroke of a comparative example. [Fig. 8] is a table diagram showing a conveyance stroke of a comparative example. [Fig. 9] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 10] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 11] A diagram showing a flow of setting a conveyance stroke according to the embodiment. [FIG. 12] is a schematic diagram showing the unit block of the coating and developing device. [Fig. 13] is a flowchart showing a setting procedure for setting the number of dwell cycles in the conveyance stroke. [Fig. 14] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 15] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 16] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 17] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 18] is a table diagram showing the conveyance stroke of the embodiment. [Fig. 19] is a table diagram showing the conveyance stroke of the embodiment.

Claims (17)

A substrate processing apparatus is provided with a processing block that sequentially transports and processes substrates from a module on the upstream side to a module on the downstream side, and is characterized in that it is provided with: a transport mechanism for loading and unloading, which is connected to a carrier that stores the substrate and the above-mentioned The substrate is transferred between the processing blocks, and the substrate is moved in and out of the processing block; and the unloading module is used to place the processed substrates that have been moved out from the processing block by the loading and unloading transport mechanism. a substrate; a multi-module composed of a plurality of modules on the upstream side of the unloading module in which the order of conveying the substrate in the processing block is the same; and a main conveying mechanism equipped with mutually independent The plurality of substrate holding parts that each module moves forward and backward circulates in the conveyance path provided in the processing block, and transfers the substrate between modules. If the time it takes for the main conveyance mechanism to circle the conveyance path once is regarded as cycle time, then The control unit is based on the transfer time of the substrate corresponding to the number of transfer processes of the main transfer mechanism required to transfer the substrate loaded into the processing block to the unload module, or the control unit includes the multiple modules and can The method of processing the substrate in multiple steps is provided in the module group of the processing block. The necessary residence time of the substrate for the module of the step is divided by the number of modules that can be used for the same step. This time parameter is related to the maximum time among the times obtained in each step, the residence time of the necessary substrates of the modules constituting the multi-module set, and the cycle time. This includes determining the number of modules in the multi-module set to which the substrates are to be transported and the number of cycles of the main transport mechanism after the substrates are carried into the multi-module set until the substrates are carried out. The setting of the first conveyance stroke determines the number of dwell cycles. The substrate processing apparatus according to claim 1, wherein the number of modules to be the transfer destinations of the substrates in the multi-module set is determined by a value of a parameter corresponding to a required residence time of the substrates of the module divided by the time. The value of , the number of dwell cycles mentioned above is determined based on the number of modules. The substrate processing apparatus of Claim 1 or 2, wherein the parameter of the time is the larger of the maximum time among the transfer time of the substrate and the time obtained for each of the steps. The substrate processing apparatus of claim 1 or 2, wherein the processing blocks are N ( N is an integer). The transfer time of the substrate corresponds to the number of transfer processes and the time of N. The number of modules that can be used in the same step is the time between each unit block. The total number of modules that can be used in the same step, the number of modules to which the substrate is transferred, and the number of dwell cycles are determined for each of the unit blocks. The substrate processing apparatus according to claim 4, wherein the control unit calculates each unit based on the necessary residence time of the substrate for the module in each of the steps divided by the number of usable modules. The maximum value of the bit block and the parameter of the time determine the ratio of the number of the substrates loaded between the unit blocks. The substrate processing apparatus according to Claim 5, wherein the number of modules serving as transfer destinations for the substrates of the multi-module set in each of the unit blocks is determined to correspond to the necessary substrates for the module. The residence time is a value obtained by dividing the parameter of the time, and the control unit applies the number of modules to which the substrates are transported, the residence time of the substrates necessary in the modules, and the cycle time, and The number of residence cycles of the substrates in the multi-module set for each unit block is determined based on an arithmetic expression corresponding to the order of the ratio of the number of loaded pieces. For example, the substrate processing device of claim 6, wherein the N unit blocks include the first unit block and the second unit block, and regarding the ratio of the number of the substrates loaded in, if the first unit block is If it is larger than the second unit block, when the substrates of the same batch are transported, among the plurality of modules, the module to which the substrates are transported is determined. In the first unit block, The subsequent substrates are loaded in the cycle in which the substrate that was carried into the module first is carried out. In the second unit block, the subsequent substrates are carried in in the cycle that is later than the cycle in which the substrate that was carried into the module first is carried out. . The substrate processing apparatus according to claim 1, wherein the control unit calculates the necessary residence time of the substrate in the modules constituting the multi-module group based on the cycle time and the setting of the first transfer stroke. The number of dwell cycles is assigned to each substrate according to the number of dwell cycles to be loaded first. When the substrates in the processing block are sequentially transferred to the transfer destinations of the modules constituting the multi-module group, the following steps are performed: A. Among the plurality of modules that can transfer the substrates, the substrate closest to the transfer destination is transferred. The second transfer stroke of the transfer destination of each substrate is determined in such a way that the module that has been transferred to the multi-module earlier than the substrate that determines the transfer destination becomes the transfer destination, up to the cycle of the base cycle of the multi-module. settings. The substrate processing apparatus of Claim 8, wherein the cycle closest to the aforementioned reference cycle contains the same cycle as the reference cycle, and in the same cycle, for one module included in the multi-module set: using one The substrate holding part is used to carry out the substrate, and the other substrate holding part is used to load the substrate in. The substrate processing apparatus of Claim 8 or 9, wherein if the batches of the substrates that are sequentially transported to the processing block are designated as the 1st batch and the 2nd batch, then the 1st batch of substrates and the 2nd batch The number of dwell cycles for a batch of substrates is calculated based on the cycle time that is commonly set for the first batch and the second batch. In the substrate processing apparatus of claim 8 or 9, if the batches of the substrates that are sequentially transported to the processing block are the first batch and the second batch, the loading and unloading transport mechanism is every N The substrate is transported to the processing block in cycles (N is an integer). The number of residence cycles is a correction of the division value obtained by dividing the residence time by the cycle time during the transportation of the first and second batches. In addition to this A value that is above the calculated value and is an integer multiple of the aforementioned N. The substrate processing apparatus of claim 11, wherein the processing block is composed of N unit blocks each equipped with a carry-out module, a multi-module module, and a main transport mechanism to perform the same processing on the substrate, The transport mechanism for loading and unloading transports the substrate to each of the N unit blocks in the N cycles. The substrate processing apparatus of claim 8, wherein if the batches of the substrates that are sequentially transported to the processing block are the first batch and the second batch, then the cycle time corresponding to the first batch and the cycle time corresponding to the first batch The cycle time of the second batch is a parameter determined based on the aforementioned residence time and the number of modules constituting the aforementioned multi-module group. The substrate processing apparatus of claim 8, wherein the multi-module group includes an upstream-side multi-module group and a downstream-side multi-module group in the conveyance process of the substrate, and the upstream-side multi-module group and the downstream-side multi-module group For each multi-module unit, the transfer destination of the substrate is determined according to the above-mentioned A. The substrate processing apparatus of claim 8, wherein if the batches of the substrates that are continuously transported to the processing block are the first batch and the second batch, the multi-module performs the predetermined processing The parameters will be different from each other. When the first batch and the second batch are processed separately, the same number of boards as the number of the above-mentioned multi-modules starting from the first batch of the second batch will be determined according to A. The transportation destination is B. Among the plurality of modules that can transport the substrate, the distance to determine the transportation The transfer destination of each substrate is determined in such a way that the module to which the substrate is transferred earlier than the substrate determined to be transferred to the multi-module module becomes the transfer destination. Place to go. The substrate processing apparatus according to claim 15, wherein the multi-module is a heating module including a hot plate that heats the mounted substrate, or an exposure module that irradiates light from a light irradiation part to expose the substrate. , the aforementioned predetermined processing parameter is the temperature of the aforementioned hot plate or the intensity of light from the aforementioned light irradiation part. A substrate processing method using a substrate processing apparatus provided with a processing block that sequentially transports and processes substrates from an upstream module to a downstream module, the substrate processing apparatus being equipped with a transport mechanism for loading and unloading , which transfers the above-mentioned substrate between the carrier storing the above-mentioned substrate and the above-mentioned processing block, and carries out the loading and unloading of the above-mentioned substrate before going to the processing block; the transport module is placed by the above-mentioned transporting mechanism for transporting in and out The processed substrates are unloaded from the processing block; a multi-module group is composed of a plurality of modules on the upstream side of the unloading module in which the order of conveying the substrates in the processing block is the same; and a main transport mechanism, which is equipped with a plurality of substrate holding parts that advance and retreat independently of each other for each module, circulates in the transport path provided in the processing block, and transfers the substrate between modules, It is characterized by including the following process: if the time it takes for the main transport mechanism to circle the transport path once is a cycle time, it is based on: corresponding to the time required to transport the substrate carried into the processing block to the unloading module. The transfer time of the substrates of the transfer process of the main transfer mechanism may be included in the module group of the processing block including the plurality of modules and capable of processing the substrates in a plurality of steps. The module of the step The residence time of the necessary substrates for the group is divided by the number of modules that can be used in the same step, and the time parameter of the maximum time among the times obtained in each step is obtained, and the parameters of the modules constituting the multi-module set are The necessary residence time of the substrate and the cycle time are used to determine the number of modules in the multi-module set to which the substrate is to be transported, and from the time the substrate is loaded into the multi-module set to the time the substrate is unloaded. The setting of the first conveyance stroke determines the number of dwell cycles until the number of times the main conveyance mechanism circulates.

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