TWI827182B - Clock data recovery circuit - Google Patents

Abstract

A clock data recovery circuit includes a phase detector, a frequency detector, a hysteresis lock detector, a first charge pump, a second charge pump, a voltage controlled oscillator, and a frequency up/down controlled circuit. The hysteresis lock detector controls the voltage controlled oscillator with the frequency acquisition loop formed by the frequency detector through the second charge pump when the frequency difference between the voltage controlled oscillator and the input data is large. The hysteresis lock detector controls the voltage controlled oscillator with the phase-locked loop formed by the phase detector through the first charge pump when the frequency difference between the voltage controlled oscillator and the input data is small. Therefore, the clock data recovery circuit could quickly lock and avoid the two loops interfere with each other.

Description

Clock data recovery circuit

The present invention relates to a recovery circuit, and in particular to a clock data recovery circuit.

In a communication system, the clock data recovery circuit is a very important device of the receiver. This is because the clock information of the signal received by the receiver is asynchronous and is very susceptible to interference from noise signals. Therefore, the receiver needs to use the signal clock The data recovery circuit reconstructs the clock information of the received signal and then recovers the original data. In previous technologies, dual loops of phase locking and frequency acquisition were used to complete clock data recovery. However, in some dual-loop architectures, the control lines of the voltage-controlled oscillator are shared by two loops, which may cause interference with each other. In addition, , when the bandwidth design of the phase locking loop and the frequency acquisition loop is different, it will also affect the overall locking time, and cannot be used in communication networks that require fast locking.

The main purpose of the present invention is to lock the clock data by controlling the phase locking loop or the frequency acquisition loop through the hysteresis locked loop. This can avoid the mutual influence of the two loops and reduce the ripple and jitter on the control line of the voltage controlled oscillator.

A clock data recovery circuit of the present invention includes a phase detector, a frequency detector, a hysteresis lock detector, a first charge pump, a second charge pump, a voltage controlled oscillator and a voltage control oscillator. Frequency / down-frequency control circuit, the phase detector receives a same-phase clock signal and an input data, the phase detector is used to detect the phase relationship between the same-phase clock signal and the input data and output a phase detection Detection signal, the frequency detector receives the in-phase clock signal, the input data and a quadrature clock signal, the frequency detector is used to detect the frequency relationship between the in-phase clock signal and the input data and output A frequency detection signal. The hysteresis lock detector receives the in-phase clock signal and the input data. The hysteresis lock detector is used to determine the frequency difference between the in-phase clock signal and the input data and output a Locking the signal to the phase detector and the frequency detector, the first charge pump is electrically connected to the phase detector to receive the phase detection signal, and the first charge pump outputs a fine signal through a loop filter To adjust the voltage, the second charge pump is electrically connected to the frequency detector to receive the frequency detection signal, and the second charge pump charges or discharges a capacitor according to the frequency detection signal to output a coarse adjustment voltage. A voltage controlled oscillator is electrically connected to the first charge pump and the second charge pump to receive the coarse voltage and the fine voltage, and the voltage controlled oscillator outputs the in-phase clock signal and the quadrature clock signal, The frequency up/down control circuit receives the in-phase clock signal and the input data, and the frequency up/down control circuit outputs a frequency up/down control signal to the frequency detector.

The present invention uses the hysteresis lock detector to control the phase detector and the frequency detector, and can selectively perform clock data recovery through a frequency acquisition loop or a phase lock loop, which can effectively speed up the clock data recovery. The pulse data restores the locking speed of the circuit and avoids mutual influence between the two loops.

Please refer to Figure 1, which is a block diagram of a clock data recovery circuit 100 according to an embodiment of the present invention. The clock data recovery circuit 100 includes a phase detector 110, a frequency detector 120, a magnetic hysteresis lock detector 130, a first charge pump 140, a second charge pump 150, a voltage controlled oscillator 160 and an up/down frequency control circuit 170.

The phase detector 110 receives a same-phase clock signal clkI and an input data data. The phase detector 110 is used to detect the phase relationship between the same-phase clock signal clkI and the input data data and output a phase detection signal. The phase detection signal includes a phase leading detection signal PDU and a phase lagging detection signal PDD.

Please refer to Figure 2. The phase detector 110 has a first flip-flop 111, a second flip-flop 112, a third flip-flop 113, a fourth flip-flop 114, and a first mutual exclusion device. OR gate 115 and a second mutually exclusive OR gate 116 . The first flip-flop 111 receives the input data data and the in-phase clock signal clkI. The first flip-flop 111 is triggered by the positive edge of the in-phase clock signal clkI to sample the input data data and output a first sample. Signal S1. The second flip-flop 112 is electrically connected to the first flip-flop 111. The second flip-flop 112 receives the first sampling signal S1 and the in-phase clock signal clkI. The second flip-flop 112 is configured by the in-phase The positive edge of the clock signal clkI is triggered to sample the first sampling signal S1 and output a second sampling signal S2. The second sampling signal S2 is used to temporarily store the potential sampled by the previous trigger of the first sampling signal S1. The third flip-flop 113 receives the input data data and the in-phase clock signal clkI. The third flip-flop 113 is triggered by the negative edge of the in-phase clock signal clkI to sample the input data data and output a third sample. Signal S3. The fourth flip-flop 114 is electrically connected to the third flip-flop 113. The fourth flip-flop 114 receives the third sampling signal S3 and the in-phase clock signal clkI. The fourth flip-flop 114 is formed by the in-phase The positive edge of the clock signal clkI is triggered to sample the third sampling signal S3 and output a fourth sampling signal S4. The fourth sampling signal S4 is used to temporarily store the potential sampled by the previous trigger of the third sampling signal S3. The first mutually exclusive OR gate 115 is electrically connected to the first flip-flop 111 and the fourth flip-flop 114 to receive the first sampling signal S1 and the fourth sampling signal S4, and the first mutually exclusive OR gate 115 outputs the phase leading detection signal PDU. The second mutual exclusive OR gate 116 is electrically connected to the second flip-flop 112 and the fourth flip-flop 114 to receive the second sampling signal S2 and the fourth sampling signal S4, and the second mutual exclusive OR gate 116 outputs the phase lag detection signal PDD.

Please refer to Figures 3a and 3b for the timing diagram of each signal of the phase detector 110. Please refer to Figure 3a. When the phase of the in-phase clock signal clkI leads the input data data, because the second sampling signal S2 is the input data data sampled by the first rising edge of the in-phase clock signal clkI and is at a low level, and the fourth sampling signal S4 is the input data data sampled by the first falling edge of the in-phase clock signal clkI and is a high potential, the first sampling signal S1 is the input data data sampled by the second upper edge of the in-phase clock signal clkI and is a high potential. Correspondingly, please refer to Figure 3b. When the phase of the in-phase clock signal clkI lags behind the input data data, the second sampling signal S2 is the input data sampled by the first upper edge of the in-phase clock signal clkI. The input data data sampled by the first lower edge of the in-phase clock signal clkI is at a high level. The fourth sampling signal S4 is at a high level. The first sampling signal S1 is the in-phase clock signal clkI. The input data data sampled by the two upper edges is low level.

Please refer to Figures 2, 3a and 3b. Through the potential changes of the first, second and fourth sampling signals S1, S2 and S4 in different phase states, when the input data data leads the in-phase clock signal clkI, the The phase leading signal PDU output by the first mutually exclusive OR gate 115 is at a high potential, and the phase lagging signal PDD output by the second mutually exclusive OR gate 116 is at a low potential; when the input data data lags behind the in-phase clock signal clkI , the phase leading signal PDU output by the first mutually exclusive OR gate 115 is at a low level, and the phase lagging signal PDD output by the second mutually exclusive OR gate 116 is at a high level, which can be used to determine the in-phase clock signal clkI and the phase relationship between the input data data.

Preferably, the reverse reset terminal RSTb of the first flip-flop 111, the second flip-flop 112, the third flip-flop 113 and the fourth flip-flop 114 receives the lock signal lock, so as to When the lock signal lock is low, the first flip-flop 111 , the second flip-flop 112 , the third flip-flop 113 and the fourth flip-flop 114 are reset to reset the phase detector 110 phase tracking.

Referring to Figure 1, the hysteresis lock detector 130 receives the in-phase clock signal clkI and the input data data, and the hysteresis lock detector 130 is used to determine the relationship between the in-phase clock signal clkI and the input data data. According to the frequency difference between them, a lock signal lock is output to the phase detector 110 and the frequency detector 120 to determine whether the phase detector 110 or the frequency detector 120 controls the voltage controlled oscillator 160 .

Please refer to Figure 4. The hysteresis lock detector 130 has a first counter 131, a first hysteresis switch 132, a fifth flip-flop 133, a second counter 134, and a second hysteresis switch 135. , a sixth flip-flop 136 , an OR gate 137 and a logic operation unit 138 . The first counter 131 receives the input data data for counting and outputs a first counting signal A _{0 to N-1} . In this embodiment, the first counter 131 is an N-bit counter. The first hysteresis switch 132 is electrically connected to the first counter 131 to receive the two bits A ₀ and A _K of the first counting signal, and the first hysteresis switch 132 is controlled by the lock signal lock to output a The first trigger signal T1. The fifth flip-flop 133 is electrically connected to the first counter 131 and the first hysteresis switch 132 to receive the highest bit A _N-1 of the first counting signal and the first trigger signal T1. The inverter 133 is triggered by the first trigger signal T1 to sample the highest bit A _N-1 of the first count signal and output a first temporary storage signal E1. The second counter 134 receives the in-phase clock signal clkI for counting and outputs a second counting signal B _{0 ~ N-1} . In this embodiment, the second counter 134 and the first counter 131 are both N-bit elements. counter. The second hysteresis switch 135 is electrically connected to the second counter 134 to receive the two bits B ₀ and B _K of the second counting signal, and the second hysteresis switch 135 is controlled by the lock signal lock to output a The second trigger signal T2. The sixth flip-flop 136 is electrically connected to the second counter 134 and the second hysteresis switch 135 to receive the highest bit B _N-1 of the second count signal and the second trigger signal T2. The inverter 136 is triggered by the second counting signal 134 to sample the highest bit B _N-1 of the second counting signal and output a second temporary storage signal E2. The OR gate 137 is electrically connected to the fifth flip-flop 133 and the sixth flip-flop 136 to receive the first temporary signal E1 and the second temporary signal E2, and the OR gate 137 outputs a first logic Signal C. The logic operation unit 138 is electrically connected to the first counter 131, the second counter 134 and the OR gate 137 to receive the highest bit A _N-1 of the first counting signal and the highest bit B of the second counting signal. _N-1 and the first logic signal C, and the logic operation unit 138 outputs the lock signal lock.

Referring to Figure 4, the first hysteresis switch 132 has a first transmission gate 132a and a second transmission gate 132b. The first transmission gate 132a receives the lowest bit A 0 of the first count signal, and the second transmission gate 132 a receives the lowest bit A ₀ of the first count signal. The transmission gate 132b receives the K-th bit A _K of the first counting signal, and the first transmission gate 132a and the second transmission gate 132b are controlled by the lock signal lock and the reverse lock signal lockb to decide to transmit the first The lowest bit A ₀ or the Kth bit A _K of the counting signal is used as the first trigger signal T1, where K is between the lowest bit number 0 and the highest bit number N-1 of the first counting signal. Positive integer. The second hysteresis switch 135 has a third transmission gate 135a and a fourth transmission gate 135b. The third transmission gate 135a receives the lowest bit B ₀ of the second count signal, and the fourth transmission gate 135b receives the second The Kth bit B _K of the count signal, and the third transmission gate 135a and the fourth transmission gate 135b are controlled by the lock signal lock and the reverse lock signal lockb to determine the lowest bit of the second count signal B ₀ or the K-th bit B _K serves as the second trigger signal T2, where K is a positive integer between the lowest bit number 0 and the highest bit number N-1 of the second counting signal.

Please refer to Figure 4. In this embodiment, the logic operation unit 138 has an inverse-OR gate 138a, a first inverse-AND gate 138b, a second inverse-AND gate 138c, a third inverse-AND gate 138d, and a third inverse-AND gate 138d. Four reverse gates 138e, a seventh flip-flop 138f and a reverse gate 138g. The NOR gate 138a receives the inverted highest bit Ab _N-1 of the first count signal and the inverted highest bit Bb _N-1 of the second count signal and outputs an NOR signal D. The first NAND gate 138b receives the highest bit A _N-1 of the first counting signal and the highest bit B _N-1 of the second counting signal and outputs a first NAND signal. The second NAND gate 138c receives the highest bit B _N-1 of the second count signal and the first logic signal C and outputs a second inverse AND signal. The third NAND gate 138d receives the highest bit A _N of the first count signal. _-1 and the first logic signal C and output a third inverse-AND signal. The fourth inverse-AND gate 138e is electrically connected to the first, second and third inverse-AND gates 138b, 138c, 138d to receive the first and second inverse-AND gates 138b, 138c and 138d. and three inverse-AND signals, and the fourth inverse-AND gate 138e outputs a count reset signal R. The seventh flip-flop 138f is electrically connected to the inverse-OR gate 138a and the fourth inverse-AND gate 138e to receive the inverse-OR signal D and the count reset signal R, and the seventh flip-flop 138f is configured by the count reset signal. The signal R is triggered to sample the inverse-OR signal D to output the lock signal lock and the inverse lock signal lockb. The inverse gate 138g is electrically connected to the fourth inverse-AND gate 138e to receive the count reset signal R, and The reverse gate 138g outputs the reverse count reset signal Rb to the first and second counters 131 and 134 and the fifth and sixth flip-flops 133 and 136 for reset.

The first and fourth counters 131 and 134 respectively count the input data data and the in-phase clock input signal clkI, and judge and analyze the bits of the two counting signals in the back-end circuit, and at the in-phase time When the frequency difference between the pulse signal clkI and the input data data is large, the lock signal lock is at a low level, turning on the frequency detector 120 to perform large-scale frequency tracking and turning off the phase detector 110, and when the same phase When the frequency difference between the pulse signal clkI and the input data data is small, the lock signal lock is set to a high potential, the phase detector 110 is turned on for phase locking, and the frequency detector 120 is adjusted for small-amplitude frequency tracking.

Referring to Figure 1, the up/down frequency control circuit 170 receives the in-phase clock signal clkI and the input data data, and the up/down frequency control circuit 170 outputs a frequency up/down control signal UP/DN to the frequency detector 120.

Please refer to Figure 5. In this embodiment, the up/down frequency control circuit 170 has a third counter 171, a fourth counter 172, an OR gate 173, an eighth flip-flop 174, and a ninth flip-flop. 175 and a reverse gate 176. The third counter 171 receives the in-phase clock signal clkI for counting and outputs a third counting signal Q _0~4 . The fourth counter 172 receives the input data data for counting and outputs a fourth counting signal U _0~4 . The third and fourth counters 171 and 172 are both 5-bit counters. The OR gate 173 is electrically connected to the third counter 171 to receive the highest bit Q ₄ and the second highest bit Q ₃ of the third counting signals Q _{0 ~ 4} , and the OR gate 173 outputs an OR gate signal. The eighth flip-flop 174 is electrically connected to the OR gate 173 and the fourth counter 172 to receive the OR gate signal and the second highest bit U ₃ of the fourth count signal. The eighth flip-flop 174 is formed by the fourth The second-highest bit U ₃ of the counting signal is triggered to sample the OR signal, and the eighth flip-flop 174 outputs the frequency up/down control signal UP/DN from the inverse output terminal. The ninth flip-flop 175 is electrically connected to the fourth counter 172. The ninth flip-flop 175 receives the highest bit _U4 of the fourth count signal and the divided in-phase clock signal clkI/2. The ninth flip-flop 175 is triggered by the divided in-phase clock signal clkI/2 to sample the highest bit U ₄ of the fourth count signal, and the ninth flip-flop 175 outputs an up-and-down frequency count through the inverter 176 The reset signal UD_R is sent to the third and fourth counters 171 and 172 for reset.

Please refer to Figures 6a and 6b for the timing diagram of the signal of the frequency up/down control circuit 170. Please refer to Figure 6a. The second highest bit U ₃ of the fourth counting signal is second to the third counting signal Q _0~4. When the high-order bit _Q3 is faster, the frequency up/down control signal UP/DN is output to 0, which means that the input data data is faster than the in-phase clock signal clkI, and the second-highest bit _U3 of the fourth counting signal is faster than the fourth counting signal. When the second highest bit Q ₃ of the three counting signals Q _{0 to 4} is slow, the frequency up/down control signal UP/DN output is 1, which means that the input data data is slower than the in-phase clock signal clkI.

Referring to Figure 1, the frequency detector 120 receives the in-phase clock signal clkI, the input data data and a quadrature clock signal clkQ. The frequency detector 120 is used to detect the in-phase clock signal clkI and The frequency relationship between the input data data is used to output a frequency detection signal FD.

Please refer to Figure 7. In this embodiment, the frequency detector 120 has a frequency detection circuit 121 and a frequency detection selection circuit 122. The frequency detection signal has a frequency rise detection signal FDU and a frequency Drop detection signal FDD. The frequency detection circuit 121 receives the input data data, the in-phase clock signal clkI and the quadrature clock signal clkQ to detect and output a first frequency up signal UP1 and a first frequency down signal DN1. The frequency detection selection circuit 122 is electrically connected to the frequency detection circuit 121. The frequency detection selection circuit 122 receives the first frequency up signal UP1, the first frequency down signal DN1, the in-phase clock signal clkI and the input data, and the frequency detection selection circuit 122 outputs the frequency up detection signal FDU and the frequency down detection signal FDD.

The frequency detection circuit 121 has a delayer 121a, a third mutual exclusive OR gate 121b, a tenth flip-flop 121c, an eleventh flip-flop 121d, a twelfth flip-flop 121e, a tenth Three flip-flops 121f, a fourteenth flip-flop 121g, a fifteenth flip-flop 121h and an output logic circuit 121i. The delayer 121a receives the input data data and outputs a delayed data. The third exclusive OR gate 121b is electrically connected to the delayer 121a. The third exclusive OR gate 121b receives the input data data and the delayed data. The third exclusive OR gate 121b receives the input data data and the delayed data. The third mutually exclusive OR gate 121b outputs a detection trigger signal. The tenth flip-flop 121c is electrically connected to the mutually exclusive OR gate 121b. The tenth flip-flop 121c receives the in-phase clock signal clkI and the detection trigger signal, and the tenth flip-flop 121c is controlled by the detection The trigger signal triggers to sample the in-phase clock signal clkI and output a tenth sampling signal j. The eleventh flip-flop 121d is electrically connected to the tenth flip-flop 121c. The eleventh flip-flop 121d receives the tenth sampling signal j and the in-phase clock signal clkI, and the eleventh flip-flop 121d 121d is triggered by the in-phase clock signal clkI to sample the tenth sampling signal j and output an eleventh sampling signal k and an inverted eleventh sampling signal kb. The twelfth flip-flop 121e is electrically connected to the eleventh flip-flop 121d. The twelfth flip-flop 121e receives the eleventh sampling signal k and the in-phase clock signal clkI, and the twelfth flip-flop 121e The inverter 121e is triggered by the in-phase clock signal clkI to sample the eleventh sampling signal k and output a twelfth sampling signal l and an inverted twelfth sampling signal lb.

The thirteenth flip-flop 121f is electrically connected to the third mutually exclusive OR gate 121b. The thirteenth flip-flop 121f receives the quadrature clock signal clkQ and the detection trigger signal, and the thirteenth flip-flop 121f The device 121f is triggered by the detection trigger signal to sample the quadrature clock signal clkQ and output a thirteenth sampling signal m. The fourteenth flip-flop 121g is electrically connected to the thirteenth flip-flop 121f. The fourteenth flip-flop 121g receives the thirteenth sampling signal m and the in-phase clock signal clkI, and the fourteenth flip-flop 121g The inverter 121g is triggered by the in-phase clock signal clkI to sample the thirteenth sampling signal m and output a fourteenth sampling signal n and the inverted fourteenth sampling signal nb. The fifteenth flip-flop 121h is electrically connected to the fourteenth flip-flop 121g. The fifteenth flip-flop 121h receives the fourteenth sampling signal n and the in-phase clock signal clkI, and the fifteenth flip-flop 121h The inverter 121h is triggered by the in-phase clock signal clkI to sample the fourteenth sampling signal n and output a fifteenth sampling signal o and the inverted fifteenth sampling signal ob.

The output logic circuit 121i is electrically connected to the eleventh, twelfth, fourteenth and fifteenth flip-flops 121d, 121e, 121g, 121h to receive the eleventh sampling signal k and the inverted eleventh sampling signal kb, the twelfth sampling signal l, the inverted twelfth sampling signal lb, the inverted fourteenth sampling signal nb and the inverted fifteenth sampling signal ob, and the output logic circuit 121i outputs The first frequency up signal UP1 and the first frequency down signal DN1. In this embodiment, the output logic circuit 121i has a first AND gate and1, a second AND gate and2, a third AND gate and3, a fourth AND gate and4 and a fifth AND gate and5. The first AND gate and1 is electrically connected to the eleventh and twelfth flip-flops 121d and 121e to receive the inverted eleventh sampling signal kb and the twelfth sampling signal I. The second AND gate and2 is electrically connected to the fourteenth and fifteenth flip-flops 121g and 121h to receive the reverse fourteenth sampling signal nb and the reverse fifteenth sampling signal ob. The third and The gate is electrically connected to the eleventh and twelfth flip-flops 121d and 121e to receive the eleventh sampling signal k and the reversed twelfth sampling signal lb. The fourth AND gate and4 is electrically connected to the first and second AND gates and1, and2, and the fourth AND gate and4 outputs the first frequency rising signal UP1, and the fifth AND gate and5 is electrically connected to the second and third AND gates and2, and3, and the fifth AND gate and5 outputs the first frequency down signal DN1.

Referring to Figure 7, the frequency detection selection circuit 122 has a sixteenth flip-flop 122a, a first multiplexer 122b, a second multiplexer 122c, a third multiplexer 122d and a fourth Multiplexer 122e. The sixteenth flip-flop 122a receives the in-phase clock signal clkI and the input data data, and the sixteenth flip-flop 122a outputs a frequency difference signal DIFF. The frequency difference signal DIFF is the in-phase clock signal clkI and the input data data. The frequency difference between the input data data. The first multiplexer 122b is electrically connected to the sixteenth flip-flop 122a. The first multiplexer 122b receives the frequency difference signal DIFF, a ground voltage Gnd and the frequency up/down control signal UP/DN, and the The first multiplexer 122b outputs a second frequency up signal UP2. The second multiplexer 122c is electrically connected to the first multiplexer 122b and the frequency detection circuit 121. The second multiplexer 122c receives the second frequency up signal UP2, the first frequency up signal UP1 and the The lock signal is locked, and the second multiplexer 122c outputs the frequency rise detection signal FDU. The third multiplexer 122d is electrically connected to the sixteenth flip-flop 122a. The third multiplexer 122d receives the frequency difference signal DIFF, the ground voltage Gnd and the frequency up/down control signal UP/DN, and the The third multiplexer 122d outputs a second frequency down signal DN2. The fourth multiplexer 122e is electrically connected to the third multiplexer 122d and the frequency detection circuit 121. The second multiplexer 122c receives the third frequency down signal DN2. The second frequency down signal DN2, the first frequency down signal DN1 and the lock signal lock, and the fourth multiplexer 122e outputs the frequency down detection signal FDD.

Please refer to Figures 8a and 8b for the timing diagram of each signal of the frequency detection circuit 121. First, it is defined that when the in-phase clock signal clkI and the quadrature clock signal clkQ are both 0, it is state I; When the signal clkI is 0 and the quadrature clock signal clkQ is 1, it is state II; when the in-phase clock signal clkI and the quadrature clock signal clkQ are both 1, it is state III; when the in-phase clock signal clkI is 1 and When the orthogonal clock signal clkQ is 0, it is state IV. Please refer to Figure 8a. When the input data data rate is faster than the in-phase clock signal clkI, the state of the in-phase clock signal clkI and the quadrature clock signal clkQ sampled by the negative edge of the input data data changes to I →II→III→IV→I. Correspondingly, please refer to Figure 8b, when the input data data rate is slower than the in-phase clock signal clkI, the states of the in-phase clock signal clkI and the quadrature clock signal clkQ sampled by the negative edge of the input data data The change is IV→III→II→I→IV, and the frequency between the in-phase clock signal clkI and the input data data can be measured through the state changes of the in-phase clock signal clkI and the quadrature clock signal clkQ. relation.

Please refer to Figure 7 again. Since the frequency detection circuit 121 may have a state loss problem when the frequency difference between the in-phase clock signal clkI and the input data data is too large, therefore, if the lock signal lock is low, , indicating a large frequency difference, the frequency detection selection circuit 122 outputs the frequency difference signal DIFF as the frequency up detection signal FDU or the frequency down detection signal FDD. When the lock signal lock is at a high potential, it indicates that the frequency difference is small, and the frequency detection selection circuit 122 outputs the first frequency up signal UP1 or the first frequency down signal DN1 of the frequency detection circuit 121 as the frequency up signal. Detection signal FDU or frequency drop detection signal FDD.

Referring to Figure 1, the first charge pump 140 is electrically connected to the phase detector 110 to receive the phase leading signal PDU and the phase lagging signal PDD of the phase detection signal, and the first charge pump 140 passes through a The loop filter LF outputs a finely adjusted voltage Vf. The second charge pump 150 is electrically connected to the frequency detector 120 to receive the frequency up detection signal FDU and the frequency down detection signal FDD of the frequency detection signal, and the second charge pump 150 detects The measurement signal charges or discharges a capacitor Cg and outputs a coarse-adjusted voltage Vc. The voltage controlled oscillator 160 is electrically connected to the first charge pump 140 and the second charge pump 150 to receive and be controlled by the coarse voltage Vc and the fine voltage Vf, and the voltage controlled oscillator 160 is controlled by the fine voltage Vc. The in-phase clock signal clkI and the quadrature clock signal clkQ are output under the control of the adjusting voltage Vf and the coarse-adjusting voltage Vc. The in-phase clock signal clkI is output as an output frequency Fout through a buffer 180 .

The present invention uses the hysteresis lock detector 130 to control the phase detector 110 and the frequency detector 120, and can selectively perform clock data recovery through a frequency acquisition loop or a phase lock loop, which can effectively This speeds up the locking speed of the clock data recovery circuit 100 and avoids mutual influence between the two loops.

The protection scope of the present invention shall be determined by the appended patent application scope. Any changes and modifications made by anyone familiar with this art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

100: Clock data recovery circuit 110: Phase detector 111: First flip-flop 112: Second flip-flop 113: Third flip-flop 114: Fourth flip-flop 115: First mutually exclusive OR gate 116 : The second mutually exclusive OR gate 120: The frequency detector 121: The frequency detection circuit 121a: The delayer 121b: The third mutually exclusive OR gate 121c: The tenth flip-flop 121d: The eleventh flip-flop 121e: The tenth Second flip-flop 121f: Thirteenth flip-flop 121g: Fourteenth flip-flop 121h: Fifteenth flip-flop 121i: Output logic circuit 122: Frequency detection selection circuit 122a: Sixteenth flip-flop 122b: First multiplexer 122c: Second multiplexer 122d: Third multiplexer 122e: Fourth multiplexer 130: Hysteresis lock detector 131: First counter 132: First hysteresis switch 132a: First Transmission gate 132b: Second transmission gate 133: Fifth flip-flop 134: Second counter 135: Second hysteresis switch 135a: Third transmission gate 135b: Fourth transmission gate 136: Sixth flip-flop 137: OR gate 138: Logic operation unit 138a: NOR gate 138b: First NAND gate 138c: Second NAND gate 138d: Third NAND gate 138e: Fourth NAND gate 138f: Seventh flip-flop 138g: NAND gate 140 : First charge pump 150: Second charge pump 160: Voltage controlled oscillator 170: Up/down frequency control circuit 171: Third counter 172: Fourth counter 173: OR gate 174: Eighth flip-flop 175: Nine flip-flop 176: reverse gate 180: buffer clkI: in-phase clock signal data: input data clkQ: quadrature clock signal PDU: phase leading signal PDD: phase lagging signal FDU: frequency up detection signal FDD: frequency down Detection signal lock: Lock signal LF: Loop filter Vf: Fine adjustment voltage Cg: Capacitor UP/DN: Frequency rise/fall control signal S1: First sampling signal S2: Second sampling signal S3: Third sampling signal S4: The fourth sampling signal A _0~N-1 : the first counting signal Ab _N-1 : the highest bit of the reverse first counting signal T1: the first trigger signal E1: the first temporary storage signal B _0~N-1 : Second counting signal Bb _N-1 : The highest bit of the reverse second counting signal E2: The second temporary storage signal C: The first logical signal D: The inverse OR signal R: The counting reset signal Rb: The reverse counting reset Set signal Q _0~4 : The third counting signal U _0~4 : The fourth counting signal clkI/2: The same-phase clock signal of frequency division UD_R: Up and down frequency counting reset signal j: The tenth sampling signal k: The eleventh Sampling signal kb: the eleventh sampling signal in reverse l: the twelfth sampling signal lb: the twelfth sampling signal in reverse m: the thirteenth sampling signal n: the fourteenth sampling signal nb: the tenth sampling signal in reverse Four sampling signals o: the fifteenth sampling signal ob: the reverse fifteenth sampling signal and1: the first AND gate and2: the second AND gate and3: the third AND gate and4: the fourth AND gate and5: the fifth AND gate DIFF: frequency difference signal UP1: first frequency rising signal DN1: first frequency falling signal Gnd: ground voltage UP2: second frequency rising signal DN2: second frequency falling signal lockb: reverse lock signal Vc: coarse adjustment voltage Fout :Output frequency RST: Reset terminal RSTb: Reverse reset terminal

Figure 1: A block diagram of a clock data recovery circuit according to an embodiment of the present invention. Figure 2: Circuit diagram of a phase detector according to an embodiment of the present invention. Figure 3a: Timing diagram of each signal of the phase detector according to an embodiment of the present invention. Figure 3b: Timing diagram of each signal of the phase detector according to an embodiment of the present invention. Figure 4: Circuit diagram of a hysteresis lock detector according to an embodiment of the present invention. Figure 5: A circuit diagram of an up/down frequency control circuit according to an embodiment of the present invention. Figure 6a: Timing diagram of each signal of the upconversion/downconversion control circuit according to an embodiment of the present invention. Figure 6b: Timing diagram of each signal of the upconversion/downconversion control circuit according to an embodiment of the present invention. Figure 7: Circuit diagram of a frequency detector according to an embodiment of the present invention. Figure 8a: Timing diagram of each signal of the frequency detector according to an embodiment of the present invention. Figure 8b: Timing diagram of each signal of the frequency detector according to an embodiment of the present invention.

100: Clock data recovery circuit

110: Phase detector

120: Frequency detector

130:Hysteresis lock detector

140:First charge pump

150: Second charge pump

160: Voltage controlled oscillator

170: Up/down frequency control circuit

180:Buffer

clkI: In-phase clock signal

clkQ: Quadrature clock signal

PDU: phase leading signal

PDD: Phase lag signal

lock: lock signal

FDU: frequency rise detection signal

FDD: Frequency drop detection signal

UP/DN: Frequency up/down control signal

LF: loop filter

Vf: fine adjustment voltage

Vc: coarse adjustment voltage

Cg: capacitance

Fout: output frequency

Claims (9)

A clock data recovery circuit, which includes: a phase detector that receives a same-phase clock signal and an input data, and the phase detector is used to detect the phase relationship between the same-phase clock signal and the input data. Output a phase detection signal, wherein the phase detector has a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first mutually exclusive OR gate and a The second mutually exclusive OR gate, and the phase detection signal has a phase leading detection signal and a phase lagging detection signal, the first flip-flop receives the input data and the in-phase clock signal, the first flip-flop The device is triggered by the positive edge of the in-phase clock signal to sample the input data and output a first sampling signal. The second flip-flop is electrically connected to the first flip-flop, and the second flip-flop receives the first The sampling signal and the in-phase clock signal, the second flip-flop is triggered by the positive edge of the in-phase clock signal to sample the first sampling signal and output a second sampling signal, the third flip-flop receives the input data and the in-phase clock signal. The third flip-flop is triggered by the negative edge of the in-phase clock signal to sample the input data and output a third sampling signal. The fourth flip-flop is electrically connected to the third flip-flop. The fourth flip-flop receives the third sampling signal and the in-phase clock signal. The fourth flip-flop is triggered by the positive edge of the in-phase clock signal to sample the third sampling signal and output a fourth sample. signal, the first mutual exclusive OR gate is electrically connected to the first flip-flop and the fourth flip-flop to receive the first sampling signal and the fourth sampling signal, and the first mutual exclusive OR gate outputs the phase Leading the detection signal, the second mutual exclusive OR gate is electrically connected to the second flip-flop and the fourth flip-flop to receive the second sampling signal and the fourth sampling signal, and the second mutual exclusive OR gate Output the phase lag detection signal; a frequency detector receives the in-phase clock signal, the input data and a quadrature clock signal, and the frequency detector is used to detect the in-phase clock signal and the input data The frequency relationship between them outputs a frequency detection signal; A hysteresis lock detector receives the in-phase clock signal and the input data. The hysteresis lock detector is used to determine the frequency difference between the in-phase clock signal and the input data and output a lock signal to the phase detector and the frequency detector; a first charge pump, electrically connected to the phase detector to receive the phase detection signal, and the first charge pump outputs a finely adjusted voltage through a loop filter; a A second charge pump is electrically connected to the frequency detector to receive the frequency detection signal, and the second charge pump charges or discharges a capacitor according to the frequency detection signal and outputs a coarse-adjusted voltage; a voltage-controlled oscillation an oscillator, electrically connected to the first charge pump and the second charge pump to receive the coarse voltage and the fine voltage, and the voltage controlled oscillator outputs the in-phase clock signal and the quadrature clock signal; and a The up/down frequency control circuit receives the in-phase clock signal and the input data, and the up/down frequency control circuit outputs a frequency up/down control signal to the frequency detector. The clock data recovery circuit of claim 1, wherein the hysteresis lock detector has a first counter, a first hysteresis switch, a fifth flip-flop, a second counter, a second hysteresis switch, A sixth flip-flop, an OR gate and a logic operation unit, the first counter receives the input data to count and outputs a first counting signal, the first hysteresis switch is electrically connected to the first counter to receive the The first counting signal, and the first hysteresis switch is controlled by the locking signal to output a first trigger signal. The fifth flip-flop is electrically connected to the first counter and the first hysteresis switch to receive the first The counting signal and the first trigger signal. The fifth flip-flop is triggered by the first trigger signal to sample the highest bit of the first counting signal and output a first temporary storage signal. The second counter receives the in-phase time The pulse signal is counted and a second counting signal is output. The second hysteresis switch is electrically connected to the second counter to receive the second counting signal, and the second hysteresis switch is controlled by the lock signal to output a second Trigger signal, the sixth The flip-flop is electrically connected to the second counter and the second hysteresis switch to receive the second count signal and the second trigger signal. The sixth flip-flop is triggered by the second count signal to sample the second count. The highest bit of the signal and outputs a second temporary signal, the OR gate is electrically connected to the fifth flip-flop and the sixth flip-flop to receive the first temporary signal and the second temporary signal, and The OR gate outputs a first logic signal, and the logic operation unit is electrically connected to the first counter, the second counter and the OR gate to receive the first counting signal, the second counting signal and the first logic signal, And the logic operation unit outputs the lock signal. For example, the clock data recovery circuit of claim 2, wherein the first hysteresis switch has a first transmission gate and a second transmission gate, the first transmission gate receives the lowest bit of the first count signal, and the second transmission gate The transmission gate receives the K-th bit of the first counting signal, and the first transmission gate and the second transmission gate are controlled by the lock signal and the reverse lock signal to decide whether to convert the lowest bit of the first counting signal or The Kth bit serves as the first trigger signal, where K is a positive integer between the lowest bit number and the highest bit number of the first counting signal. For example, the clock data recovery circuit of claim 2, wherein the logic operation unit has an inverse-OR gate, a first inverse-AND gate, a second inverse-AND gate, a third inverse-AND gate, a fourth inverse-AND gate, A seventh flip-flop and an inverse gate. The inverted OR gate receives the highest bit of the inverted first count signal and the highest bit of the inverted second count signal and outputs an inverted OR signal. The inverted OR gate An NAND gate receives the highest bit of the first counting signal and the highest bit of the second counting signal and outputs a first NAND signal. The second NAND gate receives the highest bit of the second counting signal and The first logic signal also outputs a second inverse-AND signal. The third inverse-AND gate receives the highest bit of the first count signal and the first logic signal and outputs a third inverse-AND signal. The fourth inverse-AND gate The gate is electrically connected to the first, second and third NAND gates to receive the first, second and third NAND signals, the fourth NAND gate outputs a count reset signal, and the seventh flip-flop is electrically connected to the The NOR gate and the fourth NOR gate are used to receive the NOR signal and the count reset signal, and the seventh flip-flop is affected by the count reset signal. The count reset signal triggers sampling of the inverse OR signal to output the lock signal and the inverse lock signal. The invert gate is electrically connected to the fourth invert gate to receive the count reset signal, and the invert gate outputs the inverse The count reset signal is sent to the first and second counters and the fifth and sixth flip-flops for resetting. For example, the clock data recovery circuit of claim 1, wherein the up/down frequency control circuit has a third counter, a fourth counter, an OR gate, an eighth flip-flop, a ninth flip-flop and an inverse gate, The third counter receives the in-phase clock signal to count and outputs a third counting signal. The fourth counter receives the input data to count and outputs a fourth counting signal. The OR gate is electrically connected to the third counter to receive The highest bit and the second highest bit of the third counting signal, and the OR gate outputs an OR gate signal. The eighth flip-flop is electrically connected to the OR gate and the fourth counter to receive the OR gate signal and the third counter. The second highest bit of the fourth count signal, the eighth flip-flop is triggered by the second highest bit of the fourth count signal to sample the OR gate signal, and the eighth flip-flop outputs the frequency up/down control signal, the eighth flip-flop Nine flip-flops are electrically connected to the fourth counter. The ninth flip-flop receives the highest bit of the fourth count signal and the divided in-phase clock signal. The ninth flip-flop is divided by the divided in-phase clock signal. The clock signal is triggered to sample the highest bit of the fourth count signal, and the ninth flip-flop outputs an up-and-down frequency count reset signal to the third and fourth counters through the inverter for resetting. For example, the clock data recovery circuit of claim 1, wherein the frequency detector has a frequency detection circuit and a frequency detection selection circuit, and the frequency detection signal has a frequency rising detection signal and a frequency falling detection signal, The frequency detection circuit receives the input data, the in-phase clock signal and the quadrature clock signal to detect and output a first frequency rising signal and a first frequency falling signal. The frequency detection selection circuit is electrically connected The frequency detection circuit, the frequency detection selection circuit receives the first frequency rising signal, the first frequency falling signal, the in-phase clock signal and the input data, and the frequency detection selection circuit outputs the frequency rising detection signal and the frequency drop detection signal. For example, the clock data recovery circuit of claim 6, wherein the frequency detection circuit has a delayer, a third mutually exclusive OR gate, a tenth flip-flop, an eleventh flip-flop, and a twelfth flip-flop. inverter, a thirteenth flip-flop, a fourteenth flip-flop, a fifteenth flip-flop and an output logic circuit, the delay device receives the input data and outputs a delayed data, the third mutex The OR gate is electrically connected to the delay device, the third mutual exclusive OR gate receives the input data and the delayed data, the third mutual exclusive OR gate outputs a detection trigger signal, and the tenth flip-flop is electrically connected to the mutual exclusive OR gate. reject or gate, the tenth flip-flop receives the in-phase clock signal and the detection trigger signal, and the tenth flip-flop outputs a tenth sampling signal, and the eleventh flip-flop is electrically connected to the tenth A flip-flop, the eleventh flip-flop receives the tenth sampling signal and the in-phase clock signal, and the eleventh flip-flop outputs an eleventh sampling signal and the inverted eleventh sampling signal, The twelfth flip-flop is electrically connected to the eleventh flip-flop, the twelfth flip-flop receives the eleventh sampling signal and the in-phase clock signal, and the twelfth flip-flop outputs a first Twelve sampling signals and the reversed twelfth sampling signal, the thirteenth flip-flop is electrically connected to the third mutually exclusive OR gate, and the thirteenth flip-flop receives the quadrature clock signal and the detection The trigger signal is detected, and the thirteenth flip-flop outputs a thirteenth sampling signal. The fourteenth flip-flop is electrically connected to the thirteenth flip-flop, and the fourteenth flip-flop receives the thirteenth sampling signal. The sampling signal and the in-phase clock signal, and the fourteenth flip-flop outputs a fourteenth sampling signal and the inverted fourteenth sampling signal, the fifteenth flip-flop is electrically connected to the fourteenth positive inverter an inverter, the fifteenth flip-flop receives the fourteenth sampling signal and the in-phase clock signal, and the fifteenth flip-flop outputs a fifteenth sampling signal and the inverted fifteenth sampling signal, The output logic circuit is electrically connected to the eleventh, twelfth, fourteenth and fifteenth flip-flops to receive the eleventh sampling signal, the inverted eleventh sampling signal, the twelfth sampling signal, the inverse The twelfth sampling signal in the direction, the fourteenth sampling signal in the opposite direction, and the fifteenth sampling signal in the opposite direction, and the output logic circuit outputs the first frequency rising signal and the first frequency falling signal. The clock data recovery circuit of claim 7, wherein the output logic circuit has a first A AND gate, a second AND gate, a third AND gate, a fourth AND gate and a fifth AND gate, the first AND gate is electrically connected to the eleventh and twelfth flip-flops to receive the reverse The eleventh sampling signal and the twelfth sampling signal, the second and gate are electrically connected to the fourteenth and fifteenth flip-flops to receive the reversed fourteenth sampling signal and the reversed third Fifteenth sampling signal, the third and gate are electrically connected to the eleventh and twelfth flip-flop to receive the eleventh sampling signal and the reversed twelfth sampling signal, the fourth and gate are electrically connected The first and second AND gates, and the fourth AND gate output the first frequency rising signal, the fifth AND gate is electrically connected to the second and third AND gate, and the fifth AND gate outputs the first frequency falling signal signal. For example, the clock data recovery circuit of claim 6, wherein the frequency detection selection circuit has a sixteenth flip-flop, a first multiplexer, a second multiplexer, a third multiplexer and a first multiplexer. Four multiplexers, the sixteenth flip-flop receives the in-phase clock signal and the input data, and the sixteenth flip-flop outputs a frequency difference signal, the first multiplexer is electrically connected to the sixteenth flip-flop Flip-flop, the first multiplexer receives the frequency difference signal, a ground voltage and the frequency rise/fall control signal, and the first multiplexer outputs a second frequency rise signal, the second multiplexer electrically The first multiplexer and the frequency detection circuit are connected, the second multiplexer receives the second frequency increase signal, the first frequency increase signal and the lock signal, and the second multiplexer outputs the frequency increase To detect the signal, the third multiplexer is electrically connected to the sixteenth flip-flop, the third multiplexer receives the frequency difference signal, the ground voltage and the frequency rise/fall control signal, and the third multiplexer The second multiplexer outputs a second frequency down signal, the fourth multiplexer is electrically connected to the third multiplexer and the frequency detection circuit, the second multiplexer receives the second frequency down signal, the first frequency down signal signal and the lock signal, and the fourth multiplexer outputs the frequency drop detection signal.

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