TWI825773B - Flyback power converter having emulated demagnetized signal and primary-side control circuit and control method thereof - Google Patents
Flyback power converter having emulated demagnetized signal and primary-side control circuit and control method thereof Download PDFInfo
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本發明係有關一種返馳式轉換器,特別是指一種具仿去磁訊號的返馳式轉換器。本發明也有關於用以控制具仿去磁訊號的返馳式轉換器的切換控制電路與控制方法。 The present invention relates to a flyback converter, and in particular to a flyback converter with a simulated demagnetization signal. The present invention also relates to a switching control circuit and a control method for controlling a flyback converter with a simulated demagnetization signal.
請參閱圖1,圖1顯示先前技術美國專利US 5,959,850的非對稱占空比返馳式轉換器(Asymmetrical Duty Cycle Flyback Converter),此先前技術揭露了具有零電壓切換(zero voltage switching,ZVS)的半橋返馳式轉換器,藉此達成較高的功率效率。零電壓切換可被定義為當電晶體的跨壓(例如:汲源極電壓)為零或接近於零時,將電晶體切換為導通。然而,本先前技術的缺點為,於輕負載狀態中,電源轉換器的功率轉換效率較低。 Please refer to Figure 1. Figure 1 shows an asymmetrical duty cycle flyback converter (Asymmetrical Duty Cycle Flyback Converter) in the prior art US Pat. No. 5,959,850. This prior art discloses an Asymmetrical Duty Cycle Flyback Converter with zero voltage switching (ZVS). Half-bridge flyback converter to achieve higher power efficiency. Zero-voltage switching can be defined as switching a transistor on when the voltage across the transistor (for example, the drain-to-source voltage) is zero or close to zero. However, a disadvantage of this prior art is that the power conversion efficiency of the power converter is low in light load conditions.
上述先前技術的另一個缺點在於,該電源轉換器的輸出電壓係不可變的,具體而言,上述先前技術若要改為具有可變輸出電壓的零電壓切換返馳式轉換器,必須藉由偵測其變壓器之去磁時段而控制變壓器的切換。 Another shortcoming of the above-mentioned prior art is that the output voltage of the power converter is non-variable. Specifically, if the above-mentioned prior art is to be changed to a zero-voltage switching flyback converter with a variable output voltage, it must be Detect the demagnetization period of its transformer and control the switching of the transformer.
另一先前技術美國專利US 7,151,681為測量變壓器的反射電壓與放電時段的多重取樣電路(Multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer),此先前技術揭露一種偵測變壓器的輸出電壓與去磁時段的方法,然而,本先前技術無法達成電源轉換器的零電壓切換,其係用於不連續導通模式(discontinuous conduction mode,DCM)的操作。 Another prior art, US Patent No. 7,151,681, is a multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer. This prior art discloses a method for detecting the output voltage and discharge time of a transformer. The method of degaussing period, however, this prior art cannot achieve zero-voltage switching of the power converter, which is used for discontinuous conduction mode (DCM) operation.
圖2顯示先前技術之半橋返馳式轉換器於輕負載狀態中操作於不連續導通模式之波形圖。驅動訊號SH用以驅動半橋返馳式轉換器的上橋開關,以激磁變壓器,驅動訊號SL用以驅動半橋返馳式轉換器的下橋開關,激磁電流IM的訊號波形顯示變壓器操作於不連續導通模式。當半橋返馳式轉換器的輸出功率下降時,驅動訊號SH的脈寬PW因半橋返馳式轉換器的回授控制而降低,驅動訊號SL的脈寬亦對應降低,因此,半橋返馳式轉換器的切換頻率增加,切換損失也因而增加。當驅動訊號SH轉為低位準(關斷)後,於變壓器的去磁時段中,驅動訊號SL的第一個脈波被致能。驅動訊號SL的第二脈波被致能以產生循環電流,藉此達成上橋開關的零電壓切換。 Figure 2 shows a waveform diagram of a prior art half-bridge flyback converter operating in discontinuous conduction mode in a light load state. The drive signal SH is used to drive the upper-bridge switch of the half-bridge flyback converter to excite the transformer. The drive signal SL is used to drive the lower-bridge switch of the half-bridge flyback converter. The signal waveform of the excitation current IM shows that the transformer operates in Discontinuous conduction mode. When the output power of the half-bridge flyback converter decreases, the pulse width PW of the drive signal SH decreases due to the feedback control of the half-bridge flyback converter, and the pulse width of the drive signal SL also decreases accordingly. Therefore, the half-bridge As the switching frequency of the flyback converter increases, the switching losses also increase. When the driving signal SH turns to a low level (off), the first pulse of the driving signal SL is enabled during the demagnetization period of the transformer. The second pulse wave of the driving signal SL is enabled to generate a circulating current, thereby achieving zero-voltage switching of the upper bridge switch.
上述先前技術的缺點在於,當操作於不連續導通模式時,驅動訊號SL於一個切換週期需切換導通/關斷兩次,因此大幅增加驅動訊號SL之平均切換頻率,造成大量的切換損失且導致下橋開關的能量耗損。 The disadvantage of the above-mentioned prior art is that when operating in the discontinuous conduction mode, the driving signal SL needs to be switched on/off twice in one switching cycle. Therefore, the average switching frequency of the driving signal SL is greatly increased, resulting in a large amount of switching losses and leading to Energy loss in the lower-side switch.
相較於先前技術美國專利US 7,151,681,本發明提供一種具有省略週期的諧振半橋返馳式轉換器,以改善中負載、輕負載之操作狀態中的功率效率。 Compared with the prior art US Patent No. 7,151,681, the present invention provides a resonant half-bridge flyback converter with omitted cycles to improve power efficiency in medium load and light load operating conditions.
相較於先前技術美國專利US 5,959,850,本發明提供一種產生去磁訊號的方法以及切換控制電路,其中去磁訊號的期間等於變壓器的 去磁時段,本發明可用於具有可程式化輸出電壓的零電壓切換返馳式轉換器,例如:USB PD電源轉換器。 Compared with the prior art US Patent No. 5,959,850, the present invention provides a method for generating a demagnetization signal and a switching control circuit, in which the period of the demagnetization signal is equal to the period of the transformer. During the demagnetization period, the present invention can be used in zero-voltage switching flyback converters with programmable output voltages, such as USB PD power converters.
相較於圖2的先前技術,本發明提供一種非對稱半橋(asymmetrical half-bridge,AHB)返馳式轉換器的控制電路,以三個電晶體改善中負載與輕負載之操作狀態的功率轉換效率。 Compared with the prior art in Figure 2, the present invention provides a control circuit for an asymmetrical half-bridge (AHB) flyback converter, using three transistors to improve the power in the operating states of medium load and light load. conversion efficiency.
就其中一個觀點言,本發明提供了一種返馳式轉換器,包含:一第一電晶體,用以切換一變壓器以產生一一次側開關電流及一輸出電壓;以及一第二電晶體,用以產生一循環電流以達成該第一電晶體的零電壓切換(zero voltage switching,ZVS);其中當該返馳式轉換器根據該一次側開關電流而判斷為已有一預設數量之切換週期係操作於一非不連續導通模式(non-discontinuous conduction mode,non-DCM)時,該返馳式轉換器主動強制至少一個切換週期操作於一不連續導通模式(discontinuous conduction mode,DCM)。 From one of the aspects, the present invention provides a flyback converter, including: a first transistor for switching a transformer to generate a primary-side switching current and an output voltage; and a second transistor, Used to generate a circulating current to achieve zero voltage switching (ZVS) of the first transistor; wherein the flyback converter determines that there has been a preset number of switching cycles based on the primary side switching current. When operating in a non-discontinuous conduction mode (non-DCM), the flyback converter actively forces at least one switching cycle to operate in a discontinuous conduction mode (DCM).
在一較佳實施例中,該返馳式轉換器用以產生一去磁訊號,其中該去磁訊號仿擬該變壓器的一去磁時段,以於該非不連續導通模式期間控制該第二電晶體,其中該返馳式轉換器根據該主動強制之不連續導通模式期間的該去磁時段而校正該去磁訊號。 In a preferred embodiment, the flyback converter is used to generate a demagnetization signal, wherein the demagnetization signal simulates a demagnetization period of the transformer to control the second transistor during the non-discontinuous conduction mode. , wherein the flyback converter corrects the degaussing signal according to the degaussing period during the actively forced discontinuous conduction mode.
在一較佳實施例中,於該主動強制之不連續導通模式中,該返馳式轉換器從該變壓器的一輔助繞組偵測一反射電壓,以於該第一電晶體關斷期間校正該去磁訊號,其中該反射電壓出現之時間長度相關於該變壓器的該去磁時段。 In a preferred embodiment, in the actively forced discontinuous conduction mode, the flyback converter detects a reflected voltage from an auxiliary winding of the transformer to correct the first transistor during the off period. A degaussing signal, in which the length of time the reflected voltage occurs is related to the degaussing period of the transformer.
在一較佳實施例中,該第一電晶體與該第二電晶體形成一半橋電路,其中於該主動強制之不連續導通模式中,在該第一電晶體關斷後,該第二電晶體被控制為關斷,使得該半橋電路操作於一非同步模式。 In a preferred embodiment, the first transistor and the second transistor form a half-bridge circuit, wherein in the actively forced discontinuous conduction mode, after the first transistor is turned off, the second transistor The crystal is controlled off, causing the half-bridge circuit to operate in an asynchronous mode.
在一較佳實施例中,該返馳式轉換器更包含一週期計數器,該週期計數器用以計算該返馳式轉換器操作於該非不連續導通模式的切換週期數量,使得當該一次側開關電流已有一預設數量之切換週期係操作於該非不連續導通模式時,致能該返馳式轉換器主動強制操作於不連續導通模式。 In a preferred embodiment, the flyback converter further includes a cycle counter, the cycle counter is used to count the number of switching cycles in which the flyback converter operates in the non-discontinuous conduction mode, so that when the primary side switch When the current has been operating in the non-discontinuous conduction mode for a preset number of switching cycles, the flyback converter is enabled to actively force operation in the discontinuous conduction mode.
在一較佳實施例中,該去磁訊號的一脈波期間用以控制該第二電晶體的最小導通時間,藉此於該第一電晶體關斷後,去磁該變壓器。 In a preferred embodiment, a pulse period of the demagnetization signal is used to control the minimum conduction time of the second transistor, thereby demagnetizing the transformer after the first transistor is turned off.
在一較佳實施例中,該去磁訊號的一脈波期間相關於該變壓器之一激磁時段中的一輸入電壓之一位準、該變壓器的該輸出電壓之一位準以及該第一電晶體的一導通期間。 In a preferred embodiment, a pulse period of the degaussing signal is related to a level of an input voltage in an excitation period of the transformer, a level of the output voltage of the transformer and the first voltage. A conduction period of the crystal.
在一較佳實施例中,該返馳式轉換器更包含一電阻,其中該去磁訊號的一脈波期間根據該電阻之電阻值而決定;其中該返馳式轉換器根據該變壓器於該主動強制之不連續導通模式期間的該去磁時段而調整該電阻之電阻值,以校正該去磁訊號。 In a preferred embodiment, the flyback converter further includes a resistor, wherein a pulse period of the degaussing signal is determined based on the resistance value of the resistor; wherein the flyback converter is based on the transformer in the transformer. The resistance value of the resistor is adjusted during the degaussing period during the active forced discontinuous conduction mode to correct the degaussing signal.
在一較佳實施例中,於該主動強制之不連續導通模式期間關斷該第一電晶體後,該變壓器的一去磁電流的一部分流經該第二電晶體的一本體二極體。 In a preferred embodiment, after turning off the first transistor during the actively forced discontinuous conduction mode, a portion of a demagnetization current of the transformer flows through a body diode of the second transistor.
在一較佳實施例中,該返馳式轉換器為一諧振返馳式轉換器,更包含一諧振電容,該諧振電容串聯耦接於該變壓器。 In a preferred embodiment, the flyback converter is a resonant flyback converter and further includes a resonant capacitor, and the resonant capacitor is coupled in series to the transformer.
在一較佳實施例中,一第二驅動訊號於該不連續導通模式後的第一個脈波用以導通該第二電晶體,以自該諧振電容提供一激磁電流至 該變壓器激磁該變壓器,進而產生一負循環電流以達成該第一電晶體的零電壓切換。 In a preferred embodiment, a first pulse wave of a second driving signal after the discontinuous conduction mode is used to turn on the second transistor to provide an exciting current from the resonant capacitor to The transformer energizes the transformer, thereby generating a negative circulating current to achieve zero-voltage switching of the first transistor.
就另一個觀點言,本發明也提供了一種切換控制電路,用以控制一返馳式轉換器,其中該返馳式轉換器包括:一第一電晶體,用以切換一變壓器以產生一一次側開關電流及一輸出電壓;以及一第二電晶體,用以產生一循環電流以達成該第一電晶體的零電壓切換(zero voltage switching,ZVS),該切換控制電路包含:一控制元件,用以產生一第一訊號及一第二訊號,該第一訊號及該第二訊號根據一回授訊號分別控制該第一電晶體及該第二電晶體,其中該回授訊號相關於該輸出電壓;以及一週期計數器,用以根據該一次側開關電流而計算該返馳式轉換器操作於一非不連續導通模式的切換週期數量;其中當該控制元件根據該一次側開關電流而判斷為已有一預設數量之切換週期係操作於該非不連續導通模式時,該控制元件主動強制至少一個切換週期操作於一不連續導通模式(discontinuous conduction mode,DCM)。 From another point of view, the present invention also provides a switching control circuit for controlling a flyback converter, wherein the flyback converter includes: a first transistor for switching a transformer to generate a The secondary side switching current and an output voltage; and a second transistor to generate a circulating current to achieve zero voltage switching (ZVS) of the first transistor, the switching control circuit includes: a control element , used to generate a first signal and a second signal, the first signal and the second signal respectively control the first transistor and the second transistor according to a feedback signal, wherein the feedback signal is related to the Output voltage; and a period counter for calculating the number of switching cycles in which the flyback converter operates in a non-discontinuous conduction mode based on the primary-side switching current; wherein when the control element determines based on the primary-side switching current When there has been a preset number of switching cycles operating in the non-discontinuous conduction mode, the control element actively forces at least one switching cycle to operate in a discontinuous conduction mode (DCM).
在一較佳實施例中,該切換控制電路更包含一去磁仿擬器,該去磁仿擬器用以產生一去磁訊號以仿擬該變壓器的一去磁時段,進而於該非不連續導通模式期間控制該第二電晶體,其中該去磁仿擬器根據該主動強制之不連續導通模式期間的該去磁時段而校正該去磁訊號。 In a preferred embodiment, the switching control circuit further includes a demagnetization simulator, which is used to generate a demagnetization signal to simulate a demagnetization period of the transformer, and then during the non-discontinuous conduction The second transistor is controlled during the mode, wherein the degaussing simulator corrects the degaussing signal according to the degaussing period during the actively forced discontinuous conduction mode.
在一較佳實施例中,於該主動強制之不連續導通模式中,該去磁仿擬器從該變壓器的一輔助繞組偵測一反射電壓,以於該第一電晶體關斷期間校正該去磁訊號,其中該反射電壓出現之時間長度相關於該變壓器的該去磁時段。 In a preferred embodiment, in the actively forced discontinuous conduction mode, the degaussing simulator detects a reflected voltage from an auxiliary winding of the transformer to correct the first transistor during the off period. A degaussing signal, in which the length of time the reflected voltage occurs is related to the degaussing period of the transformer.
在一較佳實施例中,該第一電晶體與該第二電晶體形成一半橋電路,其中於該主動強制之不連續導通模式中,在該第一電晶體關斷後,該第二電晶體被控制為關斷,使得該半橋電路操作於一非同步模式。 In a preferred embodiment, the first transistor and the second transistor form a half-bridge circuit, wherein in the actively forced discontinuous conduction mode, after the first transistor is turned off, the second transistor The crystal is controlled off, causing the half-bridge circuit to operate in an asynchronous mode.
在一較佳實施例中,該去磁訊號的一脈波期間用以控制該第二電晶體的最小導通時間,藉此於該第一電晶體關斷後,去磁該變壓器。 In a preferred embodiment, a pulse period of the demagnetization signal is used to control the minimum conduction time of the second transistor, thereby demagnetizing the transformer after the first transistor is turned off.
在一較佳實施例中,該去磁訊號的一脈波期間相關於該變壓器之一激磁時段中的一輸入電壓之一位準、該變壓器的該輸出電壓之一位準以及該第一電晶體的一導通期間。 In a preferred embodiment, a pulse period of the degaussing signal is related to a level of an input voltage in an excitation period of the transformer, a level of the output voltage of the transformer and the first voltage. A conduction period of the crystal.
在一較佳實施例中,該切換控制電路更調整一電阻之電阻值,以根據該變壓器於該主動強制之不連續導通模式期間的該去磁時段而校正該去磁訊號,其中該電阻耦接於該返馳式轉換器,其中該去磁訊號的一脈波期間根據該電阻之電阻值而決定。 In a preferred embodiment, the switching control circuit further adjusts the resistance value of a resistor to correct the degaussing signal according to the degaussing period of the transformer during the active forced discontinuous conduction mode, wherein the resistor couple Connected to the flyback converter, a pulse period of the demagnetization signal is determined according to the resistance value of the resistor.
在一較佳實施例中,於該主動強制之不連續導通模式期間,該控制元件控制該第二電晶體關斷,使得該第一電晶體關斷後,該變壓器的一去磁電流的一部分流經該第二電晶體的一本體二極體。 In a preferred embodiment, during the active forced discontinuous conduction mode, the control element controls the second transistor to turn off, so that after the first transistor turns off, a part of the demagnetization current of the transformer Flow through a body diode of the second transistor.
在一較佳實施例中,一第二驅動訊號於該不連續導通模式後的第一個脈波用以導通該第二電晶體,以自該返馳式轉換器的一諧振電容提供一激磁電流至該變壓器激磁該變壓器,進而產生一負循環電流以達成該第一電晶體的零電壓切換,其中該諧振電容串聯耦接於該變壓器。 In a preferred embodiment, a first pulse of a second drive signal after the discontinuous conduction mode is used to turn on the second transistor to provide an excitation from a resonant capacitor of the flyback converter. Current flows to the transformer to excite the transformer, thereby generating a negative circulating current to achieve zero-voltage switching of the first transistor, wherein the resonant capacitor is coupled in series to the transformer.
在一較佳實施例中,該去磁仿擬器包括:一積分電容及一開關,其中該開關耦接以取樣維持『sample and hold是一種專用動詞,有空可以解釋,也可以上網先查一下,蠻常用到』一電流感測訊號,其中該電流感測訊號相關於該一次側開關電流;以及一放電電路,用以產生一放電電流以將該積分電容放電,其中該放電電流相關於該輸出電壓;其中該去磁訊號根 據該積分電容的一跨壓而產生,其中該放電電流從激磁該變壓器的一端將該積分電容放電。 In a preferred embodiment, the degaussing simulator includes: an integrating capacitor and a switch, wherein the switch is coupled to sample and hold. "Sample and hold is a special verb. You can explain it when you have time, or you can check it online first." Now, it is quite common to use a current sensing signal, wherein the current sensing signal is related to the primary side switch current; and a discharge circuit to generate a discharge current to discharge the integrating capacitor, wherein the discharge current is related to The output voltage; where the demagnetization signal root It is generated according to a voltage across the integrating capacitor, wherein the discharge current discharges the integrating capacitor from one end of the energized transformer.
就另一個觀點言,本發明也提供了一種控制方法,用以控制一返馳式轉換器,其中該返馳式轉換器包括:一第一電晶體,用以切換一變壓器以產生一一次側開關電流及一輸出電壓;以及一第二電晶體,用以產生一循環電流以達成該第一電晶體的零電壓切換(zero voltage switching,ZVS),該控制方法包含:產生一第一訊號及一第二訊號,該第一訊號及該第二訊號根據一回授訊號分別控制該第一電晶體及該第二電晶體,其中該回授訊號相關於該輸出電壓;根據該一次側開關電流而計算該返馳式轉換器操作於一非不連續導通模式的切換週期數量;以及當根據該一次側開關電流而判斷為已有一預設數量之切換週期係操作於該非不連續導通模式時,主動強制至少一個切換週期操作於一不連續導通模式(discontinuous conduction mode,DCM)。 From another point of view, the present invention also provides a control method for controlling a flyback converter, wherein the flyback converter includes: a first transistor for switching a transformer to generate a primary side switch current and an output voltage; and a second transistor for generating a circulating current to achieve zero voltage switching (ZVS) of the first transistor. The control method includes: generating a first signal and a second signal, the first signal and the second signal respectively control the first transistor and the second transistor according to a feedback signal, wherein the feedback signal is related to the output voltage; according to the primary side switch current to calculate the number of switching cycles in which the flyback converter operates in a non-discontinuous conduction mode; and when it is determined based on the primary side switch current that a predetermined number of switching cycles have been operated in the non-discontinuous conduction mode. , actively forcing at least one switching cycle to operate in a discontinuous conduction mode (DCM).
在一較佳實施例中,該控制方法更包含:產生一去磁訊號以仿擬該變壓器的一去磁時段,進而於該非不連續導通模式期間控制該第二電晶體;以及根據該主動強制之不連續導通模式期間的該去磁時段而校正該去磁訊號。 In a preferred embodiment, the control method further includes: generating a demagnetization signal to simulate a demagnetization period of the transformer, thereby controlling the second transistor during the non-discontinuous conduction mode; and according to the active forcing The degaussing signal is corrected during the degaussing period during the discontinuous conduction mode.
在一較佳實施例中,校正該去磁訊號之步驟包括:於該主動強制之不連續導通模式中,從該變壓器的一輔助繞組偵測一反射電壓,以於該第一電晶體關斷期間校正該去磁訊號,其中該反射電壓出現之時間長度相關於該變壓器的該去磁時段。 In a preferred embodiment, the step of correcting the degaussing signal includes detecting a reflected voltage from an auxiliary winding of the transformer in the active forced discontinuous conduction mode to turn off the first transistor. The degaussing signal is corrected during a period, wherein the length of time during which the reflected voltage occurs is related to the degaussing period of the transformer.
在一較佳實施例中,該第一電晶體與該第二電晶體形成一半橋電路,其中校正該去磁訊號之步驟更包括:於該主動強制之不連續導通模 式中,在該第一電晶體關斷後,控制該第二電晶體為關斷,使得該半橋電路操作於一非同步模式。 In a preferred embodiment, the first transistor and the second transistor form a half-bridge circuit, wherein the step of correcting the demagnetization signal further includes: in the actively forced discontinuous conduction mode In the formula, after the first transistor is turned off, the second transistor is controlled to be turned off, so that the half-bridge circuit operates in an asynchronous mode.
在一較佳實施例中,產生該第一訊號及該第二訊號之步驟包括:根據該去磁訊號的一脈波期間而控制該第二電晶體的最小導通時間,藉此於該第一電晶體關斷後,去磁該變壓器。 In a preferred embodiment, the step of generating the first signal and the second signal includes: controlling the minimum conduction time of the second transistor according to a pulse period of the degaussing signal, thereby controlling the first After the transistor is turned off, the transformer is demagnetized.
在一較佳實施例中,該去磁訊號的一脈波期間相關於該變壓器之一激磁時段中的一輸入電壓之一位準、該變壓器的該輸出電壓之一位準以及該第一電晶體的一導通期間。 In a preferred embodiment, a pulse period of the degaussing signal is related to a level of an input voltage in an excitation period of the transformer, a level of the output voltage of the transformer and the first voltage. A conduction period of the crystal.
在一較佳實施例中,校正該去磁訊號之步驟包括:調整一電阻之電阻值,以根據該變壓器於該主動強制之不連續導通模式期間的該去磁時段而校正該去磁訊號,其中該電阻耦接於該返馳式轉換器,其中該去磁訊號的一脈波期間根據該電阻之電阻值而決定。 In a preferred embodiment, the step of correcting the degaussing signal includes: adjusting a resistance value of a resistor to correct the degaussing signal according to the degaussing period during the active forced discontinuous conduction mode of the transformer, The resistor is coupled to the flyback converter, and a pulse period of the demagnetization signal is determined according to the resistance value of the resistor.
在一較佳實施例中,該控制方法更包含:於該主動強制之不連續導通模式期間,控制該第二電晶體關斷,使得該第一電晶體關斷後,該變壓器的一去磁電流的一部分流經該第二電晶體的一本體二極體。 In a preferred embodiment, the control method further includes: controlling the second transistor to turn off during the active forced discontinuous conduction mode, so that after the first transistor turns off, a demagnetization of the transformer Part of the current flows through a body diode of the second transistor.
在一較佳實施例中,該控制方法更包含:藉由一第二驅動訊號於該不連續導通模式後的第一個脈波導通該第二電晶體,以自該返馳式轉換器的一諧振電容提供一激磁電流至該變壓器以激磁該變壓器,進而產生一負循環電流以達成該第一電晶體的零電壓切換,其中該諧振電容串聯耦接於該變壓器。 In a preferred embodiment, the control method further includes: using a second driving signal to conduct the second transistor in the first pulse wave after the discontinuous conduction mode to convert the flyback converter from A resonant capacitor provides an excitation current to the transformer to excite the transformer, thereby generating a negative circulating current to achieve zero-voltage switching of the first transistor, wherein the resonant capacitor is coupled in series to the transformer.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。 It will be easier to understand the purpose, technical content, characteristics and achieved effects of the present invention through detailed description of specific embodiments below.
10:變壓器 10: Transformer
100:二次側控制器 100: Secondary side controller
20:諧振電容 20: Resonant capacitor
200:一次側控制器 200: Primary side controller
201:一次側控制器 201: Primary side controller
205:時脈產生器 205: Clock generator
208:一次側控制器 208: Primary side controller
22:計時器 22: timer
230:電容 230: Capacitor
231:開關 231: switch
240:控制元件 240:Control components
243:控制元件 243:Control components
248:控制元件 248:Control components
25:計時器 25: timer
250:去磁仿擬器 250:Degaussing simulator
255:電阻 255: Resistor
260:週期計數器 260: Period counter
271,272:電晶體 271,272: Transistor
280:比較器 280: Comparator
285:邏輯電路 285:Logic circuit
30:第一電晶體 30:The first transistor
300:諧振半橋返馳式轉換器 300: Resonant half-bridge flyback converter
35:本體二極體 35:Body diode
40:第二電晶體 40:Second transistor
45:本體二極體 45:Body diode
51,52,55,60:電阻 51,52,55,60: Resistor
70:二次側同步整流器 70: Secondary side synchronous rectifier
75:本體二極體 75:Body Diode
90:光耦合器 90: Optocoupler
900:諧振半橋返馳式轉換器 900: Resonant half-bridge flyback converter
C:電容值 C: capacitance value
CPO:比較器輸出 CPO: comparator output
DCM:不連續導通模式 DCM: discontinuous conduction mode
ID:放電電流 ID: discharge current
IM:激磁電流 IM: exciting current
IP:一次側開關電流 IP: primary side switching current
IS:二次側開關電流 IS: secondary side switching current
kn:膝點 kn: knee point
Lr:漏電感 Lr: leakage inductance
LX:切換節點 LX: switch node
M1:第一電晶體 M1: the first transistor
M2:第二電晶體 M2: Second transistor
M3:第三電晶體 M3: The third transistor
n,m:匝數比 n,m: turns ratio
NA:輔助繞組 NA: auxiliary winding
NC:正整數 NC: positive integer
NNP:耦接節點 NNP: coupling node
NP:一次側繞組 NP: primary winding
NS:二次側繞組 NS: secondary winding
PW:脈寬 PW: pulse width
PZV:零電壓切換脈波 PZV: zero voltage switching pulse
Rs:電阻值 Rs: resistance value
Rt:電阻值 Rt: resistance value
S1:第一驅動訊號 S1: first driving signal
S2:第二驅動訊號 S2: second drive signal
S3:第三驅動訊號 S3: The third driving signal
Sdmg:去磁訊號 Sdmg: degaussing signal
SG:驅動訊號 SG: drive signal
SH:驅動訊號 SH: drive signal
SL:驅動訊號 SL: drive signal
SMP:取樣訊號 SMP: sampling signal
t1-t9:時點 t1-t9: time point
t3’:時點 t3’: time point
ta-te:時點 ta-te: time point
TA:第一時段 TA: first period
ta’,tc’:時點 ta’,tc’: time point
TB:第二時段 TB: Second period
TC:第三時段 TC: The third period
Tcyc1:切換週期 Tcyc1: switching cycle
Tcyc2:切換週期 Tcyc2: switching cycle
Td1:第一不導通時段 Td1: first non-conduction period
Td2:第二不導通時段 Td2: The second non-conduction period
TDS:去磁時段 TDS: degaussing period
TDSX:導通期間 TDSX: conduction period
TDSX’:導通期間 TDSX’: conduction period
TRH:時段 TRH: time period
TRL:時段 TRL: time period
TSL:導通期間 TSL: conduction period
TW:激磁時段 TW: Excitation period
Tx:省略週期 Tx: Omit cycle
TZ:第三不導通時段 TZ: The third non-conduction period
VAUX:輔助訊號 VAUX: auxiliary signal
VC:跨壓 VC: voltage across
Vcr:跨壓 Vcr: cross voltage
VCS:電流感測訊號 VCS: current sensing signal
VCSp:電壓位準 VCSp: voltage level
VDP:電壓降 VDP: voltage drop
VFB:回授訊號 VFB: feedback signal
Vg:電壓位準 Vg: voltage level
VHB:切換節點電壓 VHB: switching node voltage
VIN:輸入電壓 VIN: input voltage
Vinx:電壓位準 Vinx: voltage level
VNA:輔助繞組訊號 VNA: auxiliary winding signal
VO:輸出電壓 VO: output voltage
VPK:電壓突波 VPK: voltage surge
Vref:參考電壓 Vref: reference voltage
Vth:電壓閾值 Vth: voltage threshold
VX:反射電壓 VX: reflected voltage
圖1顯示先前技術之非對稱占空比返馳式轉換器。 Figure 1 shows a prior art asymmetric duty cycle flyback converter.
圖2顯示先前技術之半橋返馳式轉換器於輕負載狀態中操作於不連續導通模式之波形圖。 Figure 2 shows a waveform diagram of a prior art half-bridge flyback converter operating in discontinuous conduction mode in a light load state.
圖3顯示本發明之諧振半橋返馳式轉換器之一實施例示意圖。 FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention.
圖4顯示對應於圖3之實施例的操作波形圖。 FIG. 4 shows an operating waveform diagram corresponding to the embodiment of FIG. 3 .
圖5顯示降低驅動訊號SH與驅動訊號SL的切換頻率之操作波形圖。 FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL.
圖6顯示本發明之具有省略週期的諧振半橋返馳式轉換器的一實施例之操作波形圖。 FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.
圖7顯示本發明之諧振半橋返馳式轉換器中一次側控制器之一實施例方塊圖。 FIG. 7 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention.
圖8顯示本發明之諧振半橋返馳式轉換器中一次側控制器之一實施例方塊圖。 FIG. 8 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention.
圖9顯示本發明之去磁仿擬器產生去磁訊號之操作波形圖。 FIG. 9 shows the operation waveform diagram of the degaussing signal generated by the degaussing simulator of the present invention.
圖10顯示本發明去磁仿擬器產生去磁訊號Sdmg之一具體實施例示意圖。 FIG. 10 shows a schematic diagram of a specific embodiment of the degaussing simulator generating the degaussing signal Sdmg according to the present invention.
圖11顯示本發明之諧振半橋返馳式轉換器之一較佳實施例示意圖。 FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention.
圖12顯示本發明之一次側控制器201操作於不連續導通模式之一較佳實施例操作波形圖。
FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-
圖13顯示本發明一次側控制器之一較佳實施例方塊圖。 Figure 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention.
本發明中的圖式均屬示意,主要意在表示各電路間之耦接關係,以及各訊號波形之間之關係,至於電路、訊號波形與頻率則並未依照比例繪製。 The diagrams in the present invention are schematic and are mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.
圖3顯示本發明之諧振半橋返馳式轉換器之一實施例示意圖。諧振半橋返馳式轉換器300包含:第一電晶體30及第二電晶體40,用以構成半橋電路。變壓器10及諧振電容20彼此串聯並耦接於半橋電路的切換節點LX,變壓器10包括一次側繞組NP、二次側繞組NS以及輔助繞組NA,其中一次側繞組NP及二次側繞組NS具有匝數比n,二次側繞組NS及輔助繞組NA具有匝數比m。一次側控制器200產生驅動訊號SH及驅動訊號SL,驅動訊號SH及驅動訊號SL經由半橋電路切換變壓器10,以於變壓器10的二次側產生輸出電壓VO。驅動訊號SH驅動第一電晶體30,以激磁變壓器10。驅動訊號SL於變壓器10的去磁與諧振時段中導通第二電晶體40,驅動訊號SL亦用於導通第二電晶體40以產生流經變壓器10的循環電流,以達成第一電晶體30的零電壓切換。電阻60藉由偵測變壓器10的一次側開關電流IP而產生電流感測訊號VCS。
FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-
驅動訊號SH及驅動訊號SL根據回授訊號VFB而產生,其中回授訊號VFB根據諧振半橋返馳式轉換器300的輸出功率而產生。二次側控制器100耦接於輸出電壓VO以產生回授訊號VFB,回授訊號VFB經由光耦合器90耦接於一次側控制器200。二次側控制器100亦用以產生驅動訊號SG,以於變壓器10的去磁時段TDS中驅動二次側同步整流器70。輔助繞組NA於變壓器10切換時產生輔助繞組訊號VNA,電阻51、電阻52用以將輔助繞組訊號VNA衰減以產生輔助訊號VAUX,輔助訊號VAUX耦接於一次側控制器200。在一實施例中,電阻55耦接於一次側控制器200,藉由電阻55以設定參數而產生去磁訊號Sdmg。
The driving signal SH and the driving signal SL are generated according to the feedback signal VFB, wherein the feedback signal VFB is generated according to the output power of the resonant half-
圖4顯示對應於圖3之實施例的操作波形圖。當驅動訊號SH導通時,變壓器10被激磁並產生激磁電流IM,當驅動訊號SH不導通時,變壓器10被去磁。於去磁時段TDS中,變壓器10產生二次側開關電流IS,驅動訊號SL相關於變壓器10的去磁時段TDS。在一實施例中,驅動訊號SL之導通期間TSL(亦即脈寬)等於或長於變壓器10的去磁時段TDS,藉此避免變壓器10操作於連續導通模式(continuous conduction mode,CCM)。於變壓器10的去磁時段TDS中,諧振電容20上產生反射電壓VX,其中反射電壓VX與輸出電壓VO之關係為:VX=n*VO。
FIG. 4 shows an operating waveform diagram corresponding to the embodiment of FIG. 3 . When the driving signal SH is turned on, the
當驅動訊號SH不導通時,驅動訊號SL可被導通,而當驅動訊號SL不導通時,驅動訊號SH可被導通。驅動訊號SH與驅動訊號SL之間(即驅動訊號SH與驅動訊號SL皆不導通時)可包括空滯時間(例如時段TRH、時段TRL)。 When the driving signal SH is not conductive, the driving signal SL may be turned on, and when the driving signal SL is not conductive, the driving signal SH may be turned on. The period between the driving signal SH and the driving signal SL (that is, when neither the driving signal SH nor the driving signal SL is conductive) may include a dead time (such as a period TRH, a period TRL).
圖4之不同時段中的操作細節詳見下列說明。 Details of the operations in different time periods in Figure 4 are detailed in the following description.
時點t1至時點t2之時段為激磁變壓器週期,本時段中第一電晶體30導通且第二電晶體40關斷,流經變壓器10中的一次側開關電流IP增加且諧振電容20之電壓亦增加,此時變壓器10被激磁而諧振電容20進行充電,二次側同步整流器70關斷且其本體二極體75具有逆向偏壓,因此,此時並無能量被轉換至二次側。
The period from time point t1 to time point t2 is the excitation transformer period. During this period, the
時點t2至時點t3之時段為第一循環電流週期,本時段中第一電晶體30與第二電晶體40均關斷,變壓器10的循環電流強制半橋電路的切換節點電壓VHB下降,直到第二電晶體40的本體二極體45導通為止。時點t2至時點t3之時段相關於準諧振時段(quasi-resonant period),以達成第二電晶體40的零電壓切換,此時變壓器10的一次側電壓與諧振電容20於時點t3之電壓相同。
The period from time point t2 to time point t3 is the first circulating current period. During this period, the
時點t3至時點t4之時段為諧振週期(正電流),本時段中,在零電壓切換的狀態下,第一電晶體30關斷且第二電晶體40導通,此時輸出電壓VO等於諧振電容20的跨壓Vcr除以匝數比n,電流開始流經二次側同步整流器70,儲存於變壓器10的能量被轉換至輸出端而產生輸出電壓VO。由於變壓器10的漏電感Lr與諧振電容20(Cr)形成電感電容槽(LC tank),因此二次側電流於諧振頻率Lr及Cr所決定的時段中為正弦波的形式。變壓器10的一次側電流為激磁電流IM與二次側開關電流IS之和。流經諧振槽(Lr,Cr)的電流仍為正電流,其主要由變壓器10的激磁電感驅動,並且流經諧振電容20。
The period from time point t3 to time point t4 is the resonance period (positive current). During this period, in the zero-voltage switching state, the
時點t4至時點t5之時段為諧振週期(負電流),本時段中第一電晶體30繼續關斷且第二電晶體40繼續導通,能量持續轉換至二次側,但諧振槽電流被諧振電容20的電壓反向驅動,諧振電容20的能量不僅被轉換至二次側,更於第二電晶體40持續導通(例如時點t4至時點t5)時,用以將變壓器10的激磁電流位準拉至負值。
The period from time point t4 to time point t5 is the resonance period (negative current). During this period, the
時點t5至時點t6之時段為反向激磁變壓器週期(負電流),本時段自變壓器10的去磁時段TDS結束時至第二電晶體40關斷時,諧振電容20反向激磁變壓器10,並產生負電流。
The period from time point t5 to time point t6 is the reverse excitation transformer period (negative current). In this period from the end of the demagnetization period TDS of the
時點t6至時點t7之時段為第二循環電流週期,本時段中第一電晶體30與第二電晶體40均關斷,變壓器10的負電流於時點t5至時點t6被感應而產生,以強制半橋電路中切換節點LX上的切換節點電壓VHB增加,直到其導通第一電晶體30的本體二極體35為止。
The period from time point t6 to time point t7 is the second circulating current period. During this period, the
時點t7之後,開始另一個與時點t1至時點t2之時段相似的週期,第一電晶體30在零電壓切換狀態下導通且第二電晶體40關斷,若變壓器諧振槽中的循環電流仍為負電流,則諧振槽中多餘的能量將被送回輸入端(供應輸入電壓VIN的節點)。
After time point t7, another period similar to the period from time point t1 to time point t2 begins. The
在輕負載的狀態下,當輸出功率降低時,驅動訊號SH與驅動訊號SL的脈寬將對應減少,故驅動訊號SH與驅動訊號SL的切換頻率於輕負載狀態下增加,由於鐵芯損失(core loss)、開關損耗(switching loss)等功率損耗增加,因此導致功率轉換器的功率轉換效率變差。 In the light load state, when the output power decreases, the pulse widths of the drive signal SH and the drive signal SL will decrease accordingly. Therefore, the switching frequency of the drive signal SH and the drive signal SL increases in the light load state. Due to the core loss ( Power losses such as core loss and switching loss increase, thus causing the power conversion efficiency of the power converter to deteriorate.
圖5顯示降低驅動訊號SH與驅動訊號SL的切換頻率之操作波形圖。一種改善功率效率的方式是,藉由延長驅動訊號SL關斷(例如時點t3)至驅動訊號SH導通(例如時點t5)之間的時間,可降低切換頻率,然而,驅動訊號SL的關斷將產生循環電流,進而導致切換節點電壓VHB的電壓突波VPK以及輔助訊號VAUX的電壓降VDP,電壓突波VPK與電壓降VDP將造成功率損耗與雜訊。 FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL. One way to improve power efficiency is to reduce the switching frequency by extending the time between the turning off of the driving signal SL (for example, time point t3) and the turning on of the driving signal SH (for example, time point t5). However, the turning off of the driving signal SL will A circulating current is generated, which in turn causes a voltage surge VPK of the switching node voltage VHB and a voltage drop VDP of the auxiliary signal VAUX. The voltage surge VPK and voltage drop VDP will cause power loss and noise.
需注意的是,前述驅動訊號SH與驅動訊號SL的導通或關斷皆各自對應於第一電晶體30與第二電晶體40的導通或關斷。
It should be noted that the aforementioned turning on or off of the driving signal SH and the driving signal SL respectively corresponds to the turning on or off of the
圖6顯示本發明之具有省略週期的諧振半橋返馳式轉換器的一實施例之操作波形圖。 FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.
請參閱圖6,在一實施例中,驅動訊號SH於激磁變壓器10的激磁週期中(例如時點t1至時點t2)導通,以激磁變壓器10。驅動訊號SH關斷後,驅動訊號SL於諧振週期中(例如時點t2至時點t3)導通,且具有諧振脈波(例如時點t2至時點t3),一個激磁週期與一個諧振週期形成一個切換週期(例如時點t1至時點t3)。
Referring to FIG. 6 , in one embodiment, the driving signal SH is turned on during the excitation period of the excitation transformer 10 (for example, from time point t1 to time point t2 ) to excite the
如圖6所示,在一實施例中,省略週期Tx起始於驅動訊號SH轉為不導通的不導通時點(例如時點t4),且當省略週期Tx終止時(例如時點t6),驅動訊號SL轉為導通。在一實施例中,當輸出功率因省電而降低時,省略週期Tx將對應增加(即切換頻率減少)。 As shown in FIG. 6 , in one embodiment, the omitting period Tx starts from the non-conducting time point when the driving signal SH turns non-conductive (for example, time point t4), and when the omitting period Tx ends (for example, time point t6), the driving signal SH SL turns conductive. In one embodiment, when the output power is reduced due to power saving, the omission period Tx will be correspondingly increased (ie, the switching frequency is reduced).
請繼續參閱圖6,相較於無省略週期之時段,例如時點t1至時點t3,驅動訊號SL於省略週期中(例如Tx)不導通而無諧振脈波,舉例而言,在先前技術中,驅動訊號SL於時點t4至時點t5所存在的一個脈波,即驅動訊號SL之諧振脈波,在本實施例中已被省略,如圖6所示,因此,於省略週期中(時點t4至時點t6),並無負循環電流產生。先前技術中,切換節點電壓VHB產生的電壓突波VPK以及輔助訊號VAUX產生的電壓降VDP,在本實施例中亦已被避免。在一實施例中,如圖6所示,驅動訊號SH於省略週期中(例如Tx)亦為不導通狀態。 Please continue to refer to Figure 6. Compared with the period without omitted periods, such as time point t1 to time point t3, the driving signal SL is not conductive and has no resonant pulse in the omitted period (such as Tx). For example, in the prior art, A pulse wave of the driving signal SL from time point t4 to time point t5, that is, the resonance pulse wave of the driving signal SL, has been omitted in this embodiment, as shown in Figure 6. Therefore, in the omitted period (time point t4 to time point t5), At time t6), no negative circulating current is generated. In the prior art, the voltage surge VPK generated by the switching node voltage VHB and the voltage drop VDP generated by the auxiliary signal VAUX have also been avoided in this embodiment. In one embodiment, as shown in FIG. 6 , the driving signal SH is also in a non-conducting state during the omitted period (eg, Tx).
在一實施例中,當驅動訊號SH關斷後,於省略週期的部分時間中(例如於時點t4至時點t5之間的一部份時間),變壓器10的去磁電流的一部分流經第二電晶體40的本體二極體45。換言之,在一實施例中,驅動訊號SL中並無雙脈波(double pulses)。在一實施例中,驅動訊號SH中亦無雙脈波。就一觀點而言,於驅動訊號SH的單一脈波之後,接著產生驅動訊號SL的單一脈波,於驅動訊號SL的單一脈波之後,接著產生驅動訊號SH的單一脈波,即便諧振半橋返馳式轉換器操作於具有省略週期的狀態亦同。就另一觀點而言,於驅動訊號SH的兩個連續脈波之間,驅動訊號SL包括最多一個脈波,於驅動訊號SL的兩個連續脈波之間,驅動訊號SH包括最多一個脈波。
In one embodiment, after the driving signal SH is turned off, part of the demagnetization current of the
在一實施例中,於輸出功率低於預設閾值時,產生省略週期Tx。在一實施例中,省略週期Tx隨著輸出功率的降低而對應增加。在一實施例中,即使在驅動訊號SL無法達成第一電晶體30的零電壓切換的情況下,第二驅動訊號於第一驅動訊號的兩個連續脈波之間不包括第二個脈波,因而不以第二個脈波達成第一電晶體30的零電壓切換。
In one embodiment, when the output power is lower than the preset threshold, the omitted period Tx is generated. In one embodiment, the omission period Tx increases correspondingly as the output power decreases. In one embodiment, even when the driving signal SL cannot achieve zero-voltage switching of the
請繼續參閱圖6,在一實施例中,驅動訊號SL之零電壓切換脈波(例如PZV)於省略週期經過後導通第二電晶體40,以達成零電壓切換週期(例如時點t6至時點t7)。
Please continue to refer to FIG. 6 . In one embodiment, the zero-voltage switching pulse wave (for example, PZV) of the driving signal SL turns on the
如圖6所示,在一實施例中,於省略週期後的零電壓切換脈波PZV之後,接著產生至少一個切換週期(例如時點t7至時點t9)。 As shown in FIG. 6 , in one embodiment, after the zero-voltage switching pulse wave PZV after the omitted period, at least one switching period (for example, time point t7 to time point t9 ) is generated.
請繼續參閱圖6,在一實施例中,諧振週期可包括延續零電壓切換期間(例如時點t3’至時點t3),延續零電壓切換期間用以達成第一電晶體30的零電壓切換。換言之,本實施例中,諧振脈波的第一部分(例如時點t2至時點t3’)用以達成變壓器10與諧振電容20之諧振,而諧振脈波的第二部分(例如時點t3’至時點t3)用以產生循環電流以達成第一電晶體30的零電壓切換。
Please continue to refer to FIG. 6 . In one embodiment, the resonance period may include a continuous zero-voltage switching period (for example, from time point t3′ to time point t3 ). The continuous zero-voltage switching period is used to achieve zero-voltage switching of the
圖7顯示本發明之諧振半橋返馳式轉換器中一次側控制器之一實施例方塊圖。在一實施例中,一次側控制器200包括計時器25以及控制元件240。在一實施例中,控制元件240用以根據輸入電壓VIN(經由輔助訊號VAUX)與回授訊號VFB而產生驅動訊號SH與驅動訊號SL,計時器25用以產生前述省略週期Tx。
FIG. 7 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the
如圖7所示,在一實施例中,計時器25根據相關於輸出功率之資訊,判斷輸出功率是否低於預設閾值,當輸出功率被判斷為低於預設閾值時,計時器25開始計算省略週期Tx,並控制控制元件240於省略週期Tx中省略驅動訊號SH與驅動訊號SL之脈波。
As shown in FIG. 7 , in one embodiment, the timer 25 determines whether the output power is lower than a preset threshold based on information related to the output power. When the output power is determined to be lower than the preset threshold, the timer 25 starts The omission period Tx is calculated, and the
請再次參閱圖4,當諧振半橋返馳式轉換器處於中負載及輕負載的狀態時,時點t4至時點t5之諧振週期較短,無法產生足夠的負電流(能量)以達成零電壓切換,因此,負電流的主要部分係來自時點t5至時點t6所產生之電流。 Please refer to Figure 4 again. When the resonant half-bridge flyback converter is in a medium load or light load state, the resonance period from time point t4 to time point t5 is short and cannot generate enough negative current (energy) to achieve zero-voltage switching. , therefore, the main part of the negative current is the current generated from time point t5 to time point t6.
然而,較高的負電流將導致較高的功率損耗,為了將達成零電壓切換的負電流控制在適當位準,去磁時段的控制必須準確,因此需產生去磁訊號Sdmg對應於變壓器10的去磁時段TDS。
However, a higher negative current will lead to a higher power loss. In order to control the negative current to achieve zero-voltage switching at an appropriate level, the demagnetization period must be accurately controlled. Therefore, a demagnetization signal Sdmg corresponding to the
圖8顯示本發明之諧振半橋返馳式轉換器中一次側控制器之一實施例方塊圖。在一實施例中,一次側控制器208包括去磁仿擬器250以及控制元件248。在一實施例中,控制元件248用以根據輸入電壓VIN(經由輔助訊號VAUX)與回授訊號VFB而產生驅動訊號SH與驅動訊號SL,去磁仿擬器250用以根據去磁相關訊號而產生去磁訊號Sdmg,以仿擬去磁時段TDS,其中去磁相關訊號例如變壓器10的反射電壓(經由輔助訊號VAUX)。
FIG. 8 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the
請同時參閱圖9,圖9顯示本發明之去磁仿擬器產生去磁訊號之操作波形圖。 Please also refer to FIG. 9 , which shows an operation waveform diagram of the degaussing simulator of the present invention generating a degaussing signal.
於切換週期中,諧振半橋返馳式轉換器週期性地操作於非不連續導通模式(例如時點ta至時點tc’),驅動訊號SH首先導通第一電晶體30,以激磁變壓器10進而產生一次側開關電流IP(例如時點ta’至時點tb),於第一電晶體30關斷後,驅動訊號SL用以於諧振週期中(時點tb至時點tc)導通(例如時點tb至時點tc’)第二電晶體40,並用以產生循環電流(例如時點tc至時點tc’)以達成第一電晶體30的零電壓切換。於非不連續導通模式的切換週期中,驅動訊號SL的導通期間TSL(例如時點tb至時點tc’)由去磁訊號Sdmg的脈寬(例如TDSX’)決定,其中去磁訊號Sdmg係由去磁仿擬器250根據先前強制插入的不連續導通模式中的校正而產生。在一實施例中,去磁訊號Sdmg的導通期間TDSX’於先前主動強制之不連續導通模式期間中被校正,並用以使得控制元件248控制第二電晶體40的最小導通時間,藉此於第一電晶體30關斷後的非不連續導通模式期間,去磁變壓器10。在一實施例中,如圖9所示,驅動訊號SL的導通期間TSL(例如時點tb至時點tc’)可為去磁訊號Sdmg的導
通期間TDSX’加上一延遲時間(例如時點tc至時點tc’),以於去磁時段後,在一次側開關電流IP上建立負循環電流,以達成第一電晶體30的零電壓切換。
During the switching cycle, the resonant half-bridge flyback converter periodically operates in the non-discontinuous conduction mode (for example, from time point ta to time point tc'), and the driving signal SH first turns on the
需注意的是,非不連續導通模式係指不是不連續導通模式的操作模式,例如:連續導通模式(continuous conduction mode,CCM),或準諧振模式(quasi-resonant mode,QRM)之操作,準諧振模式又稱為邊界導通模式(boundary conduction mode,BCM)。 It should be noted that non-discontinuous conduction mode refers to an operation mode that is not a discontinuous conduction mode, such as continuous conduction mode (CCM) or quasi-resonant mode (QRM) operation. The resonant mode is also called the boundary conduction mode (BCM).
在一實施例中,當一次側開關電流IP已有預設數量(例如一正整數NC)之切換週期(例如時點ta至時點t1)係操作於非不連續導通模式(例如準諧振模式)時,至少一個切換週期被主動強制操作於不連續導通模式(例如時點t1至時點t3)。因此,去磁仿擬器250用以於強制插入的不連續導通模式中,根據變壓器10的去磁時段TDS而校正去磁訊號Sdmg的導通期間TDSX。
In one embodiment, when the primary side switch current IP has a preset number (for example, a positive integer NC) of switching periods (for example, time point ta to time point t1), the operation is in a non-discontinuous conduction mode (for example, quasi-resonant mode). , at least one switching cycle is actively forced to operate in the discontinuous conduction mode (for example, from time point t1 to time point t3). Therefore, the
如圖9所示,於強制插入的不連續導通模式中,變壓器10的去磁時段TDS從輔助訊號VAUX之上升緣(rising edge)開始,並於輔助訊號VAUX(例如時點t2至時點t3)之下降緣(falling edge,即膝點kn)結束。具體而言,本實施例中,可藉由感測輔助訊號VAUX而偵測反射電壓,輔助訊號VAUX來自第一電晶體30的關斷期間中,變壓器10的輔助繞組NA。反射電壓出現之時間長度,即輔助訊號VAUX自上升緣至膝點kn的脈寬,相關於變壓器10的去磁時段TDS。
As shown in FIG. 9 , in the forced insertion discontinuous conduction mode, the degaussing period TDS of the
在一實施例中,一次側控制器208更包括週期計數器260,週期計數器260用以根據一次側開關電流IP而計算切換週期操作於非不連續導通模式的數量,且當一次側開關電流IP被判斷為已有預設數量之切換週期非操作於不連續導通模式時,週期計數器260用以控制控制元件248主動強制操作於不連續導通模式。在一實施例中,週期計數器260可經由電流感測訊號VCS而感測一次側開關電流IP,藉此判斷操作於非不連續導通模式。
In one embodiment, the
在一實施例中,如圖9所示,於強制不連續導通模式切換週期中,驅動訊號SL持續控制第二電晶體40為不導通,使得半橋電路不僅操作於不連續導通模式,亦操作於非同步切換模式,其中於強制不連續導通模式切換週期中,變壓器10的去磁電流(例如時點t2至時點t2’之IP)的一部分流經第二電晶體40的本體二極體45。
In one embodiment, as shown in FIG. 9 , during the forced discontinuous conduction mode switching period, the driving signal SL continuously controls the
請繼續參閱圖9,在不連續導通模式DCM之後(例如時點t4至時點t5),驅動訊號SL的第一脈波導通第二電晶體40,以自諧振電容20至變壓器10激磁變壓器10,進而產生負循環電流(時點t4至時點t5之IP)以達成第一電晶體30的零電壓切換。
Please continue to refer to FIG. 9. After the discontinuous conduction mode DCM (for example, from time point t4 to time point t5), the first pulse wave of the driving signal SL conducts the
圖10顯示本發明產生去磁訊號Sdmg之去磁仿擬器的一具體實施例示意圖。在一實施例中,去磁仿擬器250包括計時產生器205、比較器280以及邏輯電路285。
FIG. 10 shows a schematic diagram of a specific embodiment of a demagnetization simulator for generating a demagnetization signal Sdmg according to the present invention. In one embodiment, the
在一實施例中,計時產生器205包括積分器,積分器由開關231及電容230組成,開關231由取樣訊號SMP所控制,取樣訊號SMP相關於驅動訊號SH以對電流感測訊號VCS取樣。放電電流ID相關於n*VO,用以將電容230的跨壓VC放電。跨壓VC藉由比較器280而與參考電壓Vref進行比較。邏輯電路285根據比較器輸出CPO與相關於驅動訊號SH的取樣訊號SMP而產生去磁訊號Sdmg。在一實施例中,參考電壓Vref為0伏特,當一次側開關電流IP為0時,電流感測電壓VCS為0。
In one embodiment, the
在一實施例中,去磁訊號Sdmg的時間長度相關於變壓器10的輸入電壓之電壓位準(Vinx),亦即如圖3所示,一次側繞組NP與諧振電容20之耦接節點NNP上的電壓,去磁訊號Sdmg的時間長度也相關於變壓器10的輸出電壓之電壓位準(例如n*VO)及變壓器10於第一電晶體30導通時的激磁
時段(TW)。需注意的是,變壓器10的輸入電壓之電壓位準Vinx等於輸入電壓VIN減去諧振電容20的跨壓Vcr。
In one embodiment, the time length of the demagnetization signal Sdmg is related to the voltage level (Vinx) of the input voltage of the
根據變壓器10被去磁的磁通量等於變壓器10被激磁的磁通量,可列出以下式1:Vinx*TW=n*VO*TDS (式1)
According to the fact that the magnetic flux demagnetized by the
其中TW為在變壓器10的激磁時段中,變壓器10的輸入電壓之電壓位準Vinx之出現時間;n*VO為在變壓器10的去磁時段TDS中,變壓器10的電壓。n為一次側繞組NP及二次側繞組NS之匝數比,VO為二次側繞組NS之電壓(即輸出電壓)。
TW is the occurrence time of the voltage level Vinx of the input voltage of the
在變壓器10被激磁後,電流感測訊號VCS之位準VCSp相關於一次側開關電流IP於激磁過程結束之峰值,且於圖3所示之電阻60上產生,其可以下列式2表示:VCSp=(Vinx/L)*TW*Rs (式2)
After the
其中L為變壓器10之一次側繞組NP之電感,Rs為電阻60之電阻值,VCSp為變壓器10於激磁過程結束之電壓位準。
Wherein, L is the inductance of the primary winding NP of the
設ID=n*VO/Rt,其中Rt為電阻55之電阻值。
Assume ID=n*VO/Rt, where Rt is the resistance value of
去磁訊號Sdmg之脈寬TDSX可被表示為:TDSX=(C*VCSp)/ID,其中C為電容230之電容值。
The pulse width TDSX of the demagnetization signal Sdmg can be expressed as: TDSX=(C*VCSp)/ID, where C is the capacitance value of the
TDSX=(Rt*C*VCSp)/(n*VO) TDSX=(Rt*C*VCSp)/(n*VO)
TDSX=(Rt*C/(n*VO))*(Rs/L)*Vinx*TW TDSX=(Rt*C/(n*VO))*(Rs/L)*Vinx*TW
設Rt=L/(Rs*C) (式3) Let Rt=L/(Rs*C) (Formula 3)
TDSX=(Vinx*TW)/(n*VO) (式4) TDSX=(Vinx*TW)/(n*VO) (Formula 4)
當式3之條件滿足時,式4所示之去磁訊號Sdmg之導通期間TDSX等於變壓器10之去磁時段TDS。
When the condition of
請繼續參閱圖10,開關231導通以對電流感測訊號VCS取樣至電容230,且於開關231關斷時(即激磁結束時),電流感測訊號VCS之位準VCSp被保持在電容230,開關231由取樣訊號SMP控制。當開關231關斷時,去磁訊號Sdmg被致能(例如藉由邏輯電路285),換言之,當去磁訊號Sdmg開始致能時,電容230之跨壓VC為電流感測訊號VCS的峰值。在開關231關斷之後,放電電流ID開始將電容230放電,當電容230經由放電電流ID(ID=n*VO/Rt)完全放電完成時(VC=0V),去磁訊號Sdmg禁能。圖10及圖3所示之電阻55用以設定去磁訊號Sdmg的預設脈寬。
Please continue to refer to Figure 10. The
在一實施例中,於強制插入的不連續導通模式切換週期中,去磁訊號Sdmg的脈寬TDSX可藉由去磁仿擬器250而與輔助訊號VAUX的脈寬所示意的去磁時段TDS做比較,因此去磁訊號Sdmg的脈寬TDSX可被校正而用於接下來的非不連續導通模式切換週期。在一實施例中,去磁仿擬器250更用以根據不連續導通模式中所偵測到的去磁時段TDS而調整電阻255之電阻值,以校正去磁訊號Sdmg的脈波期間TDSX。
In one embodiment, in the discontinuous conduction mode switching period of forced insertion, the pulse width TDSX of the degaussing signal Sdmg can be compared with the degaussing period TDS represented by the pulse width of the auxiliary signal VAUX by the
在其他實施例中,除了調整電阻255之電阻值外,去磁仿擬器250亦可藉由以下方式校正去磁訊號Sdmg的脈波期間TDSX:調整電壓閾值Vth以決定去磁訊號Sdmg之結束,或調整電容230的電容值,或調整例如圖10中電晶體271與電晶體272所組成的電流鏡之比值。
In other embodiments, in addition to adjusting the resistance value of the
圖11顯示本發明之諧振半橋返馳式轉換器之一較佳實施例示意圖。諧振半橋返馳式轉換器900相似於圖3之諧振半橋返馳式轉換器300。在本實施例中,諧振半橋返馳式轉換器900包括第一電晶體M1、第二電晶體M2及第三電晶體M3,第一電晶體M1、第二電晶體M2及第三電晶體M3用以構成半橋電路。就一觀點而言,第一電晶體M1與第三電晶體M3配
置為諧振半橋返馳式轉換器900之下橋電晶體,且第二電晶體M2配置為諧振半橋返馳式轉換器900之上橋電晶體。
FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-
根據回授訊號VFB及輸入電壓VIN,一次側控制器201用以產生第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3耦接以經由半橋電路而切換變壓器10,藉此於變壓器10之二次側產生輸出電壓VO。第二驅動訊號S2驅動第二電晶體M2以激磁變壓器10,第三驅動訊號S3於變壓器10之去磁與諧振時段中導通第三電晶體M3,第三驅動訊號S3也用於導通第三電晶體M3以產生流經變壓器10的循環電流,並於重負載狀態中達成第二電晶體M2的零電壓切換。換言之,第二電晶體M2為諧振半橋返馳式轉換器900之一次側上橋開關且可對應於圖3之第一電晶體30,第三電晶體M3為諧振半橋返馳式轉換器900之一次側下橋開關且可對應於圖3之第二電晶體40。就一觀點而言,第一電晶體M1用以並聯於第三電晶體M3且作為輔助一次側下橋開關,具有獨立的控制訊號S1。
According to the feedback signal VFB and the input voltage VIN, the
在一實施例中,在輕負載狀態且操作於不連續導通模式時,藉由導通第二電晶體M2而激磁變壓器10之後,第三電晶體M3於變壓器10之去磁與諧振時段中被控制為導通。於去磁之後,當第三電晶體M3持續關斷,第一驅動訊號S1用以導通第一電晶體M1,以產生流經變壓器10的循環電流而達成第二電晶體M2的零電壓切換時,。因此,第三電晶體M3在不連續導通模式之一個切換週期中可避免切換兩次。
In one embodiment, after the
由於第一電晶體M1只用以產生循環電流以達成零電壓切換,在一實施例中,第一電晶體M1之實際尺寸(例如長寬比)可配置為遠小於第三電晶體M3之實際尺寸。因此,第一電晶體M1的驅動能力及寄生電容(例 如閘極電容)低於第三電晶體M3的寄生電容,第一電晶體M1的切換損耗也因此低於第三電晶體M3的切換損耗。 Since the first transistor M1 is only used to generate circulating current to achieve zero voltage switching, in one embodiment, the actual size (such as aspect ratio) of the first transistor M1 can be configured to be much smaller than the actual size of the third transistor M3 size. Therefore, the driving capability of the first transistor M1 and the parasitic capacitance (eg For example, the gate capacitance) is lower than the parasitic capacitance of the third transistor M3, so the switching loss of the first transistor M1 is also lower than the switching loss of the third transistor M3.
舉例而言,電晶體的閘極切換損耗Pg可被表示為:Pg=0.5*Ciss*Vg*Vg*Freq For example, the gate switching loss Pg of the transistor can be expressed as: Pg=0.5*Ciss*Vg*Vg*Freq
其中Ciss為電晶體之輸入電容,Vg為閘極驅動訊號之電壓位準,Freq為閘極驅動訊號之切換頻率。 Where Ciss is the input capacitance of the transistor, Vg is the voltage level of the gate drive signal, and Freq is the switching frequency of the gate drive signal.
如上述開關功率損耗方程式,實際尺寸較小的第一電晶體M1用以專用於不連續導通模式中達成第二電晶體M2的零電壓切換,因此第一電晶體M1的閘極切換損耗低於實際尺寸較大的第三電晶體M3。 As shown in the above switching power loss equation, the first transistor M1 with a smaller actual size is used exclusively to achieve zero-voltage switching of the second transistor M2 in the discontinuous conduction mode. Therefore, the gate switching loss of the first transistor M1 is lower than The third transistor M3 is actually larger in size.
此外,在一實施例中,第一驅動訊號S1的電壓位準(即Vg)之振幅低於第三驅動訊號S3的電壓位準之振幅,因此更可降低第一電晶體M1之切換損耗,且在一實施例中,第一電晶體M1之閘極最大額定值(例如閘源極電壓)也可低於第三電晶體M3之閘極最大額定值。 In addition, in one embodiment, the amplitude of the voltage level (ie, Vg) of the first driving signal S1 is lower than the amplitude of the voltage level of the third driving signal S3, so the switching loss of the first transistor M1 can be further reduced. And in one embodiment, the gate maximum rating (eg gate-source voltage) of the first transistor M1 may also be lower than the gate maximum rating of the third transistor M3.
電阻60藉由偵測變壓器10的一次側開關電流IP而產生電流感測訊號VCS,一次側控制器201用以根據輸入電壓VIN而產生第一驅動訊號S1,並根據輸入電壓VIN及/或輸出電壓VO而產生第三驅動訊號S3。一次側控制器201更用以根據回授訊號VFB而產生第二驅動訊號S2。
The
圖12顯示本發明之一次側控制器201操作於不連續導通模式之一較佳實施例操作波形圖。於不連續導通模式之操作中,一次側控制器201操作於第一切換週期Tcyc1並控制第一驅動訊號S1於第一時段TA中導通第一電晶體M1,藉此產生循環電流以達成第二電晶體M2導通時的零電壓切換。經過第一時段TA後,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3用以於第一不導通時段Td1(即空滯時段)中,關斷第一電晶體M1、第二電晶體M2及第三電晶體M3。在一實施例中,第一不導通時段Td1相關於用
以達成第二電晶體M2之零電壓切換的準諧振時段。經過第一不導通時段Td1後,第二驅動訊號S2於第二時段TB中,導通第二電晶體M2,第二電晶體M2之導通用以激磁變壓器10。經過第二時段TB後,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3用以於(即空滯時段)中,關斷第一電晶體M1、第二電晶體M2及第三電晶體M3。在一實施例中,第二不導通時段Td2相關於用以達成第三電晶體M3之零電壓切換的另一準諧振時段。經過第二不導通時段Td2後,第三驅動訊號S3於第三時段TC中,導通第三電晶體M3,第三電晶體M3於變壓器10之去磁時段中導通。經過第三時段TC後,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3用以於第三不導通時段TZ中,關斷第一電晶體M1、第二電晶體M2及第三電晶體M3,其中激磁電流IM於第三不導通時段TZ中(即不連續導通模式)維持在零。經過第三不導通時段TZ後,開始另一切換週期Tcyc2。
FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-
圖13顯示本發明一次側控制器之一較佳實施例方塊圖。在一實施例中,一次側控制器213包括計時器22及控制元件243。控制元件243用以根據輸入電壓VIN(經由VAUX)及回授訊號VFB而產生第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3。
Figure 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention. In one embodiment, the
計時器22用以計時而產生第三不導通時段TZ,第三不導通時段TZ起始於第三驅動訊號S3脈波結束時(例如下降緣)。在一實施例中,當諧振半橋返馳式轉換器的輸出功率減少時,第三不導通時段TZ對應增加,因此,諧振半橋返馳式轉換器的切換頻率亦能因諧振半橋返馳式轉換器的輸出功率減少而對應減少,藉此改善輕負載操作狀態中的效能。
The
圖3顯示本發明之諧振半橋返馳式轉換器之一實施例示意圖。諧振半橋返馳式轉換器300包含:第一電晶體30及第二電晶體40,用以
構成半橋電路。變壓器10及諧振電容20彼此串聯並耦接於半橋電路的切換節點LX,變壓器10包括一次側繞組NP、二次側繞組NS以及輔助繞組NA,其中一次側繞組NP及二次側繞組NS具有匝數比n,二次側繞組NS及輔助繞組NA具有匝數比m。一次側控制器200產生驅動訊號SH及驅動訊號SL,驅動訊號SH及驅動訊號SL經由半橋電路切換變壓器10,以於變壓器10的二次側產生輸出電壓VO。驅動訊號SH驅動第一電晶體30,以激磁變壓器10。驅動訊號SL於變壓器10的去磁與諧振時段中導通第二電晶體40,驅動訊號SL亦用於導通第二電晶體40以產生流經變壓器10的循環電流,以達成第一電晶體30的零電壓切換。電阻60藉由偵測變壓器10的一次側開關電流IP而產生電流感測訊號VCS。
FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-
驅動訊號SH及驅動訊號SL根據回授訊號VFB而產生,其中回授訊號VFB根據諧振半橋返馳式轉換器300的輸出功率而產生。二次側控制器100耦接於輸出電壓VO以產生回授訊號VFB,回授訊號VFB經由光耦合器90耦接於一次側控制器200。二次側控制器100亦用以產生驅動訊號SG,以於變壓器10的去磁時段TDS中驅動二次側同步整流器70。輔助繞組NA於變壓器10切換時產生輔助繞組訊號VNA,電阻51、電阻52用以將輔助繞組訊號VNA衰減以產生輔助訊號VAUX,輔助訊號VAUX耦接於一次側控制器200。在一實施例中,電阻55耦接於一次側控制器200,藉由電阻55以設定參數而產生去磁訊號Sdmg。
The driving signal SH and the driving signal SL are generated according to the feedback signal VFB, wherein the feedback signal VFB is generated according to the output power of the resonant half-
圖4顯示對應於圖3之實施例的操作波形圖。當驅動訊號SH導通時,變壓器10被激磁並產生激磁電流IM,當驅動訊號SH不導通時,變壓器10被去磁。於去磁時段TDS中,變壓器10產生二次側開關電流IS,驅動訊號SL相關於變壓器10的去磁時段TDS。在一實施例中,驅動訊號SL之導通期間TSL(亦即脈寬)等於或長於變壓器10的去磁時段TDS,藉此避免變壓器
10操作於連續導通模式(continuous conduction mode,CCM)。於變壓器10的去磁時段TDS中,諧振電容20上產生反射電壓VX,其中反射電壓VX與輸出電壓VO之關係為:VX=n*VO。
FIG. 4 shows an operating waveform diagram corresponding to the embodiment of FIG. 3 . When the driving signal SH is turned on, the
當驅動訊號SH不導通時,驅動訊號SL可被導通,而當驅動訊號SL不導通時,驅動訊號SH可被導通。驅動訊號SH與驅動訊號SL之間(即驅動訊號SH與驅動訊號SL皆不導通時)可包括空滯時間(例如時段TRH、時段TRL)。 When the driving signal SH is not conductive, the driving signal SL may be turned on, and when the driving signal SL is not conductive, the driving signal SH may be turned on. The period between the driving signal SH and the driving signal SL (that is, when neither the driving signal SH nor the driving signal SL is conductive) may include a dead time (such as a period TRH, a period TRL).
圖4之不同時段中的操作細節詳見下列說明。 Details of the operations in different time periods in Figure 4 are detailed in the following description.
時點t1至時點t2之時段為激磁變壓器週期,本時段中第一電晶體30導通且第二電晶體40關斷,流經變壓器10中的一次側開關電流IP增加且諧振電容20之電壓亦增加,此時變壓器10被激磁而諧振電容20進行充電,二次側同步整流器70關斷且其本體二極體75具有逆向偏壓,因此,此時並無能量被轉換至二次側。
The period from time point t1 to time point t2 is the excitation transformer period. During this period, the
時點t2至時點t3之時段為第一循環電流週期,本時段中第一電晶體30與第二電晶體40均關斷,變壓器10的循環電流強制半橋電路的切換節點電壓VHB下降,直到第二電晶體40的本體二極體45導通為止。時點t2至時點t3之時段相關於準諧振時段(quasi-resonant period),以達成第二電晶體40的零電壓切換,此時變壓器10的一次側電壓與諧振電容20於時點t3之電壓相同。
The period from time point t2 to time point t3 is the first circulating current period. During this period, the
時點t3至時點t4之時段為諧振週期(正電流),本時段中,在零電壓切換的狀態下,第一電晶體30關斷且第二電晶體40導通,此時輸出電壓VO等於諧振電容20的跨壓Vcr除以匝數比n,電流開始流經二次側同步整流器70,儲存於變壓器10的能量被轉換至輸出端而產生輸出電壓VO。由於變壓器10的漏電感Lr與諧振電容20(Cr)形成電感電容槽(LC tank),因此二次側
電流於諧振頻率Lr及Cr所決定的時段中為正弦波的形式。變壓器10的一次側電流為激磁電流IM與二次側開關電流IS之和。流經諧振槽(Lr,Cr)的電流仍為正電流,其主要由變壓器10的激磁電感驅動,並且流經諧振電容20。
The period from time point t3 to time point t4 is the resonance period (positive current). During this period, in the zero-voltage switching state, the
時點t4至時點t5之時段為諧振週期(負電流),本時段中第一電晶體30繼續關斷且第二電晶體40繼續導通,能量持續轉換至二次側,但諧振槽電流被諧振電容20的電壓反向驅動,諧振電容20的能量不僅被轉換至二次側,更於第二電晶體40持續導通(例如時點t4至時點t5)時,用以將變壓器10的激磁電流位準拉至負值。
The period from time point t4 to time point t5 is the resonance period (negative current). During this period, the
時點t5至時點t6之時段為反向激磁變壓器週期(負電流),本時段自變壓器10的去磁時段TDS結束時至第二電晶體40關斷時,諧振電容20反向激磁變壓器10,並產生負電流。
The period from time point t5 to time point t6 is the reverse excitation transformer period (negative current). In this period from the end of the demagnetization period TDS of the
時點t6至時點t7之時段為第二循環電流週期,本時段中第一電晶體30與第二電晶體40均關斷,變壓器10的負電流於時點t5至時點t6被感應而產生,以強制半橋電路中切換節點LX上的切換節點電壓VHB增加,直到其導通第一電晶體30的本體二極體35為止。
The period from time point t6 to time point t7 is the second circulating current period. During this period, the
時點t7之後,開始另一個與時點t1至時點t2之時段相似的週期,第一電晶體30在零電壓切換狀態下導通且第二電晶體40關斷,若變壓器諧振槽中的循環電流仍為負電流,則諧振槽中多餘的能量將被送回輸入端(供應輸入電壓VIN的節點)。
After time point t7, another period similar to the period from time point t1 to time point t2 begins. The
在輕負載的狀態下,當輸出功率降低時,驅動訊號SH與驅動訊號SL的脈寬將對應減少,故驅動訊號SH與驅動訊號SL的切換頻率於輕負載狀態下增加,由於鐵芯損失(core loss)、開關損耗(switching loss)等功率損耗增加,因此導致功率轉換器的功率轉換效率變差。 In the light load state, when the output power decreases, the pulse widths of the drive signal SH and the drive signal SL will decrease accordingly. Therefore, the switching frequency of the drive signal SH and the drive signal SL increases in the light load state. Due to the core loss ( Power losses such as core loss and switching loss increase, thus causing the power conversion efficiency of the power converter to deteriorate.
圖5顯示降低驅動訊號SH與驅動訊號SL的切換頻率之操作波形圖。一種改善功率效率的方式是,藉由延長驅動訊號SL關斷(例如時點t3)至驅動訊號SH導通(例如時點t5)之間的時間,可降低切換頻率,然而,驅動訊號SL的關斷將產生循環電流,進而導致切換節點電壓VHB的電壓突波VPK以及輔助訊號VAUX的電壓降VDP,電壓突波VPK與電壓降VDP將造成功率損耗與雜訊。 FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL. One way to improve power efficiency is to reduce the switching frequency by extending the time between the turning off of the driving signal SL (for example, time point t3) and the turning on of the driving signal SH (for example, time point t5). However, the turning off of the driving signal SL will A circulating current is generated, which in turn causes a voltage surge VPK of the switching node voltage VHB and a voltage drop VDP of the auxiliary signal VAUX. The voltage surge VPK and voltage drop VDP will cause power loss and noise.
需注意的是,前述驅動訊號SH與驅動訊號SL的導通或關斷皆各自對應於第一電晶體30與第二電晶體40的導通或關斷。
It should be noted that the aforementioned turning on or off of the driving signal SH and the driving signal SL respectively corresponds to the turning on or off of the
圖6顯示本發明之具有省略週期的諧振半橋返馳式轉換器的一實施例之操作波形圖。 FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.
請參閱圖6,在一實施例中,驅動訊號SH於激磁變壓器10的激磁週期中(例如時點t1至時點t2)導通,以激磁變壓器10。驅動訊號SH關斷後,驅動訊號SL於諧振週期中(例如時點t2至時點t3)導通,且具有諧振脈波(例如時點t2至時點t3),一個激磁週期與一個諧振週期形成一個切換週期(例如時點t1至時點t3)。
Referring to FIG. 6 , in one embodiment, the driving signal SH is turned on during the excitation period of the excitation transformer 10 (for example, from time point t1 to time point t2 ) to excite the
如圖6所示,在一實施例中,省略週期Tx起始於驅動訊號SH轉為不導通的不導通時點(例如時點t4),且當省略週期Tx終止時(例如時點t6),驅動訊號SL轉為導通。在一實施例中,當輸出功率因省電而降低時,省略週期Tx將對應增加(即切換頻率減少)。 As shown in FIG. 6 , in one embodiment, the omitting period Tx starts from the non-conducting time point when the driving signal SH turns non-conductive (for example, time point t4), and when the omitting period Tx ends (for example, time point t6), the driving signal SH SL turns conductive. In one embodiment, when the output power is reduced due to power saving, the omission period Tx will be correspondingly increased (ie, the switching frequency is reduced).
請繼續參閱圖6,相較於無省略週期之時段,例如時點t1至時點t3,驅動訊號SL於省略週期中(例如Tx)不導通而無諧振脈波,舉例而言,在先前技術中,驅動訊號SL於時點t4至時點t5所存在的一個脈波,即驅動訊號SL之諧振脈波,在本實施例中已被省略,如圖6所示,因此,於省略週期中(時點t4至時點t6),並無負循環電流產生。先前技術中,切換節點電壓VHB 產生的電壓突波VPK以及輔助訊號VAUX產生的電壓降VDP,在本實施例中亦已被避免。在一實施例中,如圖6所示,驅動訊號SH於省略週期中(例如Tx)亦為不導通狀態。 Please continue to refer to Figure 6. Compared with the period without omitted periods, such as time point t1 to time point t3, the driving signal SL is not conductive and has no resonant pulse in the omitted period (such as Tx). For example, in the prior art, A pulse wave of the driving signal SL from time point t4 to time point t5, that is, the resonance pulse wave of the driving signal SL, has been omitted in this embodiment, as shown in Figure 6. Therefore, in the omitted period (time point t4 to time point t5), At time t6), no negative circulating current is generated. In the prior art, the switching node voltage VHB The voltage surge VPK generated and the voltage drop VDP generated by the auxiliary signal VAUX have also been avoided in this embodiment. In one embodiment, as shown in FIG. 6 , the driving signal SH is also in a non-conducting state during the omitted period (eg, Tx).
在一實施例中,當驅動訊號SH關斷後,於省略週期的部分時間中(例如於時點t4至時點t5之間的一部份時間),變壓器10的去磁電流的一部分流經第二電晶體40的本體二極體45。換言之,在一實施例中,驅動訊號SL中並無雙脈波(double pulses)。在一實施例中,驅動訊號SH中亦無雙脈波。就一觀點而言,於驅動訊號SH的單一脈波之後,接著產生驅動訊號SL的單一脈波,於驅動訊號SL的單一脈波之後,接著產生驅動訊號SH的單一脈波,即便諧振半橋返馳式轉換器操作於具有省略週期的狀態亦同。就另一觀點而言,於驅動訊號SH的兩個連續脈波之間,驅動訊號SL包括最多一個脈波,於驅動訊號SL的兩個連續脈波之間,驅動訊號SH包括最多一個脈波。
In one embodiment, after the driving signal SH is turned off, part of the demagnetization current of the
在一實施例中,於輸出功率低於預設閾值時,產生省略週期Tx。在一實施例中,省略週期Tx隨著輸出功率的降低而對應增加。在一實施例中,即使在驅動訊號SL無法達成第一電晶體30的零電壓切換的情況下,第二驅動訊號於第一驅動訊號的兩個連續脈波之間不包括第二個脈波,因而不以第二個脈波達成第一電晶體30的零電壓切換。
In one embodiment, when the output power is lower than the preset threshold, the omitted period Tx is generated. In one embodiment, the omission period Tx increases correspondingly as the output power decreases. In one embodiment, even when the driving signal SL cannot achieve zero-voltage switching of the
請繼續參閱圖6,在一實施例中,驅動訊號SL之零電壓切換脈波(例如PZV)於省略週期經過後導通第二電晶體40,以達成零電壓切換週期(例如時點t6至時點t7)。
Please continue to refer to FIG. 6 . In one embodiment, the zero-voltage switching pulse wave (for example, PZV) of the driving signal SL turns on the
如圖6所示,在一實施例中,於省略週期後的零電壓切換脈波PZV之後,接著產生至少一個切換週期(例如時點t7至時點t9)。 As shown in FIG. 6 , in one embodiment, after the zero-voltage switching pulse wave PZV after the omitted period, at least one switching period (for example, time point t7 to time point t9 ) is generated.
請繼續參閱圖6,在一實施例中,諧振週期可包括延續零電壓切換期間(例如時點t3’至時點t3),延續零電壓切換期間用以達成第一電晶
體30的零電壓切換。換言之,本實施例中,諧振脈波的第一部分(例如時點t2至時點t3’)用以達成變壓器10與諧振電容20之諧振,而諧振脈波的第二部分(例如時點t3’至時點t3)用以產生循環電流以達成第一電晶體30的零電壓切換。
Please continue to refer to FIG. 6. In one embodiment, the resonance period may include a continuation of a zero-voltage switching period (for example, from time point t3' to time point t3). The continuation of the zero-voltage switching period is used to achieve the first transistor
Zero voltage switching of
圖7顯示本發明之諧振半橋返馳式轉換器中一次側控制器之一實施例方塊圖。在一實施例中,一次側控制器200包括計時器25以及控制元件240。在一實施例中,控制元件240用以根據輸入電壓VIN(經由輔助訊號VAUX)與回授訊號VFB而產生驅動訊號SH與驅動訊號SL,計時器25用以產生前述省略週期Tx。
FIG. 7 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the
如圖7所示,在一實施例中,計時器25根據相關於輸出功率之資訊,判斷輸出功率是否低於預設閾值,當輸出功率被判斷為低於預設閾值時,計時器25開始計算省略週期Tx,並控制控制元件240於省略週期Tx中省略驅動訊號SH與驅動訊號SL之脈波。
As shown in FIG. 7 , in one embodiment, the timer 25 determines whether the output power is lower than a preset threshold based on information related to the output power. When the output power is determined to be lower than the preset threshold, the timer 25 starts The omission period Tx is calculated, and the
請再次參閱圖4,當諧振半橋返馳式轉換器處於中負載及輕負載的狀態時,時點t4至時點t5之諧振週期較短,無法產生足夠的負電流(能量)以達成零電壓切換,因此,負電流的主要部分係來自時點t5至時點t6所產生之電流。 Please refer to Figure 4 again. When the resonant half-bridge flyback converter is in a medium load or light load state, the resonance period from time point t4 to time point t5 is short and cannot generate enough negative current (energy) to achieve zero-voltage switching. , therefore, the main part of the negative current is the current generated from time point t5 to time point t6.
然而,較高的負電流將導致較高的功率損耗,為了將達成零電壓切換的負電流控制在適當位準,去磁時段的控制必須準確,因此需產生去磁訊號Sdmg對應於變壓器10的去磁時段TDS。
However, a higher negative current will lead to a higher power loss. In order to control the negative current to achieve zero-voltage switching at an appropriate level, the demagnetization period must be accurately controlled. Therefore, a demagnetization signal Sdmg corresponding to the
圖8顯示本發明之諧振半橋返馳式轉換器中一次側控制器之一實施例方塊圖。在一實施例中,一次側控制器208包括去磁仿擬器250以及控制元件248。在一實施例中,控制元件248用以根據輸入電壓VIN(經由輔助訊號VAUX)與回授訊號VFB而產生驅動訊號SH與驅動訊號SL,去磁仿擬
器250用以根據去磁相關訊號而產生去磁訊號Sdmg,以仿擬去磁時段TDS,其中去磁相關訊號例如變壓器10的反射電壓(經由輔助訊號VAUX)。
FIG. 8 shows a block diagram of an embodiment of a primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the
請同時參閱圖9,圖9顯示本發明之去磁仿擬器產生去磁訊號之操作波形圖。 Please also refer to FIG. 9 , which shows an operation waveform diagram of the degaussing simulator of the present invention generating a degaussing signal.
於切換週期中,諧振半橋返馳式轉換器週期性地操作於非不連續導通模式(例如時點ta至時點tc’),驅動訊號SH首先導通第一電晶體30,以激磁變壓器10進而產生一次側開關電流IP(例如時點ta’至時點tb),於第一電晶體30關斷後,驅動訊號SL用以於諧振週期中(時點tb至時點tc)導通(例如時點tb至時點tc’)第二電晶體40,並用以產生循環電流(例如時點tc至時點tc’)以達成第一電晶體30的零電壓切換。於非不連續導通模式的切換週期中,驅動訊號SL的導通期間TSL(例如時點tb至時點tc’)由去磁訊號Sdmg的脈寬(例如TDSX’)決定,其中去磁訊號Sdmg係由去磁仿擬器250根據先前強制插入的不連續導通模式中的校正而產生。在一實施例中,去磁訊號Sdmg的導通期間TDSX’於先前主動強制之不連續導通模式期間中被校正,並用以使得控制元件248控制第二電晶體40的最小導通時間,藉此於第一電晶體30關斷後的非不連續導通模式期間,去磁變壓器10。在一實施例中,如圖9所示,驅動訊號SL的導通期間TSL(例如時點tb至時點tc’)可為去磁訊號Sdmg的導通期間TDSX’加上一延遲時間(例如時點tc至時點tc’),以於去磁時段後,在一次側開關電流IP上建立負循環電流,以達成第一電晶體30的零電壓切換。
During the switching cycle, the resonant half-bridge flyback converter periodically operates in the non-discontinuous conduction mode (for example, from time point ta to time point tc'), and the driving signal SH first turns on the
需注意的是,非不連續導通模式係指不是不連續導通模式的操作模式,例如:連續導通模式(continuous conduction mode,CCM),或準諧振模式(quasi-resonant mode,QRM)之操作,準諧振模式又稱為邊界導通模式(boundary conduction mode,BCM)。 It should be noted that non-discontinuous conduction mode refers to an operation mode that is not a discontinuous conduction mode, such as continuous conduction mode (CCM) or quasi-resonant mode (QRM) operation. The resonant mode is also called the boundary conduction mode (BCM).
在一實施例中,當一次側開關電流IP已有預設數量(例如一正整數NC)之切換週期(例如時點ta至時點t1)係操作於非不連續導通模式(例如準諧振模式)時,至少一個切換週期被主動強制操作於不連續導通模式(例如時點t1至時點t3)。因此,去磁仿擬器250用以於強制插入的不連續導通模式中,根據變壓器10的去磁時段TDS而校正去磁訊號Sdmg的導通期間TDSX。
In one embodiment, when the primary side switch current IP has a preset number (for example, a positive integer NC) of switching periods (for example, time point ta to time point t1), the operation is in a non-discontinuous conduction mode (for example, quasi-resonant mode). , at least one switching cycle is actively forced to operate in the discontinuous conduction mode (for example, from time point t1 to time point t3). Therefore, the
如圖9所示,於強制插入的不連續導通模式中,變壓器10的去磁時段TDS從輔助訊號VAUX之上升緣(rising edge)開始,並於輔助訊號VAUX(例如時點t2至時點t3)之下降緣(falling edge,即膝點kn)結束。具體而言,本實施例中,可藉由感測輔助訊號VAUX而偵測反射電壓,輔助訊號VAUX來自第一電晶體30的關斷期間中,變壓器10的輔助繞組NA。反射電壓出現之時間長度,即輔助訊號VAUX自上升緣至膝點kn的脈寬,相關於變壓器10的去磁時段TDS。
As shown in FIG. 9 , in the forced insertion discontinuous conduction mode, the degaussing period TDS of the
在一實施例中,一次側控制器208更包括週期計數器260,週期計數器260用以根據一次側開關電流IP而計算切換週期操作於非不連續導通模式的數量,且當一次側開關電流IP被判斷為已有預設數量之切換週期非操作於不連續導通模式時,週期計數器260用以控制控制元件248主動強制操作於不連續導通模式。在一實施例中,週期計數器260可經由電流感測訊號VCS而感測一次側開關電流IP,藉此判斷操作於非不連續導通模式。
In one embodiment, the
在一實施例中,如圖9所示,於強制不連續導通模式切換週期中,驅動訊號SL持續控制第二電晶體40為不導通,使得半橋電路不僅操作於不連續導通模式,亦操作於非同步切換模式,其中於強制不連續導通模式切換週期中,變壓器10的去磁電流(例如時點t2至時點t2’之IP)的一部分流經第二電晶體40的本體二極體45。
In one embodiment, as shown in FIG. 9 , during the forced discontinuous conduction mode switching period, the driving signal SL continuously controls the
請繼續參閱圖9,在不連續導通模式DCM之後(例如時點t4至時點t5),驅動訊號SL的第一脈波導通第二電晶體40,以自諧振電容20至變壓器10激磁變壓器10,進而產生負循環電流(時點t4至時點t5之IP)以達成第一電晶體30的零電壓切換。
Please continue to refer to FIG. 9. After the discontinuous conduction mode DCM (for example, from time point t4 to time point t5), the first pulse wave of the driving signal SL conducts the
圖10顯示本發明產生去磁訊號Sdmg之去磁仿擬器的一具體實施例示意圖。在一實施例中,去磁仿擬器250包括計時產生器205、比較器280以及邏輯電路285。
FIG. 10 shows a schematic diagram of a specific embodiment of a demagnetization simulator for generating a demagnetization signal Sdmg according to the present invention. In one embodiment, the
在一實施例中,計時產生器205包括積分器,積分器由開關231及電容230組成,開關231由取樣訊號SMP所控制,取樣訊號SMP相關於驅動訊號SH以對電流感測訊號VCS取樣。放電電流ID相關於n*VO,用以將電容230的跨壓VC放電。跨壓VC藉由比較器280而與參考電壓Vref進行比較。邏輯電路285根據比較器輸出CPO與相關於驅動訊號SH的取樣訊號SMP而產生去磁訊號Sdmg。在一實施例中,參考電壓Vref為0伏特,當一次側開關電流IP為0時,電流感測電壓VCS為0。
In one embodiment, the
在一實施例中,去磁訊號Sdmg的時間長度相關於變壓器10的輸入電壓之電壓位準(Vinx),亦即如圖3所示,一次側繞組NP與諧振電容20之耦接節點NNP上的電壓,去磁訊號Sdmg的時間長度也相關於變壓器10的輸出電壓之電壓位準(例如n*VO)及變壓器10於第一電晶體30導通時的激磁時段(TW)。需注意的是,變壓器10的輸入電壓之電壓位準Vinx等於輸入電壓VIN減去諧振電容20的跨壓Vcr。
In one embodiment, the time length of the demagnetization signal Sdmg is related to the voltage level (Vinx) of the input voltage of the
根據變壓器10被去磁的磁通量等於變壓器10被激磁的磁通量,可列出以下式1:Vinx*TW=n*VO*TDS (式1)
According to the fact that the magnetic flux demagnetized by the
其中TW為在變壓器10的激磁時段中,變壓器10的輸入電壓之電壓位準Vinx之出現時間;n*VO為在變壓器10的去磁時段TDS中,變壓器10的電壓。n為一次側繞組NP及二次側繞組NS之匝數比,VO為二次側繞組NS之電壓(即輸出電壓)。
TW is the occurrence time of the voltage level Vinx of the input voltage of the
在變壓器10被激磁後,電流感測訊號VCS之位準VCSp相關於一次側開關電流IP於激磁過程結束之峰值,且於圖3所示之電阻60上產生,其可以下列式2表示:VCSp=(Vinx/L)*TW*Rs (式2)
After the
其中L為變壓器10之一次側繞組NP之電感,Rs為電阻60之電阻值,VCSp為變壓器10於激磁過程結束之電壓位準。
Wherein, L is the inductance of the primary winding NP of the
設ID=n*VO/Rt,其中Rt為電阻55之電阻值。
Assume ID=n*VO/Rt, where Rt is the resistance value of
去磁訊號Sdmg之脈寬TDSX可被表示為:TDSX=(C*VCSp)/ID,其中C為電容230之電容值。
The pulse width TDSX of the demagnetization signal Sdmg can be expressed as: TDSX=(C*VCSp)/ID, where C is the capacitance value of the
TDSX=(Rt*C*VCSp)/(n*VO) TDSX=(Rt*C*VCSp)/(n*VO)
TDSX=(Rt*C/(n*VO))*(Rs/L)*Vinx*TW TDSX=(Rt*C/(n*VO))*(Rs/L)*Vinx*TW
設Rt=L/(Rs*C) (式3) Let Rt=L/(Rs*C) (Formula 3)
TDSX=(Vinx*TW)/(n*VO) (式4) TDSX=(Vinx*TW)/(n*VO) (Formula 4)
當式3之條件滿足時,式4所示之去磁訊號Sdmg之導通期間TDSX等於變壓器10之去磁時段TDS。
When the condition of
請繼續參閱圖10,開關231導通以對電流感測訊號VCS取樣至電容230,且於開關231關斷時(即激磁結束時),電流感測訊號VCS之位準VCSp被保持在電容230,開關231由取樣訊號SMP控制。當開關231關斷時,去磁訊號Sdmg被致能(例如藉由邏輯電路285),換言之,當去磁訊號Sdmg開始致能時,電容230之跨壓VC為電流感測訊號VCS的峰值。在開關231關斷
之後,放電電流ID開始將電容230放電,當電容230經由放電電流ID(ID=n*VO/Rt)完全放電完成時(VC=0V),去磁訊號Sdmg禁能。圖10及圖3所示之電阻55用以設定去磁訊號Sdmg的預設脈寬。
Please continue to refer to Figure 10. The
在一實施例中,於強制插入的不連續導通模式切換週期中,去磁訊號Sdmg的脈寬TDSX可藉由去磁仿擬器250而與輔助訊號VAUX的脈寬所示意的去磁時段TDS做比較,因此去磁訊號Sdmg的脈寬TDSX可被校正而用於接下來的非不連續導通模式切換週期。在一實施例中,去磁仿擬器250更用以根據不連續導通模式中所偵測到的去磁時段TDS而調整電阻255之電阻值,以校正去磁訊號Sdmg的脈波期間TDSX。
In one embodiment, in the discontinuous conduction mode switching period of forced insertion, the pulse width TDSX of the degaussing signal Sdmg can be compared with the degaussing period TDS represented by the pulse width of the auxiliary signal VAUX by the
在其他實施例中,除了調整電阻255之電阻值外,去磁仿擬器250亦可藉由以下方式校正去磁訊號Sdmg的脈波期間TDSX:調整電壓閾值Vth以決定去磁訊號Sdmg之結束,或調整電容230的電容值,或調整例如圖10中電晶體271與電晶體272所組成的電流鏡之比值。
In other embodiments, in addition to adjusting the resistance value of the
圖11顯示本發明之諧振半橋返馳式轉換器之一較佳實施例示意圖。諧振半橋返馳式轉換器900相似於圖3之諧振半橋返馳式轉換器300。在本實施例中,諧振半橋返馳式轉換器900包括第一電晶體M1、第二電晶體M2及第三電晶體M3,第一電晶體M1、第二電晶體M2及第三電晶體M3用以構成半橋電路。就一觀點而言,第一電晶體M1與第三電晶體M3配置為諧振半橋返馳式轉換器900之下橋電晶體,且第二電晶體M2配置為諧振半橋返馳式轉換器900之上橋電晶體。
FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-
根據回授訊號VFB及輸入電壓VIN,一次側控制器201用以產生第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3耦接以經由半橋電路而切換變壓器10,藉此於變壓器10之二次側產生輸出電壓VO。第二驅動訊號S2驅動第二電晶
體M2以激磁變壓器10,第三驅動訊號S3於變壓器10之去磁與諧振時段中導通第三電晶體M3,第三驅動訊號S3也用於導通第三電晶體M3以產生流經變壓器10的循環電流,並於重負載狀態中達成第二電晶體M2的零電壓切換。換言之,第二電晶體M2為諧振半橋返馳式轉換器900之一次側上橋開關且可對應於圖3之第一電晶體30,第三電晶體M3為諧振半橋返馳式轉換器900之一次側下橋開關且可對應於圖3之第二電晶體40。就一觀點而言,第一電晶體M1用以並聯於第三電晶體M3且作為輔助一次側下橋開關,具有獨立的控制訊號S1。
According to the feedback signal VFB and the input voltage VIN, the
在一實施例中,在輕負載狀態且操作於不連續導通模式時,藉由導通第二電晶體M2而激磁變壓器10之後,第三電晶體M3於變壓器10之去磁與諧振時段中被控制為導通。於去磁之後,當第三電晶體M3持續關斷,第一驅動訊號S1用以導通第一電晶體M1,以產生流經變壓器10的循環電流而達成第二電晶體M2的零電壓切換時,。因此,第三電晶體M3在不連續導通模式之一個切換週期中可避免切換兩次。
In one embodiment, after the
由於第一電晶體M1只用以產生循環電流以達成零電壓切換,在一實施例中,第一電晶體M1之實際尺寸(例如長寬比)可配置為遠小於第三電晶體M3之實際尺寸。因此,第一電晶體M1的驅動能力及寄生電容(例如閘極電容)低於第三電晶體M3的寄生電容,第一電晶體M1的切換損耗也因此低於第三電晶體M3的切換損耗。 Since the first transistor M1 is only used to generate circulating current to achieve zero voltage switching, in one embodiment, the actual size (such as aspect ratio) of the first transistor M1 can be configured to be much smaller than the actual size of the third transistor M3 size. Therefore, the driving capability and parasitic capacitance (such as gate capacitance) of the first transistor M1 are lower than the parasitic capacitance of the third transistor M3, and the switching loss of the first transistor M1 is also lower than the switching loss of the third transistor M3. .
舉例而言,電晶體的閘極切換損耗Pg可被表示為:Pg=0.5*Ciss*Vg*Vg*Freq For example, the gate switching loss Pg of the transistor can be expressed as: Pg=0.5*Ciss*Vg*Vg*Freq
其中Ciss為電晶體之輸入電容,Vg為閘極驅動訊號之電壓位準,Freq為閘極驅動訊號之切換頻率。 Where Ciss is the input capacitance of the transistor, Vg is the voltage level of the gate drive signal, and Freq is the switching frequency of the gate drive signal.
如上述開關功率損耗方程式,實際尺寸較小的第一電晶體M1用以專用於不連續導通模式中達成第二電晶體M2的零電壓切換,因此第一電晶體M1的閘極切換損耗低於實際尺寸較大的第三電晶體M3。 As shown in the above switching power loss equation, the first transistor M1 with a smaller actual size is used exclusively to achieve zero-voltage switching of the second transistor M2 in the discontinuous conduction mode. Therefore, the gate switching loss of the first transistor M1 is lower than The third transistor M3 is actually larger in size.
此外,在一實施例中,第一驅動訊號S1的電壓位準(即Vg)之振幅低於第三驅動訊號S3的電壓位準之振幅,因此更可降低第一電晶體M1之切換損耗,且在一實施例中,第一電晶體M1之閘極最大額定值(例如閘源極電壓)也可低於第三電晶體M3之閘極最大額定值。 In addition, in one embodiment, the amplitude of the voltage level (ie, Vg) of the first driving signal S1 is lower than the amplitude of the voltage level of the third driving signal S3, so the switching loss of the first transistor M1 can be further reduced. And in one embodiment, the gate maximum rating (eg gate-source voltage) of the first transistor M1 may also be lower than the gate maximum rating of the third transistor M3.
電阻60藉由偵測變壓器10的一次側開關電流IP而產生電流感測訊號VCS,一次側控制器201用以根據輸入電壓VIN而產生第一驅動訊號S1,並根據輸入電壓VIN及/或輸出電壓VO而產生第三驅動訊號S3。一次側控制器201更用以根據回授訊號VFB而產生第二驅動訊號S2。
The
圖12顯示本發明之一次側控制器201操作於不連續導通模式之一較佳實施例操作波形圖。於不連續導通模式之操作中,一次側控制器201操作於第一切換週期Tcyc1並控制第一驅動訊號S1於第一時段TA中導通第一電晶體M1,藉此產生循環電流以達成第二電晶體M2導通時的零電壓切換。經過第一時段TA後,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3用以於第一不導通時段Td1(即空滯時段)中,關斷第一電晶體M1、第二電晶體M2及第三電晶體M3。在一實施例中,第一不導通時段Td1相關於用以達成第二電晶體M2之零電壓切換的準諧振時段。經過第一不導通時段Td1後,第二驅動訊號S2於第二時段TB中,導通第二電晶體M2,第二電晶體M2之導通用以激磁變壓器10。經過第二時段TB後,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3用以於(即空滯時段)中,關斷第一電晶體M1、第二電晶體M2及第三電晶體M3。在一實施例中,第二不導通時段Td2相關於用以達成第三電晶體M3之零電壓切換的另一準諧振時段。經過第二
不導通時段Td2後,第三驅動訊號S3於第三時段TC中,導通第三電晶體M3,第三電晶體M3於變壓器10之去磁時段中導通。經過第三時段TC後,第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3用以於第三不導通時段TZ中,關斷第一電晶體M1、第二電晶體M2及第三電晶體M3,其中激磁電流IM於第三不導通時段TZ中(即不連續導通模式)維持在零。經過第三不導通時段TZ後,開始另一切換週期Tcyc2。
FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-
圖13顯示本發明一次側控制器之一較佳實施例方塊圖。在一實施例中,一次側控制器213包括計時器22及控制元件243。控制元件243用以根據輸入電壓VIN(經由VAUX)及回授訊號VFB而產生第一驅動訊號S1、第二驅動訊號S2及第三驅動訊號S3。
Figure 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention. In one embodiment, the
計時器22用以計時而產生第三不導通時段TZ,第三不導通時段TZ起始於第三驅動訊號S3脈波結束時(例如下降緣)。在一實施例中,當諧振半橋返馳式轉換器的輸出功率減少時,第三不導通時段TZ對應增加,因此,諧振半橋返馳式轉換器的切換頻率亦能因諧振半橋返馳式轉換器的輸出功率減少而對應減少,藉此改善輕負載操作狀態中的效能。
The
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。所說明之各個實施例,並不限於單獨應用,亦可以組合應用,舉例而言,兩個或以上之實施例可以組合運用,而一實施例中之部分組成亦可用以取代另一實施例中對應之組成部件。此外,在本發明之相同精神下,熟悉本技術者可以思及各種等效變化以及各種組合,舉例而言,本發明所稱「根據某訊號進行處理或運算或產生某輸出結果」,不限於根據該訊號的本身,亦包含於必要時,將該訊號進行電壓電流轉換、電流電壓轉換、及/或比例轉換等,之後根據轉換後的訊號進行處理或運算產生某輸出結果。由此可 知,在本發明之相同精神下,熟悉本技術者可以思及各種等效變化以及各種組合,其組合方式甚多,在此不一一列舉說明。因此,本發明的範圍應涵蓋上述及其他所有等效變化。 The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those familiar with the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace those in another embodiment. Corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or computing according to a certain signal or generating a certain output result", which is not limited to Depending on the signal itself, it also includes performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or calculating the converted signal to produce an output result. From this it can be It is understood that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. There are many combinations, and they are not listed here. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes.
DCM:不連續導通模式 DCM: discontinuous conduction mode
IP:一次側開關電流 IP: primary side switching current
kn:膝點 kn: knee point
NC:正整數 NC: positive integer
Sdmg:去磁訊號 Sdmg: degaussing signal
SH:驅動訊號 SH: drive signal
SL:驅動訊號 SL: drive signal
t1-t5:時點 t1-t5: time point
ta-te:時點 ta-te: time point
ta’,tc’,t2’:時點 ta’,tc’,t2’: time point
TDS:去磁時段 TDS: degaussing period
TDSX:導通期間 TDSX: conduction period
TDSX’:導通期間 TDSX’: conduction period
TSL:導通期間 TSL: conduction period
TW:激磁時段 TW: Excitation period
VAUX:輔助訊號 VAUX: auxiliary signal
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US17/673158 | 2022-02-16 |
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Publication number | Priority date | Publication date | Assignee | Title |
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TWM312840U (en) * | 2006-11-24 | 2007-05-21 | Ching-Ming Lai | Single level logic connection controlled power converter characterized by high power factor |
TW201503558A (en) * | 2013-07-01 | 2015-01-16 | Univ Nat Formosa | Self-oscillating and single stage high power factor driver circuit |
CN110249516A (en) * | 2017-02-03 | 2019-09-17 | 哈佛大学校长及研究员 | Highly integrated high-pressure activated device driver |
US20200112257A1 (en) * | 2018-10-05 | 2020-04-09 | Infineon Technologies Austria Ag | Asymmetric power converter, power converters, and operating power converters |
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- 2022-06-17 CN CN202210689138.1A patent/CN115940647A/en active Pending
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Publication number | Priority date | Publication date | Assignee | Title |
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TWM312840U (en) * | 2006-11-24 | 2007-05-21 | Ching-Ming Lai | Single level logic connection controlled power converter characterized by high power factor |
TW201503558A (en) * | 2013-07-01 | 2015-01-16 | Univ Nat Formosa | Self-oscillating and single stage high power factor driver circuit |
CN110249516A (en) * | 2017-02-03 | 2019-09-17 | 哈佛大学校长及研究员 | Highly integrated high-pressure activated device driver |
US20200112257A1 (en) * | 2018-10-05 | 2020-04-09 | Infineon Technologies Austria Ag | Asymmetric power converter, power converters, and operating power converters |
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