TWI825754B - Display driving circuit and related display device - Google Patents

Abstract

The present disclosure provides a display driving circuit and a related display device. The display driving circuit includes a grayscale generating circuit, a pulse width modulation control circuit, and a plurality of channel driving circuits. The grayscale generating circuit is configured to generate an original clock signal according to the display data. The pulse width modulation control circuit is configured to generate at least one first clock signal according to the display data, wherein a pulse width of the first clock signal is less than or equal to a pulse width of the original clock signal. Each channel driving circuit includes a current source, at least one first switch circuit and a second switch circuit. The current source is configured to provide driving current. The first switch circuit is coupled to the current source for receiving the driving current and turns on selectively according to the first clock signal. The second switch circuit is coupled to the current source through the first switch circuit, and configured to turn on selectively according to the original clock signal.

Description

Display drive circuits and related display devices

This disclosure document relates to a display driving circuit and related display devices, in particular to a display driving circuit and related display devices with high grayscale resolution and low pin count.

The grayscale resolution of a light emitting diode (LED) display can be expressed in bits. The higher the total number of bits, the higher the grayscale resolution of the LED display, and the finer the grayscale it can present. On the contrary, the lower the total number of bits, the lower the gray-scale resolution of the LED display, which in turn affects the discrimination of the LED display in gray-scale display (especially low gray-scale).

Multiple parameters of LED displays: frame rate, grayscale resolution, and the number of scan lines driven by each scanning chip are related to each other. When the frame rate is fixed, if the number of scan lines driven by each scanning chip is increased, although the number of chips can be reduced to save manufacturing costs, the scan line time (line time) will be shortened and the grayscale resolution will be reduced. On the other hand, if the number of scan lines driven by each scanning chip is reduced, although the scan line time can be increased and the grayscale resolution can be improved, the manufacturing cost will be increased.

Therefore, how to balance the manufacturing cost and grayscale resolution of LED displays is an issue in this field.

In order to solve the above problems, this disclosure document provides a display driving circuit, which includes a grayscale generation circuit, a pulse width modulation (pulse width modulation, PWM) control circuit, and a plurality of channel driving circuits. The gray scale generation circuit is used to generate the original clock signal based on the display data. The PWM control circuit is used to generate at least one first clock signal according to the display data, wherein the pulse width of the at least one first clock signal is less than or equal to the pulse width of the original clock signal. Each channel driving circuit includes a current source, at least a first switch circuit and a second switch circuit. The current source is used to provide driving current. The first switch circuit is coupled to the current source for receiving the driving current and for selectively conducting according to at least one first clock signal. The second switch circuit is coupled to the current source through at least one first switch circuit for selectively conducting according to the original clock signal.

This disclosure document further provides a display device, including a display driving circuit, a plurality of data lines, and a plurality of pixels. The display driving circuit includes a gray scale generation circuit, a PWM control circuit and a plurality of channel driving circuits. The gray scale generation circuit is used to generate the original clock signal based on the display data. The PWM control circuit is used to generate at least one first clock signal according to the display data, wherein the pulse width of the at least one first clock signal is less than or equal to the pulse width of the original clock signal. Each channel driving circuit includes a current source, at least a first switch circuit and a second switch circuit. The current source is used to provide driving current. The first switch circuit is coupled to the current source for receiving the driving current and for selectively conducting according to at least one first clock signal. The second switch circuit is coupled to the current source through at least one first switch circuit for selectively conducting according to the original clock signal. Each pixel is coupled to the display driving circuit through one of the plurality of data lines to receive driving current.

The advantage of the above-mentioned display driving circuit and display device is that it can improve the resolution of LED displays with low grayscale bits, thereby improving the problem of low recognition at low grayscales. In addition, you can also reduce or adjust the difference between different gray levels.

In this disclosure document, when a component is referred to as "connected" or "coupled," it may mean "electrically connected" or "electrically coupled." "Connection" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more elements. In addition, although terms such as “first”, “second”, etc. are used in this disclosure document to describe different components, these terms are only used to distinguish components or operations described by the same technical terms. Unless the context clearly indicates otherwise, such terms do not specifically refer to or imply a sequence or sequence, nor are they intended to limit this disclosure document.

Figure 1 is a simplified functional block diagram of a display device 1 according to some embodiments. The display device 1 includes a display driving circuit 10, a scan switch circuit 12, pixel units P[11]˜P[MN], M scan lines SL[1]˜SL[M], and N data lines DL[1]˜ DL[N], where M and N are integers greater than 1.

Structurally, in one embodiment, each pixel unit P[11]~P[MN] is implemented with a light-emitting diode, and the anodes of the N diodes in each row are electrically connected and scanned. One of the lines SL[1]~SL[M], the cathodes of the M diodes in each row (column) are electrically connected to one of the data lines DL[1]~DL[N]. The pixel units P[11]~P[MN] are coupled to the scan switch circuit 12 through the scan lines SL[1]~SL[M], and coupled to the display driver through the data lines DL[1]~DL[N]. Circuit 10. The display driving circuit 10 is used to provide driving current to the data lines DL[1]~DL[N]. The scanning switch circuit 12 is used to select the column to be emitted in the pixel units P[11]˜P[MN], where the brightness generated by the pixel units P[11]˜P[MN] corresponds to the received driving current.

FIG. 2 is a schematic diagram of a display driving circuit 20 according to some embodiments, wherein the display driving circuit 20 can be used to implement the display driving circuit 10 of FIG. 1 . The display driving circuit 20 includes a gray scale generation circuit 200 and a plurality of channel driving circuits 210_1˜210_N. The grayscale generation circuit 200 generates and adjusts a plurality of original clock signals Gray0_1~Gray0_N according to the display data Data, and transmits the original clock signals Gray0_1~Gray0_N to the channel driving circuits 210_1~210_N respectively. The channel driving circuits 210_1~210_N selectively provide driving current to the data lines DL[1]~DL[N] according to the original clock signals Gray0_1~Gray0_N. If the display device 1 adopts the display driving circuit 20 of FIG. 2 as the display driving circuit 10, the display device 1 may have a lower grayscale resolution, or it may be difficult to light the pixel units P[11]˜P[MN ]. To illustrate these problems, the operation of the display driving circuit 20 will be described below with reference to Figures 2, 3A and 3B.

Please refer to Figure 2 first. The channel driving circuits 210_1~210_N have similar components, connection relationships and operations. For the sake of simplicity, only the channel driving circuit 210_1 will be described below. In some embodiments, the channel driving circuit 210_1 includes the current source 106 and the second switch circuit SW2. One end of the current source 106 is coupled to the ground power supply GND, and the other end is coupled to one end of the second switch circuit SW2. One end of the second switch circuit SW2 is coupled to the current source 106, the other end is coupled to the data line DL[1], and the control end is coupled to the gray scale generation circuit 200 for receiving the original clock pulse from the gray scale generation circuit 200. Signal Gray0_1 is selectively turned on.

The current source 106 is used to provide a driving current to the data line DL[1] through the second switch circuit SW2, for example, to extract the driving current from the data line DL[1]. In one embodiment, when there is a scanning voltage on SL[1] and the current source 106 draws the driving current from the data line DL[1], the pixel unit P[11] will generate a brightness of a specific gray level. In one embodiment, when there is a scanning voltage on SL[2] and the current source 106 draws the driving current from the data line DL[1], the pixel unit P[21] will generate a brightness of a specific gray level.

Please refer to Figures 3A and 3B. FIG. 3A is a schematic diagram of a subframe of the display device 1 drawn according to the embodiment of FIG. 2 . FIG. 3B is a timing diagram of the display driving circuit 20 drawn according to the embodiment of FIG. 2 . For example, when the frame rate of the display device 1 is 60Hz, one frame has 64 subframes, and the number of scan line groups is 53, it can be estimated that the scan line time of the display device 1 is 1/ (60×64×53) seconds, which is approximately 4.91 microseconds. In one embodiment, the scan switch circuit 12 in FIG. 1 includes a plurality of scan chips, each scan chip is used to drive a predetermined number of scan lines, and the number of scan line groups refers to the aforementioned predetermined number of scan lines. Assuming that the sum of the dead time (ie, dead time and dummy time) before the LED lights up and after it goes out is 2.4 microseconds, it can be calculated that the LED enable time is 4.91-2.4=2.51 microseconds. When the number of grayscale bits of the display device 1 is 13 bits (hereinafter referred to as "13 bits/53 scans"), it means that one frame corresponds to 2 to the 13th power (i.e. 8192) global clocks The signal period represents the period of 8192/64=128 global clock signals in a subframe. Therefore, it can be calculated that the frequency of the global clock signal must be at least 1/(2.51×10 ^-6 /128)Hz, which is approximately 50MHz. In one embodiment, the global clock signal refers to the clock signal to which all clock signals in the entire integrated circuit are referenced. For example, if the channel driving circuit 210_1 in Figure 2 is to provide a driving current corresponding to a gray scale value of 1 to the data line DL[1], then the enable time of the original clock signal Gray0_1 is equal to a global clock The period of the signal. If the channel driving circuit 210_1 in Figure 2 provides a driving current corresponding to a gray scale value of 2 to the data line DL[1], then the enable time of the original clock signal Gray0_1 is equal to the periods of the two global clock signals. , and so on.

Similarly, when other parameters of the display device 1 remain unchanged and the number of grayscale bits is changed to 16 bits, it can be calculated that the frequency of the global clock signal must be at least 407MHz. In today's technology, in order to give the LED sufficient on-time to fully light up the LED, the frequency of the appropriate global clock signal is below 100MHz, so the 407MHz global clock signal is too fast for the LED. If you want to keep the number of grayscale bits at 16 bits, and the frequency of the global clock signal does not exceed 100MHz, you need to change the number of scan line groups to 20 (hereinafter referred to as "16 bits/20 scans" ). However, the 16-bit/20-scan setting will require the use of more wafers to manufacture the scan switch circuit 12, which is detrimental to the manufacturing cost.

The display driving circuit 40 in FIG. 4 enables the display device 1 to use a lower frequency global clock signal and a smaller number of chips (for example, a global clock signal with the same frequency and the same number of scan switches as 13-bit/53 scan). chip of circuit 12), achieving 16-bit resolution.

FIG. 4 is a schematic diagram of a display driving circuit 40 according to some embodiments. The display driving circuit 40 can be used to implement the display driving circuit 10 of FIG. 1 . The display driving circuit 40 includes a gray scale generation circuit 400, a PWM control circuit 402, and a plurality of channel driving circuits 410_1˜410_N. The PWM control circuit 402 generates and adjusts a plurality of first clock signals PWM1_1 to PWM1_N according to the display data Data, and transmits the first clock signals PWM1_1 to PWM1_N to the channel driving circuits 410_1 to 410_N respectively. In some embodiments, the pulse widths of the first clock signals PWM1_1 to PWM1_N are equal to or smaller than the pulse widths of the original clock signals Gray0_1 to Gray0_N. The channel driving circuits 410_1~410_N selectively provide driving currents to the data lines DL[1]~DL[N] according to the original clock signals Gray0_1~Gray0_N and the first clock signals PWM1_1~PWM1_N. The following embodiments of this disclosure document will take the channel driving circuit 410_1 as an example for description. The components, connection relationships and operations of the other channel driving circuits 410_2 ~ 410_N are similar to the channel driving circuit 410_1. For the sake of simplicity, the relevant content will be Not repeated.

In some embodiments, the channel driving circuit 410_1 includes a current source 106, a first switch circuit SW1 and a second switch circuit SW2. One end of the first switch circuit SW1 is coupled to the current source 106, the other end is coupled to the second switch circuit SW2, and the control end is coupled to the PWM control circuit 402 for receiving the first clock signal PWM1_1 from the PWM control circuit 402. , thereby selectively conducting.

One end of the second switch circuit SW2 is coupled to the first switch circuit SW1, the other end is coupled to the data line DL[1], and the control end is coupled to the gray scale generation circuit 400 for receiving the original signal from the gray scale generation circuit 400. The clock signal Gray0_1 is selectively turned on.

The current source 106 is used to provide a driving current to the data line DL[1] through the first switch circuit SW1 and the second switch circuit SW2, for example, extract the driving current from the data line DL[1]. In one embodiment, when there is a scanning voltage on SL[1] and the current source 106 draws the driving current from the data line DL[1], the pixel unit P[11] will generate a brightness of a specific gray level. In one embodiment, when there is a scanning voltage on SL[2] and the current source 106 draws the driving current from the data line DL[1], the pixel unit P[21] will generate a brightness of a specific gray level.

5A and 5B are timing diagrams of the display driving circuit 40 according to the embodiment of FIG. 4 . The period T ₁₆ is the period of the 16-bit/20-scan LED display that outputs the original clock signal Gray0_1 with a gray-scale value of 1. The period T ₁₃ is the original time period of the 13-bit/53-scan LED display that outputs the gray-scale value of 1. As for the period of the pulse signal Gray0_1, it can be known from the above that the period T ₁₃ is approximately twice the period T ₁₆ .

When the gray scale generation circuit 400 transmits the original clock signal Gray0_1 to the second switch circuit SW2, the PWM control circuit 402 simultaneously transmits the first clock signal PWM1_1 to the first switch circuit SW1. The current source 106 can only deliver the driving current when the first switch circuit SW1 and the second switch circuit SW2 are enabled at the same time. Therefore, by adjusting the pulse width of the first clock signal PWM1_1, the pulse width of the driving current output by the channel driving circuit 410_1 can be controlled. In the embodiment of Figure 5A, if the duty ratio of the first clock signal PWM1_1 is set to 50%, the pulse width of the driving current can be shortened to the same as the period T ₁₆ (that is, 0.5 times the period T ₁₃ ), Achieve the advantages described in this disclosure document.

Similarly, for a clock with an output grayscale value of 2, the duty ratio of the first clock signal PWM1_1 can be set to 50% at the first global clock signal (GCLK), and at the second global clock signal When the duty ratio of the first clock signal PWM1_1 is set to 50%, the driving current of gray scale value 2 has two pulse waves of 0.5 times the period T ₁₃ .

In some embodiments, through the display driving circuit 40 of the present disclosure, the difference between different gray levels can also be reduced or adjusted. Please refer to Figure 5B. For a clock with an output grayscale value of 2, if the duty ratio of the first clock signal PWM1_1 is set to 30% at the first global clock signal (GCLK), at the second When a global clock signal is used, the duty ratio of the first clock signal PWM1_1 is set to 50%, then the total pulse width of the driving current with grayscale value 2 is 80% of the previous embodiment (0.3 times the period T ₁₃ and 0.5 Doubling the period T ₁₃ ) further reduces the brightness difference between gray scale value 1 and gray scale value 2.

FIG. 6 is a circuit schematic diagram of a display driving circuit 60 according to some embodiments. In some embodiments, the display driving circuit 60 includes a gray scale generation circuit 600, a PWM control circuit 602, channel driving circuits 610_1˜610_N, and a switching signal control circuit 608. The connection relationship between the gray scale generation circuit 600, PWM control circuit 602 and channel driving circuits 610_1~610_N in Figure 6 is the same as the gray scale generation circuit 400, PWM control circuit 402 and channel driving circuits 410_1~410_N in Figure 4 The connection relationships between them are similar, so the differences will be explained below. In addition, the following embodiments of this disclosure document will take the channel driving circuit 610_1 as an example for description. The components, connection relationships and operations of the other channel driving circuits 610_2 ~ 610_N are similar to the channel driving circuit 610_1. For the sake of simplicity, the relevant The content will not be repeated.

In some embodiments, the PWM control circuit 602 includes a plurality of sub-PWM control circuits 602_1 and 602_2 for generating corresponding plurality of first clock signals PWM1_11 and PWM1_12. In some embodiments, the channel driving circuit 610_1 includes a current source 106, first switch circuits SW1_1, SW1_2, and a second switch circuit SW2.

The switch signal control circuit 608 is coupled to the first switch circuits SW1_1 and SW1_2, and is used to generate the first control signals SS1_11 and SS1_12 according to the display data Data to turn on the activation switches OS1 and OS2 corresponding to the first switch circuits SW1_1 and SW1_2.

In operation, the first switch circuits SW1_1 and SW1_2 are coupled in parallel between the current source 106 and the second switch circuit SW2 for controlling the corresponding first clock signals PWM1_11 and PWM1_12 and the corresponding first control respectively. The signals SS1_11 and SS1_12 are selectively turned on, and the first clock signals PWM1_11 and PWM1_12 respectively have different duty ratios (for example, 30% and 50% respectively).

In some embodiments, each of the first switch circuits SW1_1 and SW1_2 includes corresponding enable switches ES1 and ES2 and output switches OS1 and OS2 respectively. The enable switches ES1 and ES2 are coupled between one of the sub-PWM control circuits 602_1 and 602_2 and the control terminals of the corresponding output switches OS1 and OS2 for selectively conducting according to the corresponding first control signals SS1_11 and SS1_12. The output switches OS1 and OS2 are coupled between the current source 106 and the second switch circuit SW2 for selectively turning on according to corresponding ones of the first clock signals PWM1_11 and PWM1_12 and the first control signals SS1_11 and SS1_12.

In some embodiments, the PWM control circuit 602 also includes a sub-PWM control circuit 602_3. The sub-PWM control circuit 602_3 is used to generate the second clock signal PWM2_1, and the second clock signal PWM2_1 has a duty ratio of 100%. The channel driving circuit further includes a third switch circuit SW3, the third switch circuit SW3 is coupled between the current source 106 and the second switch circuit SW2, and the third switch circuit SW3 includes a start switch ES3 and an output switch OS3, where the switch signal The control circuit 608 is coupled to the third switch circuit SW3 and used to generate the second control signal SS2_1 according to the display data Data to turn on the activation switch ES3 of the third switch circuit SW3.

In operation, the enabling sequence and time of the first switch circuits SW1_1, SW1_2 and the third switch circuit SW3 can be determined according to the timing of the first control signals SS1_11, SS1_12 and the second control signal SS2_1 generated by the switch signal control circuit 608. In other words, according to the first clock signals PWM1_11, PWM1_12, the second clock signal PWM2_1, the first control signals SS1_11, SS1_12 and the second control signal SS2_1, the timing of the current source 106 providing the driving current can be controlled, that is, the timing of the driving current can be controlled. The duty ratio of the clock signal output by the channel driving circuit 610_1.

FIG. 7 is a timing diagram of the display driving circuit 60 according to the embodiment of FIG. 6 . In Figure 7, similar to the embodiment of Figure 5B, in order to output the driving current of gray scale value 2, the first clock signal PWM1_11 with a duty ratio of 30% and the first clock signal PWM1_11 with a duty ratio of 50% can be used. Pulse signal PWM1_12. In operation, when the first control signal SS1_11 is logic high, the first switch circuit SW1_1 will be enabled, so that the pulse wave of the driving current is 0.3 periods T ₁₃ ; when the first control signal SS1_12 is logic high, the first switch circuit SW1_1 will be enabled. A switch circuit SW1_2 will be enabled, so that the pulse wave of the driving current is 0.5 period T ₁₃ ; when the second control signal SS2_1 is logic high, the third switch circuit SW3 will be enabled, but due to the original clock signal Gray0_1 At this time, the logic is low, so the channel driving circuit 610_1 will not output a driving current.

As learned from the above, in the embodiments shown in Figures 6 to 7, the difference between different gray levels can be reduced or adjusted by controlling the switching timing of different first switch circuits.

It should be noted that the number of sub-PWM control circuits, first switch circuits, first clock signals and first control signals in this disclosure document are only examples and do not limit this disclosure document. Other numbers of sub-PWM control circuits, first switching circuits, first clock signals and first control signals are within the scope of this disclosure document.

In summary, the display driving circuit and related display devices disclosed in this disclosure document can improve the resolution of LED displays with lower grayscale bits by controlling the enabling timing of the channel driving circuit, thereby improving the performance of LED displays. The problem of low recognition at low gray levels. In addition, by controlling the load ratio of the first clock signal, the difference between different gray levels can also be reduced or adjusted.

1: Display device 10: Display driving circuit 12: Scan switch circuit 106: Current source 20: Display driving circuit 200: Gray scale generation circuit 210_1~210_N: Channel driving circuit 40: Display driving circuit 400: Gray scale generation circuit 402: PWM Control circuit 410_1~410_N: Channel drive circuit 60: Display drive circuit 600: Gray scale generation circuit 602_1~602_3: Sub-PWM control circuit 602: PWM control circuit 608: Switch signal control circuit 610_1~610_N: Channel drive circuit Gray0_1~Gray0_N: Original clock signal PWM1_1~PWM1_N: first clock signal PWM1_11~PWM1_N1: first clock signal PWM1_12~PWM1_N2: first clock signal PWM2_1~PWM2_N: second clock signal Data: display data DL[1]~DL [N]: Data lines ES1~ES3: Start switch GCLK: Global clock signal GND: Ground power supply OS1~OS3: Output switch P[11]~P[MN]: Pixel unit SL[1]~SL[M] :Scan line SS1_11~SS1_N1: first control signal SS1_12~SS1_N2: first control signal SS2_1~SS2_N: second control signal SW1: first switch circuit SW1_1, SW1_2: first switch circuit SW2: second switch circuit SW3: Three-switch circuit T ₁₃ , T ₁₆ : period

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a functional block diagram of a display device according to some embodiments; Figure 2 is a partial circuit schematic diagram of a display driving circuit according to some embodiments; Figures 3A and 3B are timing diagrams of the display driving circuit 10 drawn according to the embodiment of Figure 2; Figure 4 is a partial circuit schematic diagram of a display driving circuit according to some embodiments; Figures 5A and 5B are timing diagrams of the display driving circuit according to the embodiment of Figure 4; Figure 6 is a circuit schematic diagram of a display driving circuit according to some embodiments; and FIG. 7 is a timing diagram of a display driving circuit according to the embodiment of FIG. 6 .

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40: Display drive circuit 400: Gray scale generation circuit 402:PWM control circuit 410_1~410_N: Channel drive circuit 106:Current source Gray0_1~Gray0_N: original clock signal PWM1_1~PWM1_N: first clock signal DL[1]~DL[N]: data line GND: Ground power supply SW1: first switch circuit SW2: Second switch circuit

Claims (10)

A display driving circuit includes: a gray scale generation circuit for generating an original clock signal based on a display data; a PWM control circuit for generating at least a first clock signal based on the display data, wherein the at least one The pulse width of the first clock signal is less than or equal to the pulse width of the original clock signal; and a plurality of channel driving circuits, wherein each channel driving circuit includes: a current source for providing a driving current; at least one A first switching circuit coupled to the current source for receiving the driving current and selectively conducting according to the at least one first clock signal; and a second switching circuit coupled through the at least one first switching circuit Connected to the current source for selective conduction based on the original clock signal. The display driving circuit of claim 1, wherein the PWM control circuit is used to adjust the duty ratio of the at least one first clock signal according to the display data. The display driving circuit of claim 1, wherein the at least one first switch circuit includes a plurality of first switch circuits, and the at least one first clock signal includes a plurality of first clock signals, wherein the first switches The circuit is coupled in parallel between the current source and the second switch circuit to respectively respond to the first clock signals. And a plurality of first control signals are selectively turned on, wherein the first clock signals respectively have a plurality of different load ratios. The display driving circuit of claim 3, wherein the PWM control circuit further includes a plurality of sub-PWM control circuits, and the sub-PWM control circuits are used to generate the first clock signals. The display driving circuit of claim 4, wherein each first switch circuit further includes a start switch and an output switch, wherein the start switch of the first switch circuit is coupled to one of the sub-PWM control circuits. and a control end of the output switch for selectively conducting according to one of the first control signals to transmit the corresponding one of the first clock signals; the output switch coupling of the first switch circuit Connected between the current source and the second switch circuit, for selectively conducting according to the corresponding one of the first clock signals. The display driving circuit of claim 5, wherein the display driving circuit further includes a switching signal control circuit, the switching signal control circuit is coupled to the first switching circuits and is used to generate the first switching circuits based on the display data. The control signal is used to turn on the start switch of one of the first switch circuits. The display driving circuit as described in claim 6, wherein the The sub-PWM control circuit is also used to generate a second clock signal, the second clock signal has a duty ratio of 100%, wherein each channel drive circuit also includes a third switch circuit, the third switch circuit is coupled between the current source and the second switch circuit, and the third switch circuit includes a start switch and an output switch, wherein the switch signal control circuit is coupled to the third switch circuit for generating a signal based on the display data. A second control signal is used to turn on the start switch of the third switch circuit. A display device includes a display driving circuit, a plurality of data lines and a plurality of pixels, wherein the display driving circuit includes: a gray scale generation circuit for generating an original clock signal based on a display data; a PWM control circuit , used to generate at least one first clock signal based on the display data, wherein the duty ratio of the at least one first clock signal is less than or equal to the duty ratio of the original clock signal; and a plurality of channel drive circuits, each of which The channel driving circuit includes: a current source for providing a driving current; at least a first switch circuit coupled to the current source for receiving the driving current and for selectively controlling the at least one first clock signal. Turn on; and a second switch circuit, coupled to the current source through the at least one first switch circuit, for selectively turning on according to the original clock signal; wherein each pixel passes through one of the plurality of data lines. coupled to the display drive circuit to receive the drive current. The display device of claim 8, wherein the at least one first switch circuit includes a plurality of first switch circuits, and the at least one first clock signal includes a plurality of first clock signals, wherein the first switch circuits is coupled in parallel between the current source and the second switch circuit for selectively conducting according to the first clock signals and a plurality of first control signals respectively, wherein the first clock signals are respectively With different load ratios. The display device of claim 9, wherein the PWM control circuit further includes a plurality of sub-PWM control circuits, and the sub-PWM control circuits are used to generate the first clock signals.

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