TWI824847B - Method and apparatus for controlling shared memory, shareable memory and electrical device using the same - Google Patents

Abstract

The present invention relates to a method and an apparatus for controlling shared memory a shareable memory and an electrical device using the same. The method includes: providing a plurality of memory blocks; pre-allocating the memory blocks to a plurality of systems; when a specific system of the systems output an access request, the method further includes: enabling the allocated memory block(s) of the specific system; and electrically connecting an access signal to the enabled allocated memory block(s).

Description

Memory sharing device, method, shareable memory and electronic device using the same Prepare

The present invention relates to a memory control technology, and in particular to a memory sharing device, method, shareable memory and electronic equipment using the same.

Random Access Memory (RAM) is an internal memory that exchanges data with the processor. Generally, it can be read and written at any time, and it is very fast. It is usually used as a temporary data storage medium for the operating system or other running programs. When designing random access memory, the address size, data length, etc. that can be accessed by each random access memory interface are all fixed. Therefore, when multiple systems want to share memory, each system must use the same address width access method. In addition, general memory only has a single port (Single Port), and all access depends on this single port. Therefore, a rather complex memory sharing mechanism is required to prevent the accessed memories from overlapping each other and causing data errors. .

In addition, in the prior art, there is also a dual-ported random access memory (Dual-Ported RAM, DPRAM). FIG. 1 is a circuit block diagram of a dual-port random access memory 10 in the prior art. Please refer to Figure 1. This kind of dual-port random access memory is a kind of memory that allows simultaneous (or almost simultaneous) operation by two Random access memory accessed by systems 101 and 102. Dual-port random access memory has two sets of address buses and two sets of data buses (hence the name "dual port"), thus allowing access by two devices, while the address of a general random access memory There is only one set of bus and data bus. Generally, if dual-port random access memory is used, if different data are written by different devices at the same location at the same time (or almost at the same time), there will be a race hazard (Race Hazard) problem, which will lead to data errors.

The present invention provides a memory sharing device, method, shareable memory and electronic equipment using the same to provide a flexible and low-cost method to allow multiple systems to access the same memory device, and each system Different address widths are possible, enabling simple control, allowing for a variety of memory widths, and avoiding data errors.

Embodiments of the present invention provide a shareable memory for sharing memory to multiple systems. The shareable memory includes multiple memory blocks (Ranks) and a memory sharing device according to embodiments of the present invention. , the memory sharing device includes a selection circuit and an interface selection control circuit. The selection circuit includes a plurality of receiving ports and an output port, wherein each address receiving port is coupled to a corresponding system, and wherein the address output port is coupled to each memory block. The interface selection control circuit is coupled to the selection circuit, and according to the access request of at least one specific system output in the above system, electrically connects the receiving port of the selection circuit corresponding to the specific system to the output port of the selection circuit, and causes Within the memory block, the memory block allocated to a specific system can be used to access the above-mentioned shareable memory.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the method of allocating the memory block to a specific system in the enabling memory block further includes an interface selection control. The control circuit outputs a chip selection (Chip Selection) signal so that the memory block can be allocated to a specific system.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the selection circuit further includes a plurality of address multiplexers and a plurality of read data multiplexers. Each address multiplexer includes multiple address receiving ports and an address output port. The address receiving port of each address multiplexer receives the address signal output by the above system respectively. Each address multiplexer The address output port of the device is respectively coupled to the address receiving port of each memory block. Each read data multiplexer includes a plurality of read data receiving ports and a read data input port. The read data receiving ports of each read data multiplexer are respectively coupled to the above systems. Each read data multiplexer The read data input port of the processor is respectively coupled to the read data output port of each memory block. When the interface selection control circuit outputs a read request based on a specific system, the interface selection control circuit controls the address receiving port of the memory block corresponding to the specific system in the multiple address multiplexers to be electrically connected to the memory corresponding to the specific system. The address output port of the address multiplexer of the block. The interface selection control circuit controls multiple read data multiplexers. The read data receiving port of the memory block corresponding to the specific system is electrically connected to the corresponding specific Read data input ports for multiple read data multiplexers of the system's memory block.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the selection circuit further includes a plurality of chip selection multiplexers, and each chip selection multiplexer includes a plurality of chip selection signals. A receiving port and a chip selection signal output port. The chip selection signal receiving ports of each of the chip selection multiplexers respectively receive the chip selection signals corresponding to the systems. The chip selection signals of each of the chip selection multiplexers are The signal output port is respectively coupled to the chip selection signal receiving end of each memory block. When the interface selection control circuit responds to the reading request of the specific system output, the interface selection control circuit controls the address receiving port corresponding to the specific system in each of the chip selection multiplexers. Electrically connected to the address output port of each chip select multiplexer so as to correspond to the memory block of a specific system.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the selection circuit further includes a plurality of write data multiplexers. Each write data multiplexer includes a plurality of write data receiving ports and a write data output port. The write data receiving ports of each write data multiplexer are respectively coupled to the above system. Each write data multiplexer The write data output port of the processor is respectively coupled to the write data input port of each memory block. When the interface selection control circuit outputs a write request based on a specific system, the interface selection control circuit controls the address receiving port of the memory block corresponding to the specific system in the multiple address multiplexers to be electrically connected to the memory corresponding to the specific system. The address output port of the address multiplexer of the block block, the interface selection control circuit controls multiple write data multiplexers, and the write data receiving port of the memory block corresponding to the specific system is electrically connected to the corresponding specific Write data output port for multiple write data multiplexers of the system's memory block. In another preferred embodiment, when the interface selection control circuit outputs a writing request according to a specific system, the interface selection control circuit controls each chip selection multiplexer to electrically connect the address receiving port corresponding to the specific system to each A chip selects the address output port of the multiplexer so that it corresponds to the memory block of a specific system.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the selection circuit further includes a plurality of address multiplexers and a plurality of read data multiplexers. Each address multiplexer includes N address receiving ports and an address output port. The address output ports of each of the address multiplexers are respectively coupled to the address receiving ports of each of the memory blocks. Port, wherein the I-th system is coupled to the I-th address receiving port among the address multiplexers coupled to the memory blocks of the I-th system to receive the I-th system respectively. The output address signal. Each read data multiplexer includes a plurality of read data receiving ports and a read data input port. The read data input ports of each read data multiplexer are respectively coupled to The read data output port of each memory block, wherein the 1st read data receiving port of the read data multiplexer coupled to the memory block of the 1st system is respectively coupled to the 1st read data output port system. When the interface selection control circuit responds to the read request output by a specific system, the interface selection control circuit controls the address receiving port of the memory block corresponding to the specific system in the multiple address multiplexers to be electrically connected to the memory block corresponding to the specific system. The address output port of the address multiplexer of the memory block, the interface selection control circuit controls multiple read data multiplexers, and the read data receiving port of the memory block corresponding to the specific system is electrically connected to the corresponding Read data input port for multiple read data multiplexers of a specific system's memory block.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the selection circuit further includes a plurality of write data multiplexers. Each write data multiplexer includes a plurality of write data receiving ports and a write data output port. The write data output ports of each write data multiplexer are respectively coupled to the write data of each memory block. A data input port, wherein the first write data receiving port of the write data multiplexer coupled to the memory block of the first system is coupled to the first system respectively. When the interface selection control circuit outputs a write request according to a specific system, the interface selection control circuit controls the address receiving port of the memory block corresponding to the specific system in the multiple address multiplexers to be electrically connected to the address corresponding to the specific system. The address output port of the address multiplexer of the memory block, the interface selection control circuit controls multiple write data multiplexers, and the write data receiving port of the memory block corresponding to the specific system is electrically connected to the corresponding The write output port for multiple write multiplexers of a specific system's memory block.

According to the memory sharing device and the shareable memory according to the preferred embodiment of the present invention, the above-mentioned interface selection control circuit further includes a lookup table for storing the corresponding relationship between each system and the above-mentioned memory block, so as to select the corresponding memory block according to the specific System access requirements enable the corresponding memory block.

In addition, a preferred embodiment of the present invention provides an electronic device, including the above-mentioned shareable memory and at least one peripheral device, electrically connected to one of the plurality of systems through a bus.

Furthermore, a preferred embodiment of the present invention proposes a memory sharing method. The memory sharing method includes the following steps: providing multiple memory blocks; and pre-allocating each memory block to multiple systems according to needs. ; When in each system, at least one specific system outputs an access request, the memory sharing method includes: enabling the memory block allocated to the specific system in the memory block; and outputting the access request from the specific system The signal is electrically connected to the enabled memory block.

According to the memory sharing method according to the preferred embodiment of the present invention, the memory sharing method further includes providing a lookup table to store the corresponding relationship between each system and the memory blocks, so as to store the memory blocks according to the specific system. Get the request and enable the corresponding memory block.

According to the memory sharing method according to the preferred embodiment of the present invention, the memory sharing method further includes: coupling a plurality of address multiplexers between each memory block and the systems; A plurality of read data multiplexers are coupled between the memory block and the above-mentioned system; when a specific system outputs a read request, the above-mentioned memory sharing method includes: controlling the above-mentioned multiple address multiplexers so that the specific system The system is electrically connected to the memory block corresponding to the specific system to provide an address to the memory block corresponding to the specific system; and the plurality of read data multiplexers are controlled so that the specific system is electrically connected to The memory block corresponding to that specific system to read the data.

According to the memory sharing method according to the preferred embodiment of the present invention, a plurality of address multiplexers are coupled between each memory block and the systems, and further includes: in each of the bits The address multiplexer provides a plurality of address input ports, wherein the 1st system is coupled to the 1st address input port of the address multiplexer between the 1st system and the corresponding memory block, and is empty Connect other address input ports; among them, multiple read data multiplexers are coupled between each memory block and the systems, and further include: providing multiple read data multiplexers in each of the read data multiplexers. read data output port, wherein the I-th system is coupled to the I-th system The first read data output port of the read data multiplexer between the system and the corresponding memory block is connected to the remaining read data output ports.

According to the memory sharing method according to the preferred embodiment of the present invention, the memory sharing method further includes: coupling a plurality of address multiplexers between each memory block and the systems; Multiple write data multiplexers are coupled between the memory block and the systems; when a specific system outputs a write request, the memory sharing method includes: controlling the multiple address multiplexers so that the The specific system is electrically connected to the memory block corresponding to the specific system to provide an address to the memory block corresponding to the specific system; and the plurality of write data multiplexers are controlled to electrically connect the specific system to the memory block corresponding to the specific system to write data to the memory block corresponding to the specific system.

According to the memory sharing method according to the preferred embodiment of the present invention, a plurality of address multiplexers are coupled between each memory block and the systems, and further includes: in each of the bits The address multiplexer provides a plurality of address input ports, wherein the 1st system is coupled to the 1st address input port of the address multiplexer between the 1st system and the corresponding memory block, and is empty Connect other address input ports; among them, multiple write data multiplexers are coupled between each memory block and the systems, and further include: providing multiple write data multiplexers in each of the write data multiplexers. A write data input port, wherein the 1st system is coupled to the 1st write data input port of the write data multiplexer between the 1st system and the corresponding memory block, and is connected to the remaining write data input ports. Enter the data input port.

To sum up, the spirit of the embodiments of the present invention is to use the selection circuit to couple each system, and to use the interface selection control circuit to control the selection circuit and enable the corresponding internal memory block. Through the selection circuit, the desired memory is The access command of the system fetching the memory is passed to the enabled memory block, thereby allowing each system to access different blocks in the same shareable memory module. Since the number of enabled memory blocks can be adjusted according to different systems, it can be compatible with different memory address widths. In addition, by Different memory blocks are enabled according to different system accesses, so data errors or data overwriting problems will not occur. Furthermore, since the selection circuit is used for memory sharing, the internal wiring of the memory module does not need to be changed at all. Only the wiring between the selection circuit and the system needs to be changed. The circuit complexity can be reduced and the cost of use is also reduced.

In order to further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and drawings are only used to refer to and illustrate the implementation of the present invention, and are not intended to limit the present invention.

10:Dual port random access memory

101, 102: System

20:First system

21:Second system

22:Third system

23: Shareable memory

24:Peripheral devices

R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15: memory block

301: Select circuit

302: Interface selection control circuit

30:Memory module

401 lookup table

ADD0, ADD1, ADD2, ADD3, ADD4, ADD5, ADD6, ADD7: address multiplexer

WDAT0, WDAT1, WDAT2, WDAT3, WDAT4, WDAT5, WDAT6, WDAT7: write data multiplexer

RDAT0, RDAT1, RDAT2, RDAT3, RDAT4, RDAT5, RDAT6, RDAT7: read data multiplexer

C0, C1, C2, C3: Chip Selection multiplexer

601, 602, 603, 604, 605, 606, 607, 608: multiplex circuit

S901~S910: Process steps of a memory sharing method according to a preferred embodiment of the present invention

The accompanying drawings are provided to enable those skilled in the art to further understand the present invention, and are incorporated into and constitute a part of the specification of the present invention. The drawings illustrate exemplary embodiments of the invention and, together with the description of the invention, serve to explain the principles of the invention.

FIG. 1 is a circuit block diagram of a dual-port random access memory in the prior art.

FIG. 2 is a schematic diagram of memory access of an electronic device according to an embodiment of the present invention.

FIG. 3 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention.

FIG. 4 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention.

FIG. 5 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention.

FIG. 6 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention.

FIG. 7A is a schematic wiring diagram of a first system 20 that can share memory and memory blocks R0 to R3 according to a preferred embodiment of the present invention.

FIG. 7B is a schematic diagram of the wiring of the second system 21 and the third system 22 that can share memory and the memory blocks R4 to R7 according to a preferred embodiment of the present invention.

FIG. 8 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention.

FIG. 9 is a flow chart of a memory sharing method according to a preferred embodiment of the present invention.

Reference will now be made in detail to exemplary embodiments of the present invention, exemplary embodiments of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts. In addition, the exemplary embodiment is only one of the implementation ways of the design concept of the present invention, and the following examples are not intended to limit the present invention.

FIG. 2 is a schematic diagram of memory access of an electronic device according to a preferred embodiment of the present invention. Please refer to Figure 2. This electronic device includes three systems 20, 21, 22, a shareable memory 23 and a peripheral device 24. Peripheral device 24 is coupled to first system 20 . In this embodiment, the above-mentioned shareable memory 23 is allocated for use by the above-mentioned three systems 20, 21, and 22. And each system 20, 21, 22 uses memory access interfaces of different widths. In this embodiment, the shareable memory 23 includes 16 memory blocks R0~R15, and each memory block R0~R15 is 32 bits. First system 20 The memory access address width is 32 bits, and the memory blocks allocated to the first system 20 are memory blocks R0~R3. Therefore, each time the first system 20 accesses the memory, it is only enabled. A memory block R0~R3. The memory access address width of the system 21 is 128 bits. The memory blocks allocated to the second system 21 are memory blocks R4~R7 and R12~R15. Therefore, every time the second system 21 accesses the memory When , four memory blocks R4~R7 or R12~R15 are enabled at one time. The memory access address width of the system 22 is 64 bits, and the memory blocks allocated to the third system 22 are memory blocks R8~R11. Therefore, each time the third system 22 accesses the memory, an error occurs. It can support two memory blocks R8~R11.

FIG. 3 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention. Please refer to Figure 3. This shareable memory includes a memory module 30 and a memory sharing device 31 according to the preferred embodiment of the present invention. The memory module 30 includes eight memory blocks R0, R1, R2, R3, R4, R5, R6, and R7. The memory sharing device 31 includes a selection circuit 301 and an interface selection control circuit 302. The selection circuit 301 includes three receiving ports and one output port in this embodiment. The address receiving port of the selection circuit 301 is coupled to the above three systems 20, 21, and 22 respectively. The address output port of the selection circuit 301 is coupled to each memory block R0, R1, R2, R3, R4, R5, R6, R7. The interface selection control circuit 302 is coupled to and used to control the selection circuit 301 .

For example, assume that the memory blocks R0, R1, R2, and R3 are allocated to the first system 20; the memory blocks R4 and R5 are allocated to the second system 21; and the memory blocks R6 and R7 are allocated to the second system 21. Three systems22. When the first system 20 wants to access, the interface selection control circuit 302 will electrically connect the access signal of the first system 20 to the output port corresponding to the above-mentioned memory blocks R0, R1, through the receiving port of the selection circuit 301. R2 and R3, and enabling the memory blocks R0, R1, R2, and R3, the first system 20 can access the memory blocks R0, R1, R2, and R3. When the second system 21 wants to access, the interface selection control circuit 302 passes the access signal of the second system 21 through the selection circuit 301 The receiving port is electrically connected to the part of the output port corresponding to the memory blocks R4 and R5, and the memory blocks R4 and R5 are enabled, the second system 21 can access the memory blocks R4 and R5. R5. Similarly, when the third system 22 wants to access, the interface selection control circuit 302 will electrically connect the access signal of the third system 22 to the output port corresponding to the above-mentioned memory block R6 through the receiving port of the selection circuit 301 , R7 part, and enabling the above-mentioned memory blocks R6 and R7, the third system 22 can access the above-mentioned memory blocks R6 and R7. The above-mentioned method of enabling the memory blocks R0 to R7 may be, for example, that the interface selection control circuit 302 outputs a chip enable signal (Chip Selection Signal) to enable different memory blocks according to the access of different systems.

As can be seen from the above embodiments, the interface selection control circuit 302 switches memory blocks (memory ranks) according to different systems. Together with the selection circuit 301, the entire memory module 30 can use the same interface to share, for example, an address (ADDR). , read data (RDATA), write data (WDATA) and other signals, in order to reduce the usage of signal lines in the memory block and reduce various problems caused by excessive signal winding and routing in the memory module 30 interference problem, and can easily lead to errors in the data being accessed.

FIG. 4 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention. Please refer to Figure 4. In this embodiment, the interface selection control circuit 302 includes a lookup table 401 to store the corresponding relationship between each system and the memory block. The interface selection control circuit 302 uses the above lookup table 401 to determine The access requirements of different systems enable corresponding memory blocks. Furthermore, in this embodiment, the selection circuit 301 is divided into 4 address multiplexers ADD0~ADD3, 4 write data multiplexers WDAT0~WDAT3, 4 read data multiplexers RDAT0~RDAT3 and 4 Chip Selection multiplexers C0~C3. In order to allow those with ordinary knowledge in the art to understand the present invention, only four memory blocks R0 to R4 are used for illustration in this embodiment. Those with ordinary knowledge in the art should know that the number of memory blocks R0 ~ R4 changes with products or different designs, and the present invention is not limited thereto.

In this embodiment, the three address input ports of each address multiplexer ADD0 ~ ADD3 respectively receive the addresses output by the three systems 20 ~ 22. The three address widths may be different, so there are many addresses. The wiring widths of the three address input ports of the processor ADD0~ADD3 can also be different. Each output port of the address multiplexers ADD0~ADD3 is coupled to four memory blocks R0~R4 respectively. The three read data output ports of each read data multiplexer RDAT0~RDAT3 are used to output data to the three systems 20~22 respectively. The read data input ports of the read data multiplexers RDAT0 ~ RDAT3 are respectively coupled to the four memory blocks R0 ~ R4. The three write data input ports of the write data multiplexers WDAT0 ~ WDAT3 are respectively used to receive data to be written into the memory by the three systems 20 ~ 22. The write data output ports of the write data multiplexers WDAT0 ~ WDAT3 are respectively coupled to the four memory blocks R0 ~ R4.

In order to conveniently illustrate the spirit of the present invention, in this embodiment, it is assumed that the memory blocks R0 and R1 are allocated to the first system 20, the memory block R2 is allocated to the second system 21, and the memory block R3 is allocated to the first system 20. Give 22 to the third system. When the interface selection control circuit 302 receives the read request output by the first system 20, the interface selection control circuit 302 uses the selection signals SEL0 and SEL1 to control the address multiplexers ADD0 and ADD1 according to the lookup table 401, and the first system 20 The corresponding address receiving port is electrically connected to the address output port of the address multiplexer ADD0 and ADD1, and the interface selection control circuit 302 uses the selection signal SEL0 and SEL1 to control the chip selection multiplexer C0 and C1 to output the corresponding chip selection. Signal enables memory blocks R0 and R1. At the same time, the interface selection control circuit 302 uses the selection signals SEL0 and SEL1 to control the read input ports of the read data multiplexers RDAT0 and RDAT1 to be electrically connected to the read data output port of the corresponding first system 20 . Therefore, the addresses input by the first system 20 can be transmitted to the memory blocks R0 and R1, and the first system 20 can obtain the corresponding read data from the read data output ports of the read data multiplexers RDAT0 and RDAT1. material.

In the above embodiment, although only the address multiplexers ADD0 and ADD1 and the read data multiplexers RDAT0 and RDAT1 are controlled, this method is a preferred embodiment. Those with ordinary knowledge in the technical field can It should be noted that each address multiplexer ADD0~ADD3 and the read data multiplexer RDAT0~RDAT3 are electrically connected to the first system 20 and can be implemented as long as the memory blocks R0 and R1 are enabled. No access errors will occur. However, such an electrical connection method requires the memory blocks R0 and R1 to have greater driving capabilities when outputting and reading data. However, the present invention is not limited to the above-mentioned preferred embodiments.

When the interface selection control circuit 302 receives the read request output by the second system 21, the interface selection control circuit 302 controls the address multiplexer ADD2 with the selection signal SEL2 according to the lookup table 401, and converts the address corresponding to the second system 21 The receiving port is electrically connected to the address output port of the address multiplexer ADD2, and the interface selection control circuit 302 uses the selection signal SEL2 to control the chip selection multiplexer C2 to output the corresponding chip selection signal to enable the memory block R2. At the same time, the interface selection control circuit 302 uses the selection signal SEL2 to control the read input port of the read data multiplexer RDAT2 to be electrically connected to the read data output port of the corresponding second system 21 . Therefore, the address input by the second system 21 can be transmitted to the memory block R2, and the second system 21 can obtain the corresponding read data from the read data output port of the read data multiplexer RDAT2.

Similarly, when the interface selection control circuit 302 receives the read request output by the third system 22, the interface selection control circuit 302 uses the selection signal SEL3 to control the address multiplexer ADD3 according to the lookup table 401, so that the third system 22 corresponds to The address receiving port is electrically connected to the address output port of the address multiplexer ADD3, and the interface selection control circuit 302 uses the selection signal SEL3 to control the chip selection multiplexer C3 to output the corresponding chip selection signal to enable the memory area. Block R3. At the same time, the interface selection control circuit 302 uses the selection signal SEL3 to control the electrical connection pair of the read input port of the read data multiplexer RDAT3. Corresponds to the read data output port of the third system 22. Therefore, the address input by the third system 22 can be transmitted to the memory block R3, and the third system 22 can obtain the corresponding read data from the read data output port of the read data multiplexer RDAT3.

In addition, when the interface selection control circuit 302 receives the write request output from the first system 20, the interface selection control circuit 302 uses the selection signals SEL0 and SEL1 to control the address multiplexers ADD0 and ADD1 according to the lookup table 401, to change the first The corresponding address receiving port of the system 20 is electrically connected to the address output ports of the address multiplexers ADD0 and ADD1, and the interface selection control circuit 302 uses the selection signals SEL0 and SEL1 to control the chip selection multiplexers C0 and C1 to output the corresponding The chip select signal enables memory blocks R0 and R1. At the same time, the interface selection control circuit 302 uses the selection signals SEL0 and SEL1 to control the write output ports of the write data multiplexers WDAT0 and WDAT1 to be electrically connected to the write data input port corresponding to the first system 20 . Therefore, the addresses input by the first system 20 can be transferred to the memory blocks R0 and R1, and the first system 20 can write the write data from the write data input ports of the write data multiplexers WDAT0 and WDAT1. into memory blocks R0 and R1.

When the interface selection control circuit 302 receives the write request output by the second system 21, the interface selection control circuit 302 controls the address multiplexer ADD2 with the selection signal SEL2 according to the lookup table 401, and converts the address corresponding to the second system 21 The receiving port is electrically connected to the address output port of the address multiplexer ADD2, and the interface selection control circuit 302 uses the selection signal SEL2 to control the chip selection multiplexer C2 to output the corresponding chip selection signal to enable the memory block R2. At the same time, the interface selection control circuit 302 uses the selection signal SEL2 to control the write output port of the write data multiplexer WDAT2 to be electrically connected to the write data input port corresponding to the second system 21 . Therefore, the address input by the second system 21 can be transmitted to the memory block R2, and the second system 21 can write the write data into the memory from the write data input port of the write data multiplexer WDAT2. Block R2.

In the same way, when the interface selection control circuit 302 receives the write request output by the third system 22, the interface selection control circuit 302 uses the selection signal SEL3 to control the address multiplexer ADD3 according to the lookup table 401, and the third system 22 The corresponding address receiving port is electrically connected to the address output port of the address multiplexer ADD3, and the interface selection control circuit 302 uses the selection signal SEL3 to control the chip selection multiplexer C3 to output the corresponding chip selection signal to enable the memory. Block R3. At the same time, the interface selection control circuit 302 uses the selection signal SEL3 to control the write output port of the write data multiplexer WDAT3 to be electrically connected to the write data input port corresponding to the third system 22 . Therefore, the address input by the third system 22 can be transmitted to the memory block R3, and the third system 22 can write the write data into the memory from the write data input port of the write data multiplexer WDAT3. Block R2.

In the above embodiments, although only the corresponding address multiplexers ADD0~ADD3 and the corresponding read data multiplexers RDAT0~RDAT3 or the corresponding write data multiplexers WDAT0~WDAT3 are controlled, however, This method is a preferred embodiment, and the reasons for its advantages have been detailed in the above embodiments and will not be repeated here. However, the present invention is not limited to the above-mentioned preferred embodiments.

FIG. 5 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention. Please refer to FIGS. 4 and 5 . In this embodiment, the difference from FIG. 4 is that the interface selection control circuit 302 only needs to use the selection signal SEL0 to allow the first system 20 to access the memories R0 and R1 . Therefore, the use of wiring can be further reduced, and the complexity of the printed circuit board or circuit layout can be reduced. Since the embodiment of FIG. 5 is similar to the embodiment of FIG. 4 , no further description is given here.

FIG. 6 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention. Please refer to Figure 6. In this embodiment, the memory blocks R0~R3 of the shareable memory are allocated to the first system 20, the memory blocks R4~R5 are allocated to the second system 21, and the memory area Blocks R6~R7 are assigned to the third system 22. Furthermore, in order to simplify the description, in this embodiment, 8 multiplexers are shown Circuits 601 to 608. These multiplexing circuits 601 to 608 respectively represent the above-mentioned address multiplexer, the above-mentioned read data multiplexer, the above-mentioned write data multiplexer and the above-mentioned chip selection multiplexer. In this embodiment, the first system 20 is only coupled to the multiplexing circuits 601 to 604 and is not coupled to the multiplexing circuits 605 to 608 .

Those with ordinary knowledge in the art should be able to understand after referring to the above embodiments of FIGS. 4 to 6 that the coupling state of the first system 20 to the memory blocks R0 to R4 should be as shown in FIG. 7A . FIG. 7A depicts This is a schematic wiring diagram of a first system 20 that can share memory and memory blocks R0 to R3 according to a preferred embodiment of the present invention. By the same token, those with ordinary knowledge in the technical field should be able to understand, after referring to the above-mentioned embodiments of FIGS. 4 to 6 , the coupling status of the second system 21 to the memory blocks R4 to R5 and the coupling status of the third system 22 to the memory blocks R4 to R5. The coupling status of the memory blocks R6~R7 should be as shown in Figure 7B. Figure 7B illustrates a second system 21, a third system 22 and a memory that can share memory according to a preferred embodiment of the present invention. Schematic diagram of the wiring of blocks R4~R7.

In the above embodiment, the first system 20 is coupled to the first address receiving ports of the address multiplexers ADD0~ADD3. The first system 20 is coupled to the first read data receiving ports of the read data multiplexers RDAT0~RDAT3. The first system 20 is coupled to the first write data receiving ports of the write data multiplexers WDAT0˜WDAT3. The second system 21 is coupled to the second address receiving ports of the address multiplexers ADD4~ADD5. The second system 21 is coupled to the second read data receiving ports of the read data multiplexers RDAT4~RDAT5. The second system 21 is coupled to the second write data receiving ports of the write data multiplexers WDAT4˜WDAT5. The third system 22 is coupled to the third address receiving ports of the address multiplexers ADD6~ADD7. The third system 23 is coupled to the third read data receiving port of the read data multiplexers RDAT6~RDAT7. The third system 23 is coupled to the third write data receiving ports of the write data multiplexers WDAT6~WDAT7.

In the above embodiment, the second and third address receiving ports of the above address multiplexers ADD0 ~ ADD3 are not coupled to any device (empty connection). The first and second bits of the above address multiplexers ADD4~ADD5 None of the third address receiving ports are connected to any devices (empty connections). The first and second address receiving ports of the above-mentioned address multiplexers ADD6~ADD7 are not coupled to any device (empty connection). The second and third read data receiving ports of the above-mentioned read data multiplexers RDAT0 ~ RDAT3 are not coupled to any device (empty connection). The first and third read data receiving ports of the above-mentioned read data multiplexers RDAT4~RDAT5 are not coupled to any device (empty connection). The first and second read data receiving ports of the above-mentioned read data multiplexers RDAT6~RDAT7 are not coupled to any device (empty connection). The second and third write data receiving ports of the above-mentioned write data multiplexers WDAT0 ~ RDAT3 are not coupled to any device (empty connection). The first and third write data receiving ports of the above-mentioned write data multiplexers WDAT4~WDAT5 are not coupled to any device (empty connection). The first and second write data receiving ports of the above-mentioned write data multiplexers WDAT6~WDAT7 are not coupled to any device (empty connection).

It can be seen from the embodiments of FIG. 6, FIG. 7A and FIG. 7B that when any system 20, 21, 22 wants to perform memory access, since the corresponding system is only coupled to the assigned memory block, Address multiplexers ADD0~ADD7, read data multiplexers RDAT0~RDAT7, and write data multiplexers WDAT0~RDAT7, so the interface selection control circuit 302 can use the selection signals SEL0~SEL7 to control all address multiplexers. ADD0~ADD7, read data multiplexers RDAT0~RDAT7, write data multiplexers WDAT0~RDAT7. For example, when the system 20 sends a read request, the interface selection control circuit 302 can use the selection signals SEL0 ~ SEL7 to switch all the address multiplexers ADD0 ~ ADD7 to the first address receiving port, and use the selection signal SEL0 ~SEL7 switches all read data multiplexers RDAT0~RDAT7 to the first read data receiving port. Since the first address receiving ports of the address multiplexers ADD4~ADD7 and the first read data receiving ports of the read data multiplexers RDAT0~RDAT7 are open, the first system 20 will only send the address to Memory blocks R0~R3, and memory blocks R0~R3 will only send the corresponding read data through the read data multiplexers RDAT0~RDAT3 Give 20 to the first system. In this way, the control logic complexity of the memory sharing device can be simplified. It can also reduce the wiring between the system and the shareable memory, and can also reduce more signal crosstalk interference (Crosstalk).

FIG. 8 is a circuit block diagram of a shareable memory according to a preferred embodiment of the present invention. Please refer to Figure 6 and Figure 8. In this embodiment, the difference from Figure 6 is that the interface selection control circuit 302 only needs to use the selection signal SEL0 to allow the first system 20 to access the memories R0~R3. Similarly , the interface selection control circuit 302 only needs to use the selection signal SEL1 to allow the second system 21 to access the memories R4~R5. Therefore, the use of wiring can be reduced and the complexity of the printed circuit board or circuit layout can be reduced compared with the embodiment of FIG. 6 . Since the embodiment of FIG. 8 is similar to the embodiment of FIG. 6 , and the control method has been described in detail in FIGS. 6 , 7A and 7B and the corresponding embodiments, they will not be described again here.

According to the above embodiments, the present invention can be summarized as a memory sharing method. FIG. 9 is a flow chart of a memory sharing method according to a preferred embodiment of the present invention. Please refer to Figure 9. This memory sharing method includes:

Step S901: Start.

Step S902: Provide multiple memory blocks. Such as the memory blocks R0~R4 or R0~R8 in the above embodiment.

Step S903: Pre-allocate each memory block to multiple systems according to requirements. For example, taking the embodiment of FIG. 4 , the memory blocks R0 ~ R1 are allocated to the first system 20 , the memory block R2 is allocated to the second system 21 , and the memory block R3 is allocated to the third system 22 . In addition, taking the embodiment of FIG. 6 as an example, the memory blocks R0~R3 are allocated to the first system 20, the memory blocks R4~R5 are allocated to the second system 21, and the memory blocks R6~R7 are allocated to the third system 20. System 22. The following description takes the embodiment of FIG. 6 as an example.

Step S904: Determine the system for access requirements. In this method embodiment, three systems are also taken as examples. When the access request is from the first system 20, step S905 is performed. When the access request is from the second system 21, step S907 is performed. When the access request is from the third system 22, step S909 is performed.

Step S905: Enable memory blocks R0~R3. Taking the embodiment of FIG. 6 as an example, when an access request from the first system 20 is received, the memory blocks R0 ~ R3 are enabled. The method of enabling the memory blocks may be to use a chip selection signal (Chip Selection Signal). ).

Step S906: Electrically connect the access signal output by the first system 20 to the enabled memory blocks R0~R3. For example, the operation of the above-mentioned selection circuit 301, the above-mentioned address multiplexers ADD0~ADD3, the above-mentioned read data multiplexers RDAT0~RDAT3, and the above-mentioned write data multiplexers WDAT0~WDAT3.

Step S907: Enable memory blocks R4~R5. Taking the embodiment of FIG. 6 as an example, when an access request from the second system 21 is received, the memory blocks R4 to R5 are enabled. The method of enabling the memory blocks may be to use a chip selection signal (Chip Selection Signal). ).

Step S908: Electrically connect the access signal output by the second system 21 to the enabled memory blocks R4~R5. For example, the operation of the above-mentioned selection circuit 301, the above-mentioned address multiplexers ADD4~ADD5, the above-mentioned read data multiplexers RDAT4~RDAT5, and the above-mentioned write data multiplexers WDAT4~WDAT5.

Step S909: Enable memory block R6 or R7. Taking the embodiment of FIG. 6 as an example, when an access request from the third system 22 is received, the memory block R6 or R7 is enabled according to the accessed address. Since the memory access width of the third system 22 is small, the memory block R6 or R7 can be selectively enabled according to the accessed address. The memory block can be enabled by using a Chip Selection Signal.

Step S910: Electrically connect the access signal output by the third system 22 to the enabled memory block memory block R6 or R7. For example, the operations of the above-mentioned selection circuit 301, the above-mentioned address multiplexers ADD6~ADD7, the above-mentioned read data multiplexers RDAT6~RDAT7, and the above-mentioned write data multiplexers WDAT6~WDAT7.

In the above embodiments, the method of electrical connection may refer to the embodiments in FIGS. 4 to 8 , and will not be described in detail here.

Based on the above, the spirit of the embodiments of the present invention is to use the selection circuit to couple each system, and to use the interface selection control circuit to control the selection circuit and enable the corresponding internal memory block. Through the selection circuit, the desired memory is The access command of the system fetching the memory is passed to the enabled memory block, thereby allowing each system to access different blocks in the same shareable memory module. Since the number of enabled memory blocks can be adjusted according to different systems, it can be compatible with different memory address widths. In addition, since different memory blocks are enabled according to different system accesses, data errors or data overwriting problems will not occur. Furthermore, since the selection circuit is used for memory sharing, the internal wiring of the memory module does not need to be changed at all. Only the wiring between the selection circuit and the system needs to be changed. The circuit complexity can be reduced and the cost of use is also reduced.

It is to be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or alterations thereof will be suggested to those skilled in the art and will be included within the spirit and scope of the application and the appended claims. within the range.

20:First system

21:Second system

22:Third system

23: Shareable memory

24:Peripheral devices

R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15: memory block

Claims (12)

A memory sharing device is used to share multiple memory blocks to multiple systems respectively. The memory sharing device includes: a selection circuit including a plurality of receiving ports and an output port, wherein each of the receiving ports The port is coupled to each of the corresponding systems, wherein the output port is coupled to each of the memory blocks; and an interface selection control circuit is coupled to the selection circuit, according to at least one of the systems in each of the systems. The specific system output access requirement is to electrically connect the receiving ports of the selection circuit corresponding to the specific system to the output port of the selection circuit, and enable the memory blocks allocated to A block of memory for this particular system. According to the memory sharing device described in claim 1, enabling the memory blocks allocated to the specific system among the memory blocks further includes: the interface selection control circuit outputs a chip selection signal to enable allocation to the System-specific memory block. The memory sharing device according to claim 1, wherein the selection circuit further includes: a plurality of address multiplexers, each of the address multiplexers includes a plurality of address receiving ports and an address output port. , the address receiving ports of each of the address multiplexers respectively receive the address signals output by the systems, and the address output ports of each of the address multiplexers are respectively coupled to each of the an address receiving port of the memory block; and a plurality of read data multiplexers, each of which includes a plurality of read data receiving ports and a read data input port, each of which The read data receiving ports of the read data multiplexer are respectively Coupling the systems, the read data input port of each of the read data multiplexers is respectively coupled to the read data output port of each of the memory blocks; wherein, when the interface selection control circuit is configured according to a specific According to the read request of the system output, the interface selection control circuit controls the address receiving port of the memory block corresponding to the specific system among the above multiple address multiplexers to be electrically connected to the memory block corresponding to the specific system. The address output port of the address multiplexer. The interface selection control circuit controls the read data receiving port of the multiple read data multiplexers corresponding to the memory block of the specific system to be electrically connected to the corresponding Read data input port for multiple read data multiplexers of a specific system's memory block. The memory sharing device according to claim 3, wherein the selection circuit further includes: a plurality of chip selection multiplexers, each of the chip selection multiplexers includes a plurality of chip selection signal receiving ports and A chip selection signal output port, the chip selection signal receiving ports of each of the chip selection multiplexers respectively receive the chip selection signals corresponding to the systems, and the chip selection signal output port of each of the chip selection multiplexers The chip selection signal receiving end is respectively coupled to each of the memory blocks, wherein when the interface selection control circuit controls each of the chip selection multiplexers according to the reading request of the specific system output In the process, the address receiving port corresponding to the specific system is electrically connected to the address output port of each of the chip select multiplexers, so as to correspond to the memory block of the specific system. The memory sharing device according to claim 1, wherein the selection circuit further includes: Multiple address multiplexers, each of the address multiplexers includes multiple address receiving ports and an address output port, and the address receiving ports of each of the address multiplexers receive the The address signals output by these systems, the address output port of each of the address multiplexers is respectively coupled to the address receiving port of each of the memory blocks; and a plurality of write data multiplexers, Each of the write data multiplexers includes a plurality of write data receiving ports and a write data output port. The write data receiving ports of each of the write data multiplexers are respectively coupled to the systems. , the write data output port of each of the write data multiplexers is respectively coupled to the write data input port of each of the memory blocks; wherein, when the interface selection control circuit outputs a write data according to a specific system It is required that the interface selection control circuit controls the address receiving port of the memory block corresponding to the specific system among the above multiple address multiplexers to be electrically connected to the address multiplexer of the memory block corresponding to the specific system. The interface selection control circuit controls the write data receiving port of the memory block corresponding to the specific system in the multiple write data multiplexers to be electrically connected to the memory corresponding to the specific system. The write output port for the block's multiple write multiplexers. The memory sharing device according to claim 5, wherein the selection circuit further includes: a plurality of chip selection multiplexers, each of the chip selection multiplexers includes a plurality of chip selection signal receiving ports and A chip selection signal output port, the chip selection signal receiving ports of each of the chip selection multiplexers respectively receive the chip selection signals corresponding to the systems, and the chip selection signal output port of each of the chip selection multiplexers The chip selection signal receiving ends respectively coupled to each of the memory blocks, Wherein, when the interface selection control circuit outputs a write request according to a specific system, the interface selection control circuit controls each of the chip selection multiplexers to electrically connect the address receiving port corresponding to the specific system to each of the chip selection multiplexers. Some chips select the multiplexer's address output port so that it corresponds to the memory block of that particular system. The memory sharing device according to claim 1, wherein a total of N systems share the memory blocks, and the selection circuit further includes: a plurality of address multiplexers, each of the address multiplexers Including N address receiving ports and an address output port, the address output ports of each of the address multiplexers are respectively coupled to the address receiving ports of each of the memory blocks, wherein the I-th The system is coupled to the I-th address receiving port among the address multiplexers coupled to the memory blocks of the I-th system to respectively receive the address signals output by the I-th system. Among them, the remaining address receiving ports of the address multiplexers coupled to the memory blocks corresponding to the I-th system are air-connected; and a plurality of read data multiplexers, each of the read data multiplexers The data multiplexer includes a plurality of read data receiving ports and a read data input port. The read data input ports of each of the read data multiplexers are respectively coupled to the reading of each of the memory blocks. Data output ports, wherein the I-th read data receiving ports of the read data multiplexers coupled to the memory blocks of the I-th system are respectively coupled to the I-th system, wherein the corresponding The remaining read data receiving ports of the read data multiplexers coupled to the memory blocks of the first system are air-connected; wherein, when the interface selection control circuit outputs a read request based on a specific system, The interface selection control circuit controls the address receiving port corresponding to the memory block of the specific system among the plurality of address multiplexers to be electrically connected to the address multiplexer corresponding to the memory block of the specific system. Address output port, this interface selects the control circuit to control the memory area corresponding to the specific system among the multiple read data multiplexers. The read data receiving port of the block is electrically connected to the read data input ports of multiple read data multiplexers corresponding to the memory block of the specific system, where N and I are natural numbers, and I is less than or equal to N. The memory sharing device according to claim 1, wherein the selection circuit further includes: a plurality of address multiplexers, each of the address multiplexers includes a plurality of address receiving ports and an address output port. , the address output port of each of the address multiplexers is respectively coupled to the address receiving port of each of the memory blocks, wherein the I-th system is coupled to the memories corresponding to the I-th system Among the address multiplexers coupled to the block, the I-th address receiving port is used to receive the address signal output by the I-th system respectively, wherein the memory areas corresponding to the I-th system The remaining address receive ports of the address multiplexers to which the block is coupled are air-connected; and a plurality of write data multiplexers, each of the write data multiplexers includes a plurality of write data receive ports and A write data output port, the write data output port of each of the write data multiplexers is respectively coupled to the write data input port of each of the memory blocks, wherein the write data input port corresponding to the I-th system The 1st write data receiving ports of the write data multiplexers coupled to the memory blocks are respectively coupled to the 1st system, wherein the memory blocks corresponding to the 1st system are coupled to The remaining write data receiving ports of the write data multiplexers connected are air-connected; among them, when the interface selection control circuit outputs a write request according to a specific system, the interface selection control circuit controls the above-mentioned multiple address multiplexers. In the processor, the address receiving port corresponding to the memory block of the specific system is electrically connected to the address output port of the address multiplexer corresponding to the memory block of the specific system. The interface selection control circuit controls the above multiplexer. write to the data multiplexer, corresponding to the memory area of that particular system The write data receiving port of the block is electrically connected to the write data output ports of multiple write data multiplexers corresponding to the memory block of the specific system, where N and I are natural numbers, and I is less than or equal to N. The memory sharing device according to claim 1, wherein the interface selection control circuit further includes: a lookup table for storing the corresponding relationship between each system and the memory blocks, so as to determine the access according to the specific system. Required to enable the corresponding memory block. A shareable memory used to share memory to multiple systems. The shareable memory includes: multiple memory blocks (Ranks); and memory sharing as described in one of requests 1 to 9 device. An electronic device, including: multiple systems; a shareable memory including: multiple memory blocks (Rank); and the memory sharing device as described in one of claims 1 to 9; and at least one peripheral The device is electrically connected to one of the plurality of systems through a bus. A memory sharing method includes: providing multiple memory blocks; pre-allocating each of the memory blocks to multiple systems according to requirements; when in each of the systems, at least one specific system outputs a memory Requirements include: Enable the memory block allocated to the specific system among the memory blocks; and electrically connect the access signal output by the specific system to the enabled memory block.