TWI823468B - Clock pulse generating device - Google Patents
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- H—ELECTRICITY
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- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15006—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two programmable outputs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
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Abstract
本發明提供一種裝置，其具備：第1輸出部，響應於複數個訊號的至少一個上升的情形而輸出第1脈衝；第2輸出部，響應於複數個訊號的至少一個下降的情形而輸出第2脈衝；檢測部，在每次成為脈衝的非檢測狀態時，檢測第1脈衝及第2脈衝中被最先輸出的先行脈衝；及選擇部，將藉由檢測部檢測到的先行脈衝的邊緣，選擇來作為時脈中所含的時脈脈衝的邊緣。 The present invention provides a device, which includes: a first output unit that outputs a first pulse in response to at least one rising condition of a plurality of signals; and a second output unit that outputs a first pulse in response to at least one falling condition of the plurality of signals. 2 pulses; a detection unit that detects the preceding pulse that is output first among the first pulse and the second pulse each time the pulse is in a non-detection state; and a selection unit that converts the edge of the preceding pulse detected by the detection unit , selected as the edge of the clock pulse contained in the clock.
Description
本發明關於裝置。 The present invention relates to devices.
在專利文獻1~3中記載有以下內容：「延遲電路101一旦接收到輸入時脈訊號CKA，便使該訊號延遲固定時間td1，製作出延遲時脈訊號CKD並加以輸出。OR(或)邏輯閘102一旦接收到延遲時脈訊號CKD與輸入時脈訊號CKA，便將輸入時脈訊號CKA的H位準的寬度擴展固定時間td1，製作出震盪控制訊號CT1並加以輸出」。 Patent Documents 1 to 3 describe the following: "Once the delay circuit 101 receives the input clock signal CKA, it delays the signal by a fixed time td1, creates a delayed clock signal CKD, and outputs it. OR logic Once the gate 102 receives the delayed clock signal CKD and the input clock signal CKA, it extends the width of the H level of the input clock signal CKA by a fixed time td1, generates and outputs the oscillation control signal CT1."
[先前技術文獻] [Prior technical literature]
(專利文獻) (patent document)
專利文獻1：日本特開2003-051737號公報。 Patent Document 1: Japanese Patent Application Publication No. 2003-051737.
專利文獻2：日本特開2017-112427號公報。 Patent Document 2: Japanese Patent Application Publication No. 2017-112427.
專利文獻3：國際公開第2008/032701號。 Patent Document 3: International Publication No. 2008/032701.
本發明的第1態樣中提供一種裝置。裝置可具備：第1輸出部，響應於複數個訊號的至少一個上升的情形而輸出第1脈衝。裝置可具備：第2輸出部，響應於複數個訊號的至少一個下降的情形而輸出第2脈衝。裝置可具備：檢測部，在每次成為脈衝的非檢測狀態時，檢測第1脈衝及第2脈衝中被最先輸出的先行脈衝。裝置可具備：選擇部，將藉由檢測部檢測到的先行脈衝的邊緣，選擇來作為時脈中所含的時脈脈衝的邊緣。A first aspect of the present invention provides a device. The device may include a first output unit that outputs a first pulse in response to at least one rising condition of the plurality of signals. The device may include a second output unit that outputs a second pulse in response to at least one of the plurality of signals falling. The device may include a detection unit that detects a preceding pulse output first among the first pulse and the second pulse each time the pulse is in a non-detection state. The device may include a selection unit that selects an edge of a preceding pulse detected by the detection unit as an edge of a clock pulse included in the clock.
第1輸出部可具有：複數個第1脈衝產生器，響應於複數個訊號中對應的任一個訊號上升的情形，分別產生第1基準寬度的基準脈衝。第1輸出部可具有：第1OR邏輯閘，將藉由複數個第1脈衝產生器的各者產生的基準脈衝的邏輯和作為第1脈衝來輸出。第2輸出部可具有：複數個第2脈衝產生器，響應於複數個訊號中對應的任一個訊號下降的情形，分別產生第1基準寬度的基準脈衝。第2輸出部可具有：第2OR邏輯閘，將藉由複數個第2脈衝產生器的各者產生的基準脈衝的邏輯和作為第2脈衝來輸出。The first output unit may include a plurality of first pulse generators, each generating a reference pulse of a first reference width in response to a rise of a corresponding signal among the plurality of signals. The first output unit may include a first OR logic gate and output the logical sum of the reference pulses generated by each of the plurality of first pulse generators as the first pulse. The second output unit may include a plurality of second pulse generators that generate reference pulses of the first reference width respectively in response to a decrease in any one of the plurality of signals. The second output unit may include a second OR logic gate and output the logical sum of the reference pulses generated by each of the plurality of second pulse generators as the second pulse.
第1基準寬度，在時脈脈衝的間隔中複數個訊號的上升及下降是逐次產生一個的情況下，可為第1脈衝與第2脈衝有至少一部分重疊的脈衝寬度。The first reference width may be a pulse width at least partially overlapping the first pulse and the second pulse when the rise and fall of a plurality of signals are generated one after another in the interval of the clock pulse.
第1基準寬度，可為比可能在時脈脈衝的間隔中產生的複數個訊號的上升與下降的間隔最大值更大的脈衝寬度。The first reference width may be a pulse width larger than the maximum value of the rising and falling intervals of a plurality of signals that may be generated in the interval of the clock pulse.
第1基準寬度，可為比時脈脈衝的基準間隔的0.4倍更大的脈衝寬度。The first reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulses.
第1基準寬度，在時脈脈衝的間隔中有複數個訊號中的2個以上的訊號上升的情況下，可為響應該2個以上的訊號的各者而產生的2個以上的基準脈衝有一部分重疊而形成1個第1脈衝的脈衝寬度，且在時脈脈衝的間隔中有複數個訊號中的2個以上的訊號下降的情況下，為響應該2個以上的訊號的各者而產生的2個以上的基準脈衝有一部分重疊而形成1個第2脈衝的脈衝寬度。The first reference width is: when two or more signals among a plurality of signals rise during the interval between clock pulses, the two or more reference pulses generated in response to each of the two or more signals are: The pulse width partially overlaps to form one first pulse, and when two or more of the plurality of signals fall during the interval between the clock pulses, it is generated in response to each of the two or more signals. Two or more reference pulses partially overlap to form a pulse width of a second pulse.
檢測部可具有：脈衝檢測部，分別檢測自第1輸出部及第2輸出部輸出的第1脈衝及第2脈衝。檢測部可具有：無效化部，在時脈脈衝的各間隔中第1脈衝與第2脈衝有一部分重疊而輸出的情況下，將針對較晚輸出的脈衝的脈衝檢測部的檢測無效化。The detection unit may include a pulse detection unit that detects the first pulse and the second pulse output from the first output unit and the second output unit, respectively. The detection unit may include an invalidation unit that invalidates the detection of the pulse that is output later by the pulse detection unit when the first pulse and the second pulse are output partially overlapping each other in each interval of the clock pulse.
檢測部，可藉由檢測第3基準寬度的第3脈衝與第3基準寬度的第4脈衝中最先產生的脈衝來檢測先行脈衝，該第3脈衝是響應於輸出第1脈衝而產生，且該第4脈衝是響應於輸出第2脈衝而產生。The detection unit can detect the preceding pulse by detecting the first pulse among the third pulse of the third reference width and the fourth pulse of the third reference width, the third pulse being generated in response to the output of the first pulse, and The fourth pulse is generated in response to the output of the second pulse.
第3基準寬度，在時脈脈衝的間隔中複數個訊號的上升及下降是逐次產生一個的情況下，可為第3脈衝與第4脈衝有至少一部分重疊的脈衝寬度。The third reference width may be a pulse width at least partially overlapping the third pulse and the fourth pulse when the rise and fall of a plurality of signals are generated one after another in the interval of the clock pulse.
第3基準寬度，可為比可能在時脈脈衝的間隔中產生的複數個訊號的上升與下降的間隔最大值更大的脈衝寬度。The third reference width may be a pulse width larger than the maximum value of the rising and falling intervals of a plurality of signals that may be generated in the interval of the clock pulse.
第3基準寬度，可為比時脈脈衝的基準間隔的0.4倍更大的脈衝寬度。 The third reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulses.
檢測部可具有：脈衝檢測部，分別檢測第3脈衝及第4脈衝。檢測部可具有：無效化部，在時脈脈衝的各間隔中第3脈衝與第4脈衝有一部分重疊而輸出的情況下，將針對較晚輸出的脈衝的脈衝檢測部的檢測無效化。 The detection unit may include a pulse detection unit that detects the third pulse and the fourth pulse respectively. The detection unit may include an invalidation unit that invalidates detection by the pulse detection unit of the pulse that is output later when the third pulse and the fourth pulse are outputted partially overlapping each other in each interval of the clock pulse.
複數個訊號，可為自基於行動産業處理器介面(MIPI)的通道實體層(C-PHY)利用3條線路來傳送的訊號所導出的3個差動訊號。 The plurality of signals may be three differential signals derived from signals transmitted using three lines based on the Mobile Industrial Processor Interface (MIPI) Channel Physical Layer (C-PHY).
此外，上述發明內容並未列舉出本發明的全部必要特徵。又，該等特徵群的子組合亦可成為發明。 In addition, the above summary of the invention does not list all necessary features of the invention. In addition, subcombinations of these feature groups can also become inventions.
以下，透過發明的實施型態來說明本發明，但以下的實施型態並不對申請專利範圍的發明加以限定。又，發明的解決手段中並不一定需要有實施型態中所說明的特徵的全部組合。 The present invention will be described below through embodiments of the invention. However, the following embodiments do not limit the invention within the scope of the patent application. In addition, the solution of the invention does not necessarily require all combinations of the features described in the embodiments.
[1.裝置1的構成] [1.Configuration of device 1]
第1圖表示本實施型態之裝置1。 Figure 1 shows the device 1 of this embodiment.
裝置1，自複數訊號產生時脈脈衝clk。例如，裝置1可自3個訊號產生時脈脈衝clk，在此之外亦可自該3個訊號讀取資料(作為一例為影像資料)。裝置1具備：Rise(上升)側輸出部2、Fall(下降)側輸出部3、檢測部4、選擇部5、資料讀取部6。該等構成可藉由邏輯電路來構成。此外，本實施型態中，作為一例，裝置1是以行動産業處理器介面(MIPI)的通道實體層(C-PHY)為基準，因此在各構成的說明前先針對C-PHY加以說明。 Device 1 generates a clock pulse clk from a complex signal. For example, the device 1 can generate the clock pulse clk from three signals, and can also read data (for example, image data) from the three signals. The device 1 includes a Rise (rising) side output unit 2 , a Fall (falling) side output unit 3 , a detection unit 4 , a selection unit 5 , and a data reading unit 6 . These structures can be formed by logic circuits. In addition, in this embodiment, as an example, the device 1 is based on the channel physical layer (C-PHY) of the Mobile Industrial Processor Interface (MIPI). Therefore, the C-PHY will be described before the description of each structure.
[1.1. C-PHY] [1.1.C-PHY]
C-PHY中，在經由3條線路來傳送的訊號A、B、C中，不僅有應該要進行通訊的資料，還嵌入有時脈訊號。訊號A、B、C的各者自High(高)、Middle(中)、Low(低)的3個值中設成不同的值，且3個訊號A、B、C整體可設為以下表1中的「+x」、「-x」、「+y」、「-y」、「+z」、「-z」的6個狀態。 In C-PHY, signals A, B, and C transmitted through three lines contain not only the data that should be communicated, but also embedded clock signals. Each of the signals A, B, and C is set to a different value from the three values of High (high), Middle (middle), and Low (low), and the three signals A, B, and C as a whole can be set as the following table The 6 states of "+x", "-x", "+y", "-y", "+z", and "-z" in 1.
訊號A、B、C整體的狀態，在每個UI(Unit Interval，單位間隔)中遷移至其他的狀態。藉此，訊號A、B、C整體能夠在各UI中傳送5值的資料(亦稱為符號)。UI是為了傳送1個符號而在訊號A、B、C的傳送側決定的單位時間，例如可具有12.5～1000ns的長度。此外，由於被傳送的訊號中會產生抖動，所以在訊號A、B、C的接收側，基於接收到的訊號A、B、C的訊號位準變化而產生時脈脈衝clk，並基於該時脈脈衝clk的時序自訊號A、B、C取得資料。The overall state of signals A, B, and C is transferred to other states in each UI (Unit Interval). In this way, the signals A, B, and C as a whole can transmit 5-valued data (also called symbols) in each UI. UI is a unit time determined on the transmitting side of signals A, B, and C in order to transmit one symbol, and may have a length of 12.5 to 1000 ns, for example. In addition, since jitter will occur in the transmitted signal, on the receiving side of the signals A, B, and C, a clock pulse clk is generated based on the signal level changes of the received signals A, B, and C, and based on this time The timing of pulse pulse clk obtains data from signals A, B, and C.
此處，如上述，訊號A、B、C整體可設為6個狀態，且根據狀態遷移而遷移至與原本的狀態不同的5個狀態的其中一個，因此結果而言可能產生30(=6x5)種狀態遷移。然而，30種狀態遷移中包含有等價的狀態遷移，30種狀態遷移使用與訊號A、B、C的差分對應的差動訊號Diff(亦稱為訊號Diff (AB)、Diff (BC)、Diff (CA))統整為以下3種狀態遷移。 Here, as mentioned above, the signals A, B, and C can be set to 6 states as a whole, and according to the state transition, they will migrate to one of the 5 states different from the original state, so as a result, 30 (=6x5 ) state migration. However, the 30 state transitions include equivalent state transitions. The 30 state transitions use the differential signal Diff (also called signal Diff (AB) , Diff (BC) , Diff (CA) ) is organized into the following three state transitions.
第1種狀態遷移是訊號Diff (AB)、Diff (BC)、Diff (CA)全部跨過電壓0(亦稱為過零，zero cross)的情況。該狀態遷移，例如是自狀態「+x」到狀態「-x」的遷移。在此情況下，訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個過零而自負值上升至正值，且殘餘的1個過零而自正值下降至負值，或者訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個過零而自正值下降至負值，且殘餘的1個過零而自負值上升至正值。 The first state transition is when the signals Diff (AB) , Diff (BC) , and Diff (CA) all cross the voltage 0 (also called zero cross). This state transition is, for example, a transition from state "+x" to state "-x". In this case, two of the signals Diff (AB) , Diff (BC) , and Diff (CA) cross zero and the positive value rises to a positive value, and the remaining one crosses zero and drops from a positive value to a negative value. Or two of the signals Diff (AB) , Diff (BC) , and Diff (CA) cross zero and drop from the positive value to the negative value, and the remaining one crosses zero and the negative value rises to the positive value.
第2種狀態遷移是訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個跨過電壓0的情況。該狀態遷移，例如是自狀態「+x」到狀態「+y」的遷移。在此情況下，訊號Diff (AB)、Diff (BC)、Diff (CA)中的1個過零而自負值上升至正值，且另外的1個過零而自正值下降至負值。 The second state transition is when two of the signals Diff (AB) , Diff (BC) , and Diff (CA) cross voltage 0. This state transition is, for example, a transition from state "+x" to state "+y". In this case, one of the signals Diff (AB) , Diff (BC) , and Diff (CA) crosses zero and rises from a positive value to a positive value, and the other one crosses zero and drops from a positive value to a negative value.
第3種狀態遷移是訊號Diff (AB)、Diff (BC)、Diff (CA)中的1個跨過電壓0的情況。該狀態遷移，例如是自狀態「+x」到狀態「-y」的遷移。在此情況下，訊號Diff (AB)、Diff (BC)、Diff (CA)中的1個過零而自負值上升至正值或是自正值下降至負值。 The third state transition is when one of the signals Diff (AB) , Diff (BC) , and Diff (CA) crosses the voltage 0. This state transition is, for example, a transition from state "+x" to state "-y". In this case, one of the signals Diff (AB) , Diff (BC) , and Diff (CA) crosses zero and the self-esteem value rises to a positive value or drops from a positive value to a negative value.
此外，在產生2個以上過零的第1、第2種狀態遷移中，在UI中過零可能以前後錯開的方式產生。例如，在產生3個過零的第1種狀態遷移中，理想上是全部的過零同時發生，但可能因抖動的影響等而以0.2UI以內的間隔來產生過零。又，在產生2個過零的第2種狀態遷移中，可能以0.4UI以內的間隔來產生過零。In addition, in the first and second state transitions that generate more than two zero-crossings, the zero-crossings may occur in a staggered manner in the UI. For example, in the first state transition that generates three zero-crossings, ideally all the zero-crossings occur at the same time, but due to the influence of jitter, etc., the zero-crossings may occur at intervals within 0.2UI. Furthermore, in the second state transition in which two zero-crossings occur, zero-crossings may occur at intervals within 0.4UI.
在該等情況下，UI內的上升的過零不會連續產生，下降的過零也不會連續產生。例如，當UI內的上升的過零先產生時，在相同UI中接下來必定產生下降的過零。同樣的，當UI內的下降的過零先產生時，在相同UI中接下來必定產生上升的過零。在上升的過零後，在不產生下降的過零的情況下無法再產生上升的過零。又，在下降的過零後，在不產生上升的過零的情況下無法再產生下降的過零。In such cases, rising zero-crossings within the UI will not occur continuously, nor will falling zero-crossings occur continuously. For example, when a rising zero-crossing occurs first in a UI, a falling zero-crossing must occur next in the same UI. Similarly, when a descending zero-crossing occurs first in a UI, a rising zero-crossing must occur next in the same UI. After a rising zero crossing, no further rising zero crossings can be made without producing a falling zero crossing. In addition, after a falling zero crossing, a falling zero crossing cannot occur without causing a rising zero crossing.
又，在連續的UI內產生第2狀態遷移時，在該等UI的各者中，上升的過零與下降的過零的順序相同。亦即，在該等UI的各者中，是在上升的過零後產生下降的過零，或是在下降的過零後產生上升的過零。Furthermore, when the second state transition occurs in consecutive UIs, the order of rising zero crossings and falling zero crossings is the same in each of the UIs. That is, in each of these UIs, either a rising zero crossing is followed by a falling zero crossing, or a falling zero crossing is followed by a rising zero crossing.
又，連續的UI中，在前一個UI中產生第2狀態遷移，且在後一個UI中產生第1狀態遷移時，上升或下降的過零中，在前一個UI中先產生的過零會在後一個UI中產生。亦即，當在前一個UI中產生上升的過零後再產生下降的過零時，會在後一個UI中產生上升的過零。Also, in consecutive UIs, when the second state transition occurs in the previous UI, and the first state transition occurs in the subsequent UI, among the rising or falling zero crossings, the zero crossing that occurred first in the previous UI will Produced in the latter UI. That is, when a rising zero crossing occurs in the previous UI and then a falling zero crossing occurs, a rising zero crossing occurs in the latter UI.
同樣的，連續的UI中，在前一個UI中產生第1狀態遷移，且在後一個UI中產生第2狀態遷移時，上升或下降的過零中，在前一個UI中產生的過零會在後一個UI中先產生。亦即，當在前一個UI中產生上升的過零時，會在後一個UI中先產生上升的過零後再產生下降的過零。Similarly, in consecutive UIs, when the first state transition occurs in the previous UI, and the second state transition occurs in the later UI, among the rising or falling zero-crossings, the zero-crossing generated in the previous UI will It is generated first in the latter UI. That is, when a rising zero crossing occurs in the previous UI, a rising zero crossing occurs first and then a falling zero crossing occurs in the subsequent UI.
在如以上進行資料傳送的C-PHY中，能夠在訊號Diff (AB)、Diff (BC)、Diff (CA)的過零時序中產生時脈脈衝clk。當在UI內產生複數個過零時，可在最前面的過零產生時脈脈衝clk。 In the C-PHY that performs data transmission as above, the clock pulse clk can be generated in the zero-crossing timing of the signals Diff (AB) , Diff (BC) , and Diff (CA) . When multiple zero-crossings occur within the UI, the clock pulse clk may be generated at the first zero-crossing.
本實施型態之裝置1，可取得自訊號A、B、C導出的3個Diff (AB)、Diff (BC)、Diff (CA)，該訊號A、B、C是以C-PHY作為基準而利用3條線路傳送的。例如，裝置1可自接收裝置取得訊號Diff (AB)、Diff (BC)、Diff (CA)，該接收裝置接收訊號A、B、C並產生訊號Diff (AB)、Diff (BC)、Diff (CA)。 The device 1 of this implementation type can obtain three Diff (AB) , Diff (BC) , and Diff (CA) derived from signals A, B, and C. The signals A, B, and C are based on C-PHY. And it is transmitted using 3 lines. For example, device 1 can obtain signals Diff (AB) , Diff (BC) , Diff (CA) from a receiving device that receives signals A, B, C and generates signals Diff (AB) , Diff (BC) , Diff ( CA) .
[1.2. Rise側輸出部2] Rise側輸出部2是第1輸出部的一例，響應於複數個訊號Diff (AB)、Diff (BC)、Diff (CA)的至少一者上升的情形而輸出Rise側脈衝。訊號Diff (AB)、Diff (BC)、Diff (CA)上升，可以是指訊號Diff (AB)、Diff (BC)、Diff (CA)過零而自負值上升至正值。Rise側輸出部2具有3個脈衝產生器20(亦稱為脈衝產生器20 (AB)、20 (BC)、20 (CA))與OR邏輯閘21。此外，脈衝產生器20 (AB)、20 (BC)、20 (CA)等記載中的附加的括弧內的記號，表示訊號Diff (AB)、Diff (BC)、Diff (CA)中的對應訊號。 [1.2. Rise-side output unit 2] The Rise-side output unit 2 is an example of the first output unit and outputs in response to at least one of a plurality of signals Diff (AB) , Diff (BC) , and Diff (CA) rising. Rise side pulse. The signal Diff (AB) , Diff (BC) , and Diff (CA) rise, which can mean that the signal Diff (AB) , Diff (BC) , and Diff (CA) cross zero and the self-esteem value rises to a positive value. The rise-side output unit 2 has three pulse generators 20 (also referred to as pulse generators 20 (AB) , 20 (BC) , and 20 (CA) ) and an OR logic gate 21. In addition, the additional symbols in parentheses in the description of the pulse generators 20 (AB) , 20 (BC) , and 20 (CA) indicate the corresponding signals in the signals Diff (AB) , Diff (BC) , and Diff (CA). .
3個脈衝產生器20 (AB)、20 (BC)、20 (CA)，響應於複數個訊號Diff (AB)、Diff (BC)、Diff (CA)中對應的任一個訊號Diff上升的情形，分別產生基準寬度的基準脈衝P rise(亦稱為基準脈衝P rise(AB)、P rise(BC)、P rise(CA))。基準脈衝P rise的基準寬度是第1基準寬度的一例，詳細後述。各脈衝產生器20，可將已產生的基準脈衝P rise供給至OR邏輯閘21。 The three pulse generators 20 (AB) , 20 (BC) , and 20 (CA) respond to the rise of any corresponding signal Diff among the plurality of signals Diff (AB) , Diff (BC) , and Diff (CA) , Reference pulses P rise (also called reference pulses P rise(AB) , P rise(BC) , P rise(CA) ) with reference widths are respectively generated. The reference width of the reference pulse P rise is an example of the first reference width and will be described in detail later. Each pulse generator 20 can supply the generated reference pulse P rise to the OR logic gate 21 .
OR邏輯閘21，連接至3個脈衝產生器20的各者。OR邏輯閘21是第1OR邏輯閘的一例，將由3個脈衝產生器20的各者產生的基準脈衝P rise的邏輯和作為Rise側脈衝來加以輸出。OR邏輯閘21，可將Rise側脈衝供給至檢測部4。又，OR邏輯閘21，可將Rise側脈衝供給至選擇部5中的「0」的輸入端子。 OR logic gate 21 is connected to each of the three pulse generators 20 . The OR logic gate 21 is an example of the first OR logic gate and outputs the logical sum of the reference pulse P rise generated by each of the three pulse generators 20 as a rise side pulse. The OR logic gate 21 can supply the Rise side pulse to the detection unit 4 . In addition, the OR logic gate 21 can supply the Rise side pulse to the "0" input terminal of the selector 5 .
[1.3. Fall側輸出部3] Fall側輸出部3是第2輸出部的一例，響應於複數個訊號Diff (AB)、Diff (BC)、Diff (CA)的至少一者下降的情形而輸出Fall側脈衝。訊號Diff (AB)、Diff (BC)、Diff (CA)下降，可以是指訊號Diff (AB)、Diff (BC)、Diff (CA)過零而自正值下降至負值。Fall側輸出部3具有3個脈衝產生器30(亦稱為脈衝產生器30 (AB)、30 (BC)、30 (CA))與OR邏輯閘31。 [1.3. Fall-side output unit 3] The Fall-side output unit 3 is an example of the second output unit and outputs in response to at least one of the plurality of signals Diff (AB) , Diff (BC) , and Diff (CA) falling. Fall side pulse. The signal Diff (AB) , Diff (BC) , and Diff (CA) decrease may mean that the signal Diff (AB) , Diff (BC) , and Diff (CA) cross zero and decrease from a positive value to a negative value. The Fall-side output unit 3 has three pulse generators 30 (also called pulse generators 30 (AB) , 30 (BC) , and 30 (CA) ) and an OR logic gate 31.
3個脈衝產生器30 (AB)、30 (BC)、30 (CA)，響應於複數個訊號Diff (AB)、Diff (BC)、Diff (CA)中對應的任一個訊號Diff下降的情形，分別產生基準寬度的基準脈衝P fall(亦稱為基準脈衝P fall(AB)、P fall(BC)、P fall(CA))。各脈衝產生器30，可將已產生的基準脈衝P fall供給至OR邏輯閘31。 The three pulse generators 30 (AB) , 30 (BC) , and 30 (CA) respond to the decline of any corresponding signal Diff among the plurality of signals Diff (AB) , Diff (BC) , and Diff (CA) , Reference pulses P fall (also called reference pulses P fall(AB) , P fall(BC) , P fall(CA) ) with reference widths are respectively generated. Each pulse generator 30 can supply the generated reference pulse P fall to the OR logic gate 31 .
OR邏輯閘31，連接至3個脈衝產生器30的各者。OR邏輯閘31是第2OR邏輯閘的一例，將由3個脈衝產生器30的各者產生的基準脈衝P fall的邏輯和作為Fall側脈衝來加以輸出。OR邏輯閘31，可將Fall側脈衝供給至檢測部4。又，OR邏輯閘31，可將Fall側脈衝供給至選擇部5中的「1」的輸入端子。 OR logic gate 31 is connected to each of the three pulse generators 30 . The OR logic gate 31 is an example of the second OR logic gate and outputs the logical sum of the reference pulse P fall generated by each of the three pulse generators 30 as a Fall side pulse. The OR logic gate 31 can supply the Fall side pulse to the detection unit 4 . In addition, the OR logic gate 31 can supply the Fall-side pulse to the "1" input terminal of the selector 5 .
[1.4. 基準脈衝P rise、 Pfall的基準寬度] 在時脈脈衝clk的間隔中訊號Diff (AB)、Diff (BC)、Diff (CA)的上升及下降是逐次產生一個的情況下，基準脈衝P rise、P fall的基準寬度，可為來自Rise側輸出部2的Rise側脈衝(此處為基準脈衝P rise本身)與來自Fall側輸出部3的Fall側脈衝(此處為基準脈衝P fall本身)有至少一部分重疊的脈衝寬度。例如，在時脈脈衝clk的間隔中有訊號Diff (AB)上升及訊號Diff (BC)下降的情況下，可為Rise側輸出部2的脈衝產生器20 (AB)所產生的基準脈衝P rise(AB)與Fall側輸出部3的脈衝產生器30 (BC)所產生的基準脈衝P fall(BC)必定有一部分重疊的脈衝寬度。 [1.4. The reference width of the reference pulses P rise and Pfall ] When the rise and fall of the signals Diff (AB) , Diff (BC) , and Diff (CA) are generated one after another in the interval of the clock pulse clk, the reference pulse The reference widths of P rise and P fall can be the Rise side pulse from the Rise side output unit 2 (here, the reference pulse P rise itself) and the Fall side pulse from the Fall side output unit 3 (here, the reference pulse P fall itself) have at least partially overlapping pulse widths. For example, when the signal Diff (AB) rises and the signal Diff (BC) falls during the interval of the clock pulse clk, it can be the reference pulse P rise generated by the pulse generator 20 (AB) of the Rise side output unit 2 (AB) A pulse width that always partially overlaps the reference pulse P fall (BC ) generated by the pulse generator 30 (BC) of the fall-side output unit 3 .
又，在時脈脈衝clk的間隔中有訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個以上的訊號上升的情況下，基準寬度可為響應該2個以上的訊號的各者而產生的2個以上的基準脈衝P rise有一部分重疊而形成1個Rise側脈衝的脈衝寬度。又，在時脈脈衝clk的間隔中有訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個以上的訊號下降的情況下，基準寬度可為響應該2個以上的訊號的各者而產生的2個以上的基準脈衝P fall有一部分重疊而形成1個Fall側脈衝的脈衝寬度。例如，在時脈脈衝clk的間隔中有2個訊號Diff (AB)、Diff (BC)上升的情況下，基準寬度可為響應該2個訊號Diff (AB)、Diff (BC)的各者而由Rise輸出部2的2個脈衝產生器20 (AB)、20 (BC)產生的2個基準脈衝P rise(AB)、P rise(BC)必定有一部分重疊而形成1個Rise側脈衝的脈衝寬度。此外，在有2個訊號Diff (AB)、Diff (BC)上升的情況下，該等上升與剩餘的訊號Diff (CA)的下降可同時產生，亦可在前個上升時序後經過基準寬度的時間之期間內，產生剩餘的訊號Diff (CA)的下降。 In addition, when two or more of the signals Diff (AB) , Diff (BC) , and Diff (CA) rise during the interval of the clock pulse clk, the reference width may be in response to the two or more signals. Two or more reference pulses P rise generated by each partially overlap and form a pulse width of one rise side pulse. In addition, when two or more of the signals Diff (AB) , Diff (BC) , and Diff (CA) fall during the interval of the clock pulse clk, the reference width may be in response to the two or more signals. Two or more reference pulses P fall generated by each partially overlap and form a pulse width of one fall-side pulse. For example, when two signals Diff (AB) and Diff (BC) rise during the interval of the clock pulse clk, the reference width can be determined in response to each of the two signals Diff (AB) and Diff (BC) . The two reference pulses P rise (AB) and P rise ( BC) generated by the two pulse generators 20 (AB) and 20 (BC) of the rise output unit 2 always partially overlap to form one rise side pulse. Width. In addition, when two signals Diff (AB) and Diff (BC) rise, the rise and the fall of the remaining signal Diff (CA) can occur at the same time, or they can pass through the reference width after the previous rising sequence. During the time period, the remaining signal Diff (CA) is generated.
又，基準寬度可為比可能在時脈脈衝clk的間隔中產生的訊號Diff (AB)、Diff (BC)、Diff (CA)的上升與下降的間隔最大值更大的脈衝寬度。上升與下降的間隔最大值，可為時脈脈衝clk的基準間隔的0.4倍長度。因此，基準寬度可為比時脈脈衝clk的基準間隔的0.4倍更大的脈衝寬度。基準間隔的長度可為在訊號A、B、C的傳送來源處所設定的UI的長度。在此情況下，基準寬度作為一例可為0.45UI，亦可為0.5UI以上。 In addition, the reference width may be a pulse width larger than the maximum value of the rising and falling intervals of the signals Diff (AB) , Diff (BC) , and Diff (CA) that may be generated in the intervals of the clock pulse clk. The maximum value of the interval between rising and falling can be 0.4 times the length of the reference interval of the clock pulse clk. Therefore, the reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulse clk. The length of the reference interval may be the length of the UI set at the transmission source of signals A, B, and C. In this case, the reference width may be 0.45UI, for example, or may be 0.5UI or more.
[1.5. 檢測部4] 檢測部4，每當成為脈衝的非檢測狀態(亦稱為等待(wait)狀態)時，檢測最先被輸出的先行脈衝。所謂脈衝的非檢測狀態，可指不對Rise側輸出部2及Fall側輸出部3所輸出的脈衝進行檢測的狀態。檢測部4，在非檢測狀態中，可檢測自Rise側輸出部2及Fall側輸出部3輸出的Rise側脈衝與Fall側脈衝中最先被輸出的脈衝，來作為先行脈衝。檢測部4具有：脈衝檢測部40、無效化部41。 [1.5. Detection part 4] The detection unit 4 detects the preceding pulse that is output first every time the pulse is in a non-detection state (also called a wait state). The pulse non-detection state refers to a state in which the pulses output by the rise-side output unit 2 and the fall-side output unit 3 are not detected. In the non-detection state, the detection unit 4 can detect the pulse that is output first among the Rise-side pulses and the Fall-side pulses output from the Rise-side output unit 2 and the Fall-side output unit 3 as the preceding pulse. The detection unit 4 includes a pulse detection unit 40 and a deactivation unit 41 .
脈衝檢測部40，分別檢測自Rise側輸出部2及Fall側輸出部3輸出的Rise側脈衝及Fall側脈衝。脈衝檢測部40，可響應於檢測到Rise側脈衝及Fall側脈衝的何者，而將選擇訊號Sel供給至選擇部5，該選擇訊號Sel使選擇部5進行選擇。本實施型態中，作為一例，脈衝檢測部40當檢測到Rise側脈衝時，可將表示「0」的選擇訊號Sel供給至選擇部5，該「0」的訊號在選擇部5中的「0」、「1」的輸入端子中是表示有Rise側脈衝輸入。同樣的，脈衝檢測部40當檢測到Fall側脈衝時，可將表示「1」的選擇訊號Sel供給至選擇部5，該「1」的訊號在選擇部5中的「0」、「1」的輸入端子中是表示有Fall側脈衝輸入。脈衝檢測部40當檢測到Rise側脈衝及Fall側脈衝的兩者時，可對選擇部5供給表示「0」的選擇訊號Sel，亦可供給表示「1」的選擇訊號Sel。The pulse detection unit 40 detects the Rise side pulse and the Fall side pulse output from the Rise side output unit 2 and the Fall side output unit 3 respectively. The pulse detection unit 40 can supply the selection signal Sel to the selection unit 5 in response to detecting which one of the Rise side pulse and the Fall side pulse is detected, and the selection signal Sel causes the selection unit 5 to select. In this embodiment, as an example, when the pulse detection unit 40 detects the Rise side pulse, it may supply the selection signal Sel indicating "0" to the selection unit 5. The input terminals of "0" and "1" indicate that there is Rise side pulse input. Similarly, when the pulse detection part 40 detects the Fall side pulse, it can supply the selection signal Sel indicating "1" to the selection part 5. The "1" signal is among "0" and "1" in the selection part 5 The input terminal indicates that there is a Fall side pulse input. When the pulse detection unit 40 detects both the Rise side pulse and the Fall side pulse, it may supply the selection signal Sel indicating "0" to the selection unit 5, or may provide the selection signal Sel indicating "1".
無效化部41，當時脈脈衝clk的各間隔中，來自Rise側輸出部2的脈衝與來自Fall側輸出部3的脈衝有一部分重疊而輸出時，使脈衝檢測部40針對較晚輸出的脈衝的檢測無效化。例如，無效化部41，可在檢測部4處於正在檢測先行脈衝的狀態(亦稱為忙碌(busy)狀態)時，使輸出而來的脈衝的檢測無效化。藉此，當來自Rise側脈衝及Fall側脈衝有一部分重疊而輸出時，僅有先行脈衝被脈衝檢測部40檢測到。換言之，在檢測部4處於未檢測先行脈衝的等待狀態時輸出而來的脈衝，會被脈衝檢測部40檢測到。無效化部41，可使脈衝檢測部40中針對Rise側脈衝的檢測功能與針對Fall側脈衝的檢測功能中，針對較晚輸出的脈衝的檢測功能失效。無效化部41，在Rise側脈衝與Fall側脈衝被同時輸出的情況下，可不使脈衝檢測部40進行的檢測無效化，亦可使Rise側脈衝與Fall側脈衝中預先決定的一方的脈衝檢測無效化。In each interval of the clock pulse clk, when the pulse from the Rise side output unit 2 partially overlaps with the pulse from the Fall side output unit 3 and is output, the invalidation unit 41 causes the pulse detection unit 40 to detect the pulse of the later output pulse. Detection invalidation. For example, the invalidation unit 41 may invalidate the detection of the output pulse when the detection unit 4 is detecting the preceding pulse (also called a busy state). Accordingly, when the pulses from the Rise side and the Fall side are partially overlapped and outputted, only the preceding pulse is detected by the pulse detection unit 40 . In other words, the pulse outputted when the detection unit 4 is in a waiting state without detecting the preceding pulse will be detected by the pulse detection unit 40 . The disabling unit 41 can disable the detection function for the pulse outputted later among the detection function for the Rise side pulse and the detection function for the Fall side pulse in the pulse detection unit 40 . When the Rise-side pulse and the Fall-side pulse are output simultaneously, the invalidation unit 41 does not need to invalidate the detection by the pulse detection unit 40, but may detect the pulse of a predetermined one of the Rise-side pulse and the Fall-side pulse. Nullification.
在Rise側脈衝及Fall側脈衝中的一方的脈衝檢測被無效化，也就是先檢測到另一方的脈衝而使檢測部4成為忙碌狀態的情況下，可響應成為該另一方的脈衝未被檢測到的狀態的情形，而使檢測部4成為脈衝的非檢測狀態，也就是等待狀態。亦即，在Rise側脈衝及Fall側脈衝中，與先行脈衝重疊而輸出的後行脈衝的檢測被無效化的情況下，後行脈衝不會被脈衝檢測部40檢測到。在該狀態中，若成為未檢測到先行脈衝的狀態(也就是若已被檢測到的先行脈衝下降)，則會成為Rise側脈衝及Fall側脈衝的任一者的脈衝皆未被檢測到的狀態，因此檢測部4可成為非檢測狀態。藉此，檢測部4可成為等待檢測下個先行脈衝的狀態。When the pulse detection of one of the Rise-side pulse and the Fall-side pulse is invalidated, that is, when the pulse of the other side is detected first and the detection unit 4 becomes busy, the response may be that the pulse of the other side is not detected. The detection unit 4 enters the pulse non-detection state, that is, the waiting state. That is, when the detection of the trailing pulse outputted overlapping with the preceding pulse among the rise-side pulses and the fall-side pulses is invalidated, the trailing pulse will not be detected by the pulse detection unit 40 . In this state, if the preceding pulse is not detected (that is, if the detected preceding pulse falls), neither the rise-side pulse nor the fall-side pulse will be detected. state, the detection unit 4 can become a non-detection state. Thereby, the detection unit 4 can be in a state of waiting to detect the next leading pulse.
在藉由無效化部41來使脈衝的檢測無效化的情況下，可響應該脈衝下降的情形而解除無效化。例如，在Rise側脈衝被作為先行脈衝而檢測到，且較晚上升的Fall側脈衝被無效化的情況下，可響應該Fall側脈衝下降的情形而解除針對Fall側脈衝的檢測的無效化。藉此，當Rise側脈衝及Fall側脈衝中，在與一方的脈衝重疊而輸出的另一方的脈衝被無效化後，重新再輸出另一方的脈衝時，該另一方的脈衝可作為先行脈衝而被檢測到。此外，在Rise側脈衝與Fall側脈衝並未重疊而輸出的情況下，由於不會藉由無效化部41來使較晚發送的Fall側脈衝檢測無效化，所以該較晚發送的Fall側脈衝可作為下一個先行脈衝而被檢測到。When the detection of pulses is invalidated by the invalidating unit 41, the invalidation can be canceled in response to the falling of the pulses. For example, when the Rise side pulse is detected as the preceding pulse and the Fall side pulse that rises later is deactivated, the deactivation of the detection of the Fall side pulse can be canceled in response to the fall of the Fall side pulse. Thereby, when the other pulse between the Rise side pulse and the Fall side pulse is outputted overlapping with one pulse and is invalidated, and the other pulse is output again, the other pulse can be used as the preceding pulse. was detected. In addition, when the Rise-side pulse and the Fall-side pulse are output without overlapping, the detection of the Fall-side pulse sent later will not be invalidated by the invalidation unit 41, so the Fall-side pulse sent later will not be invalidated. Can be detected as the next leading pulse.
無效化部41，針對時脈脈衝clk的新的間隔已開始的情形，可響應於藉由脈衝檢測部40檢測到Rise側脈衝、Fall側脈衝而檢測到，亦可響應於時脈脈衝clk自裝置1輸出而檢測到，或亦可響應於脈衝檢測部40輸出選擇訊號Sel而檢測到。The invalidation unit 41 may detect that a new interval of the clock pulse clk has started in response to the detection of the Rise side pulse and the Fall side pulse by the pulse detection unit 40, or may automatically detect the start of the clock pulse clk in response to the pulse detection unit 40. The device 1 outputs and detects, or may detect in response to the pulse detection unit 40 outputting the selection signal Sel.
[1.6. 選擇部5] 選擇部5，將檢測部4檢測到的先行脈衝的邊緣，選擇來作為時脈中所含的時脈脈衝clk的邊緣。選擇部5，可基於來自檢測部4的選擇訊號Sel，將Rise側脈衝及Fall側脈衝的任一者的邊緣選擇來作為時脈脈衝clk的邊緣。本實施型態中作為一例，選擇部5將先行脈衝的開始邊緣(例如上升邊緣)及結束邊緣(例如下降邊緣)選擇來作為時脈脈衝clk的開始邊緣及結束邊緣，也就是將先行脈衝選擇來作為時脈脈衝clk。 [1.6. Selection part 5] The selection unit 5 selects the edge of the preceding pulse detected by the detection unit 4 as the edge of the clock pulse clk included in the clock. The selection unit 5 can select the edge of either the Rise side pulse or the Fall side pulse as the edge of the clock pulse clk based on the selection signal Sel from the detection unit 4 . In this embodiment, as an example, the selection unit 5 selects the starting edge (for example, rising edge) and the ending edge (for example, falling edge) of the preceding pulse as the starting edge and ending edge of the clock pulse clk, that is, selecting the preceding pulse. Comes as clock pulse clk.
選擇部5，可響應於選擇訊號Sel是表示「0」、「1」的何者，來選擇自Rise側輸出部2輸入至「0」的輸入端子的Rise側脈衝，與自Fall側輸出部3輸入至「1」的輸入端子的Fall側脈衝。本實型態中作為一例，選擇部5可為多工器。The selection unit 5 can select the Rise side pulse input from the Rise side output unit 2 to the input terminal of "0" and the Rise side pulse input from the Fall side output unit 3 in response to which of the selection signal Sel represents "0" or "1". Fall side pulse input to the input terminal of "1". In this embodiment, as an example, the selection unit 5 may be a multiplexer.
選擇部5，可將選擇到的時脈脈衝clk供給至資料讀取部6。選擇部5，亦可將時脈脈衝clk輸出至裝置1的外部。The selection unit 5 can supply the selected clock pulse clk to the data reading unit 6 . The selection unit 5 may also output the clock pulse clk to the outside of the device 1 .
[1.7. 資料讀取部6] 資料讀取部6，鎖住訊號Diff (AB)、Diff (BC)、Diff (CA)。資料讀取部6，可配合自選擇部5供給而來的時脈脈衝clk而分別鎖住訊號Diff (AB)、Diff (BC)、Diff (CA)。藉此，例如第n個(其中n是自然數)UI的訊號Diff (AB)、Diff (BC)、Diff (CA)可對應自第n+α個(其中α是0以上的整數)的UI的訊號Diff (AB)、Diff (BC)、Diff (CA)產生的時脈脈衝clk而被鎖住。作為上述的替代方案，第n個UI的訊號Diff (AB)、Diff (BC)、Diff (CA)亦可對應自第n-α個的UI的訊號Diff (AB)、Diff (BC)、Diff (CA)產生的時脈脈衝clk而被鎖住。 [1.7. Data reading part 6] The data reading part 6 locks the signals Diff (AB) , Diff (BC) , and Diff (CA) . The data reading unit 6 can respectively lock the signals Diff (AB) , Diff (BC) , and Diff (CA) in accordance with the clock pulse clk supplied from the selecting unit 5. Thus, for example, the signals Diff (AB) , Diff (BC) , and Diff (CA) of the nth (where n is a natural number) UI can correspond to the n+αth (where α is an integer above 0) UI. The clock pulse clk generated by the signals Diff (AB) , Diff (BC) , and Diff (CA) is locked. As an alternative to the above, the signals Diff (AB) , Diff (BC) , and Diff (CA) of the nth UI can also correspond to the signals Diff (AB) , Diff (BC) , and Diff of the n-αth UI. (CA) generates the clock pulse clk and is locked.
資料讀取部6，可為針對訊號Diff (AB)、Diff (BC)、Diff (CA)的各者而設置的D正反器。資料讀取部6，可將已鎖住的訊號Diff (AB)、Diff (BC)、Diff (CA)的資料輸出至外部。例如，資料讀取部6可將已鎖住的資料供給至顯示器的顯示驅動器。 The data reading unit 6 may be a D flip-flop provided for each of the signals Diff (AB) , Diff (BC) , and Diff (CA) . The data reading unit 6 can output the data of the locked signals Diff (AB) , Diff (BC) , and Diff (CA) to the outside. For example, the data reading unit 6 may supply the locked data to the display driver of the display.
根據以上的裝置1，每次響應複數個訊號Diff (AB)、Diff (BC)、Diff (CA)中的至少1者上升、下降而輸出的Rise側脈衝、Fall側脈衝的非檢測狀態產生時，會檢測到最先輸出的先行脈衝並選擇來作為時脈脈衝clk。因此，在訊號Diff的上升及下降的變化中，能夠產生與在相同UI內先產生的變化對應的時脈脈衝clk，並且能夠防止不小心對應到較晚產生的變化來生成時脈脈衝clk。藉此，能夠提高對於抖動的耐性以及時脈脈衝clk的精準度。 According to the above device 1, the non-detection state of the Rise side pulse and the Fall side pulse outputted in response to the rise or fall of at least one of the plurality of signals Diff (AB) , Diff (BC ), and Diff (CA ) occurs every time. , the first output preceding pulse will be detected and selected as the clock pulse clk. Therefore, in the rising and falling changes of the signal Diff, the clock pulse clk corresponding to the change that occurs first in the same UI can be generated, and the clock pulse clk can be prevented from being accidentally generated corresponding to the change that occurs later. Thereby, the tolerance to jitter and the accuracy of the clock pulse clk can be improved.
又，Rise側輸出部2、Fall側輸出部3具有：複數個脈衝產生器20、脈衝產生器30，其響應於對應的任一個訊號Diff上升、下降的情形，分別產生基準寬度的基準脈衝P rise、基準P fall；及OR邏輯閘21、OR邏輯閘31，其將已產生的基準P rise的邏輯和、基準P fall的邏輯和作為脈衝來輸出。因此，能夠分別檢測到訊號Diff的上升的變化與下降的變化的各者，而確實檢測到先產生的變化。 In addition, the Rise side output unit 2 and the Fall side output unit 3 have a plurality of pulse generators 20 and 30, which respectively generate reference pulses P of a standard width in response to the rise or fall of any of the corresponding signals Diff. rise , the reference P fall ; and the OR logic gate 21 and the OR logic gate 31, which output the generated logical sum of the reference P rise and the reference P fall as pulses. Therefore, the rising change and the falling change of the signal Diff can be detected separately, and the change that occurs first can be detected reliably.
又，基準脈衝P rise、P fall的基準寬度，在時脈脈衝clk的間隔中逐次產生一個訊號Diff的上升及下降的情況下，是Rise側脈衝與Fall側脈衝有一部分重疊的脈衝寬度。因此，當同UI內先產生Rise側脈衝與Fall側脈衝的其中一方，並且另一方較晚產生時，能夠防止較晚產生的脈衝被錯誤檢測為下一個UI的先行脈衝。 In addition, the reference widths of the reference pulses P rise and P fall are pulse widths in which the rise side pulse and the fall side pulse partially overlap when the rise and fall of the signal Diff are sequentially generated in the interval of the clock pulse clk. Therefore, when one of the Rise-side pulse and the Fall-side pulse is generated first within the same UI, and the other is generated later, it is possible to prevent the later-generated pulse from being erroneously detected as the preceding pulse of the next UI.
又，基準脈衝P rise、P fall的基準寬度，是比可能在時脈脈衝clk的間隔中產生的複數個訊號Diff的上升與下降的間隔最大值更大的脈衝寬度。因此，在時脈脈衝clk的間隔中逐次產生一個訊號Diff的上升及下降的情況下，Rise側脈衝與Fall側脈衝有一部分重疊。因此，當同UI內先產生Rise側脈衝與Fall側脈衝的其中一方，並且另一方較晚產生時，能夠防止較晚產生的脈衝被錯誤檢測為下一個UI的先行脈衝。 In addition, the reference width of the reference pulses P rise and P fall is a pulse width larger than the maximum value of the rising and falling intervals of a plurality of signals Diff that may be generated at intervals of the clock pulse clk. Therefore, when the rise and fall of a signal Diff is generated successively in the interval of the clock pulse clk, the Rise side pulse and the Fall side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse is generated first within the same UI, and the other is generated later, it is possible to prevent the later-generated pulse from being erroneously detected as the preceding pulse of the next UI.
又，基準脈衝P rise、P fall的基準寬度是比時脈脈衝clk的基準間隔的0.4倍(本實施型態中作為一例為0.4UI)更大的脈衝寬度。因此，在可能在時脈脈衝clk的間隔中產生的複數個訊號Diff的上升與下降的間隔最大值被決定成基準間隔的0.4倍以下的情況下，當在時脈脈衝clk的間隔中逐次產生1個訊號Diff的上升與下降時，Rise側脈衝與Fall側脈衝有一部分重疊。因此，當同UI內先產生Rise側脈衝與Fall側脈衝的其中一方，並且另一方較晚產生時，能夠防止較晚產生的脈衝被錯誤檢測為下一個UI的先行脈衝。又，例如藉由將基準脈衝P rise、P fall的基準寬度作成0.5UI以上，即便在複數個訊號Diff的上升與下降的間隔成為0.5UI的情況下，也能夠使Rise側脈衝與Fall側脈衝有一部分重疊，而能夠防止較晚產生的脈衝被錯誤檢測為下一個UI的先行脈衝。 In addition, the reference width of the reference pulses P rise and P fall is a pulse width larger than 0.4 times the reference interval of the clock pulse clk (in this embodiment, as an example, 0.4UI). Therefore, when the maximum value of the rising and falling intervals of the plurality of signals Diff that may be generated in the interval of the clock pulse clk is determined to be less than 0.4 times the reference interval, when the intervals of the clock pulse clk are successively generated When a signal Diff rises and falls, the Rise side pulse and the Fall side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse is generated first within the same UI, and the other is generated later, it is possible to prevent the later-generated pulse from being erroneously detected as the preceding pulse of the next UI. Furthermore, for example, by setting the reference widths of the reference pulses P rise and P fall to 0.5UI or more, even when the intervals between the rise and fall of a plurality of signals Diff become 0.5UI, the rise side pulse and the fall side pulse can be There is a partial overlap, which can prevent the later generated pulse from being mistakenly detected as the preceding pulse of the next UI.
又，當在時脈脈衝clk的各間隔中Rise側脈衝與Fall側脈衝有一部分重疊而輸出時，因為較晚輸出的脈衝的檢測被無效化，所以能夠確實檢測到訊號Diff的上升的變化與下降的變化中較早產生的變化。又，在對應於較晚產生的變化的脈衝跨到下一個UI的情況下，由於該脈衝的檢測被無效化，能夠確實檢測到在下個UI中較早產生的變化。In addition, when the Rise side pulse and the Fall side pulse are partially overlapped and output at each interval of the clock pulse clk, the detection of the pulse output later is invalidated, so the change in the rise and fall of the signal Diff can be reliably detected. The change that occurs earlier in the decline. Furthermore, when a pulse corresponding to a change that occurs later reaches the next UI, detection of the pulse is invalidated, so that a change that occurs earlier in the next UI can be reliably detected.
又，在有複數個訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個以上的訊號上升的情況下，基準脈衝P rise、P fall的基準寬度可為響應該2個以上的訊號Diff的各者而產生的2個以上的基準脈衝P rise與P fall有一部分重疊而形成1個Rise側脈衝的脈衝寬度。又，在時脈脈衝clk的間隔中有複數個訊號Diff (AB)、Diff (BC)、Diff (CA)中的2個以上的訊號下降的情況下，基準脈衝P rise、P fall的基準寬度可為響應該2個以上的訊號Diff的各者而產生的2個以上的基準脈衝P rise與P fall有一部分重疊而形成1個Fall側脈衝的脈衝寬度。因此，在相同UI內有2個以上的上升產生的情況與有2個以上的下降產生的情況下，能夠防止較晚產生的基準脈衝P rise、P fall被錯誤檢測為下一個UI的先行脈衝。 Furthermore, when two or more of the plurality of signals Diff (AB) , Diff (BC) , and Diff (CA) rise, the reference widths of the reference pulses P rise and P fall may be in response to the two or more signals. Two or more reference pulses P rise and P fall generated by each of the signals Diff partially overlap to form a pulse width of one rise side pulse. In addition, when two or more of the plurality of signals Diff (AB) , Diff (BC) , and Diff (CA) fall during the interval of the clock pulse clk, the reference width of the reference pulses P rise and P fall The pulse width may be such that the two or more reference pulses P rise and P fall generated in response to each of the two or more signals Diff partially overlap to form one Fall side pulse. Therefore, when two or more rises occur and two or more falls occur within the same UI, it is possible to prevent the later-generated reference pulses P rise and P fall from being erroneously detected as preceding pulses of the next UI. .
[2. 動作例] 第2圖表示裝置1的動作波形。本圖中作為一例表示以下的波形：在第1UI內依序產生訊號Diff (AB)的上升與訊號Diff (BC)的下降，且在第2UI內依序產生訊號Diff (AB)的下降與訊號Diff (BC)的上升的情況下，自脈衝產生器20 (AB)、20 (BC)、30 (AB)、30 (BC)輸出的基準脈衝P rise(AB)、P rise(BC)、P fall(AB)、P fall(BC)、自OR邏輯閘21與31輸出的Rise側脈衝與Fall側脈衝、自檢測部4輸出的選擇訊號Sel、自選擇部5輸出的時脈脈衝clk。圖中的橫軸表示時間，縱軸表示訊號位準。此外，在本圖中，一併圖示各時間點中的檢測部4的狀態「忙碌」、「等待」。又，本動作例中，基準脈衝P rise、P fall的基準寬度可為0.6UI。 [2. Operation example] Fig. 2 shows the operation waveform of the device 1. This figure shows the following waveform as an example: the rise of signal Diff (AB) and the fall of signal Diff (BC) are sequentially generated in the 1st UI, and the fall and fall of the signal Diff (AB) are sequentially generated in the 2nd UI. When Diff (BC) rises, the reference pulses P rise(AB), P rise(BC), and P output from the pulse generators 20 (AB) , 20 (BC) , 30 (AB) , and 30 (BC ) fall(AB) , P fall(BC) , the Rise side pulse and the Fall side pulse output from the OR logic gates 21 and 31, the selection signal Sel output from the detection part 4, and the clock pulse clk output from the selection part 5. The horizontal axis in the figure represents time, and the vertical axis represents signal level. In addition, in this figure, the status "busy" and "waiting" of the detection unit 4 at each time point are also shown. In addition, in this operation example, the reference widths of the reference pulses P rise and P fall may be 0.6UI.
首先在時間t1中，一旦Diff (BC)上升且訊號Diff (AB)、Diff (CA)下降，則自脈衝產生器20 (BC)、30 (BC)、30 (CA)輸出自時間t1至時間t3(=t1+0.6UI)為止的基準脈衝P rise(BC)、P fall(AB)、P fall(CA)。藉此，自OR邏輯閘21與31輸出自時間t1至時間t3為止有0.6UI的脈衝寬度的Rise側脈衝與Fall側脈衝。本動作例中作為一例，該等Rise側脈衝與Fall側脈衝由脈衝檢測部4檢測到的結果，使得檢測部4成為忙碌狀態而自檢測部4輸出「0」的選擇訊號Sel。結果，由選擇部5選擇Rise側脈衝來作為時脈脈衝clk而輸出。檢測部4，響應於Rise側脈衝、Fall側脈衝的下降而成為等待狀態。此外，本圖中省略基準脈衝P fall(CA)的圖示。 First, at time t1, once Diff (BC) rises and the signals Diff (AB) and Diff (CA) fall, the pulse generators 20 (BC) , 30 (BC) , and 30 (CA) output from time t1 to time The reference pulses P rise(BC) , P fall(AB) , and P fall(CA) up to t3 (=t1+0.6UI). Thereby, the OR logic gates 21 and 31 output a Rise-side pulse and a Fall-side pulse having a pulse width of 0.6UI from time t1 to time t3. In this operation example, as an example, the rise-side pulse and the fall-side pulse are detected by the pulse detection unit 4 , causing the detection unit 4 to enter a busy state and output the selection signal Sel of “0” from the detection unit 4 . As a result, the selector 5 selects the Rise side pulse and outputs it as the clock pulse clk. The detection unit 4 enters a waiting state in response to the falling of the Rise side pulse and the Fall side pulse. In addition, the illustration of the reference pulse P fall (CA) is omitted in this figure.
接著，在時間t5中，一旦Diff (BC)下降，則自脈衝產生器30 (BC)輸出自時間t5至時間t7(=t5+0.6UI)為止的基準脈衝P fall(BC)。藉此，自OR邏輯閘31輸出自時間t5至時間t7為止有0.6UI的脈衝寬度的Fall側脈衝。又，該Fall側脈衝由脈衝檢測部4檢測到的結果，使得檢測部4成為忙碌狀態而自檢測部4輸出「1」的選擇訊號Sel。結果，由選擇部5選擇Fall側脈衝來作為時脈脈衝clk而輸出。檢測部4，響應於Fall側脈衝的下降而成為等待狀態。 Next, when Diff (BC) falls at time t5, the reference pulse P fall (BC) from time t5 to time t7 (=t5+0.6UI) is output from the pulse generator 30 (BC ). Thereby, the OR logic gate 31 outputs a Fall-side pulse having a pulse width of 0.6UI from time t5 to time t7. Furthermore, as a result of the Fall-side pulse being detected by the pulse detection unit 4 , the detection unit 4 becomes a busy state and the selection signal Sel of “1” is output from the detection unit 4 . As a result, the selector 5 selects the Fall side pulse and outputs it as the clock pulse clk. The detection unit 4 enters a waiting state in response to the fall of the Fall side pulse.
另一方面，在時間t6(=t5+0.5UI)中一旦Diff (AB)上升，則自脈衝產生器20 (AB)輸出自時間t6至時間t9(=t6+0.6UI)為止的基準脈衝P rise(AB)。藉此，自OR邏輯閘21輸出自時間t6至時間t9為止有0.6UI的脈衝寬度的Rise側脈衝。由於該Rise側脈衝與先行的Fall側脈衝重疊，所以根據無效化部41所進行的無效化的結果，不被脈衝檢測部40檢測到。因此，自檢測部4輸出的選擇訊號Sel或自選擇部5輸出的時脈脈衝clk，不受到來自Rise側脈衝的影響。在時刻t9中一旦Rise側脈衝下降，則針對該Rise側脈衝的檢測無效化便解除。 On the other hand, once Diff (AB) rises at time t6 (=t5+0.5UI), the pulse generator 20 (AB) outputs the reference pulse P from time t6 to time t9 (=t6+0.6UI). rise(AB) . Thereby, the OR logic gate 21 outputs a Rise side pulse having a pulse width of 0.6UI from time t6 to time t9. Since this Rise-side pulse overlaps with the preceding Fall-side pulse, it is not detected by the pulse detection unit 40 as a result of the invalidation performed by the invalidation unit 41 . Therefore, the selection signal Sel output from the detection unit 4 or the clock pulse clk output from the selection unit 5 is not affected by the pulse from the Rise side. Once the Rise-side pulse falls at time t9, the detection invalidation of the Rise-side pulse is cancelled.
又，在自時間t7至時間t9為止之間的時間t8中，一旦Diff (AB)下降，則自脈衝產生器30 (AB)輸出自時間t8起有基準寬度的基準脈衝P fall(AB)。藉此，自OR邏輯閘31輸出自時間t8起有0.6UI的脈衝寬度的Fall側脈衝。又，該Fall側脈衝由脈衝檢測部4檢測到的結果，使得檢測部4成為忙碌狀態而自檢測部4輸出「1」的選擇訊號Sel。結果，由選擇部5選擇Fall側脈衝來作為時脈脈衝clk而輸出。 In addition, when Diff (AB) falls during time t8 between time t7 and time t9, the pulse generator 30 (AB) outputs the reference pulse P fall(AB) having the reference width from time t8. Thereby, the OR logic gate 31 outputs a Fall-side pulse having a pulse width of 0.6UI from time t8. Furthermore, as a result of the Fall-side pulse being detected by the pulse detection unit 4 , the detection unit 4 becomes a busy state and the selection signal Sel of “1” is output from the detection unit 4 . As a result, the selector 5 selects the Fall side pulse and outputs it as the clock pulse clk.
[3. 變化例] 此外，上述實施型態中，是說明裝置1自接收訊號A、B、C來產生訊號Diff (AB)、Diff (BC)、Diff (CA)的接收裝置取得訊號Diff (AB)、Diff (BC)、Diff (CA)，但亦可接收訊號A、B、C來產生訊號Diff (AB)、Diff (BC)、Diff (CA)。在此情況下，裝置1可更具備：接收部，其接收訊號A、B、C；以及差動電路部，其自已接收的訊號A、B、C產生訊號Diff (AB)、Diff (BC)、Diff (CA)。 [ 3. Variation ] In addition, in the above embodiment, it is explained that the device 1 obtains the signal Diff ( AB) , Diff (BC) , Diff (CA) , but it can also receive signals A, B, C to generate signals Diff (AB) , Diff (BC) , Diff (CA) . In this case, the device 1 may further include: a receiving part that receives signals A, B, and C; and a differential circuit part that generates signals Diff (AB) and Diff (BC) based on the received signals A, B, and C. ,Diff (CA) .
又，以上是說明裝置1基於C-PHY的情形，但亦可不基於C-PHY。在此情況下，裝置1可取得與3不同的數量的複數個訊號，Rise側輸出部2可響應於該複數個訊號的至少一個上升而輸出Rise側脈衝，且Fall側輸出部3可響應於該複數個訊號的至少一個下降而輸出Fall側脈衝。In addition, the above describes the case where the device 1 is based on C-PHY, but it may not be based on C-PHY. In this case, the device 1 can obtain a plurality of signals different from 3, the rise-side output unit 2 can output a rise-side pulse in response to at least one rise of the plurality of signals, and the fall-side output unit 3 can respond to At least one of the plurality of signals falls to output a Fall side pulse.
又，以上是說明將訊號Diff (AB)、Diff (BC)、Diff (CA)的上升與下降的間隔最大值作成時脈脈衝clk的基準間隔(作為一例是UI)的0.4倍長度，但基準間隔亦可比0.4倍更長。即便在此情況下，基準脈衝P rise、P fall的基準寬度，亦可為比訊號Diff (AB)、Diff (BC)、Diff (CA)的上升與下降的間隔最大值更大的脈衝寬度。 In addition, the above is an explanation that the maximum value of the rising and falling intervals of the signals Diff (AB) , Diff (BC) , and Diff (CA) is set to 0.4 times the length of the reference interval (for example, UI) of the clock pulse clk, but the reference The interval can also be longer than 0.4 times. Even in this case, the reference width of the reference pulses P rise and P fall can also be a pulse width larger than the maximum value of the interval between the rise and fall of the signals Diff (AB) , Diff (BC) and Diff (CA) .
又，以上是說明選擇部5將先行脈衝的開始邊緣及結束邊緣選擇來作為時脈脈衝clk的開始邊緣及結束邊緣，但只要有將先行脈衝的開始邊緣選擇來作為時脈脈衝clk的開始邊緣，則亦可不將先行脈衝的結束邊緣選擇來作為時脈脈衝clk的結束邊緣。例如，選擇部5可產生將先行脈衝拉長的脈衝，將先行脈衝的開始邊緣選擇來作為時脈脈衝clk的開始邊緣，並將拉長過的脈衝的結束邊緣作為時脈脈衝clk的結束邊緣。In addition, the above description is that the selection unit 5 selects the start edge and the end edge of the preceding pulse as the start edge and the end edge of the clock pulse clk, but as long as the start edge of the preceding pulse is selected as the start edge of the clock pulse clk , then the end edge of the preceding pulse may not be selected as the end edge of the clock pulse clk. For example, the selection unit 5 may generate a pulse that stretches the preceding pulse, select the starting edge of the preceding pulse as the starting edge of the clock pulse clk, and select the ending edge of the stretched pulse as the ending edge of the clock pulse clk. .
又，以上是說明檢測部4檢測Rise側脈衝及Fall側脈衝，並檢測Rise側脈衝及Fall側脈衝中最先輸出的先行脈衝，但亦可檢測第3基準寬度的第3脈衝與第3基準寬度的第4脈衝中最先輸出的先行脈衝來檢測先行脈衝，該第3脈衝是響應於輸出Rise側脈衝而產生，且該第4脈衝是響應於輸出Fall側脈衝而產生。在此情況下，檢測部4的脈衝檢測部40可分別檢測第3脈衝及第4脈衝，且無效化部41在時脈脈衝的各間隔中第3脈衝與第4脈衝有一部分重疊而輸出的情況下，可將針對較晚輸出的脈衝的脈衝檢測部40的檢測無效化。此處，第3脈衝及第4脈衝可由輸出部2產生，亦可由檢測部4產生。在時脈脈衝clk的間隔中訊號Diff (AB)、Diff (BC)、Diff (CA)的上升及下降是逐次產生一個的情況下，第3基準寬度，可為第3脈衝與第4脈衝有至少一部分重疊的脈衝寬度。又，第3基準寬度可為比可能在時脈脈衝clk的間隔中產生的訊號Diff (AB)、Diff (BC)、Diff (CA)的上升與下降的間隔最大值更大的脈衝寬度。又，第3基準寬度可為比時脈脈衝clk的基準間隔的0.4倍更大的脈衝寬度。在檢測部4藉由如此檢測第3基準寬度的第3脈衝及第4脈衝來檢測先行脈衝的情況下，脈衝產生器20、30可產生比第3基準寬度更窄的基準寬度的基準脈衝P rise、P fall。作為一例，第3脈衝及第4脈衝的基準寬度可為0.6UI，且基準脈衝P rise、P fall的脈衝寬度可為0.25UI。 In addition, the above description is that the detection unit 4 detects the Rise-side pulse and the Fall-side pulse, and detects the preceding pulse output first among the Rise-side pulse and the Fall-side pulse. However, it may also detect the third pulse with the third reference width and the third reference pulse. The preceding pulse is detected by detecting the preceding pulse that is output first among the fourth pulses of the width. The third pulse is generated in response to the output of the Rise side pulse, and the fourth pulse is generated in response to the output of the Fall side pulse. In this case, the pulse detection unit 40 of the detection unit 4 can detect the third pulse and the fourth pulse respectively, and the invalidation unit 41 outputs the result when the third pulse and the fourth pulse partially overlap in each interval of the clock pulse. In this case, the detection by the pulse detection unit 40 of the pulse output later can be invalidated. Here, the third pulse and the fourth pulse may be generated by the output unit 2 or the detection unit 4 . When the rise and fall of the signals Diff (AB) , Diff (BC) , and Diff (CA) occur one after another in the interval of the clock pulse clk, the third reference width can be the difference between the third pulse and the fourth pulse. Pulse widths that overlap at least partially. In addition, the third reference width may be a pulse width larger than the maximum value of the rising and falling intervals of the signals Diff (AB) , Diff (BC) , and Diff (CA) that may be generated in the intervals of the clock pulse clk. In addition, the third reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulse clk. When the detection unit 4 detects the preceding pulse by detecting the third pulse and the fourth pulse of the third reference width in this way, the pulse generators 20 and 30 can generate the reference pulse P with a narrower reference width than the third reference width. rise , fall . As an example, the reference widths of the third pulse and the fourth pulse may be 0.6UI, and the pulse widths of the reference pulses P rise and P fall may be 0.25 UI.
以上，使用實施型態來說明了本發明，但是本發明的技術範圍並非限定於上述實施型態所述之範圍。該發明所屬之技術領域中具有通常知識者清楚，可對上述實施型態施加各種變更或改良。由申請專利範圍的記載可了解，施加該種變更或改良的型態亦可包含於本發明的技術範圍中。The present invention has been described above using the embodiments. However, the technical scope of the present invention is not limited to the scope described in the above-mentioned embodiments. It is clear to those with ordinary skill in the technical field to which this invention belongs that various changes or improvements can be made to the above embodiments. It can be understood from the description of the patent application that a mode in which such changes or improvements are made can also be included in the technical scope of the present invention.
應注意，申請專利範圍、說明書及圖式中所示之裝置、系統、程式及方法中的動作、次序、步驟及階段等各處理的執行順序，只要未特別明示「在……之前」、「事先」等，並且，只要未將前一處理的輸出用於後續處理，便能以任意的順序實現。關於申請專利範圍、說明書及圖式中的動作流程，即便為方便起見而使用「首先，」、「繼而，」等加以說明，亦非意指必須以該順序實施。It should be noted that the actions, sequences, steps, stages and other execution sequences of the processes in the devices, systems, programs and methods shown in the scope of the patent application, the specification and the drawings, as long as it is not specifically stated "before", " etc., and can be implemented in any order as long as the output of the previous process is not used for subsequent processing. Even if the operational procedures in the scope of the patent application, the specification and the drawings are described using "first,", "then," etc. for the sake of convenience, it does not mean that they must be implemented in that order.
1:裝置 2:Rise側輸出部 3:Fall側輸出部 4:檢測部 5:選擇部 6:資料讀取部 20:脈衝產生器 21:OR邏輯閘 30:脈衝產生器 31:OR邏輯閘 40:脈衝檢測部 41:無效化部 1:Device 2:Rise side output part 3:Fall side output part 4:Testing Department 5:Selection Department 6: Data reading department 20:Pulse generator 21:OR logic gate 30:Pulse generator 31:OR logic gate 40: Pulse detection department 41: Neutralization Department
第1圖表示實施型態之裝置1。 Figure 1 shows a device 1 according to the embodiment.
第2圖表示裝置1的動作波形。 Figure 2 shows the operation waveform of the device 1.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
1:裝置 1:Device
2:Rise側輸出部 2:Rise side output part
3:Fall側輸出部 3:Fall side output part
4:檢測部 4:Testing Department
5:選擇部 5:Selection department
6:資料讀取部 6: Data reading department
20:脈衝產生器 20:Pulse generator
21:OR邏輯閘 21:OR logic gate
30:脈衝產生器 30:Pulse generator
31:OR邏輯閘 31:OR logic gate
40:脈衝檢測部 40: Pulse detection department
41:無效化部 41: Neutralization Department
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| TW201626720A (en) * | 2011-12-29 | 2016-07-16 | 英特爾股份有限公司 | Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement |
| TW201433092A (en) * | 2012-11-15 | 2014-08-16 | Microchip Tech Inc | Complementary output generator module |
| TW202123019A (en) * | 2019-12-04 | 2021-06-16 | 韓商愛思開海力士有限公司 | Semiconductor devices and semiconductor systems |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202308312A (en) | 2023-02-16 |
| CN115905091A (en) | 2023-04-04 |
| KR102660687B1 (en) | 2024-04-26 |
| KR20230020896A (en) | 2023-02-13 |
| JP2023023090A (en) | 2023-02-16 |
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