TWI822111B - Semiconductor device and method of forming the same - Google Patents

Abstract

A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Description

Semiconductor device and method of forming same

Embodiments of the present invention generally relate to integrated circuit devices, and more particularly to multi-gate devices such as fully wound gate devices.

The electronics industry's demand for smaller, faster electronic devices that simultaneously support a large number of complex functions continues to increase. In order to meet these needs, the continued trend in the integrated circuit industry is to manufacture low-cost, high-performance, and low-energy-consumption integrated circuits. The main method to achieve these goals is to reduce the size of integrated circuits (such as the minimum integrated circuit structure size) to improve production capacity and reduce related costs. However, shrinking the size also increases the complexity of the integrated circuit manufacturing process. Therefore, in order to achieve continued progress in integrated circuit devices and their performance, similar progress in integrated circuit process technology is also required.

Recently, multi-gate devices have been introduced to improve gate control. Multiple gate devices can increase gate-channel coupling, reduce off-state current, and/or reduce short channel effects. One of the multi-gate devices is a fully wound gate device, which includes a gate structure that can partially or completely extend around the channel area to contact at least two sides of the channel area. Fully wound gate devices can significantly shrink integrated circuit technology, maintain gate control, mitigate short channel effects, and be seamlessly integrated into existing integrated circuit manufacturing processes. As fully wound gate devices continue to shrink, challenges arising from the different channel requirements of n-type metal oxide half and p-type metal oxide half devices may Deteriorating the performance of fully wound gate devices.

A method of forming a semiconductor device according to an embodiment of the present invention includes forming p-type wells and n-type wells in a substrate. The method further includes forming a stack of a plurality of staggered first semiconductor material layers and a plurality of second semiconductor material layers on the p-type well and the n-type well, the first semiconductor material layer having a first thickness, and the second semiconductor material layer Has a second thickness, and the second thickness is different from the first thickness. The method further includes annealing the stack of alternating first and second semiconductor material layers. In some embodiments, the method further includes patterning the stack to form a plurality of fin structures, the fin structures including a first fin structure on the n-type well and a second fin structure on the p-type well. The method further includes performing an etching process to remove the second semiconductor material layer from the first fin structure and the second fin structure, wherein the first semiconductor material layer and the second fin structure in the first fin structure after the etching process The first semiconductor material layer in has a different thickness. The method further includes forming a metal gate on the first fin structure and the second fin structure.

In another embodiment, a method of forming a semiconductor device includes receiving a substrate including a p-type well and an n-type well. The method further includes forming a plurality of semiconductor layers stacked on the p-type well and the n-type well of the substrate. The stack of semiconductor layers includes a plurality of staggered first semiconductor material layers and a plurality of second semiconductor material layers. In some embodiments, the method further includes performing an annealing process on the stack of semiconductor layers to drive dopants from the p-type well into the second semiconductor material layer above the p-type well. The method further includes etching the stack of semiconductor layers to form a first fin structure on the p-type well and a second fin structure on the n-type well. In some examples, the method further includes removing a second semiconductor material layer from the first fin structure and the second fin structure, wherein the first semiconductor material layer in the first fin structure after removing the second semiconductor material layer is different from the thickness of the first semiconductor material layer in the second fin structure.

In yet another embodiment, a semiconductor device includes a substrate. The semiconductor device further includes a first fin structure located on the first region of the substrate and including a first group of a plurality of first channel layers, and each of the first channel layers has a first thickness. The device further includes a second fin structure located on the second region of the substrate and including a second group of a plurality of second channel layers, each of the second channel layers having a second thickness, and the second thickness is greater than the first thickness. In some embodiments, the semiconductor device further includes a gate structure located on the first fin structure and the second fin structure and covering the first group of first channel layers and the second group of second channel layers.

A-A,B-B,C-C,D-D: hatching line

I,II: area

t1,t2,t3,t4: thickness

100:Method

102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136: Steps

200:Artifact

202:Substrate

203A:p-type well

203B: n-type well

204:Stacking

206:Sacrificial layer

206T: Top sacrificial layer

208: Channel layer

210: Fin-like structure

210B: Bottom

210T:Top

212: Fin grooves

214: Hard mask layer

216:Isolation structure

218:Dielectric Fins

220: Cladding

222: First dielectric layer

224: Second dielectric layer

226: High dielectric constant dielectric layer

240: Dummy gate stack

242: Dummy dielectric layer

244: Dummy gate

246: Hard mask on top of gate

248: Silicon nitride mask layer

250: Silicon oxide mask layer

252: Gate spacer

254: Source/Drain recess

258:Inner spacer structure

260: Source/drain structure

266: Gate trench

270: Contact etch stop layer

272:Interlayer dielectric layer

274: Gate structure

276: Gate dielectric layer

278: Gate layer

280:Metal cover

282:Self-aligned cover

284: Gate cutting structure

1A and 1B are flowcharts of a method of manufacturing a semiconductor device in one or more embodiments of the present invention.

FIG. 2 is a perspective view of a semiconductor device according to one or more embodiments of the invention.

Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, and 18A are the semiconductors shown in Figure 2 in one or more embodiments of the present invention. A cross-sectional view along line A-A of the device at various manufacturing stages of the method of Figures 1A and 1B.

Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, and 18B are the semiconductors shown in Figure 2 in one or more embodiments of the present invention. A cross-sectional view along line B-B of the device at various manufacturing stages of the method of Figures 1A and 1B.

3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, and 18C are the semiconductors shown in FIG. 2 in one or more embodiments of the present invention. A cross-sectional view along line C-C of the device in various manufacturing stages of the method of Figures 1A and 1B.

Figures 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, 15D, 16D, 17D, and 18D are the semiconductors shown in Figure 2 in one or more embodiments of the present invention. Installed in Figure 1A and cross-sectional views along line D-D of various production stages of method 1B.

The following detailed description may be accompanied by accompanying drawings to facilitate understanding of various aspects of the present invention. It is important to note that the various structures are for illustrative purposes only and are not drawn to scale, as is the norm in this industry. Indeed, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of illustration.

The same reference numbers may be repeatedly used in multiple examples of the present invention for simplicity, but elements with the same reference numbers in various embodiments and/or arrangements do not necessarily have the same corresponding relationship. The following content provides different embodiments or examples for implementing different structures of the invention. In addition, the following examples of specific components and arrangements are used to simplify the content of the present invention but not to limit the present invention. For example, the description of forming the first component on the second component includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by other additional components rather than in direct contact. In addition, in embodiments of the invention in which a structure is formed on, connected to, and/or coupled to another structure, the structure may directly contact the other structure, or additional structures may be formed on the structure. and another structure so that there is no direct contact between the structure and the other structure.

In addition, spatially relative terms such as "below", "below", "lower", "above", "higher", or similar terms are used to describe some elements or structures in the diagram and A relationship between another element or structure. These spatially relative terms include the orientation of a device in use or operation and the orientation depicted in the drawings. When the device is turned in a different direction (rotated 90 degrees or other angles), the spatially relative adjectives used will also be interpreted according to the turned direction.

Embodiments of the present invention generally relate to semiconductor devices and methods of fabricating the same, and particularly relate to integrated circuits of transistors with different thicknesses of channel elements in different regions to improve overall performance. In various embodiments, fully wound gate transistors with different channel element thicknesses on the same substrate are placed on a single A first region (such as an n-type metal oxide semi-transistor) and a second region (such as a p-type metal oxide semi-transistor) in an integrated circuit chip. The first zone and the second zone may be directly adjacent to each other. In various embodiments of the present invention, different dopants are implanted in the first region and the second region and an etching process is performed to achieve channel components with different thicknesses. Although the stacked semiconductor channel layers included in the embodiments are in the form of nanowire or nanosheet channel components in the drawings, the embodiments of the present invention are not limited thereto and can be implemented in other multi-gate devices, such as other types of fully wound devices. Type gate transistor or fin field effect transistor.

Various embodiments of the present invention will be described in detail with reference to the flowchart of the method 100 of forming a semiconductor device shown in FIGS. 1A and 1B . Method 100 is only an example, and does not limit the embodiments of the present invention to the actual description of method 100. Additional steps may be provided before, during, and after method 100, and additional embodiments of the method may substitute, omit, or swap some of the steps. All steps are not detailed here to simplify the explanation. The method 100 is described below with reference to FIGS. 2 to 18D , which show partial perspective and cross-sectional views of the workpiece 200 at various stages of fabrication of the method 100 . Since a semiconductor device is formed from the workpiece 200, the workpiece 200 may be considered a semiconductor device or device, as the context requires.

In some embodiments, the workpiece 200 is an integrated circuit chip, a single-chip system, or a portion thereof, which may include a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect resistors, etc. Crystal, n-type field effect transistor, fin field effect transistor, nanochip field effect transistor, nanowire field effect transistor, other types of multi-gate field effect transistor, metal oxide half field effect transistor, complementary Metal oxide semi-transistors, bipolar junction transistors, laterally diffused metal oxide semi-transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations of the above. 2 to 18D have been simplified to clarify the drawings and facilitate understanding of the inventive concept of the embodiments of the present invention. Additional structures may be added to the workpiece 200, and other embodiments of the workpiece 200 may substitute, adapt, or omit some of the structures described below. The workpiece 200 includes a first region for n-type field effect transistors, such as region I, and a second region for p-type field effect transistors, such as region II.

FIG. 2 shows a perspective view of the workpiece 200, and FIGS. 3A to 18D show partial cross-sectional views of the workpiece 200 along lines A-A, B-B, C-C, and D-D in FIG. 2 respectively. Specifically, the partial cross-sectional views of section lines A-A and B-B are respectively the channel area of the transistor to be formed in area I and area II (such as cutting the Y-Z plane in the channel area, which is along the length direction of the gate structure). perpendicular to the length of the channel assembly). The partial cross-sectional views of section lines C-C and D-D are respectively along the length direction of the channel component of the transistor to be formed in regions I and II (for example, along the length direction of the channel component through the channel region and adjacent to the source/drain Cross-sectional view of the polar region in the X-Z plane). In this embodiment, the terms "source" and "drain" are interchangeable.

As shown in FIGS. 2 and 3A to 3D , step 102 ( FIG. 1A ) of the method 100 forms p-type wells 203A and n-type wells 203B in the workpiece 200 . Workpiece 200 includes substrate 202 . In one embodiment, the substrate 202 may be a silicon substrate. In some other embodiments, substrate 202 may include other semiconductor materials such as germanium, silicon germanium, or III-V semiconductor materials. Examples of III-V semiconductor materials may include gallium arsenide, indium phosphide, gallium phosphide, gallium nitride, gallium arsenide phosphorus, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, or gallium arsenide Indium. In various embodiments, substrate 202 is a substrate that extends continuously from region I to region II, where region I includes p-type well 203A and region II includes n-type well 203B.

The p-type well 203A may be formed by using an ion implantation process to dope p-type dopants such as boron, boron difluoride, or boron tetrafluoride into the substrate 202 in region I (see FIGS. 3A and 3C ). The ion implantation process may use p-type dopants to dope the substrate 202 to the doping concentration of the p-type well. The p-type well may have a doping concentration of about 1x10 ¹⁶ /cm ³ to about 1x10 ¹⁸ /cm ³ . In some embodiments, the doping concentration of the p-type well may be higher or lower. The n-type well 203B may be formed using an ion implantation process to dope n-type dopants such as phosphorus or arsenic into the substrate 202 in region II (see FIGS. 3B and 3D ). The ion implantation process may use n-type dopants to dope the substrate 202 to the doping concentration of the n-type well. The n-type well may have a doping concentration of about 1x10 ¹⁷ /cm ³ to about 1x10 ¹⁹ /cm ³ . In some embodiments, the n-type well may have a higher or lower doping concentration.

As shown in FIGS. 2 and 4A to 4D , step 104 ( FIG. 1A ) of method 100 forms stack 204 on region I and region II of substrate 202 of workpiece 200 , and anneals workpiece 200 . Stack 204 may include alternating channel layers 208 and sacrificial layers 206 on substrate 202 and include a top sacrificial layer 206T on sacrificial layers 206 and channel layers 208 . The channel layer 208 may have a thickness t1 and the sacrificial layer 206 may have a thickness t2, and the thickness t2 is less than the thickness t1. The thickness t1 may be about 1.4 times to about 1.5 times greater than the thickness t2, and may be about 1.46 times. If the ratio is greater than 1.5, there may not be enough space to form a metal gate to properly surround the channel layer 208 . If the ratio is less than 1.4, device performance may be degraded.

The deposition method of the sacrificial layer 206, the channel layer 208, and the top sacrificial layer 206T may be an epitaxial process. Examples of epitaxy processes may include vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and/or other suitable processes. Channel layer 208 and sacrificial layer 206 may have different semiconductor compositions. In some embodiments, channel layer 208 is composed of silicon and sacrificial layer 206 is composed of silicon germanium. The additional germanium content in sacrificial layer 206 can be used to selectively remove or selectively recess sacrificial layer 206 without substantially etching channel layer 208 . The sacrificial layer 206 and the channel layer 208 may be deposited in a staggered manner such that the channel layer is sandwiched between the sacrificial layer 206 . FIG. 2 shows three sacrificial layers 206 and three channel layers 208 that are staggered and vertically stacked. This is only used to illustrate the embodiments of the present invention and does not limit the embodiments of the present invention to areas not actually stated in the claims. The number of layers depends on the number of channel layers 208 required for the semiconductor device such as workpiece 200. In some embodiments, the number of channel layers 208 is between 2 and 7.

The top sacrificial layer 206T is similar to the sacrificial layer 206 and may be composed of silicon germanium. In some examples, sacrificial layer 206 is substantially the same composition as top sacrificial layer 206T. The top sacrificial layer 206T may be thicker than the sacrificial layer 206 to protect the stack 204 from damage during the fabrication process. In some examples, the thickness of top sacrificial layer 206T can be between about 20 nm and about 40 nm, and the thickness of sacrificial layer 206 can be between about 4 nm. to about 15nm.

As shown in FIGS. 4A to 4D , step 106 ( FIG. 1A ) of the method 100 performs an annealing process on the workpiece 200 . The annealing process can diffuse the p-type dopant in the p-type well in region I into the sacrificial layer 206 in region I to create a doped sacrificial layer 206 . The annealing process may further diffuse the n-type dopant in the n-type well in region II into the sacrificial layer 206 in region II to create a doped sacrificial layer 206 . The rates at which n-type dopants and p-type dopants diffuse into sacrificial layer 206 may be different. The diffusion of the n-type dopant and the p-type dopant may change the etching profile of the sacrificial layer 206 so that the sacrificial layer 206 in region I has a first etching rate and the sacrificial layer 206 in region II has a second etching rate. In some embodiments, the first etch rate is different than the second etch rate. The annealing process can further diffuse the n-type dopants and p-type dopants into the channel layer 208 . The concentration of p-type dopants and n-type dopants diffused into the channel layer 208 must not be high enough to degrade channel mobility. The effect on device performance is therefore essentially insignificant. The annealing process may apply a temperature of about 900°C to about 1000°C to the workpiece 200 . The annealing process may also include applying a pressure of about 10 Torr to about 20 Torr to the workpiece 200 . In some embodiments, an annealing process may be performed in subsequent steps of fabricating the workpiece 200 .

As shown in FIGS. 5A to 5D , step 108 of method 100 ( FIG. 1A ) patterns stack 204 and substrate 202 to form fin structures 210 separated by fin trenches 212 . To pattern stack 204 and substrate 202, a hard mask layer 214 may be deposited on top sacrificial layer 206T. Hard mask layer 214 is then patterned to serve as an etch mask for patterning top sacrificial layer 206T, stack 204, and the top of substrate 202. In some embodiments, the hard mask layer 214 may be deposited using chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, or another suitable deposition method. Hard mask layer 214 may be a single layer or multiple layers. When the hard mask layer 214 is multi-layered, the hard mask layer 214 may include a pad oxide layer and a pad nitride layer. In another embodiment, hard mask layer 214 may include silicon. The patterning method of the fin structure 210 may adopt a suitable process, including a double patterning or a multi-patterning process. Generally speaking, double Patterning or multi-patterning processes can combine photolithography and self-alignment processes to produce pattern pitches that are smaller than those achieved using a single direct photolithography process. For example, one embodiment forms a material layer on a substrate and uses a photolithography process to pattern the material layer. A self-aligned process is used to form spacers along the sides of the patterned material layer. The material layer is then removed, and the remaining spacers or cores can then be used to pattern the hard mask layer 214 . Then, using the patterned hard mask layer 214 as an etch mask, the stack 204 and the substrate 202 can be etched to form the fin structure 210 . The etching process may include dry etching, wet etching, reactive ion etching, and/or other suitable processes.

As shown in FIGS. 5A-5D , the fin structures 210 may each include a bottom 210B formed from a portion of the substrate 202 , ie, a top 210T formed from the stack 204 . Top 210T sits on bottom 210B. The length direction of the fin structure 210 may extend along the X direction, and may extend vertically from the substrate 202 along the Z direction. Fin trenches 212 may separate fin structures 210 along the Y direction. In some examples, fin trenches 212 may have a width of about 20 nm to about 50 nm to define a space between adjacent fin structures 210 .

As shown in FIGS. 6-6D , step 110 ( FIG. 1A ) of method 100 forms isolation structure 216 in fin trench 212 . Isolation structure 216 may be considered a shallow trench isolation structure. In an example process for forming isolation structure 216 , dielectric material may be deposited on workpiece 200 to fill fin trenches 212 with the dielectric material. In some embodiments, the dielectric material may include tetraethoxysilane oxide, undoped silicate glass, or doped silicon oxide (such as boron phosphosilicate glass, fluorosilicate glass, phosphorus silicate glass, borosilicate glass, and/or other suitable dielectric materials). In various embodiments, the method of depositing the dielectric material in step 110 may be flowable chemical vapor deposition, spin coating, and/or other suitable processes. The deposited dielectric material may then be thinned and planarized, such as using a chemical mechanical polishing process, until the hard mask layer 214 is exposed.

After planarization, an etch-back process can be performed to recess the deposited dielectric material until Stack 204 is fully raised above isolation structure 216 . In the embodiment, the bottom 210B may also be partially exposed, as shown in the figure. For example, the etch-back process of step 110 may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. The hard mask layer 214 can also be removed by an etch-back process or other suitable processes (such as ashing or photoresist stripping).

As shown in Figures 7A-7D, 8A-8D, and 9A-9D, step 112 (Figure 1A) of method 100 forms dielectric fins 218. In the illustrated embodiment, step 112 may form dielectric fins 218 in fin trenches 212 . An example process for forming dielectric fins 218 may include compliantly depositing a coating 220 (as shown in FIGS. 7A-7D ), compliantly depositing a first dielectric layer 222 and compliantly depositing a second dielectric layer 224 in the fin trenches. in trench 212 (as shown in FIGS. 8A to 8D ), and depositing a high-k dielectric layer 226 on top of the first dielectric layer 222 and the second dielectric layer 224 (as shown in FIGS. 9A to 9D ). .

Coating 220 is deposited on workpiece 200 , including on top of the sidewalls and bottom 210B of stack 204 in Regions I and II. In some embodiments, the composition of cladding layer 220 may be similar to the composition of top sacrificial layer 206T or sacrificial layer 206. In one example, the coating layer 220 may be composed of silicon germanium. The above common composition allows the subsequent etching process to selectively remove the sacrificial layer 206 and the cladding layer 220 simultaneously. In some embodiments, vapor phase epitaxy or molecular beam epitaxy may be used to compliantly epitaxially grow the coating 220 . As shown in FIGS. 7A-7D , cladding 220 may be selectively located on exposed sidewall surfaces in fin trenches 212 . Depending on the selective growth amount of the cladding layer 220, an etch back process may be performed to expose the isolation structure 216.

An example process of forming the dielectric fins 218 may further include sequentially depositing the first dielectric layer 222 and the second dielectric layer 224 on the workpiece 200 . The first dielectric layer 222 may surround the second dielectric layer 224. The first dielectric layer 222 may be conformally deposited using chemical vapor deposition, atomic layer deposition, or a suitable method. The first dielectric layer 222 lines the sidewalls and lower surface of the fin trench 212 . Then chemical vapor deposition, high density plasma chemical vapor deposition, flowable chemical vapor deposition, and/or other suitable processes may be used. The second dielectric layer 224 is compliantly deposited on the first dielectric layer 222 . In some examples, the dielectric constant of second dielectric layer 224 is less than the dielectric constant of first dielectric layer 222 . The first dielectric layer 222 may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, oxide hafnium, or other suitable dielectric material. In one embodiment, first dielectric layer 222 includes aluminum oxide. The second dielectric layer 224 may include silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbonitride, or other suitable dielectric materials. In one embodiment, second dielectric layer 224 includes silicon oxide. As shown in some examples in FIGS. 8A to 8D , a chemical mechanical polishing process is performed after depositing the first dielectric layer 222 and the second dielectric layer 224 to remove excess material and planarize the upper surface of the workpiece 200 to expose the top. Sacrificial layer 206T.

An example process for forming dielectric fins 218 may further include depositing a high-k dielectric layer 226 . In some examples, a recessing process is performed to remove the tops of the first dielectric layer 222 and the second dielectric layer 224 . The recessing process may include a dry etching process, a wet etching process, and/or a combination of the above. In some embodiments, the depth of the recess step is controlled (eg, by controlling the etching time) to achieve a desired recess depth. After performing the recessing process, a high-k dielectric layer 226 may be deposited in the trench formed by the recessing process. In some embodiments, high-k dielectric layer 226 may include hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, yttria, aluminum oxide, or another high-k material. The high-k dielectric layer 226 may be deposited by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, and/or other suitable processes. The high-k dielectric layer described herein includes a dielectric material whose dielectric constant is greater than the dielectric constant of thermally oxidized silicon (approximately 3.9). As shown in FIGS. 9A to 9D , after depositing the high-k dielectric layer 226 , a chemical mechanical polishing process may be performed to remove excess material and planarize the upper surface of the workpiece 200 . Once step 112 is completed, the lower portion of dielectric fin 218 (containing the recessed portions of first dielectric layer 222 and second dielectric layer 224) and the upper portion (containing the high dielectric constant dielectric layer 226). Dielectric fins 218 may also be considered hybrid fins.

As shown in Figures 10A-10D, step 114 (Figure 1A) of method 100 removes top sacrificial layer 206T in fin structure 210. Step 114 etch workpiece 200 to selectively remove a portion of top sacrificial layer 206T and capping layer 220 to expose topmost channel layer 208 without substantially damaging dielectric fins 218 . In some embodiments, since the composition of the top sacrificial layer 206T and the cladding layer 220 is silicon germanium, the etching process in step 114 may be selective to silicon germanium. For example, a selective wet etching process may be used to etch the capping layer 220 and the top sacrificial layer 206T, including using ammonium hydroxide, hydrofluoric acid, hydrogen peroxide, or a combination thereof. After removing the top sacrificial layer 206T and a portion of the cladding layer 220, the dielectric fin 218 is raised above the topmost channel layer 208.

As shown in FIGS. 11A to 11D , step 116 ( FIG. 1A ) of the method 100 forms a dummy gate stack 240 on the channel region of the fin structure 210 . In some embodiments, a gate replacement process (or gate post-processing process) is used, in which the dummy gate stack 240 serves as a placeholder for the functional gate structure. Other processes and settings are also possible. In the embodiment, the dummy gate stack 240 includes a dummy dielectric layer 242 and a dummy gate 244 located on the dummy dielectric layer 242 . A gate top hard mask 246 may be deposited on dummy gate stack 240 for patterning purposes. The gate top hard mask 246 may be multi-layered and may include a silicon nitride mask layer 248 and a silicon oxide mask layer 250 located on the silicon nitride mask layer 248 . The area of the fin structure 210 under the dummy gate stack 240 can be regarded as a channel area. The channel regions in the fin structure 210 are each sandwiched between two source/drain regions. The source/drain regions are used to form the source/drain as described below. In an example process, the dummy dielectric layer 242 may be blanket deposited on the workpiece 200 by chemical vapor deposition. Then, a layer of material used for the dummy gate 244 is blanket deposited on the dummy dielectric layer 242 . Then, a photolithography process may be used to pattern the material layers used for the dummy dielectric layer 242 and the dummy gate 244 to form the dummy gate stack 240 . In some embodiments, dummy dielectric layer 242 may include silicon oxide and dummy gate 244 may include polysilicon.

As shown in FIGS. 11A-11D , step 118 of method 100 ( FIG. 1A ) forms gate spacers 252 along the sidewalls of dummy gate stack 240 . Gate spacer 252 may include two or more gate spacer layers. The dielectric material used for gate spacers 252 is selected to selectively remove dummy gate stack 240 . Suitable dielectric materials may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarb, silicon carbide, silicon oxynitride, and/or combinations thereof. In an example process, chemical vapor deposition, sub-pressure chemical vapor deposition, or atomic layer deposition may be used to conformally deposit the gate spacer 252 on the workpiece 200, and then anisotropically etch the gate spacer 252 to The horizontal portions are removed leaving the vertical portions of the gate spacers 252 on the sidewalls of the dummy gate stack 240 .

As shown in FIGS. 12A to 12D , step 120 of the method 100 ( FIG. 1A ) recesses the source/drain regions of the fin structure 210 to form source recesses and drain recesses (which may be collectively referred to as source/drain recesses). Trench or source/drain recess 254). Using the dummy gate stack 240 and gate spacers 252 as etching masks, the workpiece 200 can be anisotropically etched to form source/drain recesses 254 on the source/drain regions of the fin structure 210 . In the illustrated embodiment, step 118 removes the sacrificial layer 206, the channel layer 208, and the capping layer 220 from the source/drain regions in Region I and Region 11 to expose bottom 210B. The anisotropic etching in step 120 may include a dry etching process. For example, the dry etching process can be carried out using hydrogen, fluorine-containing gases (carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and/or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, Carbon tetrachloride, and/or boron trichloride), bromine-containing gases (such as hydrogen bromide and/or bromoform), iodine-containing gases, other suitable gases and/or plasma, and/or combinations of the above.

As shown in Figures 13A-13D, step 122 of method 100 forms inboard spacer structure 258. In some embodiments, step 122 first selectively recesses the exposed portion of the sacrificial layer 206 in the source/drain recess 254 to form an inner spacer recess without substantially etching the exposed channel layer 208 . In one embodiment, the channel layer 208 is substantially composed of silicon, and the sacrificial layer 206 is substantially composed of silicon germanium, then The process of selectively recessing portions of the sacrificial layer 206 may include a silicon germanium oxidation process followed by a silicon germanium oxide removal process. In this embodiment, the silicon germanium oxidation process may include the use of ozone. In some other embodiments, the step of partially recessing may include a selective etching process such as selective dry etching or selective wet etching, and the amount of recessing of the sacrificial layer 206 may be controlled by the time of the etching process. The selective dry etching process may use one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include ammonium hydroxide, hydrofluoric acid, hydrogen peroxide, or a combination thereof (APM etching includes a mixture of ammonium hydroxide, hydrogen peroxide, and water.). After forming the inner spacer recess, chemical vapor deposition or atomic layer deposition may be used to compliantly deposit an inner spacer material layer on the workpiece 200 , including in and on the inner spacer recess. The inner spacer material may include silicon nitride, silicon oxycarbonitride, silicon nitride carbonitride, silicon oxide, silicon oxycarb, silicon carbide, or silicon oxynitride. After depositing the inner spacer material layer, the inner spacer material layer may be etched back to form inner spacer structures 258, as shown in Figures 13A-13D.

As shown in Figures 13A-13D, step 124 of method 100 forms source/drain structure 260. Source/drain structure 260 may be selectively epitaxially deposited on bottom 210B of source/drain recess 254 and on the exposed semiconductor surface of channel layer 208 . The source/drain structure 260 may be deposited using an epitaxial process, such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and/or other suitable processes. Source/drain structure 260 may include germanium, silicon, gallium arsenide, aluminum gallium arsenide, silicon germanium, gallium arsenide phosphide, silicon phosphide, or other suitable materials. In some embodiments, the source/drain structure 260 can be doped in situ during the epitaxial process. For example, the epitaxially grown silicon germanium source/drain structures of some embodiments may be doped with boron. In some examples, the epitaxial source/drain structure of epitaxially grown silicon can be doped with carbon to form a carbon-doped silicon source/drain structure, and can be doped with phosphorus to form a phosphorus-doped silicon source/drain structure. drain structure, or doped with carbon and phosphorus to form a silicon source/drain structure doped with carbon and phosphorus. In some embodiments, the source/drain structure 260 is not doped in situ, but instead a implantation process is performed to dope the source/drain structure 260 . The etching process can include dry etching, wet etching, Reactive ion etching, and/or other suitable processes.

As shown in FIGS. 14A to 14D , step 126 of method 100 ( FIG. 1A ) deposits contact etch stop layer 270 and interlayer dielectric layer 272 on workpiece 200 . In an example process, the contact etch stop layer 270 is first conformably deposited on the workpiece 200 , and then the interlayer dielectric layer 272 is blanket deposited on the contact etch stop layer 270 . Contact etch stop layer 270 may include silicon nitride, silicon oxide, silicon oxynitride, and/or other materials known in the art. The contact etch stop layer 270 may be deposited using atomic layer deposition, plasma-assisted chemical vapor deposition, and/or other suitable deposition or oxidation processes. In some embodiments, interlayer dielectric layer 272 includes a material such as tetraethoxysilane oxide, undoped silicate glass, or doped silicate oxide (eg, borophosphosilicate glass, fluorosilicate Glass, phosphosilicate glass, borosilicate glass, and/or other suitable dielectric materials. The deposition method of the interlayer dielectric layer 272 may be spin coating, flowable chemical vapor deposition, or other suitable Deposition technology. In some embodiments, after forming the interlayer dielectric layer 272, the workpiece 200 may be annealed to improve the integrity of the interlayer dielectric layer 272. In order to remove excess material (including the gate top hard mask 246) and expose the dummy gate On the upper surface of the dummy gate 244 of the electrode stack 240, a planarization process such as a chemical mechanical polishing process can be performed on the workpiece 200 to provide a flat upper surface.

As shown in Figures 15A-15D, step 128 (Figure 1A) of method 100 selectively removes dummy gate stack 240. The dummy gate stack 240 exposed in step 126 may be removed from the workpiece 200 by a selective etching process. The selective etching process may be a selective wet etching process, a selective dry etching process, or a combination of the above. In the embodiment, the selective etching process can selectively remove the dummy dielectric layer 242 and the dummy gate 244 without substantially damaging the channel layer 208 and the gate spacer 252 . Removal of dummy gate stack 240 causes gate trench 266 to be located over the channel region. After the dummy gate stack 240 is removed, the channel layer 208, the sacrificial layer 206, and the cladding layer 220 in the channel region are exposed in the gate trench 266.

As shown in Figures 16A-16D, step 130 (Figure 1A) of method 100 moves from gate trench 266 The sacrificial layer 206 and the cladding layer 220 are removed to release the channel layer 208. A comprehensive etching process may be performed to selectively remove the sacrificial layer 206 and the cladding layer 220 . As mentioned above, the annealing process of step 106 can diffuse the p-type dopant in the p-type well into the sacrificial layer 206 in region I, and diffuse the n-type dopant in the n-type well into the sacrificial layer 206 in region II. . As a result, the sacrificial layer 206 in region I has a first etching rate, the sacrificial layer 206 in region II has a second etching rate, and the second etching rate is different from the first etching rate. During the etching process, the sacrificial layer 206 and the cladding layer 220 can be removed. The thickness t3 of the released channel layer 208 in Region I is about 8 nm to about 12 nm. The thickness t4 of the released channel layer 208 in region II is about 9 nm to about 13 nm. Thickness t4 may be about 0.3 nm to about 0.8 nm (eg, about 0.5 nm) greater than thickness t3. The thickness difference comes from the different etching rates of the differently doped sacrificial layers. For example, the etching rate of the sacrificial layer 206 in region I is greater than the etching rate of the sacrificial layer 206 in region II. After removing all of the sacrificial layer 206 in Region I, the etchant may remove a portion of the channel layer 208 in Region I. This causes the thickness t4 of the channel layer 208 in region II to be greater than the thickness t4 of the channel layer 208 in region I. The thickness difference of the channel layer 208 can balance the drain-induced energy barrier reduction with the effective drive current to improve device speed. Furthermore, the physical height of the n-type MOSFET and p-type MOSFET devices is not affected because the step of etching the sacrificial layer 206 results in the thickness of the channel layer 208 .

The channel layer 208 released in step 130 can also be regarded as a channel component. In the embodiment, the channel components such as the channel layer 208 are in the form of sheets or nanosheets, and the channel component release process can also be regarded as a sheet forming process. Channel components such as channel layer 208 may be vertically stacked along the Z direction. All channel components such as channel layer 208 and dielectric fins 218 are laterally separated by a distance defined by the thickness of cladding layer 220 . The implementation of selectively removing the sacrificial layer 206 and the cladding layer 220 may be selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etch includes ammonium hydroxide, hydrogen fluoride, hydrogen peroxide, or a combination thereof (APM etch may include a mixture of ammonium hydroxide, hydrogen peroxide, and water). In some other embodiments, the selective removal includes silicon germanium oxide, followed by removal of the silicon germanium oxide. For example said that after ozone cleaning provides oxidation, an etchant such as ammonium hydroxide can be used to remove the silicon germanium oxide.

As shown in FIGS. 17A-17D , step 132 of method 100 (FIG. 1B) forms gate structure 274 in gate trench 266 to engage channel components such as channel layer 208. The gate structure 274 can also be regarded as a functional gate structure or a metal gate structure. In regions I and II, individual gate structures 274 may cover each channel component such as channel layer 208. Gate structures 274 may each include a gate dielectric layer 276 on a channel component such as channel layer 208 , and a gate layer 278 on gate dielectric layer 276 . In some embodiments, the gate dielectric layer 276 includes an interface layer and a high-k dielectric layer. The interface layer may include silicon oxide, which may be formed by a pre-cleaning process. Examples of pre-cleaning processes may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and/or RCA SC-2 (hydrogen chloride, hydrogen peroxide, and water). The pre-cleaning process may oxidize the exposed surfaces of channel components such as channel layer 208 to form an interface layer.

Then, atomic layer deposition, chemical vapor deposition, and/or other suitable methods are used to deposit a high-k dielectric layer on the interface layer. The high-k dielectric layer may include a high-k dielectric material. In one embodiment, the high-k dielectric layer may include hafnium oxide. The high-k dielectric layer may instead include other high-k dielectric layers, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium dioxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide , zirconium oxide, yttrium oxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, silicon nitride, oxynitride Silicon, combinations of the above, or other suitable materials. After gate dielectric layer 276 is formed, gate layer 278 may be deposited on gate dielectric layer 276 . The gate layer 278 may be a multi-layer structure including at least one work function layer and a metal filling layer. For example, the at least one work function layer may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, or tantalum carbide. The metal filling layer may include aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum silicon nitride, copper, other refractory metals, other suitable metal materials, or combinations thereof. In various embodiments, gate layer 278 The formation method may be atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. Although not shown, gate structure 274 such as a bond gate structure may be deposited and then etched back until dielectric fins 218 separate the bond gate structure into separate gate structures 274. Dielectric fins 218 may also provide electrical isolation between adjacent gate structures 274 . The step of etching back the gate structure 274 may include a selective wet etching process, which may use nitric acid, hydrogen chloride, sulfuric acid, ammonium hydroxide, hydrogen peroxide, or a combination thereof. Although in the described embodiment, the upper surface of the gate structure 274 after the etch-back process may be flush with the lower surface of the high-k dielectric layer 226 , other embodiments may have the upper surface of the gate structure 274 after the etch-back process be flush with the lower surface of the high-k dielectric layer 226 . The surface may be lower than the lower surface of the high-k dielectric layer 226 . The method of etching back the gate structure 274 may also include etching back the high-k dielectric layer 226 of the dielectric fin 218 in the channel region.

As shown in FIGS. 18A to 18D , step 134 ( FIG. 1B ) of the method 100 forms a metal capping layer 280 , a self-aligned capping layer 282 , and a gate cutting structure 284 on the front side of the workpiece 200 . In some embodiments, the metal capping layer 280 may include titanium, titanium nitride, tantalum nitride, tungsten, ruthenium, cobalt, or nickel, and its deposition method may use physical vapor deposition, chemical vapor deposition, or organic metal deposition. Chemical vapor deposition. In one embodiment, the metal capping layer 280 includes tungsten, such as fluorine-free tungsten, and its deposition method may be physical vapor deposition. In some other embodiments, the metal capping layer 280 is deposited by organic metal chemical vapor deposition to selectively deposit the metal capping layer 280 on the gate structure 274 . After the metal capping layer 280 is deposited, the self-aligned capping layer 282 can be deposited on the workpiece 200, and the deposition method can be chemical vapor deposition, plasma-assisted chemical vapor deposition, or other suitable deposition processes. The self-aligned capping layer 282 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, Zirconium aluminum oxide, hafnium oxide, or other suitable dielectric material. Then, a photolithography process and an etching process are performed to etch the deposited self-aligned capping layer 282 to form a gate cap opening to expose the upper surface of the dielectric fin 218 surface, including removing the high-k dielectric layer 226 . The dielectric material may then be deposited and planarized using a chemical mechanical polishing process to form gate cut structures 284 in the gate cut openings. The dielectric material of the gate cutting structure 284 may be deposited using high-density plasma chemical vapor deposition, chemical vapor deposition, atomic layer deposition, or a suitable deposition technology. In some examples, the gate cutting structure 284 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, Zirconium nitride, zirconium aluminum oxide, hafnium oxide, or other suitable dielectric material. In some embodiments, the gate cut structure 284 and the self-aligned capping layer 282 may have different compositions to introduce etch selectivity.

As shown in FIGS. 18A to 18D , step 136 ( FIG. 1B ) of the method 100 performs subsequent manufacturing processes on the workpiece 200 . For example, back-end processes may be performed to form interconnect layers such as front-side power rails on the front side of the workpiece 200 . In one embodiment, a damascene process, a dual damascene process, a metal patterning process, or other suitable processes may be used to form the front-side power rail. The front-side power rail can include tungsten, cobalt, molybdenum, ruthenium, copper, nickel, titanium, tantalum, titanium nitride, tantalum nitride, or other metals, and its deposition method can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or other suitable processes. Step 136 may also include forming a passivation layer on the front side of the workpiece 200, performing other back-end processes, and removing the backside carrier.

As shown in FIGS. 18A to 18D , once the method 100 is completed, a plurality of fully wound gate transistors can be formed in the regions I and II respectively. All-wound gate transistors may each include a gate structure 274 to engage one or more channel components such as channel layer 208 . Adjacent fully wound gate transistors may be electrically separated from each other by dielectric fins 218 and gate cut structures 284 landing on the dielectric fins 218 . Specifically, the channel components, such as the channel layer 208, of the fully wound gate transistor in Region I are thinner than the channel components, such as the channel layer 208, of the fully wound gate transistor in Region II, thereby balancing device performance such as drain. Extremely induced energy barrier decrease and effective driving current. This performance balance facilitates improved speed performance in complementary metal-oxide-semiconductor devices. By achieving the difference in thickness of the channel components through etching, the thickness can be better controlled without affecting the n-type metal oxide half region and p-type metal oxide half region. Energy barrier load (such as device height) between regions, which may occur when the epitaxial growth process is used to control thickness.

The invention provides many different embodiments. For example, a method for forming a semiconductor device provided by an embodiment of the present invention includes forming p-type wells and n-type wells in a substrate. The method further includes forming a stack of a plurality of staggered first semiconductor material layers and a plurality of second semiconductor material layers on the p-type well and the n-type well, the first semiconductor material layer having a first thickness, and the second semiconductor material layer Has a second thickness, and the second thickness is different from the first thickness. The method further includes annealing the stack of alternating first and second semiconductor material layers. In some embodiments, the method further includes patterning the stack to form a plurality of fin structures, the fin structures including a first fin structure on the n-type well and a second fin structure on the p-type well. The method further includes performing an etching process to remove the second semiconductor material layer from the first fin structure and the second fin structure, wherein the first semiconductor material layer and the second fin structure in the first fin structure after the etching process The first semiconductor material layer in has a different thickness. The method further includes forming a metal gate on the first fin structure and the second fin structure.

In some embodiments, the ratio of the first thickness to the second thickness is about 1.4 to about 1.5.

In some embodiments, the annealing step diffuses a plurality of first dopants in the n-type well into a second layer of semiconductor material over the p-type well and diffuses a plurality of second dopants in the p-type well into the layer over the n-type well. in the second semiconductor material layer.

In some embodiments, the first dopant reduces the etch rate of the second layer of semiconductor material over the p-type well.

In some embodiments, the etching step further includes etching a portion of the first semiconductor material layer on the p-type well after removing the second semiconductor material layer on the p-type well.

In some embodiments, the etching process is a comprehensive etching process, which is performed simultaneously with the first On the fin-like structure and the second fin-like structure.

In some embodiments, forming the p-type well further includes performing an ion implantation process to dope boron or boron tetrafluoride into the substrate.

In another embodiment, a method of forming a semiconductor device includes receiving a substrate including a p-type well and an n-type well. The method further includes forming a plurality of semiconductor layers stacked on the p-type well and the n-type well of the substrate. The stack of semiconductor layers includes a plurality of staggered first semiconductor material layers and a plurality of second semiconductor material layers. In some embodiments, the method further includes performing an annealing process on the stack of semiconductor layers to drive dopants from the p-type well into the second semiconductor material layer above the p-type well. The method further includes etching the stack of semiconductor layers to form a first fin structure on the p-type well and a second fin structure on the n-type well. In some examples, the method further includes removing a second semiconductor material layer from the first fin structure and the second fin structure, wherein the first semiconductor material layer in the first fin structure after removing the second semiconductor material layer is different from the thickness of the first semiconductor material layer in the second fin structure.

In some embodiments, removing the second semiconductor material layer further includes simultaneously removing a first portion of the second semiconductor material layer from the first fin structure and removing the second semiconductor material layer from the second fin structure. a second portion, wherein a removal rate of the first portion is greater than a removal rate of the second portion; and removing a portion of the first semiconductor material layer from the first fin structure.

In some embodiments, the method further includes removing a portion of the first semiconductor material layer of the first fin structure until the first semiconductor material layer of the first fin structure is thinner than the first semiconductor material layer of the second fin structure. About 0.5nm.

In some embodiments, the annealing process further includes driving dopants from the n-type well into the second semiconductor material layer above the n-type well.

In some embodiments, forming the stack of semiconductor layers further includes forming a first thick a first semiconductor material layer of a second thickness; and forming a second semiconductor material layer of a second thickness, wherein the first thickness is greater than the second thickness.

In some embodiments, the first thickness is about 1.4 times to about 1.5 times greater than the second thickness.

In some embodiments, the method further includes forming three first semiconductor material layers.

In yet another embodiment, a semiconductor device includes a substrate. The semiconductor device further includes a first fin structure located on the first region of the substrate and including a first group of a plurality of first channel layers, and each of the first channel layers has a first thickness. The device further includes a second fin structure located on the second region of the substrate and including a second group of a plurality of second channel layers, each of the second channel layers having a second thickness, and the second thickness is greater than the first thickness. In some embodiments, the semiconductor device further includes a gate structure located on the first fin structure and the second fin structure and covering the first group of first channel layers and the second group of second channel layers.

In some embodiments, the first region further includes a p-type well located in the substrate and under the first fin structure.

In some embodiments, the second region further includes an n-type well located in the substrate and under the second fin structure.

In some embodiments, the semiconductor device further includes a distance between the second channel layers of the second fin structure, and the second thickness is approximately 1.4 times greater than the distance.

In some embodiments, the first thickness is less than about 1.4 times greater than the distance.

In some embodiments, the first fin-shaped structure and the second fin-shaped structure are of the same height.

The features of the above embodiments are helpful for those with ordinary skill in the art to understand the present invention. Those with ordinary skill in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purposes and/or the same advantages of the above embodiments. Those with ordinary knowledge in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and may be used in the future. Changes, substitutions, or alterations may be made without departing from the spirit and scope of the invention.

D-D: section line

200:Artifact

202:Substrate

208: Channel layer

252: Gate spacer

258:Inner spacer structure

260: Source/drain structure

270: Contact etch stop layer

272:Interlayer dielectric layer

274: Gate structure

276: Gate dielectric layer

278: Gate layer

280:Metal cover

282:Self-aligned cover

Claims (10)

A method of forming a semiconductor device, including: forming a p-type well and an n-type well in a substrate; forming a stack of a plurality of staggered first semiconductor material layers and a plurality of second semiconductor material layers in the p-type well On the n-type well, the first semiconductor material layers have a first thickness, the second semiconductor material layers have a second thickness, and the second thickness is different from the first thickness; the annealing staggered The stack of a semiconductor material layer and the second semiconductor material layers; patterning the stack to form a plurality of fin structures, the fin structures including a first fin structure on the n-type well and a second fin -like structure on the p-type well; perform an etching process to remove the second semiconductor material layers from the first fin-like structure and the second fin-like structure, wherein the first fin-like structure after the etching process The thicknesses of the first semiconductor material layers and the first semiconductor material layers in the second fin-shaped structure are different; and a metal gate is formed on the first fin-shaped structure and the second fin-shaped structure. The method of forming a semiconductor device as claimed in claim 1, wherein a ratio of the first thickness to the second thickness is about 1.4 to about 1.5. The method of forming a semiconductor device as claimed in claim 1 or 2, wherein the annealing step causes the plurality of first dopants in the n-type well to diffuse into the second semiconductor material layers on the n-type well, and causes the p-type well to A plurality of second dopants are diffused into the second semiconductor material layers on the p-type well. The method of forming a semiconductor device according to claim 3, wherein the first dopants reduce the etching rate of the second semiconductor material layers on the n-type well. A method of forming a semiconductor device includes: receiving a substrate including a p-type well and an n-type well; Forming a stack of a plurality of semiconductor layers on the p-type well and the n-type well of the substrate, the stack of the semiconductor layers includes a plurality of staggered first semiconductor material layers and a plurality of second semiconductor material layers; The stack of semiconductor layers undergoes an annealing process to drive dopants from the p-type well into the second semiconductor material layers on the p-type well; the stack of semiconductor layers is etched to form a first fin a second fin-shaped structure on the p-type well, and form a second fin-shaped structure on the n-type well; and remove the second semiconductor material layers from the first fin-shaped structure and the second fin-shaped structure, wherein The thickness of the first semiconductor material layers in the first fin-shaped structure behind the second semiconductor material layers is different from the thickness of the first semiconductor material layers in the second fin-shaped structure. The method of forming a semiconductor device according to claim 5, wherein the step of removing the second semiconductor material layers further includes: simultaneously removing a first portion of the second semiconductor material layers from the first fin structure, and The second fin structure removes a second portion of the second semiconductor material layers, wherein the removal rate of the first portion is greater than the removal rate of the second portion; and removing the first portion from the first fin structure part of the first layers of semiconductor material. The method of forming a semiconductor device according to claim 6, further comprising removing the portion of the first semiconductor material layers of the first fin-shaped structure until the first semiconductor material layers of the first fin-shaped structure are smaller than the first semiconductor material layers of the first fin-shaped structure. The first semiconductor material layers of the second fin-shaped structure are about 0.5nm thin. A semiconductor device includes: a substrate; a first fin-shaped structure located on a first area of the substrate and including a first group of a plurality of first channel layers, and each of the first channel layers has a first a thickness, wherein the first channel layers have a p-type doping quality; a second fin-shaped structure located on a second area of the substrate and including a second group of a plurality of second channel layers, each of the second channel layers has a second thickness, and the second thickness Greater than the first thickness, wherein the second channel layers have an n-type dopant; and a gate structure is located on the first fin structure and the second fin structure and covers the first group the first channel layers and the second group of second channel layers. The semiconductor device of claim 8, wherein the first region further includes a p-type well located in the substrate and under the first fin structure. The semiconductor device of claim 8 or 9, wherein the second region further includes an n-type well located in the substrate and under the second fin structure.

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