TWI801864B - Semiconductor devices and methods for forming the same - Google Patents

Abstract

A semiconductor device includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.

Description

Semiconductor device and method of forming the same

Embodiments of the present invention relate to a semiconductor device and its forming method, and in particular to a multi-gate device and its forming method.

The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each with smaller and more complex circuits than the previous generation. During the evolution of integrated circuits, functional density (ie, the number of interconnected devices per die area) has generally increased while geometry size (ie, the smallest element (or line) that can be produced using a process) has decreased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of IC manufacturing and process.

For example, as integrated circuit (IC) technology has evolved towards smaller technology nodes, multi-gate devices have been introduced to reduce off-state current (OFF-state) by increasing gate-channel coupling. current) and reduce short-channel effects (SCEs) to improve gate control. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed on more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become ideal for high-performance and low-leakage current applications. Mainstream and promising candidates. FinFETs have an elevated channel with the gate wrapping around more than one side of the channel (eg, the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from the substrate). The gate structure of the MBC transistor may extend partially or completely around the channel region to provide access to two or more sides of the channel region. Since the gate structure of the MBC transistor surrounds the channel region, the MBC transistor can also be called a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of the MBC transistor can be formed by nanowires, nanosheets, other nanostructures and/or other suitable structures.

The implementation of multiple gate transistors reduces device size and increases device packaging density, which presents challenges in forming power and signal routing. Although existing source/drain contact structures are generally adequate for their intended purpose, they are not satisfactory in all respects.

Some embodiments of the present invention provide a semiconductor device, comprising: a first interconnection structure; a first transistor on the first interconnection structure and comprising: a first nanostructure; and a first source element adjoining a first nanostructure; a second transistor on the first transistor and comprising: the second nanostructure; and a second source feature adjacent to the second nanostructure; and a second interconnect structure on the second On the transistor, wherein the first source feature is coupled to the first power rail in the first interconnect structure, and the second source feature is coupled to the second power rail in the second interconnect structure.

Still other embodiments of the present invention provide a semiconductor device, comprising: a first interconnection structure; a first transistor on the first interconnection structure and comprising: a first nanostructure; and a first source element adjacent to the first a nanostructure; a second transistor on the first transistor and comprising: the second nanostructure; and a second source feature adjacent to the second nanostructure; and a second interconnect structure on the second transistor , wherein the first source feature is coupled to the first power rail in the first interconnect structure, and the second source feature is coupled to the second power rail in the first interconnect structure.

Still other embodiments of the present invention provide a method of forming a semiconductor device, including: receiving a workpiece, the workpiece includes a first substrate and a first stack on the first substrate, the first stack includes first sacrificial layers interleaved with a first plurality of sacrificial layers A plurality of channel layers; a first fin structure is formed by the first stack and part of the first substrate, the first fin structure includes a first source region and a first drain region; a first mixed fin and a second mixing fins, a first mixing fin and a second mixing fin extending parallel to the first fin structure, the first mixing fin comprising a first conductive component embedded in a first dielectric component, and the second mixing fin The fin includes a second conductive feature embedded in a second dielectric feature; a first source feature is formed on the first source region, and a first drain feature is formed on the first drain region; a second drain feature is formed on the first drain region; A source contact, the first source contact directly contacts the first source part and the first conductive part; a first drain contact is formed, the first drain contact directly contacts the first drain part; at the first a source contact and a capping layer deposited on the first drain contact; bonding a second stack on the capping layer, the second stack including a second plurality of channel layers interleaved with a second plurality of sacrificial layers; by The second stack forms a second fin structure, the second fin structure includes a second source region and a second drain region; forms a third mixed fin and a fourth mixed fin, the third mixed fin and the fourth mixed fin The fins extend parallel to the second fin structure, the third hybrid fin includes a third conductive feature embedded in the third dielectric feature, and the fourth hybrid fin includes a third conductive feature embedded in the fourth dielectric feature. forming a second source feature on the second source region, and forming a second drain feature on the second drain region; forming a second source contact, the second source contact directly contacting the second source feature and the third conductive feature; and forming a second drain contact, the second drain contact directly contacting the second drain feature.

The following provides many different embodiments or examples to implement different components of the disclosed embodiments. Specific examples of components and configurations are described below to simplify embodiments of the disclosure. Of course, these are just examples and are not intended to limit the embodiments of the present disclosure. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired characteristics of the device. In addition, in the following description, it is mentioned that the first part is formed on or on the second part, which may include an embodiment in which the first part and the second part are formed in direct contact, and may also include an embodiment where the first part and the second part are formed. An embodiment in which an additional part is formed between the second part so that the first part and the second part may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.

Furthermore, terms relative to space may be used, such as "below", "below", "lower", "above", "higher", etc., for the convenience of description The relationship between one component or feature(s) and another component(s) or feature(s) in a drawing. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein shall also be interpreted in accordance with the turned orientation.

Furthermore, when the words "about", "approximately" and similar terms are used to describe numbers or numerical ranges, the values that the words are intended to cover include the described numbers within a reasonable range, such as +/-10% of the stated number within, or other values understood by those skilled in the art to which the present invention pertains. For example, a material layer having a thickness of "about 5 nanometers" may cover a size range from 4.25 nanometers to 5.75 nanometers, which is known to those of ordinary skill in the art and with manufacturing tolerances associated with deposited material layers of + /–15%. In addition, the embodiments of the present invention may repeat element symbols and/or letters in many instances. These repetitions are for the purposes of simplicity and clarity and do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed. Some variations of the embodiment are described below.

The high packing density achieved by using MBC transistors creates challenges in forming satisfactory power and signal routing structures and components. To meet these challenges, the present disclosure provides embodiments that utilize different combinations of contact structure schemes to achieve flexibility and density of power and signal routing. When the second MBC transistor is disposed above the first MBC transistor, the contact structure scheme according to the present disclosure includes, for example, a dual interconnect structure, a hybrid fin with embedded conductive components, and a bias Set (offset) device stack. In a "dual interconnect structure", the source part of the first MBC transistor is coupled to the power rail in the first interconnect structure through the backside source contact, and the source part of the second MBC transistor is coupled to the A power rail in the second interconnect structure above the second MBC transistor. In "hybrid fins with embedded conductive features", conductive features are embedded in each hybrid fin to provide contact modules that serve as conductive paths to interconnect structures. In a "biased device stack", the source/drain regions of the first and second MBC transistors are biased against each other to increase the spacing between the contact vias and the drain features.

Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, FIGS. 1 , 18 and 36 are flowcharts of methods 100 , 300 and 500 for forming semiconductor devices from workpieces according to embodiments of the present disclosure. Methods 100 , 300 , and 500 are examples only, and are not intended to limit the present disclosure to what is explicitly shown in methods 100 , 300 , and 500 . Additional steps may be provided before, during, and after methods 100, 300, and 500, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the methods. For simplicity, this disclosure does not describe all steps in detail. Methods 100, 300 and 500 are described below in conjunction with Figures 2-10, 11A-17A, 11B-17B, 19-28, 29A-35A, 29B-35B, 37-44, 45A-50A, 45B-50B, No. 2 - Figures 10, 11A-17A, 11B-17B, 19-28, 29A-35A, 29B-35B, 37-44, 45A-50A, 45B-50B are according to embodiments of methods 100, 300 and 500, in manufactured Partial cross-sectional views of workpieces in different stages. To better illustrate various aspects of the present disclosure, each figure ending with a capital letter A depicts a partial cross-sectional view of a source region, and each figure ending with a capital letter B depicts a partial cross-section of a drain region picture. Additionally, the present disclosure provides a method 600 for forming a common gate structure that activates two vertically aligned MBC transistors. The method 600 shown in Figure 52 is described below in conjunction with the cross-sectional views in Figures 53-57. Method 600 can be used with at least methods 100 and 300 .

Referring to FIGS. 1 and 2 , the method 100 includes a step 102 of providing a workpiece 200 . It should be understood that since workpiece 200 is to be fabricated into a semiconductor device, workpiece 200 may also be referred to as semiconductor device 200 as the context requires. The workpiece 200 may include a substrate 202 . Although not explicitly shown in the drawings, the substrate 202 may include n-type well regions and p-type well regions for fabricating transistors of different conductivity types. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP) and indium gallium arsenide (InGaAs). The substrate 202 may further include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. When present, each n-type well and p-type well is formed in the substrate 202 and includes a doping profile. The n-type well may include a doping profile of n-type dopants such as phosphorous (P) or arsenic (As). The p-type well may include p-type dopants such as a doping profile of boron (B). Ion implantation or thermal diffusion can be used to form the doping of the n-type well and the p-type well and can be considered as part of the substrate 202 . For the avoidance of doubt, the X-direction, Y-direction and Z-direction are perpendicular to each other.

As shown in FIG. 2 , the workpiece 200 also includes a first stack 204 disposed over the substrate 202 . The first stack 204 includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206 . The channel layer 208 and the sacrificial layer 206 may have different semiconductor compositions. In some embodiments, the channel layer 208 is formed of silicon (Si), and the sacrificial layer 206 is formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer 206 allows selective removal or etchback of the sacrificial layer 206 with substantially no damage to the channel layer 208 . In some embodiments, the sacrificial layer 206 and the channel layer 208 are epitaxial layers and may be deposited using an epitaxial process. Suitable epitaxy processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE) ) and/or other suitable processes. As shown in FIG. 2 , sacrificial layers 206 and channel layers 208 are alternately deposited one after the other to form the first stack 204 . It should be understood that, as shown in FIG. 2 , three layers of sacrificial layers 206 and three layers of channel layers 208 are arranged alternately and vertically, and their configuration is only for illustration purposes, and is not intended to limit the content specifically described in the claims. It should be understood that any number of sacrificial layers 206 and channel layers 208 may be formed in the first stack 204 . The number of layers depends on the desired number of channel members of the semiconductor device 200 . In some embodiments, the number of channel layers 208 is between 2-10.

Referring to FIG. 1 and FIG. 3 , the method 100 includes a step 104 of forming a first fin structure 209 from the first stack 204 . In some embodiments, the first stack 204 and a portion of the substrate 202 are patterned to form the first fin structure 209 . A hard mask layer may be deposited on the first stack 204 for patterning purposes. A hard mask layer can be a single layer or multiple layers. In some examples, the hard mask layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. As shown in FIG. 3 , the first fin structure 209 extends vertically from the substrate 202 along the Z direction, and extends lengthwise along the Y direction. The first fin structure 209 includes a base portion 209B formed from the substrate 202 and a stack portion 209S formed from the first stack 204 . A suitable process, including a double patterning or multiple patterning process, may be used to pattern the first fin structure 209 . Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes to create, for example, finer pitch patterns than can be obtained using a single, direct lithography process. For example, in one embodiment, a layer of material is formed over a substrate and patterned using a lithographic process. Spacers are formed next to the patterned material layer using a self-aligned process. The layer of material is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 209 by etching the first stack 204 and the substrate 202 . The etching process may include dry etching, wet etching, reactive ion etching (RIE) and/or other suitable processes. In some embodiments shown in FIG. 3 , after forming the first fin structure 209 , the first liner layer 210 may be conformally deposited on the workpiece 200 . The first liner layer 210 may include silicon nitride and may be formed by chemical vapor deposition (CVD) or atomic layer deposition (atomic layer deposition, ALD).

Referring to FIG. 1 and FIG. 4 , the method 100 includes a step 106 of forming the isolation member 214 . The isolation feature 214 may also be referred to as a shallow trench isolation (shallow trench isolation, STI) feature 214 . In example processes, CVD, subatmospheric CVD (SACVD), flowable CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating and/or or other suitable processes to deposit the dielectric material for the isolation component 214 on the first liner 210 . Thereafter, the deposited dielectric material is planarized and etched back until the first fin structure 209 rises above the isolation features 214 . That is, after the etch back of the isolation features 214 , the base portion 209B of the first fin structure 209 is surrounded by the isolation features 214 . The dielectric material used for the isolation member 214 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (fluorine-doped silicate glass, FSG), low-k dielectric, combinations thereof, and/or other suitable Material. After the isolation part 214 is etched back, the first liner layer 210 is selectively etched back until the stacked portion 209S of the first fin structure 209 is exposed.

Referring to FIGS. 1 and 5 , the method 100 includes step 108 of depositing a sacrificial spacer layer 216 over the first fin structure 209 and the isolation features 214 . In some embodiments, sacrificial spacer layer 216 may include silicon oxide and may be conformally deposited over workpiece 200 . The sacrificial spacer layer 216 is disposed along and on the top surface of the isolation member 214, and the sacrificial spacer layer 216 is disposed along and on the top surface and sidewall of the stack portion 209S. surface and side walls.

Referring to FIGS. 1 and 6 , the method 100 includes a step 110 of depositing a first dielectric layer 218 over the sacrificial spacer layer 216 . The first dielectric layer 218 may include silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, or a dielectric material that allows selective etching of the sacrificial spacer layer 216 . The first dielectric layer 218 may be deposited using CVD. Although not explicitly shown in the figure, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the workpiece 200 to expose the top surface of the stack portion 209S. The planarization process also exposes the top surface of the sacrificial spacer layer 216 .

Referring to FIGS. 1 and 7 , the method 100 includes a step 112 of selectively etching back the sacrificial spacer layer 216 to release the stack portion 209S of the first fin structure 209 . As shown in FIG. 7, at step 112, vertical portions of the sacrificial spacer layer 216 extending along the sidewalls of the stack portion 209S are selectively removed without substantially damaging the stack portion 209S and the first dielectric layer. 218. In examples where the sacrificial spacer layer 216 is formed of silicon oxide and the first dielectric layer 218 is formed of silicon nitride, diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF) may be used. ) selectively etch the sacrificial spacer layer 216 . Here, BHF includes hydrofluoric acid and ammonium fluoride. At the end of the operation at step 112 , mixing fins 217 are formed on both sides of the stacked portion 209S and extend longitudinally parallel to the stacked portion 209S. Each hybrid fin 217 includes a sacrificial spacer layer 216 and a first dielectric layer 218 over the sacrificial spacer layer 216 .

Referring to FIGS. 1 and 8 , the method 100 includes step 114 of forming a dummy gate stack 222 over the stack portion 209S and the hybrid fin 217 . In some embodiments, a gate replacement process (or gate-last process) is used, wherein the dummy gate stack 222 is used as a placeholder for the functional gate structure. Other processes and configurations may be included. To form the dummy gate stack 222 , a dummy dielectric layer, a dummy gate electrode layer, and a gate top hard mask layer are deposited over the workpiece 200 . Deposition of these layers can include the use of low-pressure CVD (low-pressure CVD, LPCVD), CVD, plasma-enhanced CVD (plasma-enhanced CVD, PECVD), PVD, ALD, thermal oxidation, electron beam evaporation or other suitable deposition technology or a combination thereof. The dummy dielectric layer may include silicon oxide, the dummy gate electrode layer may include polysilicon, and the gate top hard mask layer may be a multilayer including silicon oxide and silicon nitride. The gate top hard mask layer can be patterned using lithography and etch processes. The lithography process may include photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinsing, drying (e.g., spin dry and/or hard bake baking), other suitable lithography techniques and/or combinations thereof. The etching process may include dry etching (eg, RIE etching), wet etching, and/or other etching methods. Afterwards, using the patterned gate top hard mask as an etching mask, the dummy dielectric layer and the dummy gate electrode layer are etched to form a dummy gate stack 222 . As shown in FIG. 8 , a dummy gate stack 222 is formed on the isolation member 214 , the mixing fin 217 and a portion of the first fin structure 209 . The dummy gate stack 222 extends longitudinally along the X direction to wrap around the first fin structure 209 . The portion of the first fin structure 209 below the dummy gate stack 222 is the channel region. The channel region and the dummy gate stack 222 also define source/drain regions that are not vertically overlapped by the dummy gate stack 222 . The channel region is disposed between the two source/drain regions along the Y direction.

Although not explicitly shown, the operations at step 114 may include forming a gate spacer layer on the top surface and sidewalls of the dummy gate stack 222 . In some embodiments, forming the gate spacer layer includes conformally depositing one or more dielectric layers on workpiece 200 . In an example process, one or more dielectric layers may be deposited using CVD, SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and/or combinations thereof.

Referring to FIG. 1 and FIG. 9 , the method 100 includes a step 116 of etching back the source/drain portion of the first fin structure 209 to form a source/drain notch 224 . It should be understood that the cross section in FIG. 9 cuts across the source region or the drain region of the first fin structure 209 , and the channel region of the first fin structure is not in the plane of the cross section. For illustration purposes, structures in the channel region are shown in dotted lines in FIG. 9 . In an example process, the workpiece 200 is etched after depositing the gate spacer layer, with the etch process selectively recessing the source/drain regions of the first fin structure 209 . Selective etchback of the source/drain regions results in source/drain trenches 224 between mixing fins 217 . The etching process at step 116 may be a dry etching process or a suitable etching process. Exemplary dry etching processes may employ oxygen-containing gases, hydrogen gases, fluorine-containing gases (eg, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and/or C ₂ F ₆ ), chlorine-containing gases (eg, Cl ₂ , CHCl ₃ , CCl ₄ and/or BCl ₃ ), bromine-containing gases (such as HBr and/or CHBR ₃ ), iodine-containing gases, other suitable gases and/or plasmas and/or combinations thereof. As shown in FIG. 9 , the sacrificial layer 206 in the channel region and the sidewalls of the channel layer 208 are exposed in the source/drain trench 224 .

Referring to FIGS. 1 and 10 , method 100 includes step 118 of forming inner spacer member 226 . At step 118, the exposed sacrificial layer 206 in the source/drain trenches 224 is selectively and partially etched back to form an inter-spacer recess, while the exposed channel layer 208 is substantially unetched. In embodiments where the channel layer 208 is formed primarily of silicon (Si) and the sacrificial layer 206 is primarily formed of silicon germanium (SiGe), the selective and partial etchback of the sacrificial layer 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. . In the above embodiments, the SiGe oxidation process may include using ozone (O ₃ ). In some other embodiments, the selective etchback may be a selective isotropic etch process (eg, a selective dry etch process or a selective wet etch process), and the degree of etchback of the sacrificial layer 206 is controlled by the duration of the etch process. time control. Selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etch process may include hydrogen fluoride (HF) or NH ₄ OH etchant. After forming the interspacer recesses, a layer of interspacer material is deposited on the workpiece 200, including depositing in the interspacer recesses. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride or suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess inner spacer material layer on the gate spacer layer and the sidewall of the channel layer 208 , thereby forming the inner spacer member 226 as shown in FIG. 10 . In some embodiments, the etch-back process at step 118 may be a dry etching process, including the use of oxygen-containing gas, hydrogen gas, nitrogen gas, fluorine-containing gas (such as CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and/or C ₂ F ₆ ), gas containing chlorine (such as Cl ₂ , CHCl ₃ , CCl ₄ and/or BCl ₃ ), gas containing bromine (such as HBr and/or CHBR ₃ ), gas containing iodine (such as CF ₃ I ), others Suitable gases and/or plasmas and/or combinations thereof.

Referring to FIGS. 1 , 11A and 11B , the method 100 includes a step 120 of forming a first source feature 228S and a first drain feature 228D in the source/drain trench 224 . It should be understood that the source region 200S and the drain region 200D are shown in FIG. 11A and FIG. 11B , respectively. Similarly, source region 200S is shown in Figures 12A to 17A, and drain region 200D is shown in Figures 12B to 17B. In some embodiments, an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes may be used to form the first source feature 228S and the first drain feature 228D. The epitaxial growth process may use gaseous and/or liquid precursors that interact with the substrate 202 and the composition of the channel layer 208 . Thus, the first source feature 228S and the first drain feature 228D are coupled to the channel layer 208 or the drained channel. Depending on the conductivity type of the MBC transistor to be formed, the first source feature 228S and the first drain feature 228D may be n-type source/drain features or p-type source/drain features. Exemplary n-type source/drain features may include Si, GaAs, GaAsP, SiP, or other suitable materials, and may be formed by introducing n-type dopants, such as phosphorus (P), arsenic (As), during the epitaxy process. In-situ doping, or ex-situ doping using an implant process (eg, junction implant process). Exemplary p-type source/drain features can include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable materials, and can be p-type doped, such as boron (B), during the epitaxy process. in-situ doping, or ex-situ doping using an implant process (eg, junction implant process).

Referring to FIG. 1 , FIG. 12A and FIG. 12B , method 100 includes step 122 of replacing dummy gate stack 222 with a first gate structure (not shown). The operations at step 122 include: depositing a first contact etch stop layer (CESL) 230; depositing a first interlayer dielectric (ILD) layer 232; removing the dummy gate stack 222; selectively removing sacrificial layer 206 to release channel features; form a first gate structure; and planarize workpiece 200 to remove excess material. The first CESL 230 may include silicon nitride, silicon oxynitride, and/or other materials known in the art, and may be deposited or oxidized by ALD, plasma-assisted chemical vapor deposition (PECVD) processes, and/or other suitable Process formation. As shown in FIGS. 12A and 12B , a first CESL 230 may be deposited on the top surfaces of the first source feature 228S, the first drain feature 228D, and the mixing fin 217 . The material of the first ILD layer 232 may include, for example, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (borophosphosilicate glass). , BPSG), fused silica glass (fused silica glass, FSG), phosphosilicate glass (phosphoric silicate glass, PSG), boron doped silicon glass (BSG) and/or other suitable dielectric materials. The first ILD layer 232 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming first ILD layer 232 , workpiece 200 may be annealed to improve the integrity of first ILD layer 232 . In order to remove excess material and expose the top surface of the dummy gate stack 222, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed.

In case the dummy gate stack 222 is exposed, step 122 removes the dummy gate stack 222 . Removing the dummy gate stack 222 may include one or more etch processes that are selective to the material in the dummy gate stack 222 . For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove dummy gate stack 222 . After the dummy gate stack 222 is removed, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region and between the source region 200S and the drain region 200D are exposed. Thereafter, the sacrificial layer 206 in the channel region is selectively removed to release the channel layer 208 as a channel member. Here, since the size of the channel member is nanoscale, the channel member may also be referred to as a nanostructure. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching or other selective etching processes. In some embodiments, the selective wet etch includes APM etch (eg, ammonia-hydrogen peroxide-water mixture). In some embodiments, selective removal includes SiGe oxidation followed by removal of SiGe oxide. For example, oxidation may be provided by an ozone clean, followed by removal of the SiGe oxide by an etchant such as _NH4OH .

With the channel members released, a first gate structure (view of which is blocked by first source feature 228S) is deposited to surround each channel member in the channel region. The gate structure includes an interface layer surrounding and in contact with the channel member, a gate dielectric layer over the interface layer, and a gate electrode layer over the gate dielectric layer. In some embodiments, the interfacial layer includes silicon oxide and may be formed during a pre-clean process. Exemplary pre-cleaning processes may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). A gate dielectric layer is then deposited on the interfacial layer using ALD, CVD, and/or other suitable methods. The gate dielectric layer may be formed of a high-k dielectric material. As used and described in this disclosure, a high-k dielectric material includes a dielectric material having a high dielectric constant, eg, a dielectric constant greater than that of thermal silicon oxide (˜3.9). The gate dielectric layer may include hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectrics such as TiO ₂ , HfZrO, Ta ₂ O ₅ , HfSiO ₄ , ZrO 2 , ZrSiO _{2 ,} La ₂ O ₃ , Al ₂ O ₃ , ZrO , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfLaO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), SiN, SiON, combinations thereof or other suitable s material.

A gate electrode layer is then deposited on the gate dielectric layer using ALD, PVD, CVD, electron beam evaporation or other suitable methods. The gate electrode layer can consist of a single layer or a multi-layer structure such as various combinations of metal layers with a selected work function to enhance device performance (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys or metal silicide. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN ), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt ), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory (refractory) metals or other suitable metal materials or combinations thereof. In addition, in the case that the semiconductor device 200 includes an n-type transistor and a p-type transistor, different gate electrode layers may be formed for the n-type transistor and the p-type transistor, and the n-type transistor and the p-type transistor may be Different metal layers are included (eg, metal layers providing different n-type and p-type work functions).

Referring to FIG. 1 , FIG. 13A and FIG. 13B , method 100 includes step 124 of forming a first drain contact 234 . In an example process, a contact opening exposing the first drain feature 228D is formed using a lithography process. In order to reduce the contact resistance, a metal layer may be deposited on the first drain member 228, and an annealing process may be performed to cause silicidation between the metal layer and the first drain member 228, so that the first drain member A silicide layer is formed on 228D. Suitable metal layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) or tungsten (W). The silicide layer may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). After forming the silicide layer, a metal fill layer may be deposited into the contact openings. Metal fill layers can include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). A planarization process may then be performed to provide a flat top surface to provide a stage for subsequent processes.

Referring to FIGS. 1 , 14A and 14B , method 100 includes step 126 of bonding second stack 240 to workpiece 200 . In some embodiments, capping layer 236 is blanket deposited on workpiece 200 . In some embodiments, capping layer 236 includes silicon oxide and may also be referred to as capping oxide layer 236 . Like the first stack 204 , the second stack 240 also includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206 . In the embodiment shown in FIG. 14A and FIG. 14B , the first stack 204 and the second stack 240 have the same number of channel layers 208 and sacrificial layers. However, the present disclosure is not limited thereto, and the first stack 204 and the second stack 240 may have different configurations, such as different numbers of film layers or different thicknesses of film layers. To facilitate bonding, a base layer 238 is formed on the bottom surface of the second stack 240 . With respect to substrate 202 , the second stack and base layer 238 may be considered another substrate. In some embodiments, base layer 238 includes silicon oxide, and may also be referred to as base oxide layer 238 . It should be understood that, for the avoidance of doubt, the second stack 240 shown in Figures 14A and 14B respectively are identical. In some embodiments, second stack 240 may be bonded directly to workpiece 200 by utilizing the interface between cap layer 236 and base layer 238 . In an exemplary direct bonding process, cap layer 236 and base layer 238 are cleaned using RCA SC-1 (ammonia, hydrogen peroxide, and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The cleaned cover layer 236 and base layer 238 are then mate and pressed together. Direct bonding can be strengthened by annealing process.

Referring to FIG. 1 , FIG. 15A and FIG. 15B , the method 100 includes step 128 , which performs the operations in steps 104 , 108 - 122 on the second stack 240 . Due to the similarity of the process steps, only the operations in step 128 are summarized for brevity. At step 104 , the second stack 240 is patterned to form a second fin structure (the view of which is blocked by other structures). Since the second fin structure is insulated by the capping layer 236 and the base layer 238 , the operation at step 106 can be omitted. At steps 108 , 110 and 112 , top mixing fins 242 are formed on both sides of the second fin structure and extend parallel to the second fin structure. At step 114 , a counterpart dummy gate stack is formed over the channel region of the second fin structure to serve as a placeholder for a functional second gate structure. At step 116 , source/drain portions of the second fin structure are etched back to form source/drain recesses, similar to source/drain trenches 224 . At step 118, the sacrificial layer 206 in the channel region is selectively and partially etched to form an inner spacer recess, and an inner spacer feature is formed in the inner spacer recess. At step 120 , a second source feature 244S and a second drain feature 244D are formed in the source/drain recesses. At step 122, the dummy gate stack above the second fin structure is replaced with the second gate structure. The sacrificial layer 206 in the channel region is selectively removed to release the channel layer 208 as channel members, and a second gate structure surrounds each channel member. A second CESL 246 and a second ILD layer 248 are sequentially deposited over the top hybrid fin 242 , the second source feature 244S, and the second drain feature 244D before replacing the dummy gate stack.

Referring to FIG. 1 , FIG. 16A and FIG. 16B , the method 100 includes a step 130 of forming a top source contact 250 , a second drain contact 252 , a first contact via 258 , and a second contact via 260 . and the third contact hole 262 . As shown in FIG. 17A, a top source contact 250 is formed over and in contact with the second source feature 244S. Similar to the first drain contact 234 , a contact opening is first formed to expose the second source feature 244S, a silicide layer is formed on the second source feature 244S, and a metal fill layer is deposited to fill the remaining contact opening. In a similar manner, a second drain contact 252 is formed over and in contact with the second drain feature 244D. After forming the top source contact 250 and the second drain contact 252, an etch stop layer (ESL) 254 and a third ILD layer 256 are deposited on the top source contact 250 and the second drain contact. 252 to passivate the top source contact 250 and the second drain contact 252 .

The formation of the first contact via 258 , the second contact via 260 and the third contact via 262 may include forming a via opening through at least the ESL 254 and the third ILD layer 256 and depositing a metal fill layer. Metal fill layers can include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). In some embodiments, each of the first contact via 258, the second contact via 260 and the third contact via 262 may include a liner between the metal fill layer and the adjacent dielectric material to improve electrical performance. Integrity (electrical integrity). The liner may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN), or tantalum nitride (TaN). Because forming the second contact via 260 requires forming not only through the ESL 254 and the third ILD layer 256 but also extending through the second ILD layer 248, the second CESL 246, the top mixing fin 242, the base layer 238, and the capping layer 236 Therefore, the via openings for the second contact via 260 are not formed simultaneously with the via openings for the first contact via 258 and the third contact via 262 . In some other embodiments, the via opening for the second contact via 260 is formed separately and etched in multiple etch stages.

Referring to FIG. 1 , FIG. 16A and FIG. 16B , the method 100 includes a step 132 of forming a top interconnect structure 270 . The top interconnect structure 270 includes a first protective layer 263 and conductive features in the first protective layer 263 . In the depicted embodiment, the conductive components include a top power rail 264 , a first wire 266 , and a second wire 268 . The top power rail 264 is in direct contact with the first contact via 258 . In other words, the first contact via 258 electrically couples the top power rail 264 and the second source feature 244S. Here, the top power rail 264 (or other power rail) is called so because it provides the positive supply voltage. In an example process, a first protective layer 263 is deposited on the workpiece 200 , thereafter the first protective layer 263 is patterned, and a conductive material is deposited on the patterned first protective layer 263 . Although the top interconnect structure 270 in FIGS. 16A and 16B includes only one interconnect layer, the top interconnect structure 270 may include more interconnect layers, and may include all interconnect layers on the workpiece 200 . As shown in FIG. 16B , the second contact via 260 directly contacts the first wire 266 , and the third contact via 262 directly contacts the second wire 268 .

Referring to FIG. 1 , FIG. 17A , and FIG. 17B , the method 100 includes a step 134 of forming a backside source contact 274 . Although not so shown in Figures 17A and 17B, the workpiece 200 may be bonded to a carrier substrate and turned upside down and the operations of step 134 performed. In an exemplary process, the substrate 202 is polished or planarized by a polishing process and/or a chemical mechanical polishing (CMP) process until the isolation features 214 are exposed. With the first patterned hard mask covering the source region 200S, the base portion 209B in the drain region 200D is selectively removed to expose the first drain feature 228D. A first nitride liner 276 and a dielectric fill 282 may be deposited over the first drain feature 228D to insulate it. In some examples, the first nitride liner 276 may include silicon nitride, silicon oxynitride, or silicon carbonitride, and the dielectric filling 282 may include silicon oxide. Afterwards, the first patterned mask is removed, and a second patterned mask is formed to cover the drain region 200D. A backside contact opening is formed to expose the first source feature 228S. A second nitride liner 277 is deposited over the backside contact opening and etched back to expose the first source feature 228S. As shown in FIG. 17A, a backside silicide layer 272 and a backside source contact 274 are formed in the backside contact opening. The backside silicide layer 272 may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). The backside source contact 274 may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W) , tantalum (Ta) or tantalum nitride (TaN).

Referring to FIG. 1 , FIG. 17A , and FIG. 17B , the method 100 includes a step 136 of forming a backside interconnect structure 290 . In the depicted embodiment, backside interconnect structure 290 includes first backside power rail 279 in second protective layer 278 . The first backside power rail 279 is in direct contact with the backside source contact 274 . Thus, the first backside power rail 279 is coupled to the first source feature 228S, while the first backside power rail 279 is insulated from the first drain feature 228D by the first nitride liner 276 and the dielectric fill 282 . Here, like top power rail 264, first backside power rail 279 is so called because it provides a positive power supply voltage. In an example process, a second protective layer 278 is deposited over the exposed isolation features 214 , the second protective layer 278 is patterned, and a conductive material is deposited on the patterned second protective layer 278 .

Reference is now made to Figures 17A and 17B. After the operations in the method 100 are completed, the first MBC transistor 10 and the second MBC transistor 20 above the first MBC transistor 10 are formed. The first MBC transistor 10 includes a channel member interposed between a first source feature 228S and a first drain feature 228D. The first gate structure of the first MBC transistor 10 , the view of which is blocked by the first source features 228S, surrounds each of its channel members. The second MBC transistor 20 includes a channel member interposed between a second source feature 244S and a second drain feature 244D. A second gate structure of the second MBC transistor 20 (view of which is blocked by a second source feature 244S and a second drain feature 244D) surrounds each of its channel members. The first source feature 228S is coupled to a first backside power rail 279 through a backside source contact 274 . A first backside power rail 279 is disposed in a backside interconnect structure 290 . The second source feature 244S is coupled to the top power rail 264 through the top source contact 250 and the first contact via 258 . Top power rail 264 is disposed in top interconnect structure 270 . Both the first drain feature 228D and the second drain feature 244D are electrically coupled to conductive features in the top interconnect structure 270 , but are insulated from the backside interconnect structure 290 . The first drain feature 228D is coupled to the first wire 266 through the first drain contact 234 and the second contact via 260 . The second contact via 260 extends through the top mixing fin 242 along the Z direction. The second drain feature 244D is coupled to the second wire 268 through the third contact via 262 .

Turning now to method 300 . FIG. 18 shows a flowchart of a method 300 according to various aspects of the present disclosure. Throughout the present disclosure, like reference numerals designate like components in terms of composition and formation. Details of some operations in method 300 may be simplified or omitted where similar details are already described for method 100 .

Referring to FIGS. 18 and 19 , the method 300 includes a step 302 of providing a workpiece 200 . The workpiece 200 includes a substrate 202 and a first stack 204 over the substrate 202 . Since the substrate 202 and the first stack 204 have been described above, their detailed descriptions are omitted here.

Referring to FIG. 18 and FIG. 20 , the method 300 includes a step 304 of forming a first fin structure 209 from the first stack 204 . Since the operation of step 304 is similar to that of step 104, its detailed description is omitted for brevity.

Referring to FIG. 18 and FIG. 21 , the method 300 includes a step 306 of forming the isolation member 214 . Since the operation at step 306 is similar to the operation at step 106, its detailed description is omitted for brevity.

Referring to FIG. 18 and FIG. 22 , the method 300 includes a step 308 of depositing a sacrificial spacer layer 216 on the first fin structure 209 and the isolation member 214 . Since the operation of step 308 is similar to that of step 108, its detailed description is omitted for brevity.

Referring to FIGS. 18 , 23 and 24 , method 300 includes step 310 of depositing second dielectric layer 2180 , conductive layer 219 and third dielectric layer 221 over sacrificial spacer layer 216 . Second dielectric layer 2180 may be conformally deposited over workpiece 200 , including over sacrificial spacer layer 216 . As shown in FIG. 23 , unlike the first dielectric layer 218 , the second dielectric layer 2180 does not completely fill the trenches defined by the sidewalls of the sacrificial spacer layer 216 . After conformal deposition of the second dielectric layer 2180 , a conductive layer 219 is deposited over the second dielectric layer 2180 to completely fill the trenches defined by the sidewalls of the sacrificial spacer layer 216 . The conductive layer 219 may include a conductive material such as titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W) , tantalum (Ta) or tantalum nitride (TaN). Then the conductive layer 219 is etched back until the top surface of the conductive layer 219 is lower than the top surface of the second dielectric layer 2180 . Accordingly, as shown in FIG. 24 , isolated conductive features 219 are formed on both sides of the first fin structure 209 . A third dielectric layer 221 is then deposited on the conductive member 219 and the second dielectric layer 2180 . Therefore, the conductive member 219 is buried or embedded in the second dielectric layer 2180 and the third dielectric layer 221 . The second dielectric layer 2180 and the third dielectric layer 221 may include silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide or dielectric materials that allow selective etching of the sacrificial spacer layer 216 . The second dielectric layer 2180 and the third dielectric layer 221 may be deposited using CVD or ALD. Although not explicitly shown in the figure, a planarization process such as a chemical mechanical polishing (CMP) process may be performed on the workpiece 200 to expose the top surface of the first fin structure 209 . The planarization process also exposes the top surface of the sacrificial spacer layer 216 .

Referring to FIG. 18 and FIG. 25 , the method 300 includes a step 312 of selectively etching back the sacrificial spacer layer 216 to release the stack portion 209S of the first fin structure 209 . Since the operation at step 312 is similar to the operation at step 112, its detailed description is omitted for brevity. With respect to method 300 , as a result of the operations of step 312 , modular mixing fins 2170 are formed. The modular mixing fins 2170 extend parallel to the first fin structure 209 . Each modular hybrid fin 2170 includes a conductive feature 219 embedded therein. As will be described further below, the modular hybrid fins 2170 can be used as contact modules to provide routing pathways as needed. When implementing modular hybrid fins, the contact vias can have a smaller aspect ratio because they can originate and end at the embedded Conductive parts.

Referring to FIG. 18 and FIG. 26 , the method 300 includes step 314 of forming a dummy gate stack 222 on the stack portion 209S and the modularized mixing fin 2170 . Since the operation of step 314 is similar to the operation of step 114, its detailed description is omitted for brevity.

Referring to FIG. 18 and FIG. 27 , the method 300 includes a step 316 of etching back the source/drain portion of the first fin structure 209 to form a source/drain notch 224 . Since the operation of step 316 is similar to that of step 116, its detailed description is omitted for brevity.

Referring to FIGS. 18 and 28 , method 300 includes step 318 of forming inner spacer member 226 . Since the operation of step 318 is similar to that of step 118, its detailed description is omitted for brevity.

Referring to FIG. 18 , FIG. 29A and FIG. 29B , the method 300 includes a step 320 of forming a first source feature 228S and a first drain feature 228D in the source/drain trench 224 . It should be understood that the source region 200S and the drain region 200D are shown in Figures 29A and 29B, respectively. Similarly, source region 200S is shown in Figures 30A-35A and drain region 200D is shown in Figures 30B-35B. Since the operation of step 320 is similar to that of step 120, its detailed description is omitted for brevity.

18, 29A, and 29B, method 300 includes step 322 of replacing dummy gate stack 222 with a first gate structure (the view of which is blocked by first source feature 228S). Since the operation of step 322 is similar to that of step 122, its detailed description is omitted for brevity.

Referring to FIG. 18 , FIG. 30A and FIG. 30B , the method 300 includes a step 324 of forming a first source contact 235 and a first drain contact 234 . In an example process, a lithography process is used to form contact openings exposing the first source feature 228S and the first drain feature 228D. In order to reduce the contact resistance, a silicide layer may be formed on the first source feature 228S and the first drain feature 228D by depositing a metal layer on the first source feature 228S and the first drain feature 228, and performing annealing process to induce silicidation between the metal layer and the first source feature 228S and between the metal layer and the first drain feature 228D. Suitable metal layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) or tungsten (W). The silicide layer may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). After forming the silicide layer, a metal fill layer may be deposited into the contact openings. Metal fill layers can include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). A planarization process may follow to provide a flat top surface, thereby providing a platform for subsequent processes. It should be understood that the position and X-direction dimension of the first source contact 235 are selected such that its sidewall contacts or merges with the adjacent conductive member 219 . Conversely, the location and X-direction dimension of the first drain contact 234 are selected such that its sidewall or any portion thereof is spaced from the adjacent conductive features 219 .

Referring to FIGS. 18 , 31A, and 31B, the method 300 includes a step 326 of bonding the second stack 240 to the workpiece 200 . Since the operation of step 326 is similar to that of step 126, its detailed description is omitted for brevity.

Referring to FIGS. 18 , 32A, 32B, 33A, and 33B, the method 300 includes step 128 of performing the operations of steps 304 , 308 - 322 on the second stack 240 . Due to the similarity of the process steps, only the operations in step 328 are summarized for brevity. Referring to FIG. 32A and FIG. 32B , at step 304 the second stack 240 is patterned to form a second fin structure 2090 . As shown in FIG. 32A and FIG. 32B , the second fin structure 2090 is vertically aligned with the first fin structure 209 . This is evidenced by the vertical alignment between the second fin structure 2090 and the base portion 209B. Since the second fin structure is insulated by the capping layer 236 and the base layer 238 , the operation at step 306 may be omitted. Continuing to refer to FIGS. 32A and 32B, at steps 308, 310, and 312, top modular mixing fins 2172 are formed on both sides of the second fin structure 2090 parallel to the longitudinal direction of the second fin structure 2090 extend. Each top modular hybrid fin 2172 includes a top conductive feature 239 embedded in the fourth dielectric layer 241 and the fifth dielectric layer 243 . The top conductive member 239 and the conductive member 219 may have the same composition. The fourth dielectric layer 241 and the fifth dielectric layer 243 have the same composition as the second dielectric layer 2180 . As shown in FIG. 32A , bridging contact vias 237 are formed to electrically couple conductive features 219 in modular hybrid fin 2170 and top conductive features 239 in top modular hybrid fin 2172 . In order to form the bridging contact vias 237, after depositing the fourth dielectric layer 241, vias are formed directly above the conductive features 219 to be connected. When the top conductive feature 239 is deposited, the bridging contact via 237 and the top conductive feature 239 connected thereto are simultaneously formed.

Referring to FIG. 33A and FIG. 33B, at step 314, a corresponding dummy gate stack is formed over the channel region of the second fin structure to serve as a placeholder for a functional second gate structure. At step 316 , source/drain portions of the second fin structure are etched back to form source/drain recesses, similar to source/drain trenches 224 . At step 318, the sacrificial layer 206 in the channel region is selectively and partially etched to form an inner spacer recess, and an inner spacer feature is formed in the inner spacer recess. At step 320, a second source feature 244S and a second drain feature 244D are formed in the source/drain recesses. At step 322, the dummy gate stack above the second fin structure is replaced with a second gate structure (not shown). The sacrificial layer 206 in the channel region is selectively removed to release the channel layer 208 as channel members, and a second gate structure surrounds each channel member. A second CESL 246 and a second ILD layer 248 are sequentially deposited over the top modular hybrid fin 2172, the second source feature 244S, and the second drain feature 244D before replacing the dummy gate stack.

Referring to FIG. 18, FIG. 34A, and FIG. 34B, the method 300 includes a step 330 of forming the top source contact 250, the second drain contact 252, the second contact via 260, and the third contact via 262. . As shown in FIG. 34A, a top source contact 250 is formed over and in contact with the second source feature 244S. A contact opening is first formed to expose the second source feature 244S, a silicide layer is formed on the second source feature 244S, and a metal filling layer is deposited to fill the remaining contact opening. In a similar manner, a second drain contact 252 is formed over and in contact with the second drain feature 244D. After the top source contact 250 and the second drain contact 252 are formed, an etch stop layer (ESL) 254 and a third ILD layer 256 are deposited over the top source contact 250 and the second drain contact 252 to protect (passivate) the top source contact 250 and the second drain contact 252 . It should be understood that the location and X-direction dimension of the top source contact 250 are selected such that its sidewalls contact or merge with the top conductive feature 239 coupled to the bridge contact via 237 . Conversely, the location and X-direction dimension of the second drain contact 252 are selected such that its sidewall or any portion thereof is spaced from the adjacent top conductive feature 239 .

The formation of the second contact via 260 and the third contact via 262 may include forming a via opening through at least the ESL 254 and the third ILD layer 256 and depositing a metal fill layer. Metal fill layers can include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). In some embodiments, each of the second contact via 260 and the third contact via 262 may include a liner between the metal fill layer and the adjacent dielectric material to improve electrical integrity. The liner may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN), or tantalum nitride (TaN). Because the formation of the second contact via 260 requires the formation of a fourth The via openings of the dielectric layer 241 , the base layer 238 , and the cap layer 236 , so the via openings for the second contact via 260 are not formed simultaneously with the via openings for the third contact via 262 . In some other embodiments, the via opening for the second contact via 260 is formed separately and etched in multiple etch stages. The second contact via 260 is spaced and isolated from the second drain feature 244D and the adjacent top conductive feature 239 . It should be appreciated that in method 300 no contact vias are formed on top source contact 250 .

Referring to FIG. 18 , FIG. 34A , and FIG. 34B , the method 300 includes a step 332 of forming the top interconnect structure 270 . The top interconnect structure 270 includes a first protective layer 263 and conductive features in the first protective layer 263 . In the embodiment depicted in FIGS. 34A and 34B , the conductive member includes a first wire 266 and a second wire 268 . In an example process, a first protective layer 263 is deposited on the workpiece 200 , thereafter the first protective layer 263 is patterned, and a conductive material is deposited on the patterned first protective layer 263 . Although the top interconnect structure 270 in FIGS. 35A and 35B includes only one interconnect layer, the top interconnect structure 270 may include more interconnect layers, and may include all interconnect layers on the workpiece 200 . As shown in FIG. 35B , the second contact via 260 is in direct contact with the first wire 266 , and the third contact via 262 is in direct contact with the second wire 268 .

Referring to FIG. 18 , FIG. 35A and FIG. 35B , the method 300 includes a step 334 of forming a first backside contact via 281 and a second backside contact via 283 . Although not so shown in FIGS. 35A and 35B , the workpiece 200 may be bonded to a carrier substrate and turned upside down and the operations of step 334 performed. In an exemplary process, the substrate 202 is polished or planarized by a polishing process and/or a chemical mechanical polishing (CMP) process until the isolation features 214 are exposed. The base portion 209B in the isolation feature 214 is removed and replaced by a first nitride liner 276 and a dielectric fill 282, which act as a dielectric for isolation. plug. In some examples, the first nitride liner 276 may include silicon nitride, silicon oxynitride, or silicon carbonitride, and the dielectric filling 282 may include silicon oxide. Backside contact openings are formed through isolation features 214 exposing conductive features 219 in modular mixing fins 2170 . A metal filling layer is then deposited in the backside contact opening to form a first backside contact via 281 and a second backside contact via 283 . Exemplary metal fill layers may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride (TaN). The first backside contact via 281 is electrically coupled to the first source contact 235 through the conductive member 219 in contact with the first source contact 235 . The second backside contact via 283 is electrically coupled to the top source contact 250 through another conductive feature 219 , the bridging contact via 237 , and the top conductive feature 239 contacts the top source contact 250 .

Referring to FIG. 18 , FIG. 35A , and FIG. 35B , method 300 includes step 336 of forming backside interconnect structure 290 . In the depicted embodiment, backside interconnect structure 290 includes second protective layer 278 , first backside power rail 279 , and second backside power rail 280 . The first backside power rail 279 is in direct contact with the first backside contact via 281 , and the second backside power supply rail 280 is in direct contact with the second backside contact via 283 . Thus, the first backside power rail 279 is coupled to the first source feature 228S, and the second backside power rail 280 is coupled to the second source feature 244S. Here, like top power rail 264, first backside power rail 279 and second backside power rail 280 are so called because they provide positive power supply voltages. In an example process, a second protective layer 278 is deposited over the exposed isolation features 214 , the second protective layer 278 is patterned, and a conductive material is deposited on the patterned second protective layer 278 .

Reference is now made to Figures 35A and 35B. After the operations in the method 300 are completed, the first MBC transistor 10 and the second MBC transistor 20 above the first MBC transistor 10 are formed. The first MBC transistor 10 includes a channel member interposed between a first source feature 228S and a first drain feature 228D. The first gate structure of the first MBC transistor 10 , the view of which is blocked by the first source features 228S, surrounds each of its channel members. The second MBC transistor 20 includes a channel member interposed between a second source feature 244S and a second drain feature 244D. A second gate structure of the second MBC transistor 20 (view of which is blocked by second source features 244S) surrounds each of its channel members. First source feature 228S is coupled to first backside power rail 279 through first source contact 235 , conductive feature 219 in modular mixing fin 2170 , and first backside contact via 281 . The second source feature 244S passes through the top source contact 250, the top conductive feature 239 in the top modular mixed fin 2172, the bridging contact via 237, the conductive feature 219 in the modular mixed fin 2170, and the second back Side contact via 283 is coupled to second backside power rail 280 . Both the first backside power rail 279 and the second backside power rail 280 are disposed in the backside interconnect structure 290 . Both the first drain feature 228D and the second drain feature 244D are electrically coupled to conductive features in the top interconnect structure 270 , but are insulated from the backside interconnect structure 290 . The first drain feature 228D is coupled to the first wire 266 through the first drain contact 234 and the second contact via 260 . The second contact via 260 extends through the fourth dielectric layer 241 of the top modular hybrid fin 2172 along the Z direction. The second drain feature 244D is coupled to the second wire 268 through the second drain contact 252 and the third contact via 262 .

Turning now to method 500 . FIG. 36 shows a flowchart of a method 500 according to various aspects of the present disclosure. In this disclosure, like reference numerals designate like components in terms of composition and formation. Details of some operations in method 500 may be simplified or omitted if similar details have already been described for method 100 or method 300 .

Referring to FIGS. 36 and 37 , the method 500 includes a step 502 of providing a workpiece 200 . Since the operation of step 502 is similar to that of step 102, its detailed description is omitted for brevity.

Referring to FIG. 36 and FIG. 38 , the method 500 includes a step 504 of forming a first fin structure 209 from the first stack 204 . Since the operation of step 504 is similar to that of step 104, its detailed description is omitted for brevity.

Referring to FIG. 36 and FIG. 39 , the method 500 includes a step 506 of forming a buried power rail 211 . In some embodiments, a metal layer for the buried power rail 211 is deposited on the workpiece 200 using metal-organic CVD or PVD before etching back the first liner layer 210 . The first liner layer and the deposited metal layer are etched back to form the buried power rail 211 . The metal layer of the buried power rail 211 may include tungsten (W), ruthenium (Ru), copper (Cu), aluminum (Al), silver (Ag), molybdenum (Mo), rhenium (Re), iridium (Ir) , cobalt (Co) or nickel (Ni). In the depicted embodiment, each buried power rail 211 includes a width W of between about 40 nm and 80 nm and a height H of between about 30 nm and about 50 nm. As shown in FIG. 39 , the stack portion 209S of the first fin structure 209 may be exposed at the end of step 506 . As shown in FIG. 39, the buried power rail 211 includes a first buried power rail 211-1 and a second buried power rail 211-2.

Referring to FIG. 36 and FIG. 40 , the method 500 includes step 508 of forming the isolation member 214 . In some embodiments, to protect the buried power rail 211 from oxidation, a second liner 213 may be deposited over the buried power rail 211 . The second liner 213 may be similar to the first liner 210 in terms of composition and formation. As shown in FIG. 41 , the buried power rail 211 is surrounded by a first liner 210 and a second liner 213 . An isolation part 214 is then formed on the second liner 213 . Since the method 100 has already described the formation of the isolation features 214, a detailed description thereof is omitted for brevity. After the isolation member 214 is formed, the second liner 213 is selectively etched away until the stacked portion 209S of the first fin structure 209 is exposed.

Referring to FIG. 36 and FIG. 41 , the method 500 includes a step 510 of depositing a sacrificial spacer layer 216 on the first fin structure 209 and the isolation features 214 . Since the operation of step 510 is similar to the operation of step 108, its detailed description is omitted for brevity.

Referring to FIGS. 36 and 41 , method 500 includes step 512 of depositing first dielectric layer 218 over sacrificial spacer layer 216 . Since the operation of step 512 is similar to the operation of step 110, its detailed description is omitted for brevity.

Referring to FIG. 36 and FIG. 42 , the method 500 includes a step 514 of selectively etching back the sacrificial spacer layer 216 to release the stack portion 209S of the first fin structure 209 . Since the operation of step 514 is similar to that of step 112, its detailed description is omitted for brevity. At the end of the operation at step 514, mixing fins 217 are formed on both sides of the stack portion 209S. Each hybrid fin 217 includes a sacrificial spacer layer 216 and a first dielectric layer 218 over the sacrificial spacer layer 216 .

Referring to FIG. 36 and FIG. 43 , method 500 includes step 516 of forming dummy gate stack 222 over stack portion 209S and hybrid fin 217 . Since the operation of step 516 is similar to that of step 114, its detailed description is omitted for brevity.

Referring to FIG. 36 and FIG. 43 , the method 500 includes a step 518 of etching back the source/drain portion of the first fin structure 209 to form the source/drain notch 224 . Since the operation of step 518 is similar to that of step 116, its detailed description is omitted for brevity.

Referring to FIGS. 36 and 44 , method 500 includes step 520 of forming inner spacer member 226 . Since the operation of step 520 is similar to that of step 118, its detailed description is omitted for brevity.

Referring to FIGS. 36 , 45A, and 45B, the method 500 includes step 522 of forming a first source feature 228S and a first drain feature 228D in the source/drain trench 224 . Since the operation of step 522 is similar to the operation of step 120, its detailed description is omitted for brevity.

Referring to FIGS. 36 , 45A, and 45B, method 500 includes step 524 of replacing dummy gate stack 222 with a first gate structure (the view of which is blocked by first source feature 228S). Since the operation of step 524 is similar to that of step 122, its detailed description is omitted for brevity.

Referring to FIG. 36 , FIG. 46A and FIG. 46B , the method 500 includes step 526 of forming the first drain contact 234 , the first source contact 235 and the fourth contact via 215 . In an example process, a lithography process is used to form contact openings exposing the first source feature 228S and the first drain feature 228D. An additional lithography process may be used to form a via opening for the fourth contact via 215, and the via opening exposes the first buried power rail 211-1. In order to reduce the contact resistance, a silicide layer may be formed on the first source feature 228S and the first drain feature 228D by depositing a metal layer on the first source feature 228S and the first drain feature 228D, and performing annealing process to induce silicidation between the metal layer and the first source feature 228S and between the metal layer and the first drain feature 228D. Here, a suitable metal layer may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The silicide layer may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). After the silicide layer is formed, a metal fill layer can be deposited into the contact openings and the contact via openings. Metal fill layers can include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). A planarization process may then be performed to remove excess material and form the fourth contact via 215 , the first source contact 235 and the first drain contact 234 .

Referring to FIGS. 36 , 47A, and 47B, the method 500 includes a step 528 of bonding the second stack 240 to the workpiece 200 . Since the operation of step 528 is similar to that of step 126, its detailed description is omitted for brevity.

Referring to FIGS. 36 , 48A, 48B, 49A, and 49B, the method 500 includes step 530 of performing the operations in steps 504 , 510 - 524 on the second stack 240 . Since the process operations are similar to those described above, only the operations in step 530 are summarized for brevity. Referring to FIG. 48A and FIG. 48B , at step 504 the second stack 240 is patterned to form a third fin structure 2092 . Unlike the second fin structure 2090, the third fin structure 2092 is not in vertical alignment with the first fin structure 209 (its position is marked by the base portion 209B). The third fin structure 2092 is intentionally offset by a distance D from the first fin structure 209 as measured from the respective midline. In some examples, the displacement distance D may be between about 5 nm and about 150 nm. In this regard, displacement distances of less than 5 nm fall within the typical misalignment range and may not be sufficient to yield a benefit. The displacement distance is less than 150 nm, which is about the largest dimension of the mixing fin 217 . If the displacement distance is greater than 150nm, the benefit of reducing parasitic capacitance may be reduced. Since the embedded power rail 211 has already been formed, the operation of step 506 can be omitted. Since the third fin structure 2092 is insulated by the capping layer 236 and the base layer 238 , the operation of step 508 can be omitted. With continued reference to FIGS. 48A and 48B , at steps 510 , 512 and 514 , top mixing fins 242 are formed on both sides of the third fin structure 2092 . At step 516, a corresponding dummy gate stack is formed over the channel region of the third fin structure 2092 to serve as a placeholder for a functional second gate structure. At step 518 , source/drain portions of the third fin structure 2092 are etched back to form source/drain recesses, similar to source/drain trenches 224 . At step 520, the sacrificial layer 206 in the channel region is selectively and partially etched to form an inner spacer recess, and an inner spacer feature is formed in the inner spacer recess. 49A and 49B, at step 522, a second source feature 244S and a second drain feature 244D are formed in the source/drain recesses. At step 524, the dummy gate stack above the third fin structure is replaced with the second gate structure. The sacrificial layer 206 in the channel region is selectively removed to release the channel layer 208 as channel members, and a second gate structure surrounds each channel member. Before replacing the dummy gate stack, a second CESL 246 and a second ILD layer 248 are sequentially deposited over the top hybrid fin 242, the second source feature 244S, and the second drain feature 244D, as shown in FIGS. 49A and 244D. Figure 49B.

Referring to FIG. 36, FIG. 50A and FIG. 50B, method 500 includes step 532, step 532 forms fifth contact via 259, top source contact 250, second drain contact 252, second contact via 260 and the third contact hole 262 . As shown in FIG. 50A, a top source contact 250 is formed over and in contact with the second source feature 244S. Similar to the first drain contact 234 , a contact opening is first formed to expose the second source feature 244S. Via openings for fifth contact vias 259 are then formed through base layer 238, cap layer 236, mixing fins 217, isolation features 214, and second liner layer 213 to expose second buried power rail 211. -2. After forming the contact opening and the via opening, a silicide layer is formed on the second source feature 244S, and a metal filling layer is deposited to fill the remaining contact opening. The fifth contact via 259 is used to couple the top source contact 250 and the second buried power rail 211-2. In a similar manner, a second drain contact 252 is formed over and in contact with the second drain feature 244D. The top source contact 250 and the second drain contact 252 can be formed in the same process step. After the top source contact 250 and the second drain contact 252 are formed, an etch stop layer (ESL) 254 and a third ILD layer 256 are deposited over the top source contact 250 and the second drain contact 252 to protect A top source contact 250 and a second drain contact 252 .

The formation of the second contact via 260 and the third contact via 262 may include forming a via opening through at least the ESL 254 and the third ILD layer 256 and depositing a metal fill layer. Metal fill layers can include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). In some embodiments, each of the second contact via 260 and the third contact via 262 may include a liner between the metal fill layer and the adjacent dielectric material to improve electrical integrity. The liner may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN), or tantalum nitride (TaN). Because forming the second contact via 260 requires forming not only through the ESL 254 and the third ILD layer 256 but also extending through the second ILD layer 248, the second CESL 246, the top mixing fin 242, the base layer 238, and the capping layer 236 The via opening for the second contact via 260 is not formed simultaneously with the via opening for the third contact via 262 . In some other embodiments, the via opening for the second contact via 260 is formed separately and etched in multiple etch stages.

Referring to FIG. 36 , FIG. 50A , and FIG. 50B , method 500 includes step 534 of forming top interconnect structure 270 . The top interconnect structure 270 includes a first protective layer 263 and conductive features in the first protective layer 263 . In the depicted embodiment, the conductive features include a first lead 266 and a second lead 268 . In an example process, a first protective layer 263 is deposited on the workpiece 200 , thereafter the first protective layer 263 is patterned, and a conductive material is deposited on the patterned first protective layer 263 . Although the top interconnect structure 270 in FIGS. 50A and 50B includes only one interconnect layer, the top interconnect structure 270 may include more interconnect layers, and may include all interconnect layers on the workpiece 200 . As shown in FIG. 50B , the second contact via 260 directly contacts the first wire 266 , and the third contact via 262 directly contacts the second wire 268 .

Reference is now made to Figures 50A and 50B. After the operations in the method 500 are completed, the first MBC transistor 10 and the second MBC transistor 20 above the first MBC transistor 10 are formed. The first MBC transistor 10 includes a channel member interposed between a first source feature 228S and a first drain feature 228D. The first gate structure of the first MBC transistor 10 , the view of which is blocked by the first source features 228S, surrounds each of its channel members. The second MBC transistor 20 includes a channel member interposed between a second source feature 244S and a second drain feature 244D. A second gate structure of the second MBC transistor 20 (view of which is blocked by second source features 244S) surrounds each of its channel members. The first source feature 228S is coupled to the first buried power rail 211 - 1 through the first source contact 235 and the fourth contact via 215 . The second source feature 244S is coupled to the first buried power rail 211 - 2 through the top source contact 250 and the fifth contact via 259 . Both the first drain feature 228D and the second drain feature 244D are electrically coupled to conductive features in the top interconnect structure 270 . The first drain feature 228D is coupled to the first wire 266 through the first drain contact 234 and the second contact via 260 . The second contact via 260 extends through the top mixing fin 242 along the Z direction. The second drain feature 244D is coupled to the second wire 268 through the third contact via 262 . Since the third fin structure 2092 is vertically offset by the displacement distance D from the first fin structure 209 along the X direction, the distance between the fifth contact via 259 and the first source part 228S and the second contact via 260 The displacement distance D is also increased by the distance from the second drain member 244D. The above increased distance can reduce parasitic capacitance and can improve process margin (windows).

FIGS. 51A and 51B illustrate alternate embodiments of structures formed using method 100 in conjunction with structures formed using method 500 . According to an alternative embodiment, the semiconductor device 200 is structurally similar to the semiconductor device 200 shown in FIGS. 17A and 17B, but the channel member of the second MBC transistor 20 is vertically offset from the channel member of the first MBC transistor 10. Set displacement distance D. In an alternative embodiment, the distance between the second contact via 260 and the second drain feature 244D is increased by a displacement distance D to reduce parasitic capacitance and increase process margin.

As shown in FIGS. 17A , 17B, 35A and 35B , in methods 100 and 300 , the channel member of the first MBC transistor 10 is vertically aligned with the channel member of the second MBC transistor 20 . This vertical alignment allows the formation of a common gate structure surrounding each channel member in the first MBC transistor 10 as well as in the second MBC transistor 20 . FIG. 52 illustrates a method 600 for forming a common gate structure when the channel member of the first MBC transistor 10 is vertically aligned with the channel member of the second MBC transistor 20 .

Referring to Figures 52 and 53, the method 600 includes step 602. Step 602 receives a first MBC transistor 10, and the first MBC transistor 10 includes a first channel member 2080 and a gate structure surrounding each first channel member 2080 406. In some embodiments, the first MBC transistor 10 is similar in structure to the first MBC transistor 10 shown in FIGS. 17A and 17B or FIGS. 35A and 35B. The gate structure 406 includes a first gate dielectric layer 402 and a first gate electrode layer 404 . In some embodiments, an interfacial layer is disposed between each first channel member 2080 and the first gate dielectric layer 402 . The composition and formation of the interface layer, the first gate dielectric layer 402 and the first gate electrode layer 404 are as described above, and will not be repeated here. When using the method 100, as shown in FIG. 53, the first channel member 2080 and at least a portion of the gate structure 406 are disposed between two mixing fins 217, each mixing fin includes a sacrificial spacer layer 216 and A first dielectric layer 218 on the sacrificial spacer layer 216 . When method 300 is employed (not explicitly shown), first channel member 2080 and at least a portion of gate structure 406 are disposed between two modular mixing fins 2170 , each modular mixing fin 2170 A conductive component is included embedded in the second dielectric layer and the third dielectric layer. Base portion 209B is disposed in isolation member 214 .

Referring to FIGS. 52 , 53 and 54 , method 600 includes step 604 , wherein second channel member 2082 is above first channel member 2080 . In an example process, the second fin structure 2090 is formed from the second stack 240 . The second stack 240 including the sacrificial layer 206 and the channel layer 208 is bonded to the first MBC transistor 10 by directly bonding the capping layer 236 on the first MBC transistor 10 and the base layer 238 on the bottom surface of the second stack 240 . When method 100 is employed, as shown in FIG. 53 , a second fin structure 2090 is disposed between but spaced from the two top mixing fins 242 . When method 300 is employed (not explicitly shown), second fin structure 2090 is disposed between but spaced from the two top modular mixing fins 2172 . After forming the second fin structure 2090, forming a dummy gate structure over the channel region of the second fin structure, etching back the source/drain region of the second fin structure to form a source/drain recess, And forming inner spacer features, forming source/drain features in the source/drain recesses. After removing the dummy gate structure, the sacrificial layer 206 is selectively removed to release the channel layer 208 as the second channel member 2082, as shown in FIG. 54 . The second channel member 2082 is vertically aligned with the first channel member 2080 .

Referring to FIGS. 52 and 55 , the method 600 includes a step 606 of forming an access opening 294 to the gate structure 406 . By using anisotropic etching, such as RIE or other suitable dry etching process, an access opening 294 is formed through the base layer 238 and the cap layer 236, thereby exposing the gate of the first MBC transistor 10 in the access opening 294. Structure 400.

Referring to FIGS. 52 and 56 , the method 600 includes step 608 , wherein the gate structure 406 is selectively removed to expose the first channel member 2080 . With the gate structure 406 exposed in the access opening 294 , the gate structure 406 in the access opening 294 is selectively removed to release the first channel member 2080 without substantially damaging the first channel member 2080 . In some embodiments shown in FIG. 56 , portions of base layer 238 and cap layer 236 may remain to form dielectric via feature 298 . In some other embodiments not explicitly shown, dielectric channel member 298 may not be present. It should be understood that in some embodiments, a portion of the gate structure 406 may exist between the cap layer 236 and the mixing fin 217 . In other embodiments where there are gate cut dielectric features, the gate structure 406 is not located between the cap layer and the hybrid fin 217 .

Referring to FIGS. 52 and 57 , the method 600 includes step 610 , wherein a common gate structure 412 is formed to surround each of the first channel member 2080 and the second channel member 2082 . The common gate structure 412 includes an interface layer, a common gate dielectric layer 408 above the interface layer, and a common gate electrode layer 410 above the common gate dielectric layer 408 . An interfacial layer of common gate structure 412 is disposed around and in contact with each first channel member 2080 , dielectric channel member 298 , and each second channel member 2082 . In some embodiments, the interfacial layer includes silicon oxide and may be formed during a pre-clean process. Exemplary pre-cleaning processes may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). Thereafter, a common gate dielectric layer 408 is deposited on the interface layer using ALD, CVD, and/or other suitable methods. The common gate dielectric layer 408 may be formed of a high-k dielectric material. As used and described in this disclosure, a high-k dielectric material includes a dielectric material having a high dielectric constant, eg, a dielectric constant greater than that of thermal silicon oxide (˜3.9). The common gate dielectric layer 408 may include hafnium oxide. Alternatively, the common gate dielectric layer 408 may include other high-k dielectric materials such as TiO ₂ , HfZrO, Ta ₂ O ₅ , HfSiO ₄ , ZrO ₂ , ZrSiO ₂ , La ₂ O ₃ , Al ₂ O ₃ , ZrO, Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfLaO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), SiN, SiON, combinations thereof or other suitable materials.

The common gate electrode layer 410 is then deposited on the common gate dielectric layer 408 using ALD, PVD, CVD, electron beam evaporation or other suitable methods. The common gate electrode layer 410 may comprise a single layer or alternatively a multi-layer structure such as various combinations of the following: metal layer with selected work function to enhance device performance (work function metal layer), liner layer, wetting layer, adhesion layer , metal alloys or metal silicides. For example, the common gate electrode layer 410 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations thereof. In addition, in the case that the semiconductor device 200 includes an n-type transistor and a p-type transistor, different common gate electrode layers may be formed for the n-type transistor and the p-type transistor respectively, and the n-type transistor and the p-type transistor Different metal layers may be included (eg, metal layers providing different n-type and p-type work functions).

Embodiments of the present disclosure provide several benefits. The present disclosure provides different contact structure solutions that can be combined in different embodiments. Contact structure schemes according to the present disclosure include, for example, double interconnect structures, hybrid fins with embedded conductive features, and bias device stacks. In a "dual interconnect structure", the source part of the first MBC transistor is coupled to the power rail in the first interconnect structure through the backside source contact, and the second MBC transistor (which is arranged on the first The source component on the MBC transistor) is coupled to the power rail in the second interconnect structure above the second MBC transistor. In "Hybrid Fins with Embedded Conductive Features", conductive features are embedded in each hybrid fin to provide contact modules that serve as conductive paths to interconnect structures. In the "biased device stack", the source/drain regions of the first MBC transistor and the second MBC transistor are biased against each other to increase the spacing between the contact vias and the drain features. The above-mentioned contact structure solution can provide process flexibility, and can improve device performance by reducing contact resistance or parasitic capacitance.

According to some embodiments of the present disclosure, there is provided a semiconductor device, comprising: a first interconnection structure; a first transistor on the first interconnection structure and comprising: a first nanostructure; and a first source element adjacent to (adjoining) a first nanostructure; a second transistor on the first transistor and comprising: the second nanostructure; and a second source feature adjacent to the second nanostructure; and a second interconnect structure, on a second transistor with a first source component coupled to a first power rail in a first interconnect structure and a second source component coupled to a second power rail in a second interconnect structure .

In some embodiments, the second nanostructures are vertically aligned with the first nanostructures.

In some embodiments, the first transistor further includes a first gate structure surrounding each first nanostructure, and the first gate structure extends lengthwise along a direction, wherein the first gate structure The two-transistor further includes a second gate structure surrounding each second nanostructure, and the second gate structure extends longitudinally along a direction wherein the second nanostructure is aligned with the first nanostructure along the direction Nanostructure offset (offset).

In some embodiments, it further includes: a gate structure surrounding each of the first nanostructures and each of the second nanostructures.

In some embodiments, the first transistor further includes a first drain component and a first drain contact, the first drain contact is on the first drain component and contacts the first drain component, wherein the first drain The pole contact is coupled to the first wire in the second interconnect structure through the first contact via.

In some embodiments, the second transistor further includes a second drain component and a second drain contact, the second drain contact is on the second drain component and contacts the second drain component, wherein the second drain The pole contact is coupled to a second wire in the second interconnect structure through the second contact via.

In some embodiments, the first source feature is coupled to the first power rail in the first interconnect structure through a backside source contact disposed directly below the first source feature.

According to some other embodiments of the present disclosure, there is provided a semiconductor device, including: a first interconnection structure; a first transistor on the first interconnection structure and including: a first nanostructure; and a first source component, adjoining the first nanostructure; a second transistor on the first transistor and comprising: the second nanostructure; and a second source feature adjacent to the second nanostructure; and a second interconnect structure at the Two transistors, where the first source feature is coupled to a first power rail in the first interconnect structure, and the second source feature is coupled to a second power rail in the first interconnect structure.

In some other embodiments, the first transistor further includes a first drain part and a first drain contact, the first drain contact is on the first drain part and contacts the first drain part, wherein the first The drain contact is coupled to the first wire in the second interconnect structure through the first contact via.

In some other embodiments, the second transistor further includes a second drain part and a second drain contact, and the second drain contact is on the second drain part and contacts the second drain part, wherein the second The drain contact is coupled to a second wire in the second interconnect structure through the second contact via.

In other embodiments, the first nanostructure is disposed between the first mixing fin and the second mixing fin, wherein the first mixing fin includes a first conductive component, and the first conductive component is embedded in the first interposer. Among the electrical components, wherein the second hybrid fin includes a second conductive component, the second conductive component is embedded in the second dielectric component.

In other embodiments, the first source feature is coupled to the first power supply rail in the first interconnect structure through the first conductive feature, wherein the second source feature is coupled to the power supply rail in the first interconnect structure through the second conductive feature. The second power rail in the connection structure.

In some other embodiments, the first transistor further includes a first drain part and a first drain contact, the first drain contact is on the first drain part and contacts the first drain part, wherein the first The drain feature and the first drain contact are disposed between the first mixing fin and the second mixing fin, wherein the first drain feature and the first drain contact are electrically connected to the first conductive feature and the second conductive feature. Sexual isolation.

In some other embodiments, the second nanostructure is disposed between the third mixing fin and the fourth mixing fin, wherein the third mixing fin includes a third conductive component, and the third conductive component is embedded in the first interposer. Among the electrical components, wherein the fourth mixing fin includes a fourth conductive component, the fourth conductive component is embedded in the second dielectric component.

In some other embodiments, the first transistor further includes a first drain part and a first drain contact, the first drain contact is on the first drain part and contacts the first drain part, wherein the first The drain contact is coupled to a first wire in the second interconnect structure through a first contact via extending through the first dielectric member and electrically isolated from the third conductive member.

According to still other embodiments of the present disclosure, there is provided a method of forming a semiconductor device, including: receiving a workpiece, the workpiece includes a first substrate and a first stack on the first substrate, the first stack includes a first plurality of sacrificial layers interleaved A first plurality of channel layers; a first fin structure is formed by the first stack and part of the first substrate, the first fin structure includes a first source region and a first drain region; a first mixed fin is formed and a second mixing fin, the first mixing fin and the second mixing fin extending parallel to the first fin structure, the first mixing fin comprising a first conductive component embedded in a first dielectric component, and The second hybrid fin includes a second conductive feature embedded in a second dielectric feature; a first source feature is formed on the first source region, and a first drain feature is formed on the first drain region ; forming a first source contact, the first source contact directly contacts the first source member and the first conductive member; forming a first drain contact, the first drain contact directly contacts the first drain member; Depositing a capping layer on the first source contact and on the first drain contact; bonding a second stack on the capping layer, the second stack including a second plurality of channels interleaved with a second plurality of sacrificial layers layer; form a second fin structure by the second stack, the second fin structure includes a second source region and a second drain region; form a third mixed fin and a fourth mixed fin, the third mixed fin and The fourth mixing fin extends parallel to the second fin structure, the third mixing fin includes a third conductive member embedded in a third dielectric member, and the fourth mixing fin includes a third conductive member embedded in a fourth dielectric member. A fourth conductive part among the parts; a second source part is formed on the second source region, and a second drain part is formed on the second drain region; a second source contact is formed, the second source The contact directly contacts the second source part and the third conductive part; and a second drain contact is formed, the second drain contact directly contacts the second drain part.

In still some embodiments, it further includes: forming a first contact via, the first contact via is coupled to the fourth conductive component and the second conductive component; forming a second contact via, the second contact via is connected to the first conductive component The component is below and contacts the first conductive component; and a third contact via is formed, the third contact via is below the second conductive component and contacts the second conductive component.

In still some embodiments, it further includes: forming a first interconnection structure on the second source contact and the second drain contact, the first interconnection structure including a first wire and a second wire; forming a fourth a contact via, the fourth contact via is coupled to the first drain contact and the first wire; and a fifth contact via is formed, the fifth contact via is coupled to the second drain contact and the second wire.

In yet other embodiments, the fourth contact via extends through the third dielectric member and is electrically isolated from the third conductive member.

In yet other embodiments, further comprising: forming a second interconnect structure under the first substrate, wherein the second interconnect structure includes a first power rail and a second power rail, wherein the first power rail is coupled to the second contact conductor holes, and the second power rail is coupled to a third contact via.

The components of several embodiments are summarized above so that those skilled in the art of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or advantages as the embodiments introduced here . Those who have ordinary knowledge in the technical field of the present invention should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can be made in various ways without departing from the spirit and scope of the present invention. Such changes, substitutions and substitutions. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10: The first MBC transistor 20: Second MBC transistor 100: method 102: Step 104: Step 106: Step 108: Step 110: Steps 112: Step 114: Step 116: Step 118: Step 120: Step 122: Step 124: Step 126: Step 128: Step 130: Step 132: Step 134: step 136: Step 200: workpiece 200: Semiconductor device 202: Substrate 204: First stack 206: sacrificial layer 208: Channel layer 209: fin structure 210: the first lining 211: Embedded Power Rail 213: second lining 214: isolation parts 216: sacrificial spacer layer 217: Mixed fins 218: The first dielectric layer 219: Conductive layer 221: The third dielectric layer 222:Dummy gate stack 224: source/drain notch 224: Source/drain trench 226: inner spacer part 230: first contact etch stop layer (CESL) 232: The first interlayer dielectric (ILD) layer 234: The first drain contact 235: first source contact 236: cover layer 237: Bridge contact hole 237 238: Base layer 239: Top conductive part 240: second stack 241: The fourth dielectric layer 242: top mixing fins 243: fifth dielectric layer 246:Second CESL 248:Second ILD layer 250: Top source contact 252: second drain contact 254: etch stop layer (ESL) 256: The third ILD layer 258: The first contact hole 259: Fifth contact hole 260: Second contact hole 262: The third contact hole 263: The first protective layer 264: top power rail 266: The first wire 268: Second wire 270: Top Interconnect Structure 272: back side silicide layer 274: Backside source contact 276: The first nitride liner 277: Second nitride liner 278:Second protective layer 279: First backside power rail 280: Second backside power rail 281: The first backside contact via 282: Dielectric filler 283: Second backside contact via 290:Backside Interconnection Structure 294: access opening 298:Dielectric channel components 300: method 302: Step 304: step 306: Step 308: Step 310: step 312: Step 314: Step 316: Step 318: Step 320: Step 322: Step 324: step 326: Step 328:Step 330: Step 332: Step 334: step 336: step 400: gate structure 402: the first gate dielectric layer 404: the first gate electrode layer 406:Gate structure 408: common gate dielectric layer 410: common gate electrode layer 412:Common gate structure 500: method 502: Step 504: step 506: Step 508: Step 510: step 512: Step 514: step 516: step 518:Step 520: step 522: Step 524: step 526: step 528:step 530: step 532: Step 534: step 600: method 602: Step 604: Step 606: Step 608: Step 610: Step 2080: first channel component 2082: Second channel component 2090: Second fin structure 2092: Third fin structure 2170: Modular Hybrid Fins 2172: Top Modular Hybrid Fins 2180: second dielectric layer 200D: Drain area 200S: source region 209B: Base part 209S: stacking part 211-1: First Embedded Power Rail 211-2: Second Embedded Power Rail 228D: first drain component 228S: first source component 244D: second drain component 244S: second source component D: distance H: height W: width

Various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly represent the features of the present disclosure. FIG. 1 is a flowchart illustrating a method for forming a semiconductor device having a backside power rail, according to one or more aspects of the present disclosure. Figures 2-10, 11A-17A, and 11B-17B illustrate partial cross-sectional views of a workpiece during a manufacturing process according to the method of Figure 1, according to one or more aspects of the present disclosure. FIG. 18 is a flowchart illustrating a method for forming a semiconductor device having a backside power rail, according to one or more aspects of the present disclosure. Figures 19-28, 29A-35A, and 29B-35B illustrate partial cross-sectional views of a workpiece during a fabrication process according to the method of Figure 18, according to one or more aspects of the present disclosure. FIG. 36 is a flowchart illustrating a method for forming a semiconductor device having a backside power rail, according to one or more aspects of the present disclosure. Figures 37-44, 45A-50A, and 45B-50B illustrate partial cross-sectional views of a workpiece during a fabrication process according to the method of Figure 36, according to one or more aspects of the present disclosure. 51A and 51B are partial cross-sectional views of semiconductor devices according to one or more aspects of the present disclosure. FIG. 52 is a flowchart illustrating a method for forming a common gate structure according to one or more aspects of the present disclosure. Figures 53-57 are partial cross-sectional views of the workpiece at various stages of the method of Figure 52, in accordance with one or more aspects of the present disclosure.

200: Semiconductor device

200S: source region

202: Substrate

210: the first lining

214: isolation parts

216: sacrificial spacer layer

218: The first dielectric layer

228S: first source component

230: first contact etch stop layer (CESL)

232: The first interlayer dielectric (ILD) layer

236: cover layer

242: top mixing fins

244S: second source component

246:Second CESL

248:Second ILD layer

250: Top source contact

254: etch stop layer (ESL)

256: The third ILD layer

258: The first contact hole

263: The first protective layer

264: top power rail

270: Top Interconnect Structure

Claims (15)

A semiconductor device comprising: a first interconnection structure; a first transistor on the first interconnection structure and comprising: a plurality of first nanostructures; and a first source element adjacent to (adjoining) the first nanostructures; a second transistor on the first transistor and comprising: a plurality of second nanostructures; and a second source element adjacent to the second nanostructures; and A second interconnect structure, on the second transistor, wherein the first source element is vertically separated from the second source element by an interlayer dielectric layer and a base dielectric layer, the base dielectric layer an electrical layer over the interlayer dielectric layer, wherein the base dielectric layer extends from between the first source feature and the second source feature to between the first nanostructures and the second nanostructures extending continuously, wherein the first source feature is coupled to a first power rail in the first interconnect structure, and the second source feature is coupled to a first power rail in the second interconnect structure Two power rails. The semiconductor device according to claim 1, wherein the second nanostructures are vertically aligned with the first nanostructures. The semiconductor device as claimed in claim 1, wherein the first transistor further includes a first gate structure, the first gate structure surrounds each first nanostructure, and the first gate structure is along extending lengthwise in a direction, wherein the second transistor further includes a second gate structure surrounding each second nanometer nanostructures, and the second gate structure extends longitudinally along the direction, wherein the second nanostructures are offset from the first nanostructures along the direction. The semiconductor device according to any one of claims 1 to 3, further comprising: a gate structure surrounding each first nanostructure and each second nanostructure. The semiconductor device according to any one of claims 1 to 3, wherein the first transistor further includes a first drain part and a first drain contact, and the first drain contact is on the first The drain feature is on and contacts the first drain feature, wherein the first drain contact is coupled to a first wire in the second interconnect structure through a first contact via. The semiconductor device according to any one of claims 1 to 3, wherein the second transistor further includes a second drain member and a second drain contact, and the second drain contact is on the second The drain feature is on and contacts the second drain feature, wherein the second drain contact is coupled to a second wire in the second interconnect structure through a second contact via. The semiconductor device according to any one of claims 1 to 3, wherein the first source feature is coupled to the first interconnect by a backside source contact disposed directly below the first source feature The first power rail within the structure. A semiconductor device, comprising: a first interconnection structure, including a protection layer and a first power rail disposed in the protection layer; an isolation component, disposed on the first interconnection structure; a first electrical a crystal on the isolation member and comprising: a plurality of first nanostructures; and A first source element adjacent to the first nanostructures along a first direction; a second transistor on the first transistor and including: a plurality of second nanostructures; and a second a source feature adjoining the second nanostructures along the first direction; a second interconnect structure on the second transistor; and a backside source contact from the first power rail A top surface extends through the isolation feature to be electrically coupled to the first source feature, wherein the backside source contact is directly below the first source feature, and wherein the first source feature is along a Interposed between a first mixing fin and a second mixing fin, the second direction is perpendicular to the first direction, wherein the second source feature is coupled into the first interconnect structure of a second power rail. The semiconductor device as claimed in claim 8, wherein the first nanostructures are disposed between the first hybrid fin and the second hybrid fin, wherein the first hybrid fin includes a first a conductive member embedded in a first dielectric member, wherein the second mixing fin includes a second conductive member embedded in a second dielectric member . The semiconductor device of claim 9, wherein the first source feature is coupled to the first power rail in the first interconnect structure through the first conductive feature, wherein the second source feature is coupled through the The second conductive member is coupled to the the second power rail. The semiconductor device as claimed in claim 8, wherein the second nanostructures are disposed between a third mixed fin and a fourth mixed fin, wherein the third mixed fin includes a third conductive member, The third conductive part is embedded in a first dielectric part, wherein the fourth mixing fin includes a fourth conductive part, and the fourth conductive part is embedded in a second dielectric part. A method of forming a semiconductor device, comprising: receiving a workpiece including a first substrate and a first stack on the first substrate, the first stack including a first plurality of sacrificial layers interleaved A plurality of channel layers; a first fin structure is formed from the first stack and a part of the first substrate, and the first fin structure includes a first source region and a first drain region; forming A first mixing fin and a second mixing fin, the first mixing fin and the second mixing fin extend parallel to the first fin structure, the first mixing fin includes a first mixing fin embedded in a first a first conductive part among the dielectric parts, and the second hybrid fin includes a second conductive part embedded in a second dielectric part; a first A source feature, and a first drain feature is formed on the first drain region; a first source contact is formed, and the first source contact directly contacts the first source feature and the first conductive components; forming a first drain contact directly contacting the first drain member; depositing a capping layer on the first source contact and on the first drain contact; bonding a second stack on the cap layer, the second stack including a second plurality of channel layers interleaved with a second plurality of sacrificial layers; forming a second fin structure from the second stack, The second fin structure includes a second source region and a second drain region; a third mixed fin and a fourth mixed fin are formed, and the third mixed fin and the fourth mixed fin are parallel Extending from the second fin structure, the third hybrid fin includes a third conductive member embedded in a third dielectric member, and the fourth hybrid fin includes a fourth dielectric member embedded in a fourth dielectric member. A fourth conductive member among the members; forming a second source member on the second source region, and forming a second drain member on the second drain region; forming a second source contact A member, the second source contact directly contacts the second source member and the third conductive member; and a second drain contact is formed, the second drain contact directly contacts the second drain member. The method for forming a semiconductor device as claimed in claim 12, further comprising: forming a first contact hole coupled to the fourth conductive member and the second conductive member; forming a second contact hole hole, the second contact via is under the first conductive member and contacts the first conductive member; and forming a third contact via, the third contact via is under the second conductive member and contacts the second Conductive parts. The method for forming a semiconductor device as claimed in claim 13, further comprising: forming a first interconnection structure on the second source contact and on the second drain contact, the first An interconnect structure includes a first wire and a second wire; forming a fourth contact via coupled to the first drain contact and the first wire; and forming a fifth contact The fifth contact via is coupled to the second drain contact and the second wire. The method for forming a semiconductor device according to claim 14, further comprising: forming a second interconnection structure under the first substrate, wherein the second interconnection structure includes a first power rail and a second power rail, Wherein the first power rail is coupled to the second contact via, and the second power rail is coupled to the third contact via.

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