TWI819508B - Transflective liquid crystal panel - Google Patents

Abstract

A transflective liquid crystal panel includes a first substrate, a first active device, a patterned insulation layer, a first bottom transparent electrode, a reflective layer, a planarization layer, a first top transparent electrode, a second substrate and a liquid crystal layer. The patterned insulation layer is located on the first active device and includes a raised platform, bump structures and a first opening. The first bottom transparent electrode is located above the raised platform and the bump structures, and is electrically connected with the first active device. The reflective layer is located above the bump structures. The planarization layer is located above the patterned insulation layer and the first bottom transparent electrode, and includes a first through hole overlapping the raised platform. The first top transparent electrode is electrically connected to the first bottom transparent electrode through the first through hole.

Description

Half-through reverse LCD panel

The invention relates to a semi-transflective liquid crystal panel.

With the advancement of science and technology, the application of portable electronic products has become more and more popular. For example, portable electronic products such as smart phones, tablet computers, and watches have become omnipresent in human life. Generally speaking, in order to make electronic products easier to carry, many manufacturers are committed to reducing the size of electronic products, which also limits the size and capacity of batteries of portable electronic products. Therefore, in order to ensure that electronic products have a sufficiently high battery life, it is very important to reduce the power consumption of electronic products. Among some electronic products with display functions, semi-transverse display technology that emphasizes power-saving functions and outdoor visibility is extremely competitive.

The present invention provides a semi-transflective liquid crystal panel that has the advantages of high reflective area and high penetration area.

At least one embodiment of the present invention provides a semi-transflective liquid crystal panel including a first substrate, a first active element, a patterned insulating layer, a first bottom transparent electrode, a reflective layer, a flat layer, a first top transparent electrode, a second substrate and a liquid crystal layer. The first active component is located on the first substrate. The patterned insulation layer is located on the first active component and includes a raised platform, a plurality of bump structures and a first opening. The first bottom transparent electrode is filled in the first opening and extends from the first opening to the first penetration area. The first bottom transparent electrode is located on the raised platform and part of the bump structure and is electrically connected to the first active element. The reflective layer is located on the bump structure and overlaps the first reflective area. The flat layer is located on the patterned insulating layer and the first bottom transparent electrode, and includes a first through hole overlapping the raised platform. The first top transparent electrode overlaps the first reflective area and is electrically connected to the first bottom transparent electrode through the first through hole. The second substrate overlaps the first substrate. The liquid crystal layer is located between the first substrate and the second substrate.

1,2: Semi-transverse LCD panel

100: First substrate

100t, 162t, 164t: top surface

110a: first semiconductor layer

112a, 118a, 112b, 118b: source region

115a, 115b: drain area

113a, 117a, 113b, 117b: Passage area

110b: Second semiconductor layer

120, 140: Insulating layer

132a, 134a, 132b, 134b: Gate

152a, 158a, 152b, 158b: source

155a, 155b: drain

160:Patterned insulation layer

162: Raised platform

164: Bump structure

170a: First bottom transparent electrode

172a, 176a, 172b: block part

176a, 176b: connection part

170b: Second bottom transparent electrode

180:Flat layer

190a: First transparent electrode

190b: Second top transparent electrode

190c: The third top transparent electrode

200: Second substrate

210:Black Matrix

220: Color conversion component

230: Covering layer

240: Common electrode

300: Liquid crystal layer

A-A’, B-B’, C-C’: line

BLM: light blocking layer

BP1: first buffer layer

BP2: Second buffer layer

BP3: The third buffer layer

DR1: first direction

DR2: Second direction

H1: first opening

H2: Second opening

H3: The third opening

H4: The fourth opening

HD: height difference

LS: shading area

O: Open your mouth

OP1: First opening

PX: pixel structure

R1, R2, R3: area

RL: reflective layer

RF1: first reflection area

RF2: Second reflection zone

RF3: The third reflection zone

SP1: first sub-pixel

SP2: Second sub-pixel

SP3: The third sub-pixel

T1: The first active component

T2: The second active component

TK1, TK2: Thickness

TP1: First penetration zone

TP2: Second penetration zone

TP3: The third penetration zone

w1, w2, w3, w4, w5, w6: width

θ: included angle

1A to 1I are schematic top views of the manufacturing process of a semi-transflective liquid crystal panel according to an embodiment of the present invention.

2A to 2I are schematic cross-sectional views of the manufacturing process of a semi-transflective liquid crystal panel according to an embodiment of the present invention.

3 is a schematic cross-sectional view of a semi-transflective liquid crystal panel according to an embodiment of the present invention.

Figures 1A to 1I illustrate a semi-penetrating anti-fluid system according to an embodiment of the present invention. A top view of the manufacturing process of crystal panels. 2A to 2I are cross-sectional schematic diagrams of the manufacturing process of a semi-reflective liquid crystal panel according to an embodiment of the present invention, wherein FIGS. 2A to 2I correspond to lines A-A' and B-B in FIGS. 1A to 1I 'and C-C' part. 1A to 1I and 2A to 2I take one pixel structure of the transflective liquid crystal panel as an example. However, in fact, the transflective liquid crystal panel may include multiple pixel structures.

Referring to FIGS. 1A and 2A , a first semiconductor layer 110 a and a second semiconductor layer 110 b are formed on the first substrate 100 . In this embodiment, the pixel structure PX of the semi-transflective liquid crystal panel includes a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 (drawn in Figure 1I), and the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 each include a first semiconductor layer 110a and a second semiconductor layer 110b. In other words, one pixel structure PX includes three first semiconductor layers 110a and three second semiconductor layers 110b.

The first substrate 100 is a transparent substrate, and its material is, for example, glass, quartz, organic polymer or other applicable materials.

The first semiconductor layer 110a and the second semiconductor layer 110b are single-layer or multi-layer structures, which include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, Indium gallium zinc oxide or other suitable materials or combinations of the above) or other suitable materials or combinations of the above materials.

In this embodiment, the first semiconductor layer 110a includes a drain region 115a, a source region 112a, a source region 118a, a channel region 113a and a channel region 117a. Jiji District 115a is located between the channel region 113a and the channel region 117a. The channel region 113a is located between the drain region 115a and the source region 112a. The channel region 117a is located between the drain region 115a and the source region 118a. The width w2 of the drain region 115a, the source region 112a and the source region 118a is greater than the width w1 of the channel region 113a and the channel region 117a, making it easier for the drain region 115a, the source region 112a and the source region 118a to communicate with other conductive components. Alignment/contact.

In this embodiment, the second semiconductor layer 110b includes a drain region 115b, a source region 112b, a source region 118b, a channel region 113b and a channel region 117b. The drain region 115b is located between the channel region 113b and the channel region 117b. The channel region 113b is located between the drain region 115b and the source region 112b. The channel region 117b is located between the drain region 115b and the source region 118b. The width w2 of the drain region 115b, the source region 112b and the source region 118b is greater than the width w1 of the channel region 113b and the channel region 117b, making it easier for the drain region 115b, the source region 112b and the source region 118b to communicate with other conductive components. Alignment/contact.

In some embodiments, the first semiconductor layer 110a and the second semiconductor layer 110b of the same sub-pixel are aligned along the first direction DR1, but the invention is not limited thereto. In some embodiments, the first semiconductor layers 110a of adjacent sub-pixels are aligned along the second direction DR2, and the second semiconductor layers 110b of adjacent sub-pixels are aligned along the second direction DR2, but this is not the case in the present invention. is limited. The first direction DR1 is substantially perpendicular to the second direction DR2.

Referring to FIG. 1B and FIG. 2B, an insulating layer 120 (for convenience of explanation, FIG. 1B shows the insulating layer 120 in a perspective manner) is formed on the first semiconductor layer 110a and the second semiconductor layer 110a. on the semiconductor layer 110b. Gate electrodes 132a, 134a, 132b, and 134b are formed on the insulating layer 120.

The gate 132a and the gate 134a respectively overlap the channel region 113a and the channel region 117a of the first semiconductor layer 110a. The gate 132b and the gate 134b respectively overlap the channel region 113b and the channel region 117b of the second semiconductor layer 110b.

In this embodiment, the gate 132a and the gate 134a are electrically connected to the same scan line (not shown in the figure). The scan line is, for example, directly or indirectly connected to the gate 132a and the gate 134a. The gate 132b and the gate 134b are electrically connected to another scan line (not shown in the figure), for example, the scan line is directly or indirectly connected to the gate 132b and the gate 134b.

In some embodiments, in the same pixel structure PX of the transflective liquid crystal panel, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 of different colors (drawn in Figure 1I) The plurality of gates 132a and 134a are electrically connected to the same scan line, and the plurality of gates 132b and gates of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 of different colors are electrically connected to the same scan line. Pole 134b is electrically connected to another scan line. In other words, each pixel structure PX of the transflective liquid crystal panel includes two scanning lines, wherein the two scanning lines of adjacent pixel structures (for example, the same row of pixel structures arranged along the second direction DR2) Connect to each other.

Referring to FIGS. 1C and 2C , an insulating layer 140 (for convenience of explanation, FIG. 1C shows the insulating layer 140 in perspective) is formed on the gates 132a, 134a, 132b, 134b and the insulating layer 120. The insulating layer 140 has a plurality of openings O. The openings O respectively overlap the drain region 115a, the source region 112a and the source region of the first semiconductor layer 110a. 118a and the drain region 115b, the source region 112b and the source region 118b of the second semiconductor layer 110b.

Referring to FIG. 1C, FIG. 1D and FIG. 2D, a source electrode 152a, a source electrode 158a and a drain electrode 155a are formed on the first semiconductor layer 110a. The source electrode 152a and the source electrode 158a are respectively located on both sides of the drain electrode 155a. The source electrode 152a and the source electrode 158a are electrically connected to the source electrode region 112a and the source electrode region 118a of the first semiconductor layer 110a respectively through the opening O, and the drain electrode 155a is electrically connected to the first semiconductor layer 110a through the opening O. Drain region 115a. In other words, the first semiconductor layer 110a is electrically connected to the drain electrode 155a, the source electrode 152a and the source electrode 158a.

The source electrode 152b, the source electrode 158b and the drain electrode 155b are formed on the second semiconductor layer 110b. The source electrode 152b and the source electrode 158b are respectively located on both sides of the drain electrode 155b. The source electrode 152b and the source electrode 158b are electrically connected to the source region 112b and the source region 118b of the second semiconductor layer 110b respectively through the opening O, and the drain electrode 155b is electrically connected to the second semiconductor layer 110b through the opening O. Drain region 115b. In other words, the second semiconductor layer 110b is electrically connected to the drain electrode 155b, the source electrode 152b and the source electrode 158b.

In this embodiment, the source electrode 152a and the source electrode 152b are directly connected, and the source electrode 158a and the source electrode 158b are directly connected. In this embodiment, the source electrode 152a and the source electrode 152b are electrically connected to the same data line (not shown in the figure). The source electrode 158a and the source electrode 158b are electrically connected to another same data line (not shown in the figure). The aforementioned data line is, for example, directly connected or indirectly connected to the source electrode 152a and the source electrode 152b, and the aforementioned other data line is, for example, connected to the source electrode 152a and the source electrode 152b. The source electrode 158a and the source electrode 158b are directly connected or indirectly connected.

In this embodiment, the first active device T1 includes a first semiconductor layer 110a, a gate 132a, a gate 134a, a source 152a, a source 158a and a drain 155a, and the second active device T2 includes a second semiconductor layer 110b. , gate 132b, gate 134b, source 152b, source 158b and drain 155b. In some embodiments, the first active element T1 and the second active element T2 are electrically connected to different scan lines respectively. For example, the gate 132a and the gate 134a of the first active element T1 are electrically connected to the same first scan line, and the gate 132b and the gate 134b of the second active element T2 are electrically connected to the same second scan line. Scan lines.

In some embodiments, in the same pixel structure PX (drawn in FIG. 1I ) of the semi-transverse liquid crystal panel, the first sub-pixel SP1 , the second sub-pixel SP2 and the third sub-pixel SP3 (drawn in FIG. 1I ) 1I) The source electrode 152a and the source electrode 158a of the respective first active element T1 and the source electrode 152b and the source electrode 158b of the second active element T2 are electrically connected to the same data line, and the first sub-pixel SP1 of different colors The first active element T1 and the second active element T2 of the second sub-pixel SP2 and the third sub-pixel SP3 are electrically connected to different data lines. For example, in a pixel structure PX, the source electrode 152a and the source electrode 158a of the first active element T1 of the first sub-pixel SP1 and the source electrode 152b and the source electrode 158b of the second active element T2 are electrically connected to The same first data line. In the second sub-pixel SP2, the source electrode 152a and the source electrode 158a of the first active element T1 and the source electrode 152b and the source electrode 158b of the second active element T2 are electrically connected to the same second data line. In the third sub-pixel SP3, the source electrode 152a and the source electrode 158a of the first active element T1 and the source electrode 152b and the source electrode 158b of the second active element T2 are electrically connected to the same third data line. In other words, each pixel The structure includes three data lines, in which the three data lines of adjacent pixel structures (for example, pixel structures of the same row arranged along the first direction DR1) are connected to each other.

In this embodiment, the first active element T1 and the second active element T2 are top gate thin film transistors, but the invention is not limited thereto. In other embodiments, the first active element T1 and the second active element T2 are bottom gate thin film transistors, double gate thin film transistors, or other types of thin film transistors.

Referring to FIGS. 1E and 2E , a patterned insulating layer 160 is formed on the insulating layer 140 , the source electrode 152 a , the source electrode 158 a , the drain electrode 155 a , the source electrode 152 b , the source electrode 158 b and the drain electrode 155 b . The patterned insulation layer 160 is located on the first active element T1 and the second active element T2. The patterned insulation layer 160 includes a plurality of raised platforms 162, a plurality of bump structures 164, and a plurality of first openings H1. The plurality of first openings H1 overlap the drain electrode 155a and the drain electrode 155b respectively. It should be noted that the size, shape and position of the raised platform 162 and the bump structure 164 can be adjusted according to actual needs and are not limited to the size, shape and position shown in FIG. 1E and FIG. 2E . In addition, the raised platform 162 and the bump structure 164 in FIGS. 1E and 2E are only for illustration, and the bump structures passed by the lines AA', BB' and CC' in the top view of FIG. 1E The number and shape of the bump structures 164 do not strictly correspond to the number and shape of the bump structures 164 shown in the cross-sectional view of FIG. 2E .

In some embodiments, based on the top surface 100t of the first substrate 100, the height of the top surface 162t of the raised platform 162 is higher than the height of the top surface 164t of the bump structure 164. In some embodiments, the height difference HD between the top surface 162t of the raised platform 162 and the top surface 164t of the bump structure 164 is HD. In some embodiments, the height difference HD is 0.2 micron meters to 1.6 microns.

In some embodiments, the material of patterned insulating layer 160 includes cured photoresist material. In some embodiments, the patterned insulating layer 160 is formed through one or more photolithography processes.

FIG. 1F omits the first buffer layer BP1 and the reflective layer RL. Referring to FIG. 1E, FIG. 1F and FIG. 2F, a first bottom transparent electrode 170a and a second bottom transparent electrode 170b are formed on the patterned insulating layer 160. The first bottom transparent electrode 170a is filled in part of the first opening H1 and is electrically connected to the drain 155a of the first active component T1 (please refer to FIG. 1D), and the second bottom transparent electrode 170b is filled in another part of the first opening H1. In an opening H1, and electrically connected to the drain 155b of the second active component T2 (please refer to FIG. 1D).

In this embodiment, the first bottom transparent electrode 170a and the second bottom transparent electrode 170b are located on the raised platform 162 and part of the bump structure 164. In some embodiments, the first bottom transparent electrode 170a and the second bottom transparent electrode 170b cover the corresponding top surface 162t of the raised platform 162 and the corresponding top surface 164t of the partial bump structure 164.

In some embodiments, the materials of the first bottom transparent electrode 170a and the second bottom transparent electrode 170b include metal oxides (such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or a stacked layer of at least two of the above), metal nitride or other suitable transparent conductive materials. In some embodiments, the thickness of the first bottom transparent electrode 170a and the second bottom transparent electrode 170b is 30 nm to 100 nm.

In this embodiment, the first bottom transparent electrode 170a includes a block portion 172a, a block portion 174a and a connecting portion 176a. The width of the block portion 172a and the block portion 174a The width w4 is greater than the width w3 of the connecting portion 176a, and the connecting portion 176a connects the block portion 172a and the block portion 174a. In this embodiment, the block portion 172a and the block portion 174a are located at both ends of the connecting portion 176a, and the connecting portion 176a fills the first opening H1 and is connected to the drain electrode 155a.

In this embodiment, the second bottom transparent electrode 170b includes a block portion 172b and a connecting portion 176b. The width w6 of the block portion 172b is greater than the width w5 of the connection portion 176b, and the connection portion 176b is connected to the block portion 172b, and the connection portion 176b fills the first opening H1 and is connected to the drain 155b. In this embodiment, the block portion 172b of the second bottom transparent electrode 170b is located between the block portion 172a and the block portion 174a of the first bottom transparent electrode 170a in the first direction DR1.

A first buffer layer BP1 is formed on the patterned insulating layer 160 . In some embodiments, the first buffer layer BP1 is formed on the first bottom transparent electrode 170a, the second bottom transparent electrode 170b and the patterned insulating layer 160, and the first buffer layer BP1 has a plurality of layers overlapping the raised platform 162. A second opening H2. A portion of the second opening H2 exposes the block portion 172a and the block portion 174a of the first bottom transparent electrode 170a, and the other portion of the second opening H2 exposes the block portion 172b of the second bottom transparent electrode 170b.

In some embodiments, the material of the first buffer layer BP1 is, for example, silicon oxide, silicon nitride, silicon oxynitride, polymer materials, resin or other insulating materials. In some embodiments, the thickness of the first buffer layer BP1 is 10 nm to 500 nm.

A reflective layer RL is formed on the first buffer layer BP1. The reflective layer RL is located on the bump structure 164 and has an undulating surface corresponding to the bump structure 164 . The reflective layer RL has a plurality of third openings H3 overlapping the raised platform 162 . Part three open The opening H3 exposes the block portion 172a and the block portion 174a of the first bottom transparent electrode 170a, and the other third opening H3 exposes the block portion 172b of the second bottom transparent electrode 170b.

In some embodiments, the material of the reflective layer RL includes metal, such as silver, magnesium, aluminum or alloys of the above metals. In some embodiments, the thickness of the reflective layer RL is 10 nm to 500 nm.

In some embodiments, the reflective layer RL does not overlap the first opening H1 in the normal direction of the top surface 100t of the first substrate 100 . In the normal direction of the top surface 100t of the first substrate 100, the reflective layer RL does not overlap the raised platform 162.

Referring to FIG. 1G and FIG. 2G, a flat layer 180 is formed on the reflective layer RL. In this embodiment, the flat layer 180 is located on the first bottom transparent electrode 170a, the second bottom transparent electrode 170b and the patterned insulating layer 160. The flat layer 180 has a plurality of first through holes OP1 overlapping the raised platforms 162 . In some embodiments, the reflective layer RL does not overlap the first through hole OP1 in the normal direction of the top surface of the first substrate 100 . In this embodiment, part of the first through hole OP1 overlaps the first bottom transparent electrode 170a, and another part of the first through hole OP1 overlaps the second bottom transparent electrode 170b. In this embodiment, the first through hole OP1 overlaps the block portion 172a of the first bottom transparent electrode 170a, the block portion 174a of the first bottom transparent electrode 170a, and the block portion 172b of the second bottom transparent electrode 170b respectively. In some embodiments, the area of the bottom of the first through hole OP1 is smaller than the area of the top surface of the raised platform 162 . For example, the entire bottom surface of the first through hole OP1 overlaps the top surface of the raised platform 162 .

In some embodiments, the side walls of the first through hole OP1 are inclined so that the first through hole OP1 The width of the bottom of the hole OP1 is smaller than the width of the top of the first through hole OP1. In some embodiments, there is an included angle θ between 20 degrees and 60 degrees between the first through hole OP1 and the top surface of the first bottom transparent electrode 170a (or the top surface of the second bottom transparent electrode 170b).

In this embodiment, through the design of the raised platform 162, the side wall of the first through hole OP1 can be steeper, thereby reducing the area of the side wall of the first through hole OP1 vertically projected onto the first substrate 100 to increase the number of pixels. effective opening rate. For example, the flat layer 180 includes a cured photoresist material, and the method of forming the flat layer 180 includes a photolithography process. Due to the existence of the raised platform 162, the thickness of the photoresist material at the position overlapping the raised platform 162 is smaller. Therefore, the first through hole OP1 formed by performing the photolithography process is shallower and may have steeper sidewalls.

Referring to FIGS. 1H and 2H , a first top transparent electrode 190 a , a second top transparent electrode 190 b and a third top transparent electrode 190 c are formed on the flat layer 180 . The first top transparent electrode 190a and the third top transparent electrode 190c are electrically connected to the first bottom transparent electrode 170a, and the second top transparent electrode 190b is electrically connected to the second bottom transparent electrode 170b. In some embodiments, the materials of the first top transparent electrode 190a, the second top transparent electrode 190b, and the third top transparent electrode 190c include metal oxides (such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum Zinc oxide, indium gallium zinc oxide or a stacked layer of at least two of the above), metal nitride or other suitable transparent conductive materials. In some embodiments, the thickness of the first top transparent electrode 190a, the second top transparent electrode 190b, and the third top transparent electrode 190c is 30 nanometers to 100 nanometers.

In this embodiment, the first top transparent electrode 190a passes through part of the first through hole OP1 and is electrically connected to the first bottom transparent electrode 170a, and the third top transparent electrode 190c passes through Another part of the first through hole OP1 is electrically connected to the first bottom transparent electrode 170a, and the second top transparent electrode 190b is electrically connected to the second bottom transparent electrode 170b through another part of the first through hole OP1.

In this embodiment, the pixel structure PX of the semi-transflective liquid crystal panel includes a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 (drawn in Figure 1I), and the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 each include a first top transparent electrode 190a, a second top transparent electrode 190b, and a third top transparent electrode 190c. In other words, the pixel structure PX includes three first top transparent electrodes 190a, three second top transparent electrodes 190b, and three third top transparent electrodes 190c. In some embodiments, the three first top transparent electrodes 190a, the three second top transparent electrodes 190b, and the three third top transparent electrodes 190c are structurally separated from each other.

Referring to FIGS. 1I and 2I , a second substrate 200 , a black matrix 210 , a color conversion element 220 , a covering layer 230 and a common electrode 240 are provided. The liquid crystal layer 300 is provided between the first substrate 100 and the second substrate 200 . 1I omits the second substrate 200, the color conversion element 220, the cover layer 230, the common electrode 240 and the liquid crystal layer 300.

The second substrate 200 overlaps the first substrate 100 . The second substrate 200 is a transparent substrate, and its material is, for example, glass, quartz, organic polymer, or other applicable materials. The black matrix 210 is located on the second substrate 200. The material of the black matrix 210 includes, for example, black metal, black metal oxide, black resin or other suitable materials. The color conversion element 220 is located on the black matrix 210 and the second substrate 200. The color conversion element 220 is, for example, a filter element and/or a quantum dot material. Overlay 230 is located in the color on the conversion element 220. The common electrode 240 is located on the cover layer 230 . The liquid crystal layer 300 is located between the first substrate 100 and the second substrate 200 .

In this embodiment, the pixel structure PX includes a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel Pixel SP3 respectively corresponds to sub-pixels of different colors. For example, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 respectively have color conversion elements 220 of different colors.

In this embodiment, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 are located on the first substrate 100. The first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 are located on the first substrate 100. Each of the pixels SP3 has a first transmission area TP1, a second transmission area TP2, a third transmission area TP3, a first reflection area RF1, a second reflection area RF2 and a third reflection area RF3. In this embodiment, each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 also has a light shielding area LS.

In some embodiments, the first bottom transparent electrode 170a extends from the corresponding first opening H1 to the first penetration region TP1 and the third penetration region TP3. The first bottom transparent electrode 170a overlaps the first transmission region TP1 and the third transmission region TP3. The second bottom transparent electrode 170b extends from the corresponding first opening H1 to the second penetration region TP2. The second bottom transparent electrode 170b overlaps the second penetration region TP2.

The first top transparent electrode 190a overlaps the first transmission region TP1 and the first reflection region RF1. The second top transparent electrode 190b overlaps the second transmission region TP2 and the second reflection region RF2. The third top transparent electrode 190c overlaps the third transmission region TP3 and the third reflection region RF3.

The bump structure 164 and the reflective layer RL overlap the first reflective area RF1, the second reflective area RF2, and the third reflective area RF3.

In this embodiment, through the arrangement of the first through hole OP1, the thickness TK1 of the liquid crystal layer 300 in the first transmission area TP1, the second transmission area TP2 and the third transmission area TP3 is greater than the thickness TK1 of the liquid crystal layer 300 in the first reflection area. The thickness TK2 of the area RF1, the second reflective area RF2 and the third reflective area RF3. In some embodiments, the difference between thickness TK1 and thickness TK2 is 0.2 microns to 2.6 microns.

The light shielding area LS is located between the first reflective area RF1 and the second reflective area RF2 and between the third reflective area RF3 and the second reflective area RF2. In this embodiment, the light shielding area LS is defined by the black matrix 210 . The black matrix 210 overlaps the slit between the first reflective electrode 190a and the second reflective electrode 190b and the slit between the second reflective electrode 190b and the third reflective electrode 190c, thereby converting a single sub-pixel (the first sub-pixel) The pixel SP1, the second sub-pixel SP2 or the third sub-pixel SP3) is divided into three regions R1, R2 and R3. In this embodiment, the region R1 includes a first reflection region RF1 and a first transmission region TP1, the region R2 includes a second reflection region RF2 and a second transmission region TP2, and the region R3 includes a third reflection region RF3 and a third transmission region. Transparent zone TP3. In this embodiment, the first reflection area RF1, the second reflection area RF2, and the third reflection area RF3 surround the first transmission area TP1, the second transmission area TP2, and the third transmission area TP3 respectively. The second reflective area RF2 is located between the first reflective area RF1 and the third reflective area RF3, and the second transmission area TP2 is located between the first transmission area TP1 and the third transmission area TP3.

Based on the above, through the arrangement of the raised platform 162 , the first through hole OP1 is shallower and can have a steeper sidewall, thereby reducing the sidewall of the first through hole OP1 It affects the display quality and improves the effective aperture rate of the pixel structure PX.

3 is a schematic cross-sectional view of a semi-transflective liquid crystal panel according to an embodiment of the present invention. It must be noted here that the embodiment of Figure 3 follows the component numbers and part of the content of the embodiment of Figures 1A to 1I and 2A to 2I, where the same or similar numbers are used to represent the same or similar elements, and omissions are omitted. description of the same technical content. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The difference between the transflective liquid crystal panel 2 in FIG. 3 and the transflective liquid crystal panel 1 in FIG. 2I is that the transflective liquid crystal panel 2 further includes a light-shielding layer BLM, a second buffer layer BP2 and a third buffer layer BP3.

Referring to FIG. 3 , the first buffer layer BP1 is formed on the patterned insulating layer 160 . In some embodiments, the material of the first buffer layer BP1 is, for example, silicon oxide, silicon nitride, silicon oxynitride, polymer materials, resin or other insulating materials. In some embodiments, the thickness of the first buffer layer BP1 is 10 nm to 500 nm.

The light shielding layer BLM is formed on the first buffer layer BP1. The material of the light shielding layer BLM includes, for example, black metal (such as molybdenum), black metal oxide (such as molybdenum oxide), black resin or other suitable materials. In some embodiments, the thickness of the light shielding layer BLM is 10 nanometers to 500 nanometers. The light shielding layer BLM has a fourth opening H4 overlapping the first transmission area TP1, the second transmission area TP2, and the third transmission area TP3. The fourth opening H4 overlaps the raised platform 162 .

The second buffer layer BP2 is formed on the light shielding layer BLM. The light shielding layer BLM is located between the first buffer layer BP1 and the second buffer layer BP2. In some embodiments, the second buffer layer BP2 is made of materials such as silicon oxide, silicon nitride, silicon oxynitride, polymer materials, etc. materials, resin or other insulating materials. In some embodiments, the thickness of the second buffer layer BP2 is 10 nm to 500 nm.

The first bottom transparent electrode 170a and the second bottom transparent electrode 170b are formed on the second buffer layer BP2. The third buffer layer BP3 is formed on the first bottom transparent electrode 170a and the second bottom transparent electrode 170b, and the reflective layer RL is formed on the third buffer layer BP3. The third buffer layer has a plurality of second openings H2 overlapping the raised platform 162 . Part of the second opening H2 exposes the first bottom transparent electrode 170a, and another part of the second opening H2 exposes the second bottom transparent electrode 170b. The reflective layer RL has a third opening H3, and the second opening H2 and the third opening H3 overlap the raised platform 162.

To sum up, in the present invention, through the arrangement of the raised platform, the first through hole can have a steeper side wall, thereby reducing the impact of the side wall of the first through hole on the display quality and improving the aperture ratio of the pixel structure. .

1: Half-through reverse LCD panel

100: First substrate

110a: first semiconductor layer

110b: Second semiconductor layer

120, 140: Insulating layer

152b: Source

155a, 155b: drain

160:Patterned insulation layer

162: Raised platform

164: Bump structure

170a: First bottom transparent electrode

170b: Second bottom transparent electrode

180:Flat layer

190a: First transparent electrode

190b: Second top transparent electrode

190c: The third top transparent electrode

200: Second substrate

210:Black Matrix

220: Color conversion component

230: Covering layer

240: Common electrode

300: Liquid crystal layer

A-A’, B-B’, C-C’: line

BP1: first buffer layer

H1: first opening

LS: shading area

OP1: First opening

R1, R2, R3: area

RL: reflective layer

RF1: first reflection area

RF2: Second reflection zone

RF3: The third reflection zone

TK1, TK2: Thickness

TP1: First penetration zone

TP2: Second penetration zone

TP3: The third penetration zone

Claims (10)

A semi-transverse LCD panel, including: a first substrate; a first active component located on the first substrate; A patterned insulating layer is located on the first active component and includes a raised platform, a plurality of bump structures and a first opening; A first bottom transparent electrode fills the first opening and extends from the first opening to a first penetration area, wherein the first bottom transparent electrode is located on the raised platform and part of the bump structures , and electrically connected to the first active component; A reflective layer is located on the bump structures and overlaps a first reflective area; A planar layer is located on the patterned insulating layer and the first bottom transparent electrode, and includes a first through hole overlapping the raised platform; A first top transparent electrode overlaps the first reflective area and is electrically connected to the first bottom transparent electrode through the first through hole; a second substrate overlapping the first substrate; and A liquid crystal layer is located between the first substrate and the second substrate. The transflective liquid crystal panel as claimed in claim 1, wherein the thickness of the liquid crystal layer in the first transmission area is greater than the thickness of the liquid crystal layer in the first reflection area. The semi-reflective LCD panel as described in claim 1 further includes: a first buffer layer formed on the patterned insulating layer; A light-shielding layer formed on the first buffer layer; A second buffer layer is formed on the light-shielding layer, and the first bottom transparent electrode is formed on the second buffer layer; and A third buffer layer is formed on the first bottom transparent electrode, and the reflective layer is formed on the third buffer layer, wherein the third buffer layer has a second opening, and the reflective layer has a third opening , wherein the second opening and the third opening overlap the raised platform. The semi-reflective LCD panel as described in claim 1 further includes: A color conversion element and a common electrode are located on the second substrate. The semi-transflective liquid crystal panel as claimed in claim 1, wherein based on the top surface of the first substrate, the height of the top surface of the raised platform is higher than the height of the top surfaces of the bump structures. The semi-transflective liquid crystal panel according to claim 1, wherein the side wall of the first through hole and the top surface of the first bottom transparent electrode have an included angle of 20 degrees to 60 degrees. The transflective liquid crystal panel of claim 1, wherein the reflective layer does not overlap the first through hole in the normal direction of the top surface of the first substrate. The transflective liquid crystal panel as claimed in claim 1, wherein the reflective layer does not overlap the first opening in the normal direction of the top surface of the first substrate. The semi-reflective LCD panel as described in claim 1 further includes: a second active component; a second bottom transparent electrode electrically connected to the second active component and overlapping a second penetration region, wherein the first bottom transparent electrode extends from the first penetration region to a third penetration region; a second top transparent electrode overlapping a second reflective region and electrically connected to the second bottom transparent electrode; and A third top transparent electrode overlaps a third reflective area and is electrically connected to the first bottom transparent electrode, wherein the bump structures and the reflective layer overlap the first reflective area and the second reflective area and the third reflective zone. The semi-transflective liquid crystal panel as claimed in claim 9, wherein the first active element and the second active element each include: One drain; A first source electrode and a second source electrode are respectively located on both sides of the drain electrode; a semiconductor layer electrically connected to the drain, the first source and the second source; and A first gate and a second gate overlap the semiconductor layer.

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