KR20120130983A - Array substrate for Liquid Crystal Display Device and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for liquid crystal display device and a method for fabricating the same are provided to form a storage capacitor along the edge of the pixel region, to improve storage capacity and to prevent light leakage. CONSTITUTION: A first storage electrode(111) includes a lower layer and an upper layer. The first storage electrode is separated from agate and a data line(103) in a pixel region. The lower layer is made of a transparent conductive material of first width. The upper layer is made of a low-resistance metal material of second width which is smaller than the first width. An overlapped part between a pixel electrode and the first storage electrode is formed as a second storage electrode(153). Therefore, the second storage electrode is formed as a storage capacitor and the first storage electrode.

Description

Array substrate for liquid crystal display device and method for manufacturing same {Array substrate for Liquid Crystal Display Device and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a vertical field mode liquid crystal display device and a method of manufacturing the same, which can improve the capacity of a storage capacitor without decreasing the aperture ratio.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Of these liquid crystal display devices, an active matrix type liquid crystal display device having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, .

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the liquid crystal cell process through liquid crystal in the process.

1 is an exploded perspective view of a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display device has a configuration in which the array substrate 10 and the color filter substrate 80 face each other with the liquid crystal layer 70 interposed therebetween. 1 includes a plurality of gate wirings 15 and data wirings 40 vertically and horizontally arranged on the insulating substrate 11 and upper surfaces thereof to define a plurality of pixel regions P, and the two wirings 15 and 40 The intersection point is provided with a thin film transistor Tr, which is a switching element, and is connected in one-to-one correspondence with the pixel electrode 65 provided in each pixel region P. FIG.

In addition, the upper color filter substrate 80 facing the array substrate 10 is a transparent second insulating substrate 81 and a rear surface thereof, the gate wiring 15, the data wiring 40, and the thin film transistor Tr. A grid-like black matrix 85 is formed to cover the non-display areas such as the pixels.

In addition, the color filter layer 89 including the red, green, and blue color filter patterns 89a, 89b, and 89c sequentially and repeatedly arranged in the grid of the black matrix 85 to correspond to each pixel area P is formed. The common electrode 92 is formed over the entire surface of the black matrix 85 and the lower portion of the color filter layer 89.

In addition, first and second polarizers (not shown) for transmitting only light parallel to the polarization axis are positioned on each of the outer surfaces of the array substrate 10 and the color filter substrate 80, and beneath the first polarizer (not shown). A back light (not shown), which is a separate light source, is disposed.

FIG. 2 is a plan view of one pixel area in a general array substrate for a liquid crystal display device, and FIG. 3 is a cross-sectional view taken along the cutting line III-III of FIG. 2.

As shown, gate wirings 15 (n-1) and 15 (n) are formed in the horizontal direction in the substrate 11, and the gate wirings 15 (n-1) and 15 (n) are formed. The data line 40 is formed to intersect with each other, thereby defining the pixel area P, which is an area surrounded by the gate lines 15 (n-1) and 15 (n) and the data line 40.

Further, a gate connected to the gate lines 15 (n-1) and 15 (n) at a lowermost portion in an area where the gate lines 15 (n-1) and 15 (n) intersect with the data lines 40. A semiconductor layer 35 including an electrode 18, a gate insulating layer 30 thereon, an active contact 35a in a state connected to the gate insulating layer 30, and an ohmic contact layer 35b spaced apart from each other; The thin film transistor Tr is formed as a switching element composed of source and drain electrodes 43 and 46 spaced apart from each other on the semiconductor layer 35.

The pixel electrode 65 is formed in contact with the drain electrode 46 of the thin film transistor Tr and is independent of each pixel region P. In this case, the gate lines 15 (n-1) and 15 (n) more precisely, the pixel region P in which the pixel electrode 65 is formed is driven to the n-th gate line 15 (n). In the n th pixel region P, the pixel electrode 65 defines (n-1) th pixel region (not shown) located above the n th pixel region P (n-1). The second gate wiring 15 (n-1). As a result, in the nth pixel region P, the (n-1) th gate line 15 (n-1) is defined as the first storage electrode 20, and the (n-1) th gate line. The gate insulating film 30 and the protective layer 55 formed between the first and second storage electrodes 20 and 66 using the pixel electrode overlapping the 15 (n-1) as the second storage electrode 66. ) Is formed as a storage capacitor (StgC) having a dielectric layer.

The reason why the storage capacitor StgC must be formed in each pixel region P in the array substrate 10 for the liquid crystal display device is that in each pixel region P, the voltage applied to the liquid crystal by one signal is next. This is to maintain a constant voltage state until a signal is applied.

At this time, the capacitance C of the storage capacitor StgC is expressed as follows.

C = ε * A / d ----- ①, (ε is the dielectric constant, A is the electrode area, d is the distance between two electrodes)

According to Equation 1, the capacitance C of the storage capacitor StgC is proportional to the area A of the storage electrodes facing each other and the dielectric constant? Of the dielectric inside the electrode, and is determined by the distance d between the two electrodes. Inversely proportional. That is, the larger the area (A) of the electrode, the higher the dielectric constant (ε) of the dielectric positioned between the two electrodes, or the closer the distance (d) between the two electrodes, the larger the capacitance (C). .

Therefore, the larger the area A of the electrode, the larger the capacitance is. In order to ensure that one pixel electrode 65 has a sufficient capacitance C to maintain the applied signal voltage for a predetermined time, The gate wiring must be kept somewhat thick.

Recently, a liquid crystal display having a very short frame time for displaying one image has been proposed. In the case of such a liquid crystal display, the charging time of the storage capacitor is very short, and thus a storage capacitor having a relatively larger capacity is required. It is becoming.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can improve the aperture ratio of a pixel region while improving the capacity of a storage capacitor.

In order to achieve the above object, an array substrate for a liquid crystal display device according to an embodiment of the present invention, the substrate; A gate wiring and a data wiring formed on the substrate to define a pixel region by crossing each other with a gate insulating film interposed therebetween; A first storage electrode in the pixel region, the first storage electrode comprising a lower layer formed of a transparent conductive material having a first width and an upper layer made of a low resistance metal material having a second width smaller than the first width; A thin film transistor provided in the pixel region; A protective layer formed to expose the drain electrode of the thin film transistor; A pixel electrode formed on the passivation layer in contact with the drain electrode in the pixel area, and having a side end thereof overlapping with an upper layer of the first storage electrode, wherein the pixel electrode overlaps with the first storage electrode; The storage electrode forms a storage capacitor together with the first storage electrode overlapping the storage electrode.

The lower layer has a single layer structure, and the upper layer has a single layer or a multilayer structure.

In addition, the gate wiring and the gate electrode have a structure of the lower layer made of a transparent conductive material and the upper layer made of the low resistance metal material in the same manner as the first storage electrode.

The first storage electrode has a planar shape 'ㅁ' or 'U' in the pixel area.

The first storage electrode is formed so that the upper layer and the lower layer coincide with each of the gate line and the data line and overlap the data line.

The thin film transistor further includes a gate electrode branched from the gate wiring at a lowermost portion thereof; The gate insulating layer formed over the gate electrode; An active layer of pure amorphous silicon over the gate insulating film; An ohmic contact layer made of impurity amorphous silicon and spaced apart from each other on the active layer; It includes the source electrode and the drain electrode spaced apart from each other formed on the spaced apart ohmic contact layer.

A method of manufacturing an array substrate for a liquid crystal display device according to an embodiment of the present invention is a method of manufacturing an array substrate for a liquid crystal display device, in which a gate and data wiring defining a pixel area crossing each other and a thin film transistor are formed in the pixel area. The gate wiring layer may be formed on the substrate, and the lower layer may be formed of a transparent conductive material having a first width and spaced apart from the gate and data lines in the pixel area. Forming a first storage electrode comprising an upper layer formed of the first storage electrode; Forming the thin film transistor in the pixel region; Forming a protective layer exposing the drain electrode of the thin film transistor; Forming a pixel electrode on the protective layer in contact with the drain electrode in the pixel area and overlapping an upper end of the first storage electrode with a side end thereof, wherein the pixel electrode overlaps the first storage electrode; The second storage electrode forms a storage capacitor together with the first storage electrode overlapping the second storage electrode.

Forming a gate wiring on the substrate, spaced apart from the gate and data wiring in the pixel region, and a lower layer formed of a transparent conductive material having a first width and a low resistance metal material having a second width smaller than the first width; The forming of the first storage electrode including the upper layer may include forming a transparent conductive material layer and a low resistance metal material layer on the substrate; Forming a photoresist layer on the entire surface of the low resistance metal material layer; Exposing the photoresist layer through a furnace mask having a transmissive region, a blocking region, and a transflective region to form a first photoresist pattern of a first thickness corresponding to the upper layer of the gate wiring and the first storage wiring; Forming a second photoresist pattern of a second thickness thinner than a first thickness corresponding to a portion where only the lower layer of the first storage wiring is formed; A gate having a shape in which a portion made of a transparent conductive material and a portion made of a low resistance metal material have the same width by patterning the low resistance metal layer and a transparent conductive material layer below the exposed first and second photoresist patterns Forming a wiring and a first storage electrode; Exposing a portion of the low resistance metal material of the first storage pattern by removing the second photoresist pattern by ashing; Removing a portion of the low resistance metal material of the first storage electrode exposed to the outside of the first photoresist pattern; Removing the first photoresist pattern.

The first storage electrode is formed to have a planar shape of 'ㅁ' or 'U' in the pixel area, and is formed to coincide with the upper layer and the lower layer at a side end adjacent to each of the gate lines and the data lines. The first storage electrode may be formed to overlap the data line.

The lower layer forms a single layer structure, and the upper layer is formed to form a single layer or a multilayer structure.

The forming of the thin film transistor may include forming a gate electrode branched from the gate wiring on the substrate; Forming the gate insulating film over the gate electrode; An active layer of pure amorphous silicon over the gate insulating layer, an ohmic contact layer formed of impurity amorphous silicon and spaced apart from each other on the active layer, and a source and drain electrode spaced apart from each other over the ohmic contact layer It includes a step.

As described above, the array substrate for the liquid crystal display device according to the exemplary embodiment of the present invention is formed by covering a portion where light leakage is generated by forming a storage capacitor formed in the pixel region along the edge of the pixel region, thereby forming a part of the conventional gate wiring. As a component of the storage capacitor, the storage capacity is improved, and at the same time, the black matrix width of the liquid crystal display including the array substrate having such a configuration can be reduced by blocking light leakage, thereby improving the aperture ratio.

Further, a first storage electrode connected to the storage wiring is formed to form a lower layer of the transparent conductive material and an upper layer of the low resistance metal material having a single layer or a multilayer structure, wherein the width of the lower layer of the transparent conductive material is lowered. By increasing the width of the upper layer of the resistive metal material, the storage capacity can be further improved without reducing the aperture ratio.

1 is an exploded perspective view of a general liquid crystal display device.
2 is a plan view of one pixel area in a typical array substrate for a liquid crystal display device;
3 is a cross-sectional view taken along the line III-III of FIG. 2;
4 is a plan view showing one pixel area of an array substrate for a liquid crystal display device according to a first embodiment of the present invention;
FIG. 5 is a cross-sectional view of a portion cut along the cutting line VV in FIG. 4. FIG.
FIG. 6 is a cross-sectional view of a portion cut along the cutting line VI-VI of FIG. 4. FIG.
7 is a plan view showing one pixel area of an array substrate for a liquid crystal display device according to a second embodiment of the present invention;
8 is a cross-sectional view of a portion cut along line VIII-VIII of FIG. 7;
9A to 9G are cross-sectional views of manufacturing steps of a portion cut along the cutting line VV of FIG. 4;
10A to 10G are cross-sectional views of manufacturing steps of the portion cut along the cutting line VI-VI of FIG. 4.

Hereinafter, an array substrate for a liquid crystal display device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a plan view illustrating one pixel area of an array substrate for a liquid crystal display device according to a first embodiment of the present invention, FIG. 5 is a cross-sectional view of a portion taken along the cutting line VV of FIG. FIG. 4 is a cross-sectional view of a portion cut along the cutting line VI-VI. In this case, for convenience of description, the region in which the thin film transistor Tr as the switching element is to be formed in each pixel region P is referred to as the switching region TrA and the region in which the storage capacitor StgC is to be formed as the storage region StgA. In FIG. 6, the black matrix BM included in the color filter substrate is illustrated.

First, referring to FIG. 4, referring to an array substrate 101 for a liquid crystal display device according to a first embodiment of the present invention, a plurality of gate wirings are defined by crossing pixel horizontally and vertically. 103 and the data wiring 130 are formed.

In this case, the first storage electrode 111 is formed on the same layer in which the gate line 103 is formed, and the pixel area P is formed inside the pixel area P. At this time, each of the first storage electrodes 111 adjacent to each other in the horizontal direction from which the gate wiring 103 extends is electrically connected to each other by a connection pattern made of the same material.

Common voltage Vcom is typically applied to the first storage electrode 111.

In the switching region TrA in each pixel region P, a thin film transistor, which is a switching element composed of a gate electrode 105, a gate insulating film 115, a semiconductor layer 120, and source and drain electrodes 133 and 136, is formed. Tr is connected to the gate line 103 and the data line 130.

In addition, a protective layer 140 having a drain contact hole 143 exposing the drain electrode 136 of the thin film transistor Tr is formed in the display area, and the drain contact hole is formed on the protective layer 140. The plate electrode 150 is formed in contact with the drain electrode 136 through each of the pixel regions P.

In this case, the pixel electrode 150 overlaps the first storage electrode 111 formed to surround each pixel area P inside the pixel area P, and thus the first overlapping electrode 1. The storage electrode 111 and the pixel electrode 150 form a storage capacitor StgC.

As such, the storage capacitor StgC, which has a shape that surrounds the pixel area P, that is, a 'ㅁ' shape, is formed so as to overlap with the conventional gate line 20 of FIG. 2. It has a larger area in each pixel region P relative to the '-shaped storage capacitor (StgC of FIG. 2), and thus has a large capacity.

Furthermore, the most characteristic configuration of the array substrate 101 for a liquid crystal display device according to the first embodiment of the present invention is that the first storage electrode 111 is a lower layer 109 made of a transparent conductive material and a low resistance metal material. The first layer (w1) of the lower layer 109 made of the transparent conductive material and the second layer of the upper layer 110 made of the low resistance metal material It has a value larger than two widths w2, and the lower layer 109 is formed to be exposed to the outside of the upper layer 110 in each pixel area P.

In this case, the first storage electrode 111 may be formed at an end of the lower layer 109 made of the transparent conductive material and the upper layer 110 made of the low resistance metal material at the side adjacent to the gate line 103 and the data line. It is a feature that the ends are formed to coincide.

As described above, the first storage electrode 111 having a multi-layer structure having different widths (w1> w2) has a transparent characteristic even if the first width w1 of the lower layer 109 made of the transparent conductive material is increased. As a result, the reduction of the aperture ratio is suppressed, and at the same time, the area overlapping the pixel electrode 150 in each pixel region P increases by increasing the first width w1, thereby increasing the capacitance of the storage capacitor StgC itself. Will increase.

In addition, since the first storage electrode 111, which is a component of the storage capacitor StgC, which surrounds each pixel region P, substantially serves as a black matrix, the first storage electrode 111 may be bonded to the array substrate 101 having such a configuration. The width of the black matrix BM included in the color filter substrate (not shown), which completes the liquid crystal display device, may be reduced, thereby implementing an effect of improving the aperture ratio.

A cross-sectional configuration of the array substrate 101 for a liquid crystal display device according to the first embodiment of the present invention having the planar configuration as described above will be described with reference to FIGS. 5 and 6.

As shown in the drawing, a gate wiring (103 in FIG. 4) extending in one direction is formed on a transparent insulating substrate 102, for example, a glass substrate or a plastic substrate, and the gate wiring 103 is formed in the switching region TrA. ) And a gate electrode 105 is formed.

In addition, the transparent insulating substrate 102 is spaced apart from the gate wiring 103 and has a shape that surrounds the inside of each pixel area P corresponding to each pixel area P. 1 storage electrode 111 is formed.

In this case, the first storage electrode 111 is electrically connected between the neighboring ones in the extending direction of the gate wiring 103 via a connection pattern.

Meanwhile, the first storage electrode 111, the gate wiring 103, and the gate electrode 105 are all made of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). The lower layer 109 of the layer structure and a low resistance metal material, for example, a single layer made of any one or two or more of aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum, molybdenum titanium or It is characterized by being composed of the upper layer 110 of a multilayer structure.

In this way, the first storage electrode 111 of the components formed on the transparent insulating substrate 102 is different from the first width w1 of the lower layer 109 and the second width w2 of the upper layer 110. Doing so is another feature. In this case, the first storage electrode 111 has a side surface adjacent to the gate line 103 and the data line 130 at the ends of the upper layer 110 and the lower layer 109, and each pixel area is the same. The side surface located inside (P) has a value where the first width w1 of the lower layer 109 made of the transparent conductive material is larger than the second width w2 of the upper layer 110. The lower layer 109 is characterized by forming a structure exposed to the outside of the upper layer (110).

The first storage electrode 111 has the same structure as described above and has a shape covering each pixel area P, and is made of a transparent conductive material even if the first width w1 of the lower layer 109 is increased. The opening ratio of each pixel area P is not affected at all and the capacity of the storage capacitor StgC can be improved.

Next, a gate insulating layer made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the gate wiring 103 (see FIG. 4), the gate electrode 105, and the first storage electrode 111. 115 is provided.

In addition, the pixel line P is defined on the gate insulating layer 115 to intersect with the gate line 103 in FIG. 4, and the data line 130 is formed.

In the switching region TrA, an ohmic contact made of an active layer 120a made of pure amorphous silicon corresponding to the gate electrode 105 and an impurity amorphous silicon spaced apart from each other with the gate electrode 105 interposed therebetween. The semiconductor layer 120 composed of the layer 120b is formed.

The source electrode 133 and the drain electrode 136 are formed on the semiconductor layer 120 to be in contact with the ohmic contact layer 120b and to be spaced apart from each other. In this case, the source electrode 133 is electrically connected to the data line 130.

In this case, the gate electrode 105, the gate insulating layer 115, and the source and drain electrodes 133 and 136 which are spaced apart from each other and sequentially stacked on the switching region TrA form a thin film transistor Tr. .

Meanwhile, although the first pattern 121a and the second pattern 121b made of a semiconductor material are provided between the data line 130 and the gate insulating layer 115 due to the characteristics of the manufacturing method, the first pattern 121a and the second pattern 121b are provided. The first and second patterns 121a and 121b may be omitted.

Next, a passivation layer 140 having a drain contact hole 143 exposing the drain electrode 136 of the thin film transistor Tr on the front surface of the thin film transistor Tr is formed. In this case, the protective layer 140 is made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material such as photo acryl or benzocyclobunten (BCB). )

In the drawing, the protective layer 140 is made of an inorganic insulating material, and an example is illustrated.

Next, the passivation layer 140 is formed of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), and the drain contact in an independent form for each pixel region P. Contacting the drain electrode 136 through the hole 143, overlapping the upper layer 110 of the first storage electrode 111, and having a side end thereof on the upper layer 110 of the first storage electrode 111. By forming the pixel electrode 150 as a form, the array substrate 101 for a liquid crystal display device according to the first embodiment of the present invention is completed.

In this case, a portion of the pixel electrode 150 overlapping the first storage electrode 111 in each pixel area P forms a second storage electrode 153.

Accordingly, the storage capacitor StgC is formed by using the first and second storage electrodes 111 and 153 overlapping each other, and the gate insulating layer 115 and the protective layer 140 interposed between the two components as dielectric layers. To achieve.

In the case of the array substrate 101 for a liquid crystal display device according to the first embodiment of the present invention having the above configuration, the side end of each pixel electrode 150 is positioned on the first storage electrode 111 having a double layer structure. While the first storage electrode 111 itself serves as a black matrix, the first layer w1 of the lower layer 109 made of a transparent conductive material among the first storage electrodes 111 may have an upper layer made of a low resistance metal material ( By forming a width wider than the second width w2 of the 110, the portion overlapping the pixel electrode 150 is increased without decreasing the aperture ratio, thereby increasing the capacitance of the storage capacitor StgC.

FIG. 7 is a plan view illustrating one pixel area of an array substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view of a portion taken along the line VII-VII of FIG. 7. For convenience of description, the same reference numerals are given to the same components as those in the first embodiment, and the same reference numerals are assigned to only the first storage electrodes having differentiation points. In FIG. 8, the black matrix provided in the color filter substrate is shown. (BM) is shown together.

The array substrate 101 for a liquid crystal display device according to the second embodiment of the present invention is the same as the first embodiment except for the shape of the first storage electrode 211. Will be explained mainly in the form of).

7 and 8, in the case of the array substrate 101 for a liquid crystal display according to the second embodiment of the present invention, the first storage electrode 211 has a “U” shape, and the data line 130 is formed. It is characterized by being overlapped with.

As such, the first storage electrode 211 is formed to overlap the data line 130, so that portions positioned at both ends of the data line 130 except for the portion overlapping the data line 130 are substantially each pixel. It serves as the first storage electrode 211 in the region P.

At this time, the first storage electrode 211 having a “U” shape is a single layer structure having a first width w1 as a single layer structure made of a transparent conductive material and a single layer made of a low resistance metal material as in the first embodiment. Or a multi-layered structure consisting of an upper layer 210 having a second width w2 smaller than the first width w1, which improves the capacity of the storage capacitor StgC without lowering the aperture ratio. The black matrix BM may be configured to reduce the width of the black matrix BM provided in the color filter substrate (not shown) facing the array substrate 101 having such a configuration.

In the case of the first storage electrode 211 according to the second embodiment of the present invention, since the area between the side end of the data line 130 and the side end of the pixel electrode 150 is also formed, light leakage is further increased compared to the first embodiment. It acts as a black matrix with the parts that occur.

Therefore, the array substrate 101 according to the second embodiment of the present invention having the first storage electrode 211 having such a shape has a black matrix BM formed on a color filter substrate (not shown) in consideration of the bonding margin. ) Is smaller than that of the first embodiment, so light leakage does not occur in the region between the data line 130 and the pixel electrode 150. In particular, the width of the black matrix BM formed corresponding to the data line 130 is reduced. Since it can be made relatively small, it has the effect of improving an aperture ratio.

Other components are the same as those in the above-described first embodiment, and description thereof will be omitted.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described. In the case of the array substrate for a liquid crystal display device according to the second embodiment, the array according to the first embodiment is manufactured by substantially the same manufacturing process, except that only the planar shape of the first embodiment and the first storage capacitor StgC is different. Only the manufacturing method of a board | substrate is demonstrated.

9A to 9G are cross-sectional views illustrating manufacturing steps of a portion cut along the cutting line VV of FIG. 4, and FIGS. 10A to 10G are cross-sectional views illustrating manufacturing steps of a portion cut along the cutting lines VI-VI of FIG. 4. to be.

9A and 10A, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the transparent insulating substrate 102 to form a transparent conductive material layer ( 301, and continuously depositing one or more materials of a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum and molybdenum titanium The low resistance metal layer 305 of a single layer or multilayer structure is formed. In the drawing, the low resistance metal layer 305 is formed as a single layer structure as an example.

Thereafter, a photoresist is formed on the low resistance metal layer 305 to form a photoresist layer 191, and the transmission area TA transmits light almost 100% onto the photoresist layer 191, and the light is almost transmitted. An exposure mask 195 having a blocking area BA blocking 100% and a semi-transmissive area HTA transmitting about 20% to 80% of light is positioned, and the photoresist layer (195) is disposed through the exposure mask 195. 191).

At this time, the photoresist for forming the photoresist layer 191 is largely positive type (negative type) and negative type (negative type), the negative type (negative type) is the portion that is irradiated with light remains when developing On the contrary, the positive type has a characteristic in which a portion irradiated with light is removed during development.

In the method of manufacturing the array substrate for a liquid crystal display device according to the first embodiment of the present invention, a negative type photoresist is used as an example. However, a positive type photoresist may be used for blocking. The same result can be obtained by performing exposure using the exposure mask which changed the position of the area | region BA and the transmission area | region TA.

 Meanwhile, the exposure of the photoresist layer 191 requires a gate wiring (103 in FIG. 4), a gate electrode (105 in FIG. 9G), and a first storage electrode (111 in FIG. 10G) having a double layer or multilayer structure formed. The semi-transmissive area corresponds to the portion where only the lower layer (109 of FIG. 10G) of the single-layer structure of the transparent conductive material is formed in the first storage electrode (111 of FIG. 10G) so that the blocking area BA corresponds to the portion to be formed. The transmissive area TA is formed so as to correspond to the HTA and to regions other than a portion where the gate wiring 103 (FIG. 4), the gate electrode (105 in FIG. 9G), and the first storage electrode 111 should be formed. The exposure mask 195 is positioned to correspond, and then proceeds.

After the exposure is performed, the development process of the photoresist layer 191 is performed. As shown in FIGS. 9B and 10B, a gate wiring having a multilayer structure over the low resistance metal layer 305 of FIG. 9A (FIG. A first photoresist pattern 191a having a first thickness is formed to correspond to 103 of 4, a gate electrode (105 in FIG. 9G), and a portion where the first storage electrode 111 is to be formed, and the first storage electrode A second photoresist pattern 191b having a second thickness thinner than the first thickness is formed to correspond to a portion where only the lower layer 109 having a single layer structure made of a transparent conductive material is to be formed. In this case, all of regions other than the portion where the gate wiring (103 in FIG. 4), the gate electrode (105 in FIG. 9G) and the first storage electrode 111 are to be formed are removed, so that the low resistance metal layer (305 in FIG. 9A) is removed. This is an exposed state.

Thereafter, the low-resistance metal layer 305 of FIG. 9A and the transparent conductive material layer 301 of FIG. 9A having the first and second photoresist patterns 191a and 191b exposed to the outside are removed by etching. On the substrate 102, a gate wiring (103 of FIG. 4), a gate electrode 105, and a first storage electrode 111 made of a low resistance metal material having a structure of at least two layers with a lower layer 109 of a transparent conductive material layer are formed. Form.

At this time, the first storage electrode 111 has a state in which the lower layer 109 made of a transparent conductive material and the upper layer 110 made of a low resistance metal material have the same first width w1.

Next, as shown in FIGS. 9C and 10C, ashing is performed to remove the second photoresist pattern (191b of FIG. 9B) having the second thickness, thereby making the transparent of the first storage electrode 111 transparent. The upper layer 110 made of the low-resistance metal material of the portion to form the single layer structure made of the conductive material is exposed.

In this case, the thickness of the first photoresist pattern 191a having the first thickness also decreases but still remains due to the ashing process.

Next, as illustrated in FIGS. 9D and 10D, the upper layer 110 of the first storage electrode 111 exposed by removing the second photoresist pattern 191b of FIG. 9C is removed by etching. A first storage electrode having a lower layer 109 of a transparent conductive material having a first width w1 and an upper layer 110 of a low resistance metal material having a second width w2 smaller than the first width w1. 111).

Next, as illustrated in FIGS. 9E and 10E, a strip process may be performed to perform first stripping on the gate wiring 103, the gate electrode 105, and the first storage electrode 111. The photoresist pattern (191a in FIG. 9D) is removed.

Subsequently, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the gate wiring (103 in FIG. 4), the gate electrode 105, and the first storage electrode 111. The insulating film 115 is formed.

Successively depositing pure amorphous silicon (a-Si), impurity amorphous silicon (n + a-Si), and a metal material on the gate insulating layer 115 in succession to form a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown). C) and a first metal material layer (not shown).

Subsequently, the first metal material layer (not shown), the impurities, and the pure amorphous silicon layer (not shown) are patterned by performing a mask process including coating of photoresist, exposure using an exposure mask, development, etching, and stripping. do.

As a result of the mask process, a data line 130 defining each pixel region P is formed on the gate insulating layer 115 to intersect with the gate line 103 in FIG. 4, and simultaneously, in the switching region TrA. In the embodiment, the semiconductor layer 120 including the ohmic contact layer 120b of the impurity amorphous silicon and the semiconductor layer 120 are spaced apart from each other in the form of an active layer 120a of pure amorphous silicon and an upper portion thereof. The source electrode 133 and the drain electrode 136 are formed. At this time, the first and second patterns 121a and 121b may be formed of the same material forming the semiconductor layer 120 under the data line 130 due to the process of forming the semiconductor layer 120 and the data line 130 at the same time. 121b) is formed, but when the mask process is performed twice, that is, the semiconductor layer 120 and the data line 130 are patterned by performing different mask processes, respectively, under the data line 130. The first and second patterns 121a and 121b may be omitted.

In this case, the source electrode 133 is formed to be connected to the data line 130, and the gate electrode 105, the gate insulating layer 115, and the semiconductor layer 120 sequentially stacked on the switching region TrA. ) And the source and drain electrodes 133 and 136 spaced apart from each other form a thin film transistor Tr.

Next, as shown in FIGS. 9F and 10F, an inorganic insulating material, eg, silicon oxide (SiO), is formed on the entire surface of the thin film transistor Tr including the data line 130 and the source and drain electrodes 133 and 136. ₂ ) or the silicon nitride (SiNx) is deposited, or the protective layer 140 is formed by applying an organic insulating material such as photoacryl or benzocyclobutene. In the drawing, the protective layer 140 having a flat surface is formed by applying an organic insulating material as an example.

Thereafter, a mask process is performed on the protective layer 140 to form a drain contact hole 143 exposing the drain electrode 136 in the switching region TrA.

Next, as shown in FIGS. 9G and 10G, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide, is disposed on the passivation layer 140 having the drain contact hole 143. (IZO) is deposited on the entire surface, and is patterned by performing a mask process to form an independent pixel electrode 150 for each pixel region P, thereby forming an array substrate for a liquid crystal display device according to a first embodiment of the present invention. Complete 101.

In this case, the pixel electrode 150 is formed to contact the drain electrode 136 through the drain contact hole 143 provided in the protective layer 140.

In addition, each pixel electrode 150 is formed to overlap the first storage electrode 111 provided in each pixel area P, and a side end of each pixel electrode 150 is formed of the first storage electrode 111. It is characterized in that it is formed so as to correspond to the portion constituting the multilayer structure of more than the double layer.

Accordingly, a portion of the pixel electrode 150 overlapping with the first storage electrode 111 forms a second storage electrode 153, and the first storage electrode 111 and the gate insulating layer 115 overlap each other. The layer 140 and the second storage electrode 153 form a storage capacitor StgC.

In the case of the array substrate 101 for a liquid crystal display device manufactured by the manufacturing method according to the first embodiment of the present invention, the first storage electrode 111 has a gate wiring and a data wiring 130 inside each pixel region P. FIG. Since the pixel area P is formed to be spaced apart from each other, it is possible to increase the area to improve the capacity of the storage capacitor StgC.

Further, the first storage electrode 111 is dualized into a portion forming a multilayer structure and a portion forming a single layer structure of a transparent conductive material, thereby forming a lower layer 109 having a single layer structure made of a transparent conductive material. P) by expanding inwardly, the area can be increased to further increase the storage capacitor (StgC) capacity without lowering the aperture ratio.

In addition, the first storage electrode 111 serves as a black matrix by itself, thereby bonding the margins of the color filter substrate (not shown) which are bonded to the array substrate 101 having such a structure to form a liquid crystal display device. The width of the considered black matrix can be reduced compared to that of an array substrate for a liquid crystal display device using a gate wiring of a conventional storage capacitor (StgC), thereby improving the aperture ratio.

101: array substrate 103: gate wiring
105: gate electrode 109: lower layer (of the first storage electrode)
110: upper layer (of the first storage electrode)
111: first storage electrode 130: data wiring
133: source electrode 136: drain electrode
143: drain contact hole 150: pixel electrode
153: second storage electrode
P: Pixel Area StgA: Storage Area
StgC: Storage Capacitor Tr: Thin Film Transistor
w1, w2: first, second width

Claims (14)

A substrate;
A gate wiring and a data wiring formed on the substrate to define a pixel region by crossing each other with a gate insulating film interposed therebetween;
A first storage electrode in the pixel region, the first storage electrode comprising a lower layer formed of a transparent conductive material having a first width and an upper layer made of a low resistance metal material having a second width smaller than the first width;
A thin film transistor provided in the pixel region;
A protective layer formed to expose the drain electrode of the thin film transistor;
A pixel electrode formed on the passivation layer in contact with the drain electrode in the pixel area and having a side end thereof overlapping with an upper layer of the first storage electrode
And the pixel electrode forming a storage capacitor together with the first storage electrode overlapping the first storage electrode by overlapping the first storage electrode with the second storage electrode.
The method of claim 1,
And the lower layer has a single layer structure, and the upper layer has a single layer or a multilayer structure.
The method of claim 1,
And the gate wiring and the gate electrode have a structure of the lower layer made of a transparent conductive material and the upper layer made of the low resistance metal material, similarly to the first storage electrode.
The method of claim 1,
And the first storage electrode is planar in the pixel area in a planar shape, 'U' or 'U'.
The method of claim 1,
And wherein the first and second storage electrodes coincide with the upper and lower layers at side ends adjacent to the gate and data lines.
The method of claim 1,
And the first storage electrode is formed to overlap the data line.
The method of claim 1,
The thin-
A gate electrode branched from the gate wiring at the lowermost portion;
The gate insulating layer formed over the gate electrode;
An active layer of pure amorphous silicon over the gate insulating film;
An ohmic contact layer made of impurity amorphous silicon and spaced apart from each other on the active layer;
The source electrode and the drain electrode spaced apart from each other formed on the ohmic contact layer spaced apart from each other
Array substrate for a liquid crystal display device comprising a.
A method of manufacturing an array substrate for a liquid crystal display device, wherein a gate and data line defining a pixel region crossing each other and a thin film transistor are formed in the pixel region.
Forming a gate wiring on the substrate, spaced apart from the gate and data wiring in the pixel region, and a lower layer formed of a transparent conductive material having a first width and a low resistance metal material having a second width smaller than the first width; Forming a first storage electrode composed of an upper layer;
Forming the thin film transistor in the pixel region;
Forming a protective layer exposing the drain electrode of the thin film transistor;
Forming a pixel electrode on the passivation layer in contact with the drain electrode in the pixel area, and a side end thereof overlaps with an upper layer of the first storage electrode;
Wherein the pixel electrode forms a storage capacitor together with the first storage electrode overlapping with the first storage electrode overlapping the first storage electrode to form a second storage electrode. Way.
The method of claim 8,
Forming a gate wiring on the substrate, spaced apart from the gate and data wiring in the pixel region, and a lower layer formed of a transparent conductive material having a first width and a low resistance metal material having a second width smaller than the first width; Forming the first storage electrode consisting of an upper layer,
Forming a transparent conductive material layer and a low resistance metal material layer on the substrate;
Forming a photoresist layer on the entire surface of the low resistance metal material layer;
Exposing the photoresist layer through a furnace mask having a transmissive region, a blocking region, and a transflective region to form a first photoresist pattern of a first thickness corresponding to the upper layer of the gate wiring and the first storage wiring; Forming a second photoresist pattern of a second thickness thinner than a first thickness corresponding to a portion where only the lower layer of the first storage wiring is formed;
A gate having a shape in which a portion made of a transparent conductive material and a portion made of a low resistance metal material have the same width by patterning the low resistance metal layer and a transparent conductive material layer below the exposed first and second photoresist patterns Forming a wiring and a first storage electrode;
Exposing a portion of the low resistance metal material of the first storage pattern by removing the second photoresist pattern by ashing;
Removing a portion of the low resistance metal material of the first storage electrode exposed to the outside of the first photoresist pattern;
Removing the first photoresist pattern
Method of manufacturing an array substrate for a liquid crystal display device comprising a.
The method of claim 8,
And the first storage electrode is formed to have a shape of 'ㅁ' or 'U' planarly in the pixel area.
The method of claim 8,
And wherein the first storage electrode is formed to coincide with the upper layer and the lower layer at a side end adjacent to each of the gate lines and the data lines.
The method of claim 8,
And the first storage electrode is formed to overlap the data line.
The method of claim 8,
And wherein the lower layer has a single layer structure, and the upper layer has a single layer or a multilayer structure.
The method of claim 8,
Forming the thin film transistor,
Forming a gate electrode branching from the gate wiring on the substrate;
Forming the gate insulating film over the gate electrode;
An active layer of pure amorphous silicon over the gate insulating layer, an ohmic contact layer formed of impurity amorphous silicon and spaced apart from each other on the active layer, and a source and drain electrode spaced apart from each other over the ohmic contact layer Steps to
Method of manufacturing an array substrate for a liquid crystal display device comprising a.

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